Escolar Documentos
Profissional Documentos
Cultura Documentos
H. Michalik, B. Fiethe
Requirements:
• Mission specific
• Operational radiation tolerance
control
• Specific data
• Adequate reliability
processing • Low volume and mass
• S/C TM/TC • Low power
handling
• Sufficient computing
• Autonomous
sequences power
• Real-time
requirements for high
sensor data rates
• Moderate unit costs
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08.07.2008
System-on-Chip Design Approach
Integration of all interfaces and special functions together
with processor system on radiation tolerant qualified FPGA
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08.07.2008
Basic SEU Mitigation
Configuration RAM, logic and memory prone to SEU’s
Reduction of SEU rates to negligible or tolerable values:
• Triple Modular Redundancy (TMR)
• Removal of half-latches in design
• Configuration memory scrubbing
• Error detection in configuration data stream
• Functional testing
• Detection of bus contention
• Cyclic reconfiguration to avoid persistent errors
• Processor watchdog
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08.07.2008
Advanced SEU Tolerance
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08.07.2008
VMC DPU Parameter
Processor • LEON-2 core (SPARC compatible) in XilinX-1
• 20 MIPS
Memory • 1 Gbit image mass memory (SDRAM) incl. DMA controller
• 16 Mbit SRAM
• 16 Mbit EEPROM (Program memory)
• 64 kbit PROM (Bootloader)
Error Correction • System Supervisor by rad-hard Actel FPGA
• Zero wait state Reed-Solomon single symbol correction for
program and image memory
Interface to S/C RTU & 1355 Spacewire I/F, main & redundant
Volume 250cm3
Mass 280g
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VMC DPU
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08.07.2008
Venus Monitoring Camera
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08.07.2008
VMC Verified in Space
• Routine science
operations started
• VMC switched on
>400h
• Only few single
errors in
SRAM/SDRAM
detected
• No indication of
any SEU effect in
FPGA’s
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08.07.2008
Application Roadmap
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08.07.2008
Roadmap (1): Use of Xilinx1
The SoC Approach has been proven by VMC project to
be highly advantageous for space applications
Already implemented further applications are:
- Dawn Framing Camera (Nasa Satellite)
Camera DPU (similiar to VMC but Class S Parts)
- KompSat 2: Korean Earth Observation Satellite
Implementation of high speed CCSDS
communication processor (channel coding +
encyption) within Xilinx 1
- SarLupe: German SAR Satellite:
+ high speed CCSDS communication processor
+ Crypto Coprocessor for authentication
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08.07.2008
DAWN FC DPU
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08.07.2008
KompSat 2 Communication Processor
© OHB/DSI
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08.07.2008
Roadmap (2) Future DPU: Virtex-II/IV with
Embedded Cores
Detector Spacewire
VIRTEX FPGA
I/F Drivers I/F Drivers
Ser. I/F Online
14 14 Pre-Processing Data Mux/ Space DATA
/ / & JPEG2000 Formatting Wire
Data Compression Core Core
Core
S/C
Detector On Chip
Bus System CMD
Supervisor RTU-I/F
Ser. I/F I/F CPU Core (ACTEL FPGA) TLM
Logic (Leon 3)
CTRL
Local Bus
Image Memory
Local Memory HK Interface
Buffer
128 Mbit SDRAM (Digital + Analog)
4 Gbit DRAM
8 Mbit EEPROM
(Error Corrected)
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JPEG2000 Compression Core
• Tile size of 128x128 pixels, 14 bits resolution
• 5-level lossless DWT, Tier-1 encoding
• 125MHz on Virtex-II
• Scalable to needed data rate (250 Mbit/s)
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Roadmap (2): Design Drivers for advanced
DPUs (Solar Orbiter)
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08.07.2008
Virtex-II Pro DPU Design
Spacewire
VIRTEX-II PRO FPGA
Detector I/F Drivers
or VIRTEX-4
I/F Drivers
Data
Online Online RTE S/C-I/F
Compression Space
Detector Image Pre- Inversion
Core
and Wire
Data I/F Summation Processing
or FPGA Formatting Core
Core Core Core
On Chip
Bus
CPU
Supervisor
Dual PowerPC Core (ACTEL FPGA)
ISS, I/F - real-time processing control
MPM, Logic
CTRL - instrument control
etc.
Local Bus
Image Memory
Helioseismic Local Memory
Buffer Thermal Control
Data Storage 256 Mbit SDRAM
8 Gbit DRAM + HK Interface
(EEPROM) 8 Mbit EEPROM
(Error Corrected)
HK Heaters
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08.07.2008
Advanced Scalable PDH Architecture
Ultra High Rate Interfaces
OBDH
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08.07.2008
Virtex based Processor Module
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08.07.2008
Roadmap (3): Mass Memory Modules
Example TerraSar-X SSMM Module (UFM)
High Speed (up to 2 Gbit/s)
and High Capacity (64/128
Gbit),
• G-Link serial input
interfaces and parallel
output interface
• 64/128 Gbit/Board
(256/512 Mbit SDR-SDRAM
devices)
• appr. 1.6 Gbit/s input
data rate
• appr. 300 Mbit/s output
data rate
• appr. double Eurocard
board size
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08.07.2008
Memory Module functional groups
Data Input
16 16
Data I/F Control Memory
Data Drivers
Clk Sync. 32
Logic Array
FIFO
Enable Write
/FF
Sync.
36 36 Error 72 72
FIFO
Correction
Scrub
Data Output
16 16
Data
Clk Sync. Memory Array of
32 64 Gbit User Data
FIFO
Enable
Read
/EF 256 Mbit SDRAM
in 8 high Stacks
Cmd/Status
8 8 CMD I/F 2 Latch-Up Protected
Address
/Data
Memory Partitions
5 5 Address 15 15
ModCtrl
Generator
/Int
+3,3V Power
+5V
Fast 18 18
Distribution Timing &
3 Power
PCmd
Switch Control
PE
PStat FPGA
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08.07.2008
Summary
• SRAM based FPGAs are needed for implementation of
advanced applications in space
• Future applications of Virtex II, Virtex IV, Virtex V (?) are in
– SoC DPUs and on Board Processors
– Communication Processors (Digital Radio)
– Mass Memory Control
– etc.
• Main efforts:
– coping with single event effects, failure tolerant design
– radiation characterisation of FPGAs (complex)
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08.07.2008