DISC

The first part of the experiment focuses on unclocked RS latch using NAND gates. When the LED is
turned on, it follows that Q is logic 1 and Q’ is logic 0. Qn is the fixed point of the flip flop. At Qn=S=R=0,
Qn+1 is 0. The initial state of S and R serves as the reference point. When S=0 and R=1, the values are
the same because S=0. If there is no value for set, the value of reset is neglected. When S=1 and R=0, Qn
changes since there is a new set stored at the memory of the flip flop. When S and R have an input logic
1, Q will have a logic value 1. Now this is invalid because in an RS flip flop, when S = 1 and R =1, no
matter what state Q and Q' are in, application of 1 at input of NAND gate always results in 0 at output of
NAND gate, which results in both Q and Q' set to LOW (i.e. Q = Q'). LOW in both the outputs basically is
wrong, so this case is invalid.

Meanwhile, the second part of the experiment focuses on JK flip flops. It is observed that same results
were obtained. That is because JK flip flop is exactly the same as the SR flip-flop. It is basically a gated SR
Flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition.

CONC

The experiment is about flip flops and their characteristics. It aims 1) to know the characteristics
of RS flip-flop connected from NAND gates and JK flip-flop, 2) to know the effect of clock signal in
operating a flip-flop, and 3) to create a frequency divider circuit using JK flip-flop.

An RS latch is assembled by wiring two NAND gates in such a way that the output of one feeds back to
the input of another. It has two inputs, S and R. S is called set and R is called reset. The S input is used to
produce HIGH on Q ( i.e. store binary 1 in flip-flop). The R input is used to produce LOW on Q (i.e. store
binary 0 in flip-flop). Q' is Q complementary output, so it always holds the opposite value of Q. The
output of the S-R latch depends on current as well as previous inputs or state, and its state (value
stored) can change as soon as its inputs change. An SR latch that is built from NAND gates has active low
inputs. Because the NAND inputs must normally be logic 1 to avoid affecting the latching action, the
inputs are to be inverted in this circuit. The operation has to be analyzed with the 4 inputs combinations
together with the 2 possible previous states. When both S and R inputs are LOW (S=R=0), the output is
retained as before the application of inputs. i.e. there is no state change. When S is HIGH and R is LOW
(S=1, R=0), output Q is HIGH. When S is LOW and R is HIGH (S=0, R=1), output Q is LOW. When S = 1 and
R =1, no matter what state Q and Q' are in, application of 1 at input of NAND gate always results in 0 at
output of NAND gate, which results in both Q and Q' set to LOW (i.e. Q = Q'). LOW in both the outputs
basically is wrong, so this case is invalid.

Conversely, JK flip flop is exactly the same as the SR flip-flop with the same “Set” and “Reset” inputs. The
difference is that the JK flip flop has no invalid or forbidden input states of the SR Latch even
when S and R are both at logic “1”. The JK flip flop is basically a gated SR Flip-flop with the addition of a
clock input circuitry that prevents the illegal or invalid output condition that can occur when both
inputs S and R are equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has four
possible input combinations: logic 1(J=1, K=0), logic 0 (J=0, K=1), no change (J=K=0) and toggle (J=K=1).
Often, the operation of a sequential circuit is synchronized by a clock signal. The clock signal regulates
when the circuits respond to new inputs, so that operations occur in proper sequence. The addition of
clock signal in a flip-flop synchronizes the switching from the previous state to the next state. This only
means that the clock signal should be connected first to the ground before switching occurs.

A frequency divider circuit can be constructed from JK flip flops by taking the output of one cell to the
clock input of the next. That is, there is a single connection for the J and K inputs and they are connected
to Vcc. The J and K inputs of each flip flop are set to 1 to produce a toggle at each cycle of the clock
input. For each two toggles of the first cell, a toggle is produced in the second cell, so its output is at half
the frequency of the first.