Document Type: Tutorial

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Publish Date: Dec 1, 2009

Design and Simulation of ECC Circuits Using NI

Electronics Workbench Group Software
Overview

Author: Prof. M. Altaf Mukati, Hamdard University

ECC (error control coding) circuits have been used since 1961 for correcting errors in various telecommunications and computer-related applications, especially memory. The only difference
between these two types of applications is the way the “channel” is treated (either “spatial” or “temporal”). In semiconductor memories, ECC is used for single-/multiple-bit(s) error
detection/correction in data to improve the reliability and functioning of the systems, especially critical systems. For our nearly 20 years of teaching and working on ECC circuits, National
Instruments Electronics Workbench Group software has been instrumental in our design and simulation of ECC circuits.

Table of Contents

1. Design of an ECC Decoder Based on Orthogonal Parity Checksums [4]

2. Conclusion
3. References

Semiconductor memory is currently the predominant choice for random access and read-only memory applications that require rapid access. Advances in semiconductor memory technology
toward higher-density and higher-performance memory chips have created new reliability challenges for memory system designers. Computer memory chips containing 128 MB are now quite
common, and chips of even greater bit densities are becoming available. In addition, each new computer system generation has seen a substantial increase in the number of memory chips used
with a corresponding significant increase in memory capacity.

However, larger-capacity memory systems using higher-density memory chips are more susceptible to failures. The read/write errors in semiconductor memory are generally labeled as either
“hard” or “soft” errors. Hard errors are device failures that are relatively permanent, such as defects in a dynamic single MOSFET cell (word-line, bit-line, chip-fail), while soft errors are transient and
sometimes called single event upsets (SEUs).

Probability of soft faults is generally higher than hard faults. SEUs are frequently caused by radiations, or atomic particles leaving an ion trail or “tunnel” as they pass through a device substrate. In
many device technologies, this can cause a change in the state of the affected memory cells [1]. More than 80 percent of errors are single-bit errors caused by cell faults, α-particles, and external
noises [2]. SEUs can also be caused by electronic transients induced by lightning, adjacent electrical machinery, and the ionic scintillation generated by thermonuclear weapons. Some of these
error sources can also cause hard failures [1].

Traditionally, the Hamming code has been used for SEC in volatile memories. However, in many applications, an SEC-only code is considered unsatisfactory because it accepts all blocks received.
An SEC-DED code seems safer and is most often used in computer memories. Hence, extended Hamming (8,4) code, which is an SEC-DED, is preferred over Hamming (7,4) code (where the first
and second digits represent the size of the block (n) and the number of information bits (k) per block, respectively).

While using Hamming (72, 64) code, the ECC memory was organized in the form of 8 redundant bits (check bits) and 64 information bits. A memory module comprising nine 8-bit chips was used. A
word access of 72 bits with 8 bits for each chip takes place. A single word of 8 bits is spread on different chips. The advantage of this interleaving of bits is that if a few closed bits in the same chip
are corrupted due to any radiation effects, a few words will be subjected to single bit errors, which can be corrected. Today, the organization of ECC memories is often more complicated than, for
example, simply having 8 check bits and 64 information bits. Modern memories, especially the server memories, may have 16 or 32 information bytes (128 or 256 bits) checked as a single ECC
word. Because of the larger widths of word sizes, each DRAM chip may store 2, 3, or 4 bits in physically adjacent positions. Subsequently, ECC is done on alphabets of 4, 8, or 16 characters. As
the DRAM chips are usually organized in 8-, 16-, or 32-bit configurations, the memory module often provides more than enough bits to perform ECC. The extra bits can be used to perform some
other useful functions, for example 1 or 2 parity bits can be used with memory address to ensure the correct address to reach the memory, generated by CPU, etc. Hence, ECC may also be used
in nonmemory areas such as on buses.

Design of an ECC Decoder Based on Orthogonal Parity Checksums [4]

The hardware realization of Hamming codes can be carried out through pure combinational circuit. With the help of G (parity generator) and H (parity check) matrices, the design equations are
found. The other techniques or methods may involve sequential circuits or LFSR (linear feedback shift register), which may seem to be slow, but due to the availability of high speed clock and
components now, we may use such circuits. For example, a semiconductor memory with low-latency can easily accommodate such circuits, which can perform error correction between the two
accesses of the memories. In the following, we are presenting one such technique that is primarily related with the implementation of nonsystematic cyclic codes. The cyclic codes are the ones in
which every cyclic shift of a valid codeword produces another valid codeword.

This presents the simplified hardware on both encoding and decoding sides. The hardware realization of encoder merely contains an n-stage LFSR, which is used as a simple multiplier. The
decoder can be designed in various ways. One such design, based on orthogonal parity-check sums, is being presented here. The circuit has a total latency of “n” clock cycles. For the purpose of
simplicity and illustration, the design is carried out for a small value of “n,” but it can be extended for larger values of “n” as well.

For a cyclic code of length n = 2m-1, (m = 3 for n = 7, m = 4 for n = 15, and so on) nonzero elements of GF(2 m) form 2m-1 roots of +1. The following relation must hold:

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Let “k” be the degree of h(x), then the degree of g(x) is 2m-k-1. The other conclusions can be drawn as follows:

m
1. The number of rows in the H-matrix is 2 -k-1.

m
2. The number of rows in the G-matrix is 2 -k (in other words, the highest degree of polynomial in h(x)).

For example in a (15,8) cyclic code, the highest degree of polynomial in h(x) is 8, hence the highest degree of polynomial in g(x) is 7. The H-matrix will contain seven parity-check equations.

Similarly, the H-matrix for any given code length can be obtained. In Figure 1, the H-matrix for (7,4) cyclic code, which contains three parity-check equations, is shown.

Figure 1. H-matrix for (7,4) Cyclic Code

All the possible seven nonzero combinations of parity-check equations from the H-matrix in Figure 1 are shown in Table 1.

Table 1. Parity-Check Equations

Every term ri (where i = 0,1,…6) appears in exactly four different equations. According to the method, we have to select three parity-check equations in such a way that any particular r i must be
present in these equations. This r i determines the position of bit correction. The three selected equations are shown in Table 2.

Table 2. Three Selected Equations

The term r3 is common to these equations. The parity-check on r 3 is said to be orthogonal. Whenever the erroneous bit appears at position r 3, all three parity-check equations generate the odd
parity simultaneously. This scheme can be implemented in a manner where the output is taken out serially (Figure 2). In this implementation, the detection and correction are not carried out in the
same cycle.

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 Figure 2. An Alternate Implementation of Orthogonal Parity-Check Technique

The working principle is very simple. First, the 7 bits received are loaded in parallel in the shift-right register and are rotated for seven cycles. After complementation of seven cycles, the switch (sw)
is closed and the bit at position r 6 is fed to the 2 input XOR gate. If the received vector contains any erroneous bit, then it will be detected when it enters in r 3. The correction will be made three
cycles later. When the erroneous bit is in r3, it will cause “en” to be high. This will set d 1 flip-flop on the next cycle. The erroneous bit will simultaneously reach into r 4. Ultimately, when the high bit
appears in d3 flip-flop, the erroneous bit appears in r6, which is then complemented (corrected) by the XOR gate and is available at its output. The remaining 3 bits take three more cycles to output,
hence the total latency of this decoder is 13 cycles, in other words, 2n-1 cycles. Obviously this implementation is comparatively slower than the previous one, but presents an option to take the
output serially.

The selection of “rn” is very important for circuit simplification. If instead of r 3, we choose r6 to make the parity-check orthogonal on, we get not only further simplification in hardware design but also
a circuit that is more than twice as efficient. This implementation is shown in Figure 3.

Figure 3. A More Simplified Implementation of Orthogonal Parity-Check Technique

The three parity-check equations selected from Table 1 with r 6 in common are shown in Table 3.

Table 3. Parity-Check Equations with r6 in Common

The complete corrected output is available in “n-1” cycles serially and in “n” cycles in parallel. All the circuits drawn in this paper were created with NI Electronics Workbench Group software. In
figures 4 and 5, a portion of the circuit shown in Figure 3 is reproduced to show how we have used NI Electronics Workbench Group software to simulate and verify the performance of the given
ECC decoder circuit.

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 [+] Enlarge Image

Figure 4. Circuit Simulation Performed through NI Electronics Workbench Group Software

[+] Enlarge Image

Figure 5. Output on Logic Analyzer

Conclusion

An ideal error correcting code must have a high speed and simple decoder with minimum check bits. Unfortunately, speed and redundancy do not go together. Low redundancy usually implies the
requirement of a complex and slow decoder. The circuit presented in this paper provides the design simplicity and requires much less hardware than the equally as capable corresponding
Hamming circuit. It also provides an option of getting serial/parallel output. The corrected output serially is available in “n-1” cycles. It means if the circuit is working at 100 MHz, it will take 60 ns to
produce the corrected output serially and 70 ns to produce the same in parallel. Hence, for the memories having access times higher than 70 ns, one can use this method, instead of Hamming, to
obtain the added advantages.

Further, like in all other electronic design applications, NI Electronics Workbench Group software has greatly helped us to verify the ECC circuits and to demonstrate effectively to students. The
ECC circuits are frequently required to test and verify during the design phase for different data blocks containing erroneous bits at different positions. Such frequent testing and verification of the
technique is difficult to carry out through conventional methods and by making actual circuits. Therefore, NI Electronics Workbench Group software is an inevitable tool in the area of ECC.

References

[1] Wicker S.B. “Error Control Systems for Digital Communication and Storage,” Prentice- Hall, Inc., New Jersey, 2001.

[2] http://fujiwara-www.cs.titech.ac.jp/res/bitbytee.html#sec-ded-sbed, 2005.

[3] Lin, Shu, and Costello, Daniel J., Jr. “Error Control Coding: Fundamentals and Applications,” Prentice-Hall, Inc., New Jersey, 1983.

[4] Mukati, Altaf, “Fault Diagnosis and Testing of Digital Circuits with an introduction to Error Control Coding,” Higher Education Commission Pakistan, 2006

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