LABORATARY MANUAL OF

COMPUTER ORGANIZATION

II YEAR B.TECH II-SEM CSE(R-16)

CODE : CS406ES

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

CMR ENGINEERING COLLEGE

(approved by AICTE, New Delhi & Affiliated to JNTU, Hyderabad )

Kandlakoya (v), Medchal road, RR Dist
 List of Experiments

1. Implement Logic gates using NAND And NOR gates

2. Design of full adder using gates

3. Design and Implement the 4:1 MUX, 8:1 MUX using gates IC’S

4. Design and Implement a 3 to 8 decoder using gates

5. Design a 4 bit comparator using gates or IC’S

6. Design and implement a 4-bit shift Register using Flip-Flops

7. Design and implement a decade counter

STUDY OF LOGIC GATES AND UNIVERSAL GATES
IC Pin Diagrams:
 Experiment 1

AIM: To verify NAND and NOR as universal gates

Apparatus Required: IC 7420, Trainer kit, Connecting wires, patch cards.

REALIZATION OF BASIC GATE OPERATIONS USING NAND GATES:

1. AND Operation:
00
1 00
31
2 3
2

2. NOT Operation:
03
1
3
2

3. OR Operation:
03
1
3
2
03
1
3
2

03
1
3
2
4. XOR & XNOR Operation:

REALIZATION OF BASIC GATE OPERATIONS USING NOR GATE:

1. AND Operation: 02
2
1
3

02
2
1
3

02
2
1
3

2. NOT Operation:

02
2
1
3
3. OR Operation:

02
2 02
1 2
3 1
3

4. XNOR & XOR Operation:

PROCEDURE:

PART (A):

1. Supply connections are given at the corresponding pins of ICs.

2. Each IC is taken separately and the individual gates in each IC are tested by giving inputs
and the truth tables are verified.
3. Same procedure is repeated for all ICs.
PART (B):

1. Supply connections are given at the corresponding pins of ICs.

2. For realization of individual gates using NAND gates alone, the connections are made as
per the logic diagrams.
3. Inputs are given and the truth tables of individual gates are verified.
4. The same procedure is repeated for realization of individual gates using NOR gates.

PRECAUTIONS:

1. The power supply pins must be checked whether power is available at

those pins using test probes.

2. No loose connections should be there and care must be taken to avoid

shorting of pins.

RESULT:

The truth tables of individual gates are verified and their realizations using

NAND gates alone and NOR gates alone have been verified.

SAMPLE QUESTIONS:

1. If one of the inputs of an EX-OR gate is high, its output will be--------
(same as other input/inverse of other input).

2. To INHIBIT( or DISABLE) an AND gate one of its input is connected to logic level------(0/1).
3. To DISABLE a NOR gate one of its inputs needs to be connected
to logic level-------------(0/1)

4. The number of rows in a truth table of 4 variables are------------------.

5. A 3 input NOR gate is required to detect the simultaneous occurrence of all the inputs in the
LOW state. Its output is-----------------------------(active low /active-high).
6. The minimum number of bits required to distinguish 108 distinct objects is--------.
7. What is the difference between a positive logic system and negative logic system?
8. What are universal gates? Why that name?
9. Minimum number of NAND gates necessary to realize EX-OR gate using NAND gates only is ---
-----.
10. Minimum number of NOR gates necessary to realize EX-OR gate using NOR gates only is
 Experiment 2

Object: Design a Full adder using gates

Apparatus Required: IC 7408, 7432, 7486, Bread Board, Connecting wires.

Procedure:
1. For the verification of half adder the connection are made as per the logic diagaram.
2. Inputs are given and the functionality of half adder are verified
3. For the verification of Full Adder the connections are made as per the logic diagram.
4. Inputs are given and the functionality of the Full Adder are verified
PRECAUTIONS: -

1. Connection should be tight.

2. O/P should be finding sequentially.
3. IC’s should be handled carefully.

RESULT:- The operation of half adder,full adder has been verified.

 EXPERIMENT: 3

FUNCTION REALIZATION USING MULTIPLEXER

AIM: A) To verify the 8 to 1 multiplexer operation using MSI gates.

B) To implement a 4 bit odd parity checker circuit using multiplexer.

APPARATUS: Trainer kit, Connecting wires, patch cards.

S.NO. Component Type Quantity

1 8 to1 multiplexer IC 74151 1
2. Hex inverter IC 7404 1
3. Digital IC trainer - 1

BLOCK DIAGRAM: IC Pin description of 74HC151

Function table for 8x1 MUX:

Chip Enable(E) Selection lines Output

S2 S1 S0
1 x x x 0
0 0 0 0 D0
0 0 0 1 D1
0 0 1 0 D2
0 0 1 1 D3
0 1 0 0 D4
0 1 0 1 D5
0 1 1 0 D6
0 1 1 1 D7
PROCEDURE:

PART (A):

1. Suitable power supply connections and chip enable signals are given at the

Corresponding pins of the MUX IC.

2. To verify the operation of 74151 IC as multiplexer, input pins ( I0, I1,

I2,…..I7) are connected to 8 input toggle switches and the output pins

Z and Z′ are connected to output indicators.

3. The selection lines pins (S2, S1, S0) are connected to three input toggle

switches.

1. The selection lines are varied from binary 000 to 111 and we will observe the
data at the corresponding inputs ( 0 or 1) will find its way to the output.

PART (B):

1. First, identify the size of MUX needed for implementing the given circuit

using MUX.

2. Complete the procedure for implementing any Boolean function using MUX.

Three input variables of the function are connected to selection lines pins

And the fourth input variable is given as input to the MUX as per the table.

3. The corresponding inputs from the derived table are given to the MUX IC

and the output pins are connected to output indicators.

4. The 4 input variables are varied from 0000 to 1111 and the truth table for the

given circuit operation is verified.

PRECAUTIONS:

1. Suitable signals must be given to enable pins of IC in order to enable the

chip.

2. The order in which we are connecting the input variables to selection

pins must be proper.

RESULT:

The Muliplexer operation is verified

SAMPLE QUESTIONS:

1. What is a multiplexer? Why we call it as data selector?

2. How will you specify the size of a given MUX?
3. Give some practical applications of multiplexers.
4. Realize basic gates using a Multiplexer of suitable size.
5. Design a BCD – to- Gray code converter using Muliplexers.
6. How will you implement a multiplerxer with decoders?
7. Construct a 4x1 multiplexer from no. of 2x1 multiplexers only.
 EXPERIMENT NO: 4

FUNCTION REALIZATION USING DECODER

AIM: A) To verify the operation of binary to Octal decoder IC 74138 and realize
4 to 16 line decoder using 3 to 8 decoders
B) To implement a Full adder circuit using decoder and basic gates

APPARATUS:

S.NO. Component Type Quantity

1 3 to 8 line decoder IC 74138 2
2 Quad 2 input OR gates IC 7432 2
3. Hex inverter IC 7404 2
4. Digital IC trainer - 1

74138 3x8 Decoder Block diagram:

Expressions:
CIRCUIT DIAGRAM:

PROCEDURE:

PART (A):
1. Power supply connections are made at pins 8(GND) and 16(Vcc) of 74138 IC.
2. To enable the chip operation, the corresponding enable pins are given signals. E1′, E2′,
E3’ are connected to LOW, LOW and HIGH respectively.
3. To verify the operation of binary to Octal decoder, three input pins A2, A1, A0 are
connected to input toggle switches and eight outputs O0′, O1′, O2′,.. O7′, are connected to
output indicators and the truth table is verified.
4. To extend this 3 to 8 line decoder into a 4 to 16 line decoder, two separate 74138 ICs are
taken and connections are made as per the circuit diagram (i) and the truth table is
verified.

PRECAUTIONS:

2. The corresponding chip enable signals must be enabled for normal operation.
3. Care must be taken to ensure that there are no shorting of pins
4. It is always good practice to ensure the correct operation of individual gates which are used
as part of the circuit.

RESULT: The operation of 3 to 8 decoder is verified and it is extended as 4 to 16

Decoder and a full adder circuit is realized using 3 to 8 decoder.
SAMPLE QUESTIONS:

1. What is a decoder? How to specify its size?

2. What is a demultiplexer? How a decoder with enable input functions like demultiplexer?
3. Design a 2 to 4 line decoder with enable input using basic gates.
4. Is there any similarity between decoder and code converters?
5. Give some practical applications of decoder circuits?
6. A decoder with 64 output lines has -------------------data inputs.
7. What is the function of enable pin in any standard IC?
8. How many minterms a 3x8 decoder generates?
9. Show experimentally implementation of
(i). Half adder
(ii). Full subtractor circuit using 3x8 decoder and the necessary gates.
 EXPERIMENT NO: 5

DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

AIM: To design and implemt 4-bit magnitude comparator using IC 7485

Apparatus Required: IC 7485, 4-BIT Digital Comparator Trainer Kit, Patch Chords

IC Pin Description :

Truth Table
LOGIC DIAGRAM: 2 BIT MAGNITUDE COMPARATOR
PROCEDURE:

1) Connections are given as per circuit diagram

2) Logical inputs are given as per circuit diagram
3) Observe the output and verify the truth table

RESULT:

Thus the design and implementation of magnitude comparator were done

 EXPERIMENT NO: 6

SHIFT REGISTERS

AIM: A) To verify the operation of shift register (7490 IC).

APPARATUS: 8 Bit Shift Register Trainer Kit, IC 7474, Patch chords

Pin Description of IC 7474

PROCEDURE:

PART (A):

1. The function table for the 7474 shows the mode of operation of the register.

When the clear input goes to 0, the four flip-flops clear to 0 asynchronously,

That is, without the need of a clock. Synchronous operations are affected by

a positive transition of the clock. To load the input data, the PRE must be

equal to 0 and a positive clock-pulse transition must occur. To shift right,

the PRE must be equal to 1. The D inputs must be connected

together to form the serial input.

2. Make connections according to the pin assignment to the inputs and outputs

as shown in fig.

3. Vary the inputs and verify all the operations listed in the function table of the

7474 IC.

PRECAUTIONS:

1. While verifying the individual operations, corresponding inputs must

 be applied.

RESULT:

The shift register operations are verified using 74195 IC.

SAMPLE QUESTIONS:

1. Write some applications of shift registers.

2. What is a universal shift register?

3. Draw the timing waveforms for the 4- bit ring counter?

4. What is serial and parallel loading of register? How to convert serial data to parallel and parallel
data to serial? What type of register is used?

5. Write some commonly used shift register ICs?

6. How many no. of states a) a 5-bit ring counter b) a 5-bit Johnson counter will go

through?
 EXPERIMENT NO: 7

DESIGN OF ASYNCHRONOUS COUNTERS

AIM: To construct and test decade decimal BCD counter using 7490 IC

APPARATUS: 4-Bit Decade counter Trainer Kit, Patch chords, IC7490.

4- BIT DECADE COUNTER:

Pin description

State diagram of Decimal BCD COUNTER.

COUNT SEQUENCES:

MOD-10 COUNTER:

BLOCK DIAGRAM

PROCEDURE:

1 Connect the circuit diagram as shown in the figure.

2 Connect 1 hz clock to pin cpo
3 Connect the reset terminal (R1, R2) to high and set terminals (s1,s2) to zero and observe
the out put
4 Now connect set and reset inputs to zero and observe the output.
5 Record the counter states for each clock cycle.
PRECAUTIONS:

1. No pins must be left open. If we are not using particular pins in that

application, disable those pins.

2. Care has to be taken in identifying the LSB and MSBs.

2. Avoid loose connections and shorting of pins.

RESULT:

The 4- bit Asynchronous counter decade BCD counters constructed and their operation is verified.

SAMPLE QUESTIONS:

1. Draw the timing diagrams showing the relationship between clock and the four outputs of 4- bit
UP counter(Ripple)

2. What is the main classification of counters and define?

3. What do you mean by modulus of a counter?

4. How do you determine the maximum frequency range of a given n- bit counter?

5. How many flip flops are needed for a Mod-100 counter?

6. What is the difference between counters and registers?

7. State some commonly available asynchronous counter ICs?

8. What is the difference between edge triggered and level triggered circuits?

9. A counter counts no. of ---------- to the circuit.

10. Draw the logic diagram of 4-bit binary ripple down counter.

SAMPLE QUESTIONS:

1. What is the difference in operations of synchronous and Ripple counters?

2. The modulus of a 4- bit counter is-----------------.

3. The count of a 4- bit binary DOWN counter is 0000. When a clock pulse is applied its count
will be--------------.

4. The cascade of divide- by 5 counter followed by divide-by-2 counter is in state 0000. When a
clock pulse is applied, its state will be ----------------.

Assume negative edge triggered circuits.

5. State some commonly available synchronous counter ICs with their features?

6. State some applications of counters.

7. What is lock-out condition in counters? How to avoid it?

8. How will you ensure whether a counter is self- starting or not?

9. What do you mean by binary counters?

10. What do you mean by triggering?

Exercises in Micro Processor programming:
Write assembly language programs for the following using GNU Assembler.
1. Write assembly language programs to evaluate the expressions:
i) a = b + c – d * e
ii) z = x * y + w – v +u / k
a. Considering 8-bit, 16 bit and 32 bit binary numbers as b, c, d, e.
b. Considering 2 digit, 4 digit and 8 digit BCD numbers.
Take the input in consecutive memory locations and also Display the results by using
“int xx” of 8086. Validate program for the boundary conditions.

2. Write an ALP of 8086 to take N numbers as input. And do the following operations on
them.
a. Arrange in ascending and descending order.
3. Write an ALP of 8086 to take N numbers as input. And do the following operations on
them.
a. Find max and minimum
b. Find average
Considering 8-bit, 16 bit binary numbers and 2 digit, 4digit and 8 digit BCD numbers.
Display the results by using “int xx” of 8086. Validate program for the boundary
conditions.
4. Write an ALP of 8086 to take a string of as input (in ‘C’ format)and do the following
Operations on it.
a. Find the length
b. Find it is Palindrome or n.
Considering 8-bit, 16 bit binary numbers and 2 digit, 4digit and 8 digit BCD numbers.
Display the results by using “int xx” of 8086. Validate program for the boundary
conditions.
5. Write an ALP of 8086 to take a string of as input (in ‘C’ format) and do the following
Operations on it.
Find whether given string substring or not.
6. Write an ALP of 8086 to take a string of as input (in ‘C’ format) and do the following
Operations on it
a. Find the Armstrong number
b. Find the Fibonacci series for n numbers
Display the results by using “int xx” of 8086.
7. Write the ALP to implement the above operations as procedures and call from the main
procedure.
8. Write an ALP of 8086 to find the factorial of a given number as a Procedure and call from
a. the main program which display the result
 EXPERIMENT 1
ARTHIMATIC OPERATIONS
AIM: To Write assembly language programs to evaluate the expressions:
i) a = b + c – d * e
ii) z = x * y + w – v +u / k

TOOLS:
GNU Assembler
PROGRAM:
i) a=b+c-d*e
TITLE (.asm)

;this program
;last update:
INCLUDE masm16.inc
.data

.code
main PROC
mov ax,@data
mov ds,ax
mov ax,3333h
mov bx,2222h
ADD ax,bx
SUB ax,4321h
mov bx,03h
mul bx
call DumpRegs

exit
main ENDP
END main

ii) z = x * y + w – v +u / k

TITLE (.asm)

;this program
;last update:
INCLUDE masm16.inc
.data

.code
main PROC
mov ax,@data
mov ds,ax
mov ax,1234h
mov bx,5h
mul bx
ADD ax,01abh
SUB ax,111ah
mov cx,ax
mov ax,10h
mov bx,08h
div bx
mov bx,ax
mov ax,cx
add ax,bx
call DumpRegs

exit
main ENDP
END main
 EXPERIMENT 2
AIM : To write an ALP of 8086 to take N numbers as input. And do the following operations on
them.
a. Arrange in ascending and descending order.
TOOLS:
GNU Assembler
PROGRAM:
i)for assending order

title (.asm)

;this program
;last update:
include masm16.inc

.data
string1 db 88h,12h,56h,45h,36h

.code
main proc
mov ax,@data
mov ds,ax
mov ch,04h
up2: mov cl,04h
lea si,string1
up1: mov al,[si]
mov bl,[si+1]
cmp al,bl
jc down
mov dl,[si+1]
xchg [si],dl
mov [si+1],dl
down: inc si
dec cl
jnz up1
dec ch
jnz up2
mov al,[si]
mov ah,[si-1]
mov bl,[si-2]
mov bh,[si-3]
mov cl,[si-4]
call dumpregs
exit
main endp
end main

ii) for desending order

title (.asm)

;this program
;last update:
include masm16.inc
.data
string1 db 99h,12h,56h,45h,36h

.code
main proc
mov ax,@data
mov ds,ax
mov ch,04h
up2: mov cl,04h
lea si,string1
up1:mov al,[si]
mov bl,[si+1]
cmp al,bl
jnc down
mov dl,[si+1]
xchg [si],dl
mov [si+1],dl
down: inc si
dec cl
jnz up1
dec ch
jnz up2
mov al,[si]
mov ah,[si-1]
mov bl,[si-2]
mov bh,[si-3]
mov cl,[si-4]
call dumpregs
exit
main endp
end main
 EXPERIMENT 3
AIM: . To write an ALP of 8086 to take N numbers as input. And do the following operations on
them.
a. Find max and minimum
b. Find average
TOOLS: GNU Assembler
PROGRAM:
i) For maximum number

TITLE (.asm)

;this program
;last update:
INCLUDE masm16.inc

.data
STRING1 DB 08h,14h,05h,0Fh,09h

.code
main PROC
mov ax,@data
mov ds, ax
mov cx, 04h

mov bl, 00h

LEA SI, STRING1
up:
mov al, [SI]
cmp al, bl
jl nxt
mov bl, al
nxt:
inc si
dec cx
jnz up
call DumpRegs
exit
main ENDP
END main

ii) For minimum number

TITLE (.asm)

;this program
;last update:
INCLUDE masm16.inc

.data
STRING1 DB 08h,14h,05h,0Fh,09h

.code
main PROC
mov ax, @data
mov ds, ax
mov cx, 04h

mov bl, 79h

LEA SI, STRING1
up:
mov al, [SI]
cmp al, bl
jge nxt
mov bl, al
nxt:
inc si
dec cx
jnz up
call DumpRegs
exit
main ENDP
END main

iii) For average of N numbers

TITLE (.asm)

;this program
;last update:
INCLUDE masm16.inc
.data
A DB 1h,2h,3h,4h,5h,6h,10h,8h,9h,0ah
.code

main PROC
MOV AX,@data
MOV DS,AX
LEA BX,A
MOV CL,10
MOV AX,0000
L1:ADD AL,BYTE PTR[BX]
INC BX
DEC CL
CMP CL,00
JNZ L1
MOV BH,10
DIV BH
call DumpRegs
exit
main ENDP
END main
 EXPERIMENT 4
AIM : To write an ALP of 8086 to take a string of as input (in ‘C’ format)and do the following
Operations on it.
a. Find the length
b. Find it is Palindrome or n.
TOOLS: GNU Assembler
PROGRAM:
i) To find the length of given string

TITLE (.asm)

;this program
;last update:
INCLUDE masm16.inc

.DATA

STR DB ‘GANGADHAR$’
MSG1 DB 10,13,’THE STRING IN THE MEMORY IS : $’
MSG2 DB 10,13,’LENGTH OF THE STRING IS :- $’
LEN DB 0H

DISPLAY MACRO MSG

MOV AH,9
LEA DX,MSG
INT 21H
ENDM

.CODE
main PROC
MOV AX,@DATA
MOV DS,AX

DISPLAY MSG1

DISPLAY STR

LEA SI,STR
NEXT:
CMP [SI],’$’
JE DONE
INC LEN
INC SI
JMP NEXT
DONE:
DISPLAY MSG2

MOV AL,LEN
ADD AL,30H

MOV DL,AL
MOV AH,2
INT 21H

MOV AH,4CH
INT 21H

call DumpRegs
exit
main ENDP
END main

ii) To find given number is palindrome or not

TITLE (.asm)

;this program
;last update:
INCLUDE masm16.inc

.data

block1 db 'malayalam'
msg1 db "it is palindrome $"
msg2 db "it is not palindrome $"
pal db 00h

print macro msg

mov ah,09h
lea dx,msg
int 21h
int 3h

endm

.extra

block2 db 9 dup(?)

.code
main PROC
mov ax,@data
mov ds,ax
mov ax,extra
mov es,ax
lea si,block1
lea di,block2+8
mov cx,00009h
back: cld
lodsb
std
stosb
loop back
lea si,block1
lea di,block2
mov cx,0009h
cld
repz cmpsb
jnz skip
print msg1
skip: print msg2
call DumpRegs
exit
main ENDP
END main
 EXPERIMENT 5
AIM: To write an ALP of 8086 to find whether given string substring or not.
TOOLS: GNU Assembler
PROGRAM:

TITLE (.asm)

;this program
;last update:
INCLUDE masm16.inc

.DATA
STR DB ‘AXYBCSDEF$’
SUBSTR DB ‘BCS$’
LEN1 DB 0
LEN2 DB 0
MSG1 DB 10,13,’STRING IS : $’
MSG2 DB 10,13,’SUBSTRING IS : $’
MSG3 DB 10,13,’SUBSTRING IS FOUND AT POSITION : $’
POS DB -1
RTN DB ‘-1$’

DISPLAY MACRO MSG

MOV AH,9
LEA DX,MSG
INT 21H
ENDM

.CODE
main PROC

MOV AX,@DATA
MOV DS,AX

DISPLAY MSG1
DISPLAY STR
DISPLAY MSG2
DISPLAY SUBSTR

LEA SI,STR
NXT1:
CMP [SI],’$’
JE DONE1
INC LEN1
INC SI
JMP NXT1
DONE1:
LEA DI,SUBSTR
NXT2:
CMP [DI],’$’
JE DONE2
INC LEN2
INC DI
JMP NXT2
DONE2:
DISPLAY MSG3

LEA SI,STR
MOV AL,LEN1
SUB AL,LEN2
MOV CL,AL
MOV CH,0
FIRST:
INC POS
MOV AL,[SI]
CMP AL,SUBSTR[0]
JE CMPR
INC SI
LOOP FIRST

CMPR: INC SI
MOV AL,[SI]
CMP AL,SUBSTR[1]
JNE NOTEQUAL
INC SI
MOV AL,[SI]
CMP AL,SUBSTR[2]
JE EQUAL

NOTEQUAL:
MOV POS,-1
DISPLAY RTN
JMP EXIT

EQUAL:
MOV DL,POS
ADD DL,30H
MOV AH,2
INT 21H

EXIT: MOV AH,4CH

INT 21H

call DumpRegs
exit
main ENDP
END main
 EXPERIMENT 6
AIM: To write an ALP of 8086 to take a string of as input (in ‘C’ format) and do the following
Operations on it
Find the Fibonacci series for n numbers

TOOLS: GNU Assembler

PROGRAM :
i) Find Fibonacci series

TITLE (.asm)

;this program
;last update:
INCLUDE masm16.inc

.DATA
RES DB ?
CNT DB 0AH ; Initialize the counter for the no of Fibonacci No needed
.CODE
main PROC
MOV AX,@DATA
MOV DS,AX
LEA SI,RES
MOV CL,CNT ; Load the count value for CL for looping
MOV AX,00H ; Default No
MOV BX,01H ; Default No
;Fibonacci Part
L1:ADD AX,BX
DAA ; Used to Present the value in Decimal Form
MOV [SI],AX
MOV AX,BX
MOV BX,[SI]
INC SI
LOOP L1
call DumpRegs
exit
main ENDP
END main
 EXPERIMENT 8

AIM: To write an ALP of 8086 to find the factorial of a given number as a Procedure and call
from the main program which display the result
TOOLS: GNU Assembler
PROGRAM:

DATA SEGMENT

NUM DB ?

FACT DB 1H

RES DB 10 DUP ('$')

MSG1 DB "ENTER NUMBER : $"

MSG2 DB 10,13,"RESULT : $"

DATA ENDS

CODE SEGMENT

ASSUME DS:DATA,CS:CODE

START:

MOV AX,DATA

MOV DS,AX

LEA DX,MSG1

MOV AH,9

INT 21H

MOV AH,1

INT 21H

SUB AL,30H

MOV NUM,AL

MOV AH,0

MOV AL,FACT
MOV CH,0

MOV CL,NUM

LABEL1: MUL CL

LOOP LABEL1

LEA SI,RES

CALL HEX2DEC

LEA DX,MSG2

MOV AH,9

INT 21H

LEA DX,RES

MOV AH,9

INT 21H

MOV AH,4CH

INT 21H

CODE ENDS

HEX2DEC PROC NEAR

MOV CX,0

MOV BX,10

LOOP1: MOV DX,0

DIV BX

ADD DL,30H

PUSH DX

INC CX

CMP AX,9

JG LOOP1

ADD AL,30H

MOV [SI],AL
LOOP2: POP AX

INC SI

MOV [SI],AL

LOOP LOOP2

RET

HEX2DEC ENDP

END START