Using Intrinsic Nodes for Practical High Efficiency PA Design

V I

Matt Ozalas
Keysight Technologies
First, the End Result…

Class J Performance vs. Prediction...

Today’s Presentation

– Quickly design a first pass high efficiency power amplifier using intrinsic nodes.

– As with any design approach, there are limitations:

• Models
• Bandwidth
• Non-obvious effects

– Before getting started, I will briefly review the concept of efficient “waveform synthesis”
Background: “Efficient” Transistor Waveforms
Voltage Current
v (t )  V p sin(t )  Vdc

i (t )  I p sin(t   )  Idc
Vdc Idc
Pdc  Pdiss  Pgen

Pdc
Pdc

Dissipated Power (Pdiss)

Generated Power (Pgen)

Pgen Pgen
(Output out  
Efficiency)
Pgen  Pdiss Pdc
 Background: PA Modes of Operation: Class A
Large Signal Input Region Output Waveforms
Iout Large Signal Output Region
Iout Voltage
-1/RL
Current
Vin Voq
Voq, Ioq
Ioq
Viq, Ioq

Vout
Vin
Dissipated Power time

Waveforms pure tones RL

Max Efficiency: 50%
Background: PA Modes of Operation: Class AB
Large Signal Input Region Output Waveforms
Iout Large Signal Output Region
Iout Voltage
-1/RL
Current
Vin Voq

Voq, Ioq
Viq, Ioq Ioq

Vout
Vin
Dissipated Power time

Voltage Waveform pure tone Harmonics RL

Current Waveform: Rectified (short)

Max Efficiency: 50-78%

Background: PA Modes of Operation: Class B
Large Signal Input Region Output Waveforms
Iout Large Signal Output Region
Iout Voltage
-1/RL
Current
Vin Voq

Viq, Ioq Voq, Ioq Ioq

Vout
Vin
Dissipated Power time

Voltage Waveform pure tone Harmonics RL

Current Waveform: Half Rectified (short)

Max Efficiency: 78.5%

Background: PA Modes of Operation: Class J
Large Signal Input Region Output Waveforms
Iout Large Signal Output Region
Iout Voltage
-1/RL
Current
Vin Voq

Viq, Ioq Voq, Ioq Ioq

Vout
Vin
Dissipated Power time

XL
Voltage Waveform “Boosted” Harmonics
Current Waveform: Half Rectified 3+

Max Efficiency: 78.5%

Harmonics
SECOND
Background: PA Modes of Operation: Class E
Large Signal Input Region
Iout Large Signal Output Region
Iout Voltage

-1/RL
Current
Vin Voq

Viq, Ioq Voq, Ioq Ioq

Vout
Vin
Dissipated Power time

XL
Voltage Waveform “Boosted”
Harmonics
Current Waveform: Switched THIRD
Max Efficiency: 78.5% Harmonics
SECOND
Background: PA Modes of Operation: Class F
Large Signal Input Region Output Waveforms
Iout Large Signal Output Region
Iout Voltage
-1/RL
Current
Vin Voq

Viq, Ioq Voq, Ioq Ioq

Vout
Vin
Dissipated Power time

Voltage Waveform: Square EVEN RL ODD

Current Waveform: Half Rectified Harmonics Harmonics

Max Efficiency: 100%

 Background: Trigonometric Fourier Series

– Any periodic signal can be expressed as a sum of sinusoids


f (t )  a0   an cos(n t )  bn sin(n t )
n 1
Harmonic Terms
1“DC” Term
a0   f (t )dt
Partially rectified sinewave
T0 T0 2
a T0 
0
0 b1sinω0 t
f(t)

t t
2
0 T0
an 
t T0

T0
f (t ) * cos(n0t ) dt
t b2sin2ω0 t
2
bn 
T0 
T0
f (t ) * sin(n0t ) dt
t b3sin3ω0 t
Example: TFS Decomposition of Class E “Switching” Waveforms
Tip: How did you do that?

7 commas
Include this many harmonic
terms in the time domain
waveform (1DC)

(2DC+1fo)

(3DC+1fo+2fo) (2=DC1fo) (1DC)

Key Point: Waveform Expression by Harmonic Z’s

FFT
Access to intrinsic device nodes

G Rg Cgd Ld Rd D
Cgs
Reactive
Intrinsic Load Value
Node Cds
ro
Extrinsic
Ls Node

S
“Embedding” Extrinsic Waveforms
– Approximate the intrinsic waveforms based on the extrinsic waveforms…

Arbitrary 2 port network

“Obvious Example”

Embedded Waveforms

Blue=Intrinsic Node
Red=De-embedded Extrinsic Waveforms
“Design Process: Big Picture

– Efficient PA: Idealized V/I waveforms at the internal current generator of the transistor

– Based on the background slides:

• Can mathematically generate and decompose voltage / current waveforms
• Can derive harmonic impedances of those waveforms
• Can access the intrinsic current generator node of a device model

– Therefore, we can synthesize a mathematically generated waveform inside a real device

• Leads to a new methodology for fast, efficient power amplifier design
Design Process
Obtain closed form expression for
Voltage and Current Waveforms

 0 ,  
V (t )  
Vos  V pk * cos       I dct ,   
 I pk * sin(   )  I dc ,   
I (t )  
 0 ,  

Class E Voltage and Current Waveforms

Design Process

1fo

Derive
3fo Equivalent
Harmonic
2fo Impedances

Class E Voltage and Current Waveforms

Design Process Device model with
intrinsic node access

(Parasitics)

Current

1fo + Gen

Derive
3fo Equivalent
Harmonic
2fo Impedances

Class E Voltage and Current Waveforms

Design Process Device model with
intrinsic node access

(Parasitics)

Current

1fo + Gen Tunable

Harmonic Load

Derive
3fo Equivalent
Harmonic
2fo Impedances

Class E Voltage and Current Waveforms

Design Process Device model with
intrinsic node access

(Parasitics)

Current

1fo + Gen Tunable

Harmonic Load

Derive
3fo Equivalent
Harmonic Zint Zext
2fo Impedances 2fo 2fo
Class E Voltage and Current Waveforms

Sweep external load impedance and

observe the resulting intrinsic impedance…
Design Process Device model with
intrinsic node access
Sweep External
(Parasitics) Load Impedance
for each harmonic
Current

1fo + Gen Tunable

Harmonic Load

Derive
3fo Equivalent
Harmonic Zint Zext
2fo Impedances 2fo 2fo
Class E Voltage and Current Waveforms Class E
Target
Sweep external load impedance and
observe the resulting intrinsic impedance…

To find the external load that provides

the target impedance internally
Design Process Device model with
intrinsic node access
Sweep External
(Parasitics) Load Impedance
for each harmonic
Current

1fo + Gen Tunable

Harmonic Load

Derive
3fo Equivalent
Harmonic Zint Zext
2fo Impedances 2fo 2fo
Class E Voltage and Current Waveforms Class E
Target

…repeat for each relevant harmonic

Freq Target Intrinsic Extrinsic
1fo 20+j*10 19.7+j*9.9 5+j*15.5
2fo 0-j*40 0-j*40.2 0+j*12
3fo 0-j*30 0-j*29.9 0-j*15
Design Process Device model with
intrinsic node access
Sweep External
(Parasitics) Load Impedance
for each harmonic
Current

1fo + Gen Tunable

Harmonic Load

Derive
3fo Equivalent
Harmonic Zint Zext
2fo Impedances 2fo 2fo
Class E
Target

Freq Target Intrinsic Extrinsic

1fo 20+j*10 19.7+j*9.9 5+j*15.5
2fo 0-j*40 0-j*40.2 0+j*12
Design a matching network to 3fo 0-j*30 0-j*29.9 0-j*15
present the extrinsic harmonic
loads to the device
Design Process Device model with
intrinsic node access

(Parasitics)

Current

1fo + Gen

Connect the matching

Derive network to the device output
3fo Equivalent
Harmonic
2fo Impedances

Design a matching network to

present the extrinsic harmonic
loads to the device
Design Process Device model with
intrinsic node access

(Parasitics)

Current

1fo + Gen

Derive
3fo Equivalent
Harmonic
2fo Impedances

Which will present the derived harmonic

impedances to the intrinsic device

Design a matching network to

present the extrinsic harmonic
loads to the device
Design Process Class E PA using Wolfspeed Device

1fo

Derive
3fo Equivalent
Harmonic
Resulting in a physical design which
2fo Impedances achieves close to the ideal waveforms!
Class E Voltage and Current Waveforms
Design Process: Summary

1. Create target waveforms

2. Map ideal intrinsic to extrinsic impedance

• Repeat for all relevant harmonics

3. Verify extrinsic impedances vs. target intrinsic waveforms

4. Create matching network based on extrinsic impedance

5. Verify performance of device + matching network

Design Goals

– Design a Class J Amplifier

• >20 W output power at 1GHz, maximize PAE.
• Use any packaged Qorvo Device, with convenient matching topology.
• https://www.qorvo.com/design-hub/design-tools/modelithics-qorvo-gan-library
• https://www.modelithics.com/mvp/qorvo
Design Process: Summary

1. Create target waveforms

• Goal: Generate ideal waveforms somehow based on device performance

• Different approaches for different classes

Class J and Continuous Modes

VA / B (t )  V pk * sin   Vdc
V pk  Vdc
VA / B (t )  Vdc (1  sin  ) sin ϴ
Vpk
Vdc

Vpk
Class J and Continuous Modes

Vj(t)
VA / B (t )  V pk * sin   Vdc
V pk  Vdc
VA / B (t )  Vdc (1  sin  ) sin ϴ

VJ (t )  VA / B (t ) * (1   cos  )
 Vdc * 1  sin   cos   sin  cos  

sin  cos  
1
sin(2 )  sin 0
2
Class J and Continuous Modes

Vj(t)
VA / B (t )  V pk * sin   Vdc
V pk  Vdc 1fo
VA / B (t )  Vdc (1  sin  ) sin ϴ

2fo
VJ (t )  VA / B (t ) * (1   cos  )
 Vdc * 1  sin   cos   sin  cos  

sin  cos  
1
sin(2 )  sin 0
2
Class J and Continuous Modes

α=1 α=-1
Vj(t)
VA / B (t )  V pk * sin   Vdc
V pk  Vdc
VA / B (t )  Vdc (1  sin  )

VJ (t )  VA / B (t ) * (1   cos  )
 Vdc * 1  sin   cos   sin  cos  

sin  cos  
1
sin(2 )  sin 0
2
Class J and Continuous Modes

α=1 α=-1
Vj(t)
VA / B (t )  V pk * sin   Vdc
V pk  Vdc
VA / B (t )  Vdc (1  sin  )

VJ (t )  VA / B (t ) * (1   cos  )
 Vdc * 1  sin   cos   sin  cos  

sin  cos  
1
sin(2 )  sin 0
2
Class J and Continuous Modes

α=1 α=-1
Vj(t)
VA / B (t )  V pk * sin   Vdc
V pk  Vdc
VA / B (t )  Vdc (1  sin  )

VJ (t )  VA / B (t ) * (1   cos  )
 Vdc * 1  sin   cos   sin  cos  

sin  cos  
1
sin(2 )  sin 0
2

Each voltage waveform, when combined with the

baseline current waveform, results in the exact
same overall power and efficiency
Waveform Generation based on DCIV
– The J mode is based on the B mode – which can be derived from a loadline
Are DC Curves Sufficient for this Approximation?
– For GaN devices biased well below breakdown with an efficient loadline, typically ‘yes
• An important part of this design process is to continuously verify that the mode will work.

“Fan” diagram showing knee walkout and thermal droop for Wolfspeed CGH60030D_r6 vs. DCIV curve

At Recommended Bias: 28V At Very High Bias (>Vbr/2): 64V

High Frequency signal

encounters knee walkout at
high voltage bias conditions
High Frequency signal does
not encounter thermal droop
Generating Fan Diagrams in ADS

Capture resistive load values Table read and present to device

Device Selection : Qorvo GaN Library, Modelithics

– Select T2G6003028_FS (30W, 28V, 6 GHz)

“Max Efficiency Loadline” “Max Power Loadline”

~ 18.4W, 71% ~ 29.5 W, 58%
Loadline selection
Design Process: Summary

1. Create target waveforms

2. Map ideal intrinsic to extrinsic impedance

• Repeat for all relevant harmonics
The equation based load
– The equation based load component is crucial to performing this simulation

Create an indexed list of harmonic impedances.

Index the list based on simulation frequency

2f0
1f0 Important Note: When running HB simulations, use at
least as many tones as harmonics you want to control!
3f0

4f0
 Extrinsic 1fo Load Sweep

Start by Sweeping the Fundamental External Load

Set Bias to
Deep A/B
XL_ext
Set pin around
compression RL_ext
(roughly)

Short external Intrinsic Response to 1fo sweep

harmonics and sweep
fundamental
Target ZL
(…monitor the intrinsic
node response)

XL_int
RL_int
 Extrinsic 2fo Load Sweep

Next, Sweep the 2fo External Load

ZL1fo_ext
Set bias and
input pwr around
compression
(roughly)

ZL2fo_ext

Set Fundamental Intrinsic Response to 2fo sweep

Sweep 2fo

ZL1fo_int

Cannot hit the target ZL for 2fo?! ZL2fo_int

Target ZL2fo
Max Frequency: T2G6003028_FS 1 MHz ZL2f0int ZL2f0ext

Sweep can hit target

1 GHz

Sweep can hit some

targets, but not this one
(Adjust Pin and ZL1f0 vs. freq for fair comparison)

Series
If your device cannot hit the 5 GHz resonance

target, this is a problem…

Sweep can only meet

very limited targets
(shorts)
Tip: Finding the Maximum Frequency of Operation
– Each high efficiency mode requires specific reactive harmonic terminations

1. Sweep external reactance at high VSWR,

2. Observe resulting intrinsic reactance
Sweep
3. At low frequencies, intrinsic node will exhibit high VSWR … external
4. At mid frequencies, intrinsic node will “De-Q” …
Z
5. At high frequencies, intrinsic will stay semi-constant, with resonance

low freq
Observe
Simple LC network does this too Pull external
internal 2fo
2fo with high
mid freq
VSWR

Series
Resonance
high freq

REQUIRED
Class J
2f0 term
Device Selection: Start over
– Class J mode for the T2G6003028_FS at 1 GHz not possible.

– Don’t waste time trying to design

– Let’s try another device…

Design Process: Summary

1. Create target waveforms

2. Map ideal intrinsic to extrinsic impedance

• Repeat for all relevant harmonics
Back to Step 1: Device QPD1015
– Let’s evaluate a different device, QPD1015 (65W, 50V, 3.7 GHz), for the same Class J mode

“Max Efficiency Loadline” “Max Power Loadline”

~ 25.8W, 77% ~ 59 W, 72%
vs. 18.4W, 71% for other device vs. 29.5 W, 58% for other device
Max Frequency: QPD_1015 1 MHz ZL2f0int ZL2f0ext
(since 2f0 this is
Apply max actually at 2MHz)
PAE 1fo load
(roughly)
Set pin around
compression
(roughly) 1 GHz

(Adjust Pin and ZL1f0 vs. freq)

At 1GHz, hitting the target implied by the

max efficiency loadline is not quite possible..

2 GHz
QPD_1015: Adjust the Class J loadline
– By raising the loadline, we can lower the reactive part of the load
1 GHz external 2fo load
sweep, intrinsic response
Max efficiency loadline Adjusted mid-power/eff loadline

At 1GHz 2fo, now

possible to realize
Class J mode
Design Process: Summary

1. Create target waveforms

2. Map ideal intrinsic to extrinsic impedance

• Repeat for all relevant harmonics
 Extrinsic 1fo Load Sweep
QPD_1015: Sweep Fundamental ZLext

In practice, need to XL_ext

iterate Pin / ZL until
compression at target RL_ext
ZL is reached

Short all
harmonics

Intrinsic Response to 1fo sweep

Target ZL

ZL changes slightly with Pin

Due to nonlinear parasitics
XL_int
Internal load External load RL_int
27.4+j*28.5 5+j*15.5
 Extrinsic 2fo Load Sweep

Set ZL1fo, Sweep ZL2fo…

Set fundamental

ZL2fo_ext

Intrinsic Response to 2fo sweep

Sweep 2fo load,

short higher harmonics ZL2fo_int

Internal 2fo load External 2fo load

-j*32 j*24

Target ZL2fo
 Extrinsic 3fo Load Sweep

Set ZL1fo, ZL2fo, Sweep ZL2fo

Set
fundamental,2fo

ZL3fo_ext

Intrinsic Response to 3fo sweep

Sweep 3fo load,

short higher harmonics ZL3fo_int

Internal 3fo load External 3fo load Target ZL3fo

j*0 -j*14
Tip: Sequential tuning, Nonlinear Parasitics
– When the second harmonic was changed, this fundamentally changes the behavior of the amplifier.

– The 2fo harmonic “boost” increases odd harmonic generation in nonlinear parasitics
• Parasitics can become unintended “sources” of harmonic energy

Gain with 1fo

Gain with 1fo and 2fo

3fo swept with 1fo load in place

3fo swept with 1fo and 2fo load in place
Step 2: End result…
Derived Class J Loads
A “recipe” to make a specific Class J waveform
Harmonic Intrinsic Target External Load
1 27.4+j*28.5 5+j*15.9
2 0-j*32 0+j*24.5
3 0 0-j*14
4 0 0-j*25
5 0 0-j*61
… … …
Design Process: Summary

1. Create target waveforms

2. Map ideal intrinsic to extrinsic impedance

• Repeat for all relevant harmonics

3. Verify extrinsic impedances vs. target intrinsic waveforms

Iterative nature of this process
Constant tuning, adjustment, and re-evaluation is an important part of the design process

Derive targets Set Pin and Set 1fo load Set 2fo load Set 3fo up to Validate internal
Bias nfo load… waveforms*

*This is step 3
Retune 1fo after setting all harmonics
Step 3: Present Derived Load
Increase HB Order
(Intrinsic Node)

Sweep
Pin

NL Parasitics
Evaluate Waveforms vs. Ideal

(@ Pin = 31)
Agreement limited by:
-- # harmonics
-- Nonlinearity
Tip: Check the extrinsic node too!
– Pext, nd much lower than expected ?!

-20% nd!
Design Process: Summary

1. Create target waveforms

2. Map ideal intrinsic to extrinsic impedance

• Repeat for all relevant harmonics

3. Verify extrinsic impedances vs. target intrinsic waveforms

When in Doubt: Start Over!
– Will a less reactive mode will better facilitate external power transfer?
Steps 2-3 with Alpha = 0.5…
Adjust first 5 harmonics
Back off
bias / pin
slightly

POWER (WATTS)
Alpha Intrinsic Extrinsic
0.5 44.2 40
1 41.1 30.5 Setting Alpha=0.5 allows
more power to be sent to
DRAIN EFFICIENCY (%) the external load, rather
Alpha Intrinsic Extrinsic than reflecting through Cgd
0.5 75.7 68.6
1 74.8 55.4
Solid = Inside Device
Dotted = At package pin
Design Process: Summary

1. Create target waveforms

2. Map ideal intrinsic to extrinsic impedance

• Repeat for all relevant harmonics

3. Verify extrinsic impedances vs. target intrinsic waveforms

4. Create matching network based on extrinsic impedance

Step 4: Convert the ideal load to a Physical Network Ideal load

The waveforms should match if loads are equal…

Desired Matching Network

(Same as ideal load)

Matching Network: Synthesize or Tune Existing

– Synthesis is non standard but some literature:

• A Complete Class of Harmonic Matching Networks: Synthesis and Application. Giannini, Scucchia, IEEE MTT 2009 .

Y4 Y3 Y2 Y1
Ɵ4 Ɵ3 Ɵ2 Ɵ1

o/s o/s

– Tuning an existing network is straightforward but limited

• Lots of networks are out there…
- Switchmode RF and Microwave Power Amplifiers (Grebennikov)
• Using an existing, well defined topology is often the best practical choice.
Matching Network Approach: Adjust an Existing App Board

– Process: start with Qorvo Application board, adjust to realize mode of operation…
• I simply downloaded the gerber files and re-created the schematic based on this

https://www.qorvo.com/products/p/QPD1015#documents
1 GHz Baseline in ADS, from Qorvo App Board

Gerber imported into ADS.

Mstrip and SMD values are
approximate

I used this to create a Tline based schematic

Here’s the imported board…

Tline based model matches Mode is already Class FJ

reported performance pretty well
Setting up the Optimization
Ideal load harmonic impedances  targets for optimization

Small Signal
Simulation(s)

Initial Condition X=Targets

O=Actual

Optimizer will adjust circuit

values to match the
1fo
impedance to the target 2fo
3fo
4fo
5fo
Optimize the output board + capacitors…
The following components were part of this optimization

Tline lengths (within reasonable physical limits)

Cap values (within reasonable SMD limits)
Optimization Results (Random)
Difficulty matching 2fo
This did not meet the target goals!

1fo
2fo X=Target, O=Actual
3fo
4fo
5fo
…and 5fo

Two choices:
(1) Change match topology
(2) Change target impedances
Design Process: Summary

1. Create target waveforms

2. Map ideal intrinsic to extrinsic impedance

• Repeat for all relevant harmonics

3. Verify extrinsic impedances vs. target intrinsic waveforms

4. Create matching network based on extrinsic impedance

Steps 1-3: Inverse Class J (Alpha=-0.5):

1 Intrinsic Loads required 2 Extrinsic Loads required 3 Waveform Verification

Intrinsic and Extrinsic P, nd

Solid = Inside Device

Dotted = At package pin
Step 4: Optimize the Matching Network for Inverse Class J
– With the new targets, optimization easily meets goals (except 5fo)
• Random: 20k runs; Gradient: “Fine Tune”; Discrete: Real Values

Random  Gradient  Discrete

Discrete
Design Process: Summary

1. Create target waveforms

2. Map ideal intrinsic to extrinsic impedance

• Repeat for all relevant harmonics

3. Verify extrinsic impedances vs. target intrinsic waveforms

4. Create matching network based on extrinsic impedance

5. Verify performance of device + matching network

Inverse Class J PA, Qorvo App Board
– Results with matching network agree well with initial prediction

Class J Performance at Intrinsic Node vs. Prediction

Updated Output Matching Network for Inverse Class J Mode

Originally,
835 mil

Originally, Originally, Originally, Originally, Originally,

428 mil 345 mil both 0.4 pF 599 mil 56 pF

Originally,
340 mil
Originally,
both 2.7 pF
Overall Amplifier Performance

Pgain
PAE
Tip: Broadbanding is an Output Matching Challenge
– Simply repeat the process across your band
(…or use traditional contour based techniques)
External loads for Class J,
Alpha=-0.5, from 0.8 to 1.2 GHz

800M

1.2G
Summary of Design Technique
– Realized close to ideal waveforms in a real device.
• Challenge:
- Before: data collection and analysis
- After: device and high efficiency mode selection, and network design

– Iterative: at each step, key is to verify performance vs. ideal!

– Why Class J?

– Class of Operation: applying a “coat” to the device.

Summary of Design Technique
– Realized close to ideal waveforms in a real device.
• Challenge:
- Before: data collection and analysis
- After: device and high efficiency mode selection, and network design

– Iterative: at each step, key is to verify performance vs. ideal!

– Why Class J? Good Question: What about Class E?

– Class of Operation: applying a “coat” to the device.

Bonus: Class E Design using the same approach!
– In the following slides, I will present a very brief overview of how I implemented a
Class E design on the exact same device with the exact same approach…

– Results were similarly well matched!

Step 1: Waveform Synthesis using Class E Design Equations
Step 2: Harmonic Load Synthesis

1fo
2fo
3fo
4fo
Step 3: Waveform Verification
Step 4: Physical Matching Network Design
Step 5: Full PA Performance (vs. prediction)

Overall PAE ~6% better than Class J baseline

Closing Comments
– Access to intrinsic nodes changes the way design can be performed
• More models and resources are becoming available !

– The design approach allows you to:

• Create ideal waveforms based on device characteristics
• Design a load to generate these waveforms inside the device
• Quickly design a matching network to match the ideal load’s performance
• Try lots of different modes and approaches to understand what works best

– Approach is general, these techniques can be applied to almost any mode or topology
For more information…

– PA videos are here:

www.keysight.com/find/eesof-how-to-videos

– Workspace and slides are here:

http://edadocs.software.keysight.com/display/eesofkcads/
Power+amplifier+design+technique+using+intrinsic+nodes