AUTOMATIC BAUDRATE GENERATOR

USING VLSI
(ABG)

PROJECT REPORT
Submitted By
S. MEENU (A1306016)
M. PRAVEENA MEENA KUMARI (A1306019)

Under the guidance of

MRS. S. PREMALATHA M.E,

In partial fulfillment of the requirements for the award of the degree of

Bachelor of Engineering In

ELECTRONICS AND COMMUNICATION

OF
MADURAI KAMARAJ UNIVERSITY

2003-2004

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

SETHU INSTITUTE OF TECHNOLOGY
PULLOOR, KARIAPATTI.

SETHU INSTITUTE OF TECHNOLOGY

 PULLOOR, KARIAPATTI – 626 106.

ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE

THIS IS TO CERTIFY THAT THE CONTENTS OF THIS PROJECT

REPORT TITLED AUTOMATIC BAUDRATE GENERATOR
U S I N G V L S I IS THE BONAFIDE WORK DONE BY S. MEENU(A1306016) &
M.PRAVEENA MEENA KUMARI(A1306019) OF ELECTRONICS AND
COMMUNICATION ENGINEERING, DURING THE YEAR 2003-2004.

PROJECT GUIDE HEAD OF THE DEPT

SUBMITTED FOR THE UNIVERSITY EXAMINATION HELD

ON_______

INTERNAL EXAMINER EXTERNAL EXAMINER

C O M PA N Y P R O F I L E
 Chip Quest is an education and R&D division rendering professional
services. Recently the company etched its future plans with the distinctive focus by
implementing ITS ladder model.

CEEP-Continuous Engineering Education Program is designed with

focus on domain education to meet industry expectations better than never before. They
are here to excel in the area of Electronics System Design and Development. Their
education is to help the student community to gain the perspective the time to market,
reducing the cost, increase productivity, and reduce the space occupied. Research and
Development focus is designed to cater the exploratory innovations to small and medium
scale technology units, manufacturing units, or public sector companies. We with their
expertise and experience to study the requirements suggest efficient and least cost
alternative to the process industries and engage ourselves in new product development.

VISION

Chip Quest has the vision transcend time with timeless services
by bringing the most advanced knowledge of high-end technology, a fierce
dedication to client satisfaction and a tradition of aspiring to that special
touch of genius.

Chip Quest has also got a distinctive focus to deliver the best of
technology services offering solutions to help our clients stay competitively ahead.

MISSION
ChipQuest has the missionary zeal of serving the students
community that is an insurmountable resource for the industry. The super
 value education on the advanced technologies is to act as incubators for new
product development and process re - engineering.

BUSINESS MODEL
Our “Ladder” Business model:

ChipQuest operate with the ITS – Industry, Technology, Services model,

we operate with the advanced electronics oriented to specific industry domains with the
professional services.

Research &
Automotives Development
S
VLSI E
Consumer
Electronics
I R Onsite
Consultancy
V
N I
Micro Electronics C Turn Key
Projects
D Embedded E
S
Telecommunication U OFDC

S
Networking
T Networking Domain
Education

Embedded Resource Program (ERP)

CEEP has a professional approach towards this program offering three

distinctive advantages. ChipQuest delivers a unique phenomenon called as “Domain
Education” by providing exposures to various technologies and in different computing
platforms and architectures.

The training is rendered on three different platforms, UNIX, Linux and

Windows that makes the candidates more versatile.

To commensurate the education, real time project experience is given to

the candidates. The complete schedule is divided in to techno-modules and given in an
interactive style.

ACKNOWLEDGEMENT

I take this opportunity to express our gratitude to Mr.S.Mohamed Jaleel

B.Sc., B.L, Correspondent, Sethu Institute Of Technology, Madurai Kamaraj University
for permitting us to do this project.
 I am thankful to Dr.Elango, B.E., M.Sc., (Engg)., Ph.D., Principal, Sethu
Institute Of Technology, Madurai Kamaraj University for facilitating this undertaking in
every possible way.

I express our profound thanks to our beloved Head of the Department of

Electronics and Communication Engineering, Mrs.Helina Rajini Suresh M.E., for her
valuable attention to us.

I sincerely thank Mrs. S. Premalatha M.E, Sethu Institute Of Technology

for her valuable guidance and keen interest, which motivates me all along the period.

I am really thankful to Mr.M. Vigneswaran M.C.A. who gave me

valuable guidance and timely support to steering this project a success.

I would also like to thank all our staff members for their kind
cooperation during this project and for providing us with the proficient and professional
resources for the project.

I would like to use this opportunity to thank my parents and family

members without whom nothing would have been possible.

Finally I would like to thank all of our friends who came with thriving
ideas regarding the project and helped me in all possible ways to make this project a
complete and successful one.

SYNOPSIS
 A network is a well – defined collection of Communication

service. It is a controllable structure that ties together systems and

components. Communication networks are used to draw together corporate

information service. The baud rate is a measure of the number of symbols

(characters) transmitted per unit of time. Each symbol will normally consist

of a number of bits, so the baud rate will only be the same as the bit rate

when there is one bit per symbol. Automatic baudrate is a state-machine

driven core that measures transition intervals in a particular character

arriving via rs232 transmission (i.e. PC serial port.).This module allows for

RS232 serial communications (UART) to automatically synthesize a BAUD

rate to match incoming serial data, regardless of the FPGA clock rate. It

works by measuring the speed of the incoming characters and producing its

own clock to match. It is coded in VHDL language and simulated in

Modelsim. It is also synthesized the coding using LeonardoSpectrum.

CONTENTS
S.NO CONTENTS PAGE. NO

1. VLSI 01
2. VHDL 04

3. Software Tools 07

3.1 Leonardospectrum 08
3.2 Modelsim 13

4. About the Project

4.1 Introduction 14
4.2 Baudrate in Communication 15
4.3 Purpose 16
4.4 Features 17
4.5 Working 18
4.6 Algorithm 24
4.7 Operation 30
4.8 Applications 47
4.9 Extent of the Project 49
4.10 Conclusion 50

5. Synthesis 51

6. Simulation 58

7. Appendix 71

8. Bibliography 78
 ABOUT VLSI

Digital circuit design has evolved rapidly over the last 25 years.

The earliest digital circuits were designed with vaccum tubes and transistors.

Integrated circuits were then invented where logic gates were placed on a

single chip .The first integrated circuit ( IC ) chips were SSI (small scale

integration) chips where the gate count was very small. As technologies

became sophisticated, designers were able to place circuits with hundreds of

gates on a chip. These chips were called MSI (medium scale integration)

chips. With thee advent of LSI (large scale integration), designers could put

thousands of gates on a single chip. At this point, design processes started

getting very complicated, and designers felt the need to automate these

processes. Computer Aided Design (CAD) techniques began to evolve. Chip

designers began to use circuit and logic simulation techniques to verify the

functionality of building blocks of the order of about 100 transistors. The

circuits were still tested on the breadboard, and the layout was done on paper

or by hand on a graphic computer terminal.

 With the advent of VLSI (very large scale integration)

technology, designers could design single chips with more than 100,000

transistors. Because of the complexity of these circuits, it was not possible to

verify these circuits on a breadboard. Computer_aided techniques became

critical for verification and design of VLSI digital circuits. Computer

programs to do automatic placement and routing of circuit layout also

became popular. The designers were now building gate-level digital circuits

manually on graphic terminals. They would build small building blocks and

then derive higher-level blocks from them. This process would continue

until they had built the top-level block. Logic simulators came into existence

to verify the functionality of these circuits before they were fabricated on a

chip.
VLSI - AN OVERVIEW

VLSI is an acronym that stands for very large scale integration.

This engineering field deals with the never-ending quest to create electronic

circuits that are physically small yet contain massive amounts of computing

power.

Gordon Moore made is famous observation in 1965,just four

years after the first planar integrated circuit was discovered. Moore’s law

states that “Number of transistors per integrated circuits would double every

11118 months”.

He forecast that this trend would continue through

1975.Though Intel’s technology. Moore’s Law has been maintained for far

longer and still holds true as we enter the new century. The mission of

Intel’s technology development team is to continue to break down barriers to

Moore’s law.
 VHDL
The letters VHDL stand for the VHSIC (Very High Speed

Integrated Circuit) Hardware Description Language. VHDL is a language for

describing the behaviour and structure of electronic circuits, and is an IEEE

standard (1076). VHDL is used to simulate the functionality of digital

electronic circuits at levels of abstraction ranging from pure behaviour down

to gate level, and is also used to synthesize (i.e. automatically generate) gate

level descriptions from more abstract (Register Transfer Level) descriptions.

VHDL is commonly used to support the high level design (or language

based design) process, in which an electronic design is verified by means of

thorough simulation at a high level of abstraction before proceeding to

detailed design using automatic synthesis tools.

VHDL became an IEEE standard in 1987, and this version of

the language has been widely used in the electronics industry and academia.

The standard was revised in 1993 to include a number of significant

improvements. The Language In this section as in the rest of the guide,

words given in Capitalized Italics are technical terms whose definitions may

be found in the main body of this guide.

 An hierarchical portion of a hardware design is described in

VHDL by an Entity together with an Architecture. The Entity defines the

interface to the block of hardware (i.e. the inputs and outputs), whilst the

Architecture defines its internal structure or behaviour. An Entity may

possess several alternative Architectures. Hierarchy is defined by means of

Components, which are analogous to chip sockets. A Component is

Instantiated within Architecture to represent a copy of a lower level

hierarchical block. The association between the Instance of the Component

and the lower level Entity and Architecture is only made when the complete

design hierarchy is assembled before simulation or synthesis (analogous to

plugging a chip into a chip socket on a printed circuit board).

The selection of which Entity and Architecture to use for each

Component is made in the Configuration, which is like a parts list for the

design hierarchy. The structure of an electronic circuit is described by

making Instances of Components within Architecture, and connecting the

Instances together using Signals. A Signal represents an electrical

connection, a wire or a bus. A Port Map is used to connect Signals to the

Ports of a Component Instantiation, where a Port represents a pin. Each

Signal has a Type, as does every value in VHDL. The Type defines both a
set of values and the set of operations that can be performed on those values.

A Type is often defined in a package, which is a piece of VHDL containing

definitions, which are common to several Entities, Architectures,

Configurations or other Packages.

Individual wires are often represented as Signals of type

Std_logic, which are defined in the package Std_logic_1164, another IEEE

standard. The behaviour of an electronic circuit is described using Processes

(which represent the leaves in the hierarchy tree of the design). Each Process

executes concurrently with respect to all other Processes, but the statements

inside a process execute in sequential order and are in many ways similar to

the statements in a software programming language. A Process can be

decomposed into named Procedures and Functions, which can be given

parameters. Common Procedures and Functions can be defined in a Package.

Compilation VHDL source code is usually typed into a text file on a

computer. That text file is then submitted to a VHDL compiler, which builds

the data files necessary for simulation or synthesis. The proper jargon for the

steps performed by the compiler are Analysis, which checks the VHDL

source for errors and puts the VHDL into a Library, and Elaboration, which

links together the Entities and Architectures of the hierarchy.

 TOOLS
METHODOLOGY OF SOFTWARE TOOLS

SIMULATOR MODELSIM

SYNTHESIS LEONARDO

DESIGN FLOW

PHASE - 1
MAIN MODELSIM RTL
(DESIGN &
MODULE DEBUGGING SYNTHE -
SIZEABLE
VHDL)
TOOL

PHASE - 2

MODELSIM
VHDL SYNTHESIS
LIBRARY
DEBUGGING

TOOL
NETLIST
-------------------------------------------------------------------------------
PHASE - 3
MODELSIM

DEBUGGING
VHDL PLACE &
LIBRARY TOOL ROUTE
NET
LIST
LEONARDOSPECTRUM

LeonardoSpectrum is a suite of high level design tools for a

Complex Programmable Logic Device (CPLD), Field Programmable Gate
Array (FPGA), or Application Specific Integrated Circuit (ASIC).
LeonardoSpectrum offers design capture, VHDL and Verilog entry, register-
transfer-level debugging for logic synthesis, constraint-based optimization,
timing analysis, encapsulated place-and-route, and schematic viewing.

LEONARDOSPECTRUM FEATURES

LeonardoSpectrum runs on Windows 98/2000/NT/XP; and

UNIX Sun and HP platforms. The tool suite can be configured into three
different levels of capability. And, a native Windows graphical user interface
(GUI) is common to all three levels. The following features are
common to all three levels:

 The same “look and feel”

 Windows editing, dragging, and dropping features are available
 SynthesisWizard, Quick Setup, and Advanced FlowTabs guide you
through your design process
 Embedded, interactive, and filtered windows extend task information
 Quick file changes with right mouse button (RMB) actions
 Popups and pulldowns menus are prevalent
 Pertinent information is parsed for quick reading
 Clickable buttons assign tasks
MENTOR GRAPHICS SOFTWARE

This section defines Mentor Graphics software for a system

manager and lists the operating systems on which Mentor Graphics software
can run, and provides a list of system management tasks.

ELECTRONIC DESIGN AUTOMATION

Mentor Graphics software is used to help automate the

electronic design cycle. The term Electronic Design Automation, or EDA,
denotes the application of computer hardware and software to assist in the
design of electronic components and systems. Mentor Graphics software is
used by ASIC designers, IC designers, PCB designers, and project managers
(to name a few) in such diverse electronic areas such as telecommunications,
aerospace, and consumer electronics. Mentor Graphics applications provide
solutions for the entire EDA cycle, from product conception, to testing, to
final manufacturing.

To produce a design using Mentor Graphics applications, your

network must contain:

 At least one Mentor Graphics software tree — A Mentor Graphics

software tree contains the actual application software.
 Parts — A part is a software model that describes the hardware
characteristics of the part to the Mentor Graphics application. Parts
are usually grouped by type into one or more libraries.
 Design data — Design data is something that application users create.
Design data is stored in one or more databases that is then accessed as
necessary by Managing Mentor Graphics Software, Operating
Systems Supported by Mentor Graphics
 Servers configured to perform a specific task — The two most
common servers are a license server (which administer the licenses for
Mentor Graphics software) and a print server (which allow you to
print designs created with Mentor Graphics applications). A Mentor
Graphics software tree is the only one of these items that is machine-
dependent.

However, both parts and design data use a machine-independent

format for data storage. Although the software that runs on a server is
machine-dependent, a server can be used to administer services to systems
of a different type.

OPERATING SYSTEMS

Mentor Graphics V8.x software runs on workstations with the

following types of operating systems:

 Hewlett-Packard HP-UX
 Sun Solaris
 IBM AIX
SYSTEM MANAGEMENT

This manual assumes you have adequate experience with

managing the operating systems and hardware on your network. The
information in this manual is most useful if you are already:

 Familiar with the operating systems and hardware on your network.

 Proficient in performing the following system management tasks:
 Installing and configuring the operating system, including patches.
 Creating, deleting, and maintaining user accounts.
 Daemon start-up, shut down, and maintenance.
 Configuring network software and hardware, including TCP/IP and
printer software.
 Configuring Network Information System (NIS) software.
 Adding and removing network peripherals, such as CD-ROM drives
and printers.
 Managing file systems, disk space, and network traffic.
 Maintaining network security.

MENTOR GRAPHICS TREE OVERVIEW

A Mentor Graphics software tree contains the binary executable

files for Mentor Graphics applications. Besides binary files, a Mentor
Graphics software tree contains supporting links, userware, default location
maps, and any other objects needed for Mentor Graphics applications to
invoke and run, including system tests to verify that your software is
functioning properly. A Mentor Graphics software tree does not contain part
library data, which you must install from source media to a separate
location.

TYPES OF MENTOR GRAPHICS TREES

There are two types of Mentor Graphics trees:

 Master tree
A Master tree is the first Mentor Graphics tree you install on a
workstation or file server and usually serves other client workstations
of the same binary type. Links within a Master tree typically resolve
to software physically located within that tree; that is, a Master tree is
a completely self-contained tree with no external links outside of the
tree.

 User tree
A User tree is a Mentor Graphics tree that resides on a user's local
system. To conserve disk space, the user tree normally contains copies
of frequently used packages and accesses other less frequently used
packages via symbolic links to a Master tree. In a User tree, the shared
directory is a link to Master tree's shared directory. User trees are
optional.

BINARY - COMPATIBILITY
 The Mentor Graphics tree structure only supports the binary
files built to execute on one type of processor, and cannot contain binary
files for more than one type of processor. Therefore, at least one Mentor
Graphics Master tree must exist for each network.

MODELSIM PROJECT

A project is a collection entity for an HDL design under

specification or test. At a minimum it has a root directory, a work library,
and a session state that is stored in a .mpf file located in the project's root
directory. With the exception of libraries, all components of a project reside
in or below the project's root directory. A project can also have associated
source files, libraries, and top-level design units. A ModelSim Library is a
directory created by ModelSim (using the vlib command or the Design >
Create a New Library menu selection). This directory contains the compiled
objects from compiling VHDL or Verilog source files.

VSIM, VCOM AND VLOG?

VSIM, VCOM and VLOG are tools used to compile and

simulate Verilog and VHDL designs. VCOM compiles a VHDL source file
into a library; VLOG compiles a Verilog source file into a library. Once a
design is compiled, you invoke VSIM with the name of the top-level design
unit (previously compiled). VSIM then loads the design components from
their libraries and performs the simulation.
 INTRODUCTION

This is a state-machine driven core that measures transition

intervals in a particular character arriving via rs232 transmission (i.e.

PCserialport).

Measurements of time intervals between transitions in the

received character are then used to generate a baud rate clock for use in

serial communications back and forth with the device that originally

transmitted the measured character.

This module allows for RS232 serial communications (UART)

to automatically synthesize a BAUD rate to match incoming serial data,

regardless of the FPGA clock rate. It works by measuring the speed of the

incoming characters, and producing its own clock to match. It has been

tested at clock rates ranging from 1.5 MHz up to 98 MHz.

 BAUDRATE IN COMMUNICATIONS

SYSTEMS

Baud rate is the number of changes per second that the

hardware generates.

Data rate is the bits per second - equal or higher than baud rate -

300 bps, 9600 bps, 14,400 bps...according to Hardware limitations.

The baud rate is a measure of the number of symbols

(characters) transmitted per unit of time. Each symbol will normally consist

of a number of bits, so the baud rate will only be the same as the bit rate

when there is one bit per symbol. The term originated as a measure for the

transmission of telegraph characters. It has little application today except in

terms of modem operation. It is recommended that all data rates are referred

to in bps, rather than baud (which is easy to misunderstand). Additionally,

baud rate cannot be equated to bandwidth unless the number of bits per

symbol is known.

NEED FOR AUTOMATIC BAUDRATE

GENERATOR

 The auto_baud generator is intended for use in "human interface"

rs232 serial applications.

 It handles situations where we might want to have the BAUDrate

change dynamically.

 It has been tested at clock rates ranging from 1.5 MHz upto 98 MHz.

 It has been tested at the lowest 110 BAUD as well the highest

115200 BAUD.

 It also supports non-standard baudrates.

 F E AT U R E S

 Tested in Xilinx XC2V200 hardware, no simulation available.

 A PC using "hyperterm" and "SecureCRT" was used for testing.

 It consumes 93 slices, operates up to 102 MHz (no constraints.)

 Default parameter settings work from 300 BAUD up to 115200

BAUD with any FPGA board clock between 30 MHz and 100 MHz.

 Clock speeds lower than 30 MHz support lower BAUD rates, like

9600.

 It has been tested at 110 BAUD as well. That is a really slow speed

due to press "enter" multiple times at the slow speeds.

 Fully parameterized module.

 Will operate just fine with "non standard" BAUD rates – such as

MIDI (musical instrument digital interface.) No calculations required.

WORKING OF AUTOMATIC BAUDRATE

GENERATOR

This module scans an incoming stream of rs232 serial

characters. It constantly looks for a new character, which it detects by seeing

the "start" bit. When a condition resembling a start bit is detected, the

module then begins a measurement window, to try and determine the BAUD

rate of the incoming character. Since many different characters have

different bit transitions because of their different data content, this module

actually only "targets" a single character -- in this case the "carriage return"

character (0x0d). Once it finishes the measurement interval (first 2 bits of

the received character) then it uses the measurement to produce a BAUD

rate clock.
 The module uses this BAUD rate clock internally to verify the

remaining 8 bits in the serial character (total of 10 bits per received

character, including start/stop bits. Parity is supported, but has never been

tested.) If the remainder of the character verifies correctly to be a carriage

return character, the measurement is accepted as valid, and the module then

produces the BAUD rate clock externally, and flags that it has "locked" onto

the BAUD rate of the incoming characters.

Received serially, the carriage return appears as the following

waveform

________ ____ _____ _______________

|__|d0|__|d2d3|________|stop
start d1 d4d5d6d7

The waveform is shown with an identical "high" time and "low"

time for each bit. However, actual measurements taken using a logic

analyzer on characters received from a PC show that the times are not equal.

The "high" times turned out shorter, and the "low" times longer... Therefore,

this module attempts to average out this discrepancy by measuring one low

time and one high time.

 Since the transition measurements must unavoidably contain

small amounts of error, the measurements are made during the beginning 2

bits of the received character, (that is, start bit and data bit zero). Then the

measurement is immediately transformed into a baud rate clock, used to

verify correct reception of the remaining 8 bits of the character

WHY DO WE USE CARRIAGE RETURN?

The particular character which is targeted for measurement and

verification in this module is: carriage return (CR) = 0x0d = 13. This

particular character was chosen because it is frequently used at the end of a

command line, as entered at a keyboard by a human user interacting with a

command interpreter. It is anticipated that the user would press the "enter"

key once upon initializing communications with the electronic device, and

the resulting carriage return character would be used for determining

BAUDrate, thus allowing the device to respond at the correct rate, and to

carry on further communications.

The electronic device using this "auto_baud" module adjusts its

baud rate to match the baud rate of the received data. This works for all
baud rates, within certain limits, and for all system clock rates, within certain

limits.

CASE 1:- (The entire character is not received correctly)

If the entire character is not received correctly using the

generated baud rate, then the measurement is scrapped, and the unit goes

into an idle scanning mode waiting for another character to test.

CASE 2:- (Receiving is not a carriage return)

This effectively filters out characters that the unit is not

interested in receiving (anything that is not a carriage return.) There is a

slight possibility that a group of other characters could appear by random

chance in a configuration that resembles a carriage return closely enough

that the unit might accept the measurement and produce a baud clock too

low.
CASE 3 :- (Multiple Carriage Return)

Press "enter" multiple times at the slow speeds. Has been tested

at 110 BAUD as well. That is a really slow speed.

CASE 4:- (Correct Performance)

This method of operation implies that each carriage return

character received will produce a correctly generated baud rate clock.

Therefore, each and every carriage return actually causes a new baud rate

clock to be produced. However, updates occur smoothly, and there should be

no apparent effect as an old BAUD clock is stopped and a new one started.

The transition is done smoothly.

MULTIPLICATION FACTOR

The clock which is generated is in reality a clock enable pulse,

one single clock wide, occurring at a rate suitable for use in serial

communications. (This means that it will be generated at 4x or 8x or 16x the

actual measured baud rate of the received character. The multiplication

factor is called "CLOCK_FACTOR_PP" and is a settable parameter within

this module. The parameter “CLOCK_FACTOR_PP" need not be a power

of two, but it should be a number between 2 and 16 inclusive.)

CALCULATION OF BAUD-RATE

This is basically a programmable 8-bit counter followed by a

switch able frequency flip flop chain which can be set up to give the

appropriate sampling and shifting rates for the desired baud rate, based on

the PIC’s crystal frequency XTAL (e.g. for 20MHz, XTAL = 20) giving: -
 It may be advantageous to use the high baud rate (BRGH = 1)

even for slower baud clocks as this may reduce baud rate error in some

cases.

ALGORITHM

S P E C I F I C AT I O N S

CLK_FACTOR_PP = 8 // Baud clock multiplier

LOG2_MAX_COUNT_PP = 16 // Bit width of measurement

Counter

LOG2_MAX_CLOCK_FACTOR = 4 // Sets the size of the

CLOCK_FACTOR prescaler.
BITS_PER_CHAR = 8 //Include parity,if used,but not

start and stop bits...

TEMPLATE_BITS = 9'h086 // Carriage return &&

termination flag

STEP:-1 (To Set Clock_Factor_PP)

 This module uses a counter to divide down the clk_i signal to produce

the baud_clk_o signal.

 The frequency of baud_clk_o is nominally

CLOCK_FACTOR_PP rx_baud_rate, where "rx_baud_rate" is the

baud rate of the received character.

 The higher you make CLOCK_FACTOR_PP, the higher the generated

baud_clk_o signal frequency, and hence the lower the resolution of

 the divider.Therefore, using a lower value for the

CLOCK_FACTOR_PP will allow you to use a lower clk_i with this

module.

clock_factor_pp => frequency of baud_clk_o(ip) =>resolution of the divider

STEP :-2 (To Set Log2_Max_Count_PP)

 To set LOG2_MAX_COUNT_PP, remember

(max_count*CLOCK_FACTOR_PP)/Fclk_i is the maximum

measurement time that can be accomodated by the circuit.(where

Fclk_i is the frequency of clk_i, and 1/Fclk_i is the period).Therefore,

set LOG2_MAX_COUNT_PP so that the maximum measurement

time is at least as long as 2x the baud interval of the slowest received

serial data (2x because there are two bits involved in the

measurement!)
 log2_max_count_pp = (max_count * clock_factor_pp)/fclk_i

EXAMPLE:-1

GIVEN: Fclk_i = 20MHz, CLOCK_FACTOR_PP = 4 and a minimum

baud rate of 115,200, you would calculate:

(max_count * CLOCK_FACTOR_PP)*1/Fclk_i >= 2/Fbaud_max -- 1

Solving for the bit width of the max_count counter...

LOG2_MAX_COUNT_PP >= ceil(log_base_2(max_count)) -- 2

Substitute 1 in 2 we get >=

ceil(log_base_2(2*Fclk_i/(Fbaud_max*CLOCK_FACTOR_PP)))

>= ceil(log_base_2(2*20E6/(115200*4)))

>= ceil(log_base_2(86.8))
 >= 7 bits.

In the above example, the maximum count would approach 87,

which means that a measurement error of 1 count is about (1/87)=approx.

1.15%. This is an acceptable level of error for a baud rate clock. Notice that

the lower baud rates have an even smaller error percentage (Yes!) but that

they require a much larger measurement counter.

EXAMPLE:-2

For instance, to lock onto 300 baud using the same

example above, would require:

LOG2_MAX_COUNT_PP >= ceil(log_base_2(40000000/1200))

>= ceil(log_base_2(33333.3))

>= ceil(15.024678)

>= 16 bits.

If the percentage error for your highest desired baud rate is

greater than a few percent, you might want to use a higher Fclk_i or else a

lower CLOCK_FACTOR_PP. The following test results were obtained,

using an actual session in hyper term, looking for correct readable character

transmission both directions.

clk_I freq (ip) baudrate

BAUDRATE (VS) FREQUENCY

Clk_i Freq. Baudrate

(MHz)

110 300 1200 2400 4800 9600 19200 57600 115200

98 Fail Pass Pass Pass Pass Pass Pass Pass Pass
55 Pass Pass Pass Pass Pass Pass Pass Pass Pass
49 Pass Pass Pass Pass Pass Pass Pass Pass Pass
24.5 Pass Pass Pass Pass Pass Pass Pass Pass Fail
12 Pass Pass Pass Pass Pass Pass Pass Pass Fail
6 Pass Pass Pass Pass Pass Pass Pass Fail Fail
3 Pass Pass Pass Pass Pass Fail Fail Fail Fail
1.5 Pass Pass Pass Pass Fail Fail Fail Fail Fail
 OPERATIONS OF AUTOMATIC

BAUDRATE GENERATOR

BLOCK DIAGRAM

The receiver contains the RDR (Receive Data Register) and

RSR (Receive Shift Register) registers and the receive control. The control
interfaces with SCSR (Serial Communications Control Register), and RDR

can drive data onto the data bus. The first process represents the

combinational network, which generates the next-state and control signals.

When there is data to be received, RxD becomes '0' which signifies the start

bit. Then, using a shift register, the eight data bits are clocked. Once the stop

bit is detected, the receiver is ready to output its data. The second process

updates the registers on the rising edge of the clock. The signal

BclkX8_rising is '1' for one system clock time following the rising edge of

BclkX8, which is output from the baud rate generator code. BclkX8_rising is

generated the same manner as Bclk_rising.

The receiver sends its data through the cipher encoder, which

will encode the data in the following manner. The VHDL code for the cipher

encoder takes the binary output from the UART receiver (RDR[7..0]) and

adds an offset to it, which in our case will be four. To implement the

modulus function, we took the result of the +4 operation and manipulated it

in the appropriate manner. For example, if the result from the +4 operation is

greater than 21 then we subtract 22 from the value to wrap back around to

the beginning of the alphabet; otherwise, the value of the letter is just the

result from the +4 operation.

 Using an ASCII lookup table, we are then able to determine the

equivalent letter of our result. This output is displayed on the LEDs, and it is

also sent to the transmitter as a binary value for displaying on the terminal

window.

The transmitter takes the binary output of the cipher encoder

and sends it back to the terminal window. In order to notify the transmitter

that there was data ready to be transmitted, we took the SetRDRF signal

from the receiver and sent it through a D-type flip-flop to delay the system

clock even further. Then the output of the D flip-flop is sent to the LoadTDR

signal in the transmitter to notify that there is data to be transmitted. Also,

the TDRE and Rst_b signals need to be set in a similar fashion.

For the TDRE, we divided the system clock further using a

second D flip-flop with the output of the first D flip-flop as an input for the

second one, and the output of the second D flip-flop was inverted and sent to

the TDRE input on the transmitter. This is because the TDRE needs to be

inverted whenever there is valid data to be transmitted. For the Rst_b signal,
we use a D flip-flop with vcc as its input, and the output of the flip-flop was

tied to the input Rst_b on the transmitter.

The transmitter contains the TDR (Transmit Data Register) and TSR

(Transmit Shift Register) registers and the transmit control. It interfaces with

TDRE (Transmit Date Register Empty) and the data bus (DBUS). The first

process represents the combinational network, which generates the next-state

and control signals. The second process updates the registers on the rising

edge of the clock. The signal Bclk_rising is '1' for one system clock time

following the rising edge of Bclk. To generate Bclk_rising, Bclk is stored in

a flip-flop named Bclk_Dlayed.

Then Bclk_rising is '1' if the current value of Bclk is '1' and the

previous value (stored in Bclk_Dlayed) is '0'. Thus, Bclk_rising <= Bclk and

not Bclk_Dlayed
 The output of the transmitter is sent to the terminal window for

display.

RS232TX

This block takes care of framing up an RS232 output word, and

sending it out the "txd" line in a serial fashion. The user is responsible for

providing appropriate clk and clock enable (tx_clk) to achieve the desired

Baudot interval (a new bit is transmitted each (tx_clk/clock_factor) pulses)

(NOTE: the state machine operates at "clock_factor" times the desired

BAUDrate. Set it to anything between 2 and 16, inclusive. It may be useful

to adjust the clock_factor in order to generate good BAUD clocks from odd

Fclk frequencies on your board.)

A load operation is requested by bringing the "load" line high.

However, the load will only be accepted when load_request is also high
(which just happens to coincide with tx_clk_1x inside of the state

machine...) Therefore, the "load_request" line may be used as a bus

acknowledgement. (load_request = "ack_o" in Wishbone terminology but it

only lasts for one single clk cycle, so be careful how you use it!) If the

"load_request" line is tied to "load," the unit will send data characters

continuously, with no gaps in between transmissions. Note that support is

not provided for 1.5 stop bits, only integral numbers of stop bits are allowed.

A selection of more than 2 for number of stop bits will still

work fine, it will simply introduce a delay between characters being

transmitted, although the length of the transmitter shift register will also

grow to include one stage for each stop bit requested.

RS232RX

This block takes care of receiving an RS232 input word, from the

"rxd" line in a serial fashion. The user is responsible for providing

appropriate CLK and clock enable (CE) to achieve the desired Baud interval

(NOTE: the state machine operates at "CLOCK_FACTOR_PP" times the

desired BAUD rate. Set it to anything between 2 and 16, inclusive. Values

higher than 16 will not "buy" much for you, and the state machine might not

work well for values less than four either, because of the difficulty in

sampling rxd at the "middle" of the bit time. However, it may be useful to

adjust the clock_factor around in order to generate good BAUD clocks from

odd Fclk frequencies on your board.)

Each time the "word_ready" line drives high the unit has put a

newly received data word into its output buffer, and is possibly already in

the process of receiving the next one. Note that support is not provided for

1.5 stop bits, only integral numbers of stop bits are allowed. However, a

selection >2 for number of stop bits will still work (it will simply receive

and count additional stop bits before reporting "word_ready".

CLOCK DIVIDER

This module implements a counter to divide down a clock

signal. I put it in a separate module because I did not know of another way to

put a timing constraint on it for synthesis.

 Clock Divider

CLOCK MULTIPLIER

This module uses the Virtex "DLL" structure to generate a 2x

and 4x clock. OVERVIEW of contents: The clock generators are

configured to provide clocks at 16x the desired transmit BAUD rates for
RS232 serial I/O. This is done so that the rs232rx module can easily share

the clock generation circuitry of the rs232tx block. The clock_gen_select

module has a BAUD rate selection input field of three bits. This field

allows the appropriate "clock_factor" clock rate to be produced once and

used on many transmitters and receivers. Alternatively, there is a

"clock_gen" block which uses parameters to specify the desired values for

the DDS and prescaler divide factor.

REG4PACK_CLRSET

The reg_4_pack_clrset address vector "adr_i" selects among

four locations present in the module. In order to read data from a register

location, the we_i line must be inactive (low), and the "sel_i" signal must

also be active (high.) Then, the unit will drive the data bus. Writing is

similar - drive we_i active (high), make sel_i high, drive the write data onto

the data bus, and provide a "posedge clk_i" to store the data into the selected

register.
 The registers are composed of d-flip-flops (DFFs), clocked by

clk_i. There is a preset/clear function added into this module, controlled by

the "pre" and "clr" input vectors. A "1" in the corresponding bit position has

the effect of presetting or clearing the associated register. The order of

priority is as follows: rst, clr, set, then normal read and write operations.

The clr and set operations are synchronous. They occur at the rising clock

edge. A parameter allows setting the number of "read-only" locations. The

convention for this parameter is the following: The lower numbered N

registers become read-only locations, and the upper (4-N) registers remain

as R/W (storage registers,) for a setting of READ_ONLY_REGS_PP = N.

Thus, for N=2, then r0 and r1 are "read-only" locations (no actual registers

are synthesized,) but r2 and r3 remain as read/write registers.

REG_8PACK

The reg_8_pack address vector "adr_i" selects among the eight

locations present in the module. In order to read data from a register

location, the we_i line must be inactive (low), and the "sel_i" signal must
also be active (high.) Then, the unit will drive the data bus. Writing is

similar - drive we_i active (high), make sel_i high, drive the write data onto

the data bus, and provide a "posedge clk_i" to store the data into the selected

register. The registers are composed of d-flip-flops (DFFs), clocked by clk_i.

A parameter allows setting the number of "read-only" locations. The

convention for this parameter is the following:

The lower numbered N registers become read-only locations,

and the upper (8-N) registers remain as R/W (storage registers,) for a

setting of READ_ONLY_REGS_PP = N. Thus, for N=4, then r0,r1,r2 and

r3 are "read-only" locations (no actual registers are synthesized,) but r4, r5,

r6 and r7 remain as registers.

SQUARE_ WAVE_DDS

This module implements a Direct Digital Synthesizer (DDS). It is

very simple: A counter advances in phase each clock cycle, and the most
significant bits are used to index into a waveform lookup table. This

particular version does not include the lookup table, because I am initially

looking for squarewave output only, so I am using the most significant bit of

the counter as the output. The frequency resolution of a DDS can be very

fine indeed, depending on how many bits are included in the phase

accumulator counter. The output frequency is given by:

Fout = frequency/(2^DDS_BITS_PP)*Fclk

Generally, outputs up to 40% of Fclk may be generated when

using a sine wave lookup table, with appropriate filtering. For the digital

squarewave output, such as that produced by this module, the output can

probably be as high as 50% of Fclk. There is jitter present in the output, in

the amount of +/- 0.5T, where T is the period of the clock.

RAM

Memory is an indispensable part of computer and Microprocessor

based systems. The data used in a program as well as the instructions for

executing the program are stored in the memory.

 A Random Access Memory (RAM) is a volatile chip Memory in

which both read and write operations can be Performed. Any random

location can be accessed for information transfer to or from the memory. It is

also called Read Write Memory(RWM).

AUTOMATIC_BAUD_WITH_TRACKING

Counter rollover condition

This condition signals the middle of a bit time, for use during

the verify stage. Also, this signal is used to advance the main count, instead

of "clock_count_rollover." This produces an effective "rounding" operation

for the measurement (which would otherwise "truncate" any fraction of time

contained in this counter at the instant the measurement is finished.

MAIN COUNTER

During measurement, it advances once for each

CLOCK_FACTOR_PP cycles of clk_i. This accumulated measurement is

then latched into "measurement" when the state machine determines that the

measurement interval is finished.

During verify time (when the new candidate baud rate clock is

being tested) this counter is allowed to run freely, advancing once each

clk_i, but being reset when it reaches a total count of "measurement" clock

cycles.

BAUD COUNTER

Once a measurement has been verified, it is stored in "baud"

and the signal "run" goes high. From then on, this counter is allowed to run

freely, advancing once each clk_i, but being reset when it reaches a total

count of "baud" clock cycles. This counter's reset signal is the output baud

rate clock.
SHIFT REGISTER

It is used to provide "target" character bits one at a time for

verification as they are "received" (sampled) using the candidate baud clock.

FLIP-FLOP

It is used to keep track of whether the verify operation is succeeding

or not. Any target bits that do not match the received data at the sampling

edge, will cause the verify_failed bit to go high. This is what the state

machine looks at to determine whether it passed or not.

MEASUREMENT STORAGE LATCH

The final measured time count from main_count is stored in

this latch upon completion of the measurement/ interval. The value stored in

this latch is used for the baud clock generated during verify, but a different

register holds the actual value being used to generate output.

BAUD STORAGE LATCH

The final verified time count from the "measurement" register

is stored in this register after a good verify. The value stored in this latch is

used in conjunction with// baud_count to produce the baud clock which is

sent to the output.

FLIP-FLOP

It is used to keep track of whether the unit is producing a baud clock

or not. Initially following reset, there is no baud clock being produced. But,

once a single measurement is verified, then the clock is produced and

tracking changes are made over time. Thus, this bit goes high as a result of

the first "verify_good" pulse, and it remains high forever, until the unit is

reset. This is state machine m1. It checks the status of the serial_dat_i line

and coordinates the measurement of the time interval of the first two bits of

the received character, which is the "measurement interval."

STATE MACHINE

Following the measurement interval, the state machine enters a new

phase of bit verification. If the measured time interval is accurate enough to

measure the remaining 8 bits of the character correctly, then the

measurement is accepted, and the baud rate clock is driven onto the

baud_clk_o output pin. Incidentally, the process of verification effectively

filters out all characters which are not the desired target character for

measurement. In this case, the target character is the carriage return.

 APPLICATIONS

 The auto_baud generator is intended for use in "human interface"

rs232 serial applications.

 It has also been tested with "text file transfer" in hyperterm and

SecureCRT terminal programs, to see if it would function during

higher speed character transfer and it worked just fine.

HYPER TERM

APC running HyperTerminal can be then used to exercise the

design manually. Implementation, the RS232 connection, etc... completely

simulated. It can also be fitted on a real FPGA board. The system the use of

the UARTS module, we have built a small application that reads in

characters.
Its Main applications are
 RS232 Serial Communication
 U A RT
 EXTENT OF THE PROJECT
I also have a new version of "rs232_syscon" which Incorporate

the auto_baud_with_tracking module, so that a serial control/debugging

session can be brought up quickly on a new board, regardless of the system

clock speed. We can change baud rates, and it follows along when you hit

"enter." Works with "rs232_syscon" for an easier bring up of debugging

sessions.

This is a state-machine driven rs232 serial port interface to a

"Wishbone" type of bus. It is intended to be used as a "Wishbone system

controller" for debugging purposes. Specifically, the unit allows the user to

send text commands to the "rs232_syscon" unit, in order to generate read

and write cycles on the Wishbone compatible bus. The command structure

is quite terse and spartan in nature, this is for the sake of the logic itself.

Because the menu-driven command structure is supported without the use of

dedicated memory blocks (in order to maintain cross-platform portability as

much as possible) the menus and command responses were kept as small as

possible. In most cases, the responses from the unit to the user consist of a
"newline" and one or two visible characters. The command structure

consists of the following commands and responses.

C O N C LU S I O N

In this project, transmitter, receiver and control module are

required for the implementation of the AUTOMATIC BAUDRATE

GENERATOR are designed using VHDL. The VHDL coding is simulated,

synthesized and then using the design manager, ’place & Route ‘ is

performed.
 APPENDIX

AU T O B AU D W I T H T R A C K I N G C O R E

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.numeric_std.all;

ENTITY auto_baud_with_tracking IS
GENERIC (
-- CLOCK_FACTOR_PP can be from [2..16] inclusive.
-- Parameters
CLOCK_FACTOR_PP : integer := 8;
LOG2_MAX_COUNT_PP : integer := 16;
m1_idle : std_logic_vector(3 DOWNTO 0) := "0000";
m1_measure_0 : std_logic_vector(3 DOWNTO 0) := "0001";
m1_measure_1 : std_logic_vector(3 DOWNTO 0) := "0010";
m1_measure_2 : std_logic_vector(3 DOWNTO 0) := "0011";
m1_measure_3 : std_logic_vector(3 DOWNTO 0) := "0100";
m1_measure_4 : std_logic_vector(3 DOWNTO 0) := "0101";
m1_verify_0 : std_logic_vector(3 DOWNTO 0) := "1000";
m1_verify_1 : std_logic_vector(3 DOWNTO 0) := "1001";
m1_run : std_logic_vector(3 DOWNTO 0) := "0110";
m1_verify_failed : std_logic_vector(3 DOWNTO 0) := "0111");
PORT (
clk_i : IN std_logic;
reset_i : IN std_logic;
serial_dat_i : IN std_logic;
auto_baud_locked_o : OUT std_logic;
baud_clk_o : OUT std_logic);
END auto_baud_with_tracking;

ARCHITECTURE translated OF auto_baud_with_tracking IS

SIGNAL mid_bit_count : std_logic;

 SIGNAL temp1 : std_logic;
SIGNAL main_count_rollover : std_logic;
SIGNAL baud_count_rollover : std_logic;
SIGNAL clock_count_rollover : std_logic;
SIGNAL enable_clock_count : std_logic;
SIGNAL verify_done : std_logic;
SIGNAL idle : std_logic;
SIGNAL measure : std_logic;
SIGNAL clear_counters : std_logic;
SIGNAL verify : std_logic;
SIGNAL t1 : std_logic;
SIGNAL verify_good : std_logic;
SIGNAL character_miscompare : std_logic;
SIGNAL run : std_logic;
SIGNAL clock_count : std_logic_vector(4 - 1 DOWNTO 0);
SIGNAL main_count : std_logic_vector(LOG2_MAX_COUNT_PP - 1
DOWNTO 0);
SIGNAL baud_count : std_logic_vector(LOG2_MAX_COUNT_PP - 1
DOWNTO 0);
SIGNAL measurement : std_logic_vector(LOG2_MAX_COUNT_PP - 1
DOWNTO 0);
SIGNAL baud : std_logic_vector(LOG2_MAX_COUNT_PP - 1
DOWNTO 0);
SIGNAL target_bits : std_logic_vector(8 DOWNTO 0);
SIGNAL m1_state : std_logic_vector(3 DOWNTO 0);
SIGNAL m1_next_state : std_logic_vector(3 DOWNTO 0);
SIGNAL auto_baud_locked_o_xhdl1 : std_logic;
SIGNAL baud_clk_o_xhdl2 : std_logic;
BEGIN

auto_baud_locked_o <= auto_baud_locked_o_xhdl1;

baud_clk_o <= baud_clk_o_xhdl2;
enable_clock_count <= measure OR (verify AND main_count_rollover) ;

PROCESS(clk_i,reset_i)

BEGIN
IF (reset_i = '1') THEN
clock_count <= "0000";
ELSE
IF (clear_counters = '1') THEN
clock_count <= "0000";
ELSE
IF (enable_clock_count = '1') THEN
IF (clock_count_rollover = '1') THEN
clock_count <= "0000";
 ELSE
clock_count <= (clock_count + "0001");
END IF;
END IF;
END IF;
END IF;
if(clock_count = conv_std_logic_vector((CLOCK_FACTOR_PP - 1), 4)) then
clock_count_rollover <='1';
else
clock_count_rollover <='0';
end if;
if (clock_count = (conv_std_logic_vector((CLOCK_FACTOR_PP/2),4) - '1')) then
temp1<='1';
else
temp1<='0';
end if;

mid_bit_count <= temp1 AND enable_clock_count ;

END PROCESS;

PROCESS(clk_i,reset_i)
BEGIN
IF (reset_i = '1') THEN
main_count <= (OTHERS => '0');
ELSE
IF (clear_counters = '1') THEN
main_count <= (OTHERS => '0');
ELSE
IF ((measure AND mid_bit_count) = '1') THEN
main_count <= main_count + "0000000000000001";
ELSE
IF (verify = '1') THEN
IF (main_count_rollover = '1') THEN
main_count <= (OTHERS => '0');
ELSE
main_count <= main_count + "0000000000000001";
END IF;
END IF;
END IF;
END IF;
END IF;
if(main_count = measurement) then
main_count_rollover <='1';
else
main_count_rollover <='0';
end if;
END PROCESS;

PROCESS(clk_i,reset_i)
BEGIN
IF (reset_i = '1') THEN
baud_count <= (OTHERS => '0');
ELSE
IF (run = '1') THEN
IF (baud_count_rollover = '1') THEN
baud_count <= (OTHERS => '0');
ELSE
baud_count <= baud_count + "0000000000000001";
END IF;
END IF;
END IF;
if(baud_count = baud) then
baud_count_rollover <= '1';
else
baud_count_rollover <= '0';
end if;
END PROCESS;

PROCESS(clk_i,reset_i)
BEGIN
IF (reset_i = '1') THEN
target_bits <= "010000110";
ELSE
IF (NOT verify = '1') THEN
target_bits <= "010000110";
END IF;
IF ((verify AND mid_bit_count) = '1') THEN
target_bits <= ('0' & target_bits(8 downto 1));
END IF;
END IF;
if (target_bits = "000000001") then
t1<='1';
else
t1<='0';
end if;
verify_done <= t1 AND verify AND mid_bit_count ;
END PROCESS;

PROCESS(clk_i,reset_i)
BEGIN
IF (reset_i = '1') THEN
character_miscompare <= '0';
 ELSE
IF (idle = '1') THEN
character_miscompare <= '0';
END IF;
IF (((verify AND mid_bit_count) AND (target_bits(0) XOR serial_dat_i)) = '1')
THEN
character_miscompare <= '1';
END IF;
END IF;
END PROCESS;

PROCESS(clk_i,reset_i)
BEGIN
measurement <= (OTHERS => '1');
ELSE
IF (clear_counters = '1') THEN
measurement <= ('0' & main_count(15 downto 1));
END IF;
END IF;
END PROCESS;

PROCESS(clk_i,reset_i)
BEGIN
IF (reset_i = '1') THEN
baud <= (OTHERS => '1');
ELSE
IF (verify_good = '1') THEN
baud <= measurement;
END IF;
END IF;
END PROCESS;

PROCESS(clk_i,reset_i)
BEGIN
IF (reset_i = '1') THEN
run <= '0';
ELSE
IF (verify_good = '1') THEN
run <= '1';
END IF;
END IF;
END PROCESS;
baud_clk_o_xhdl2 <= baud_count_rollover ;

m1_state_register : PROCESS(clk_i,reset_i)
BEGIN
 -- WAIT UNTIL (clk_i'EVENT AND clk_i = '1') OR (reset_i'EVENT AND reset_i =
'1');
IF (reset_i = '1') THEN
m1_state <= m1_idle;
ELSE
m1_state <= m1_next_state;
END IF;
END PROCESS;

m1_state_logic :
PROCESS(m1_state,mid_bit_count,serial_dat_i,verify_done,character_miscompare,run)
BEGIN
idle <= '0';
verify_good <= '0';
measure <= '0';
clear_counters <= '0';
verify <= '0';
CASE m1_state IS
WHEN "0000" =>
idle <= '1';
IF (serial_dat_i = '0') THEN
m1_next_state <= m1_measure_0;
ELSE
m1_next_state <= m1_idle;
END IF;
WHEN "0001" =>
measure <= '1';
IF ((mid_bit_count AND NOT serial_dat_i) = '1') THEN
m1_next_state <= m1_measure_1;
ELSE
IF ((mid_bit_count AND serial_dat_i) = '1') THEN
m1_next_state <= m1_idle;
ELSE
m1_next_state <= m1_measure_0;
END IF;
END IF;
WHEN "0010" =>
measure <= '1';
IF (serial_dat_i = '1') THEN
m1_next_state <= m1_measure_2;
ELSE
m1_next_state <= m1_measure_1;
END IF;
WHEN"0011" =>
measure <= '1';
IF ((mid_bit_count AND serial_dat_i) = '1') THEN
 m1_next_state <= m1_measure_3;
ELSE
IF ((mid_bit_count AND NOT serial_dat_i) = '1') THEN
m1_next_state <= m1_idle;
ELSE
m1_next_state <= m1_measure_2;
END IF;
END IF;
WHEN "0100"=>
measure <= '1';
IF (NOT serial_dat_i = '1') THEN
m1_next_state <= m1_measure_4;
ELSE
m1_next_state <= m1_measure_3;
END IF;
WHEN "0101" =>
clear_counters <= '1';
m1_next_state <= m1_verify_0;
WHEN "1000"=>
verify <= '1';
IF (verify_done = '1') THEN
m1_next_state <= m1_verify_1;
ELSE
m1_next_state <= m1_verify_0;
END IF;
WHEN "1001"=>
IF (character_miscompare = '1') THEN
m1_next_state <= m1_verify_failed;
ELSE
m1_next_state <= m1_run;
END IF;
WHEN "0111"=>
clear_counters <= '1';
m1_next_state <= m1_idle;
WHEN "0110" =>
verify_good <= '1';
m1_next_state <= m1_idle;
WHEN OTHERS =>
m1_next_state <= m1_idle;

END CASE;

auto_baud_locked_o_xhdl1 <= run ;

END PROCESS;
END translated;
 BIBLIOGRAPHY

1. Title: Introduction to NMOS and CMOS VLSI Systems Design ,

PHI. Author : Amar Mukherjee
2. Title : Basic VLSI Design, PHI
Author : Pucknell and Eshargian
3. Title : Digital Circuits and Design
Author : Salivahanan
4. Title : Digital and Logic Circuits
Author : Moris Mano
5. Title : VHDL Design, PHI
Author : Baskar

Reference

1. www.necel.com
2. www.cieloinc.com
3. www.ee.itb.ac.id
4. www.techfest.com
5. www.cisco.com
6. www.entmag.com
7. www.xilinx.com
CLOCK DIVIDER
CLOCK MULTIPLIER
REG_4_PACK_CLRSET
REG_8_PACK
SQUAREWAVE_DDS
RS232TX
AUTO_BAUD_WITH_TRACKING
CLOCK DIVIDER
CLOCK MULTIPLY
IBUF
IBUFG
OBUF
CLOCK DLL

REG4PACK_CLRSET
REG8PACK_CLRSET
SQUAREWAVE_DDS
RS232TX
RS232RX
RAM
AUTO_BAUD_WITH_TRACKING