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com/TomekD76
Silicon Carbide Diodes
in Power-Factor
Correction Circuits
Device and circuit design aspects

I
by Rahul Radhakrishnan Potera n this article, we review the application of silicon car-
and Timothy Junghee Han bide (SiC) devices, especially diodes, in power-factor
correction (PFC) circuits, and we compare various SiC
diode designs based on their impact on PFC circuits.
Furthermore, we show how device parameters reported
in datasheets can be used to estimate the performance of SiC
Digital Object Identifier 10.1109/MPEL.2018.2886105
diodes in the surge-current conditions of different durations,
Date of publication: 19 February 2019 and we point to how modifications in PFC circuits can

34 IEEE Power Electronics Magazine z March 2019 2329-9207/19©2019IEEE


iac Dp
L Dpfc
vac
I(L)
C RL
S1
ac Source Rectifier Boost PFC Filter Load
FIG 1 A diagram showing the input PFC stage of a boost
power supply.
improve performance. These analyses help the designer
combine the efficiency advantages of SiC diodes with cir-
cuit robustness that might suffer if Si diodes are simply
replaced with SiC diodes.
Requirements of a
PFC Boost Diode
Electrical loads rarely consume power with the current
fully in phase with voltage. Traditional loads, such as the
induction motor, draw currents at a significant lag to volt-
age. Today’s ubiquitous switched-mode power converters
introduce phase-change as well as higher-order frequency
­harmonics. To convert the maximum possible power as
well as reduce the harmful characteristics that harmonic
­distortions introduce to the power mains, power supplies
are equipped with PFC circuits at the input stages. A per-
fect PFC circuit would enable the mains to see the load
as an ohmic resistance, notwithstanding the load power
factor. Such standards as IEC/EN61000-3-2 and IEC/
EN61000-3-12 [7], [8] stringently regulate line-current har-
monic content.
While correcting for the power factor of input ac power,
the PFC converter also must maximize power conversion
efficiency. The voluntary “80 Plus” regulation certifies
products that deliver at least 80% energy efficiency at 20,
50, and 100% of the rated load and have a power factor of
0.9 or greater at 100% load. Many organizations adhere
to the “80 Plus Titanium” efficiency specification, which
requires a peak efficiency of 96% at half-load conditions [1].
Meeting these opposing objectives of increased efficiency
and compliance with power factor standards requires
more advanced PFC circuit designs and superior active
circuit components.
Figure 1 shows the basic components of the boost PFC
input stage of a power supply. The power loss in the switch
and diode of the PFC stage is partly static conduction loss
and partly switching loss. Static conduction loss is indepen-
dent of the switching frequency. Switching loss, meanwhile,
is proportional to the switching frequency. To reduce the
size and weight of the passive circuit components, includ-
ing input electromagnetic interference filters and a boost
inductor, the switching frequency should be increased.
However, such an increase results in more switching loss
Anode Anode Anode
P-Type P-Type
N-Type N-Type N-Type
+
Vdc
– N Substrate N Substrate N Substrate
Cathode Cathode Cathode
(a) (b) (c)
FIG 2 Illustrations of simplified cross sections of (a) p-i-n,
(b) Schottky, and (c) MPS diodes.
in the active power components. Steps should be taken to
limit this loss. In this regard, SiC Schottky diodes rated at
650 V have been a ­popular choice for replacing correspond-
ing Si p-i-n diodes in the boost PFC stage ( D pfc in Figure 1)
of power supplies in the kilowatt range [2]. Even for price-
sensitive products, the near-zero switching loss of the SiC
Schottky diode, which occurs due to its negligible reverse-
recovery charge, reduces the overall ­circuit bill of materi-
als compared to the cheaper Si p-i-n diode. A comparison of
the two diodes reveals that Schottky Si diodes would have
high static losses due to a higher forward-voltage drop, and
fast-recovery p-i-n Si diodes would have additional switch-
ing losses due to residual reverse-recovery charges at 650 V.
Unlike Si devices, SiC Schottky diodes with a combination
of a higher material band gap and high electron conductiv-
ity enable the simultaneous r­ eduction of static and switch-
ing losses at high ­frequencies (>100 kHz).
SiC Diodes and Surge Current
The PFC input stages of power supplies are subjected to
high surge currents, especially when the device
is turned on and the resulting transient
reduces the effective inductance in the
circuit due to core saturation. In Figure 1,
D p is typically an Si p-i-n diode capable of
high forward- surge currents added to
bypass the current from D pfc. In a normal
boost operation, when Vdc is greater than the rec-
tified voltage, the bypass diode does not conduct. During
surge events, depending on the rise time and pulsewidth, D p
and D pfc carry different proportions of the surge current. In
general, short and fast-rising surge events raise the voltage
across the inductor and most current flows through D p .
However, as pulsewidth increases, more current flows
through D pfc. Figure 2(a)–(c) shows the basic structure
of a p-i-n diode, a  Schottky diode, and a merged
p-i-n–Schottky (MPS) diode. SiC diodes up to
1,200 V are either Schottky or MPS, with
the former providing lower static losses
and the latter higher surge-cur-
rent capability [3].
In power switches, surge
current is often associated
March 2019 z IEEE Power Electronics Magazine 35
with short circuit conditions, whereas features of two generations of a 650-V,
circuit turn-on or powerline tran- 6-A SiC diode from the same manu-
sients are typical surge events in
Compared with Schottky facturer. Diode type A is designed for
diodes used in PFCs. However, in all diodes, MPS diodes higher voltage and has MPS implants
such cases, designs have focused on for higher surge performance in the
have a higher surge
reducing the energy dissipated in the millisecond range. However, the die
device during a surge by increasing tolerance, making size is larger, and Vf is higher than that
the device conductivity in surge condi- them more robust. of type B. Diode type B is designed for
tions. The p-i-n diodes have both elec- lower Vf by trading off surge perfor-
tron and hole carriers. In high forward mance in the millisecond range and
bias, the injection of the opposite possibly giving up some reverse-block-
carrier type across the junction significantly increases the ing characteristics. Diode type A is expected to be more
effective carrier concentration and, hence, conductivity of robust at long surge pulses. However, it is less efficient in
the diode. During forward-surge events, p-i-n diodes, com- a PFC converter compared to the type B. For 10-ns short
pared with Schottky diodes, exhibit a smaller drop in volt- surge pulses, type B, compared with type A, can support
age and, thus, less dissipation of power and less generation higher surge current even though type A is designed with
of heat. Device failure under a surge current happens when p-i-n junctions [Figure 2(a)] for higher surge current. This
heat dissipation sufficiently raises the ­temperature for the apparently counterintuitive behavior is explored further in
anode metal and causes it to melt and flow over the device the next section based on experimental results. An impor-
periphery toward the cathode potential, thus causing the tant point to address is that, while forward-surge events in
reverse-­blocking capability of the diode to deteriorate [4]. the 10-ms range are limited by a peak energy dissipation, our
Replacement of Si p-i-n diodes with SiC Schottky diodes, measurements show that shorter pulses are additionally lim-
while improving normal PFC operation, raises challenges ited by a peak current density [4].
in protecting systems against surge currents. The MPS
structure was introduced in SiC diodes by merging p-i-n Surge Current and Pulsewidth for SiC Diodes
and Schottky junctions at the anode. This improves the Second-generation SiC diodes from the Global Power Tech-
surge capability with little impact on the performance in nologies Group (GPTG) were subjected to forward-surge-
normal operation. current pulses lasting 10 ns, 250 ns, and 8.3 ms long, and
Compared with Schottky diodes, MPS diodes have a the maximum current that the device could pass without
higher surge tolerance, making them more robust. However, any parametric failure was recorded. GPTG Gen 2 SiC
the forward voltage drops more in MPS diodes, making them devices are MPS types [Figure 2(c)] with p-i-n junctions to
less efficient. Many SiC diode manufacturers are now releas- carry surge current. Current pulses 10 ns long were gener-
ing both MPS and Schottky diode products to cater to differ- ated by a custom laser pulse generator and passed through
ent applications. The MPS diode version is often designed for the device in forward bias. The current through and voltage
higher performance with lower leakage current and lower across the device were measured with a Tektronix oscillo-
thermal resistance, whereas the Schottky diode version scope, as shown in Figure 3. To reduce pulse rise-time
has a smaller area and forward-voltage drop ^Vf h but higher delays due to parasitic inductance, the surge-generator cir-
leakage current. Table 1 shows this tradeoff in the datasheet cuit was carefully designed to connect the devices in TO-220
packages directly without lead wires to the pulse generator
through a pneumatic actuator switch.
Table 1. The features of SiC diodes designed A sample of 10 parts of each device type was selected for
for robustness (A) and efficiency (B). each test. Forward bias voltage at the rated current, reverse
breakdown voltage, and reverse bias leakage current at the
Features Version
rated voltage were measured before the surge test to con-
A B firm that the devices were within datasheet limits. After sub-
Rating Voltage (Vr) 650 650 jecting each part to one surge-current pulse, device parame-
ters were reconfirmed for accuracy, and then the amplitude
Current (If ) 6 6
of the surge pulse was increased. This procedure was
Voltage (V) 1.5 1.25
repeated until any of the device parameters degraded, at
Current (nA) 0.3 >1 which point, the amplitude of the current and voltage of the
Capacitance (pF) at Vr = 0V 190 302 final surge pulse applied before failure was recorded as the
at high Vr 24 17 failure current and voltage of the part, respectively. The
Surge current (A) 291 410 average failure current and voltage across the 10 samples
at 10 ns
were then calculated. The maximum variation of failure cur-
at 10 ms 54 38
rent between the samples was 10% above and below the
Thermal resistance (K/W) 1.5 1.7 average value. A similar test apparatus was used with a

36 IEEE Power Electronics Magazine z March 2019

­ ektronix 371 A curve tracer to generate 250-ns -long cur-
T wave, while the surge pulse in a PFC circuit might be
rent pulses, and, with a power-frequency transformer, to closer to a rectangular wave. However, because the gen-
generate 8.3-ms-long current pulses. The same experiment eration of heat causes failure, the same argument can
as was done for the 10-ns test was conducted next. Figure 3 be made to allow root-mean-square current to replace
shows a 10-ns -long current and voltage pulses applied in current in (1):
forward bias to a 650-V, 5-A GPTG diode in a TO-220 pack-
age (GP2D005A065A) with the amplitude ~90 A and ~15 V
that did not cause device failure. Surge-failure current at a
Voltage: 5 V per Division
certain pulsewidth is defined as the maximum current veri-
fied to have been carried by the diode without failure in any
device parameter.
Figure 4 shows that, at low pulsewidths between 10
and 250 ns, failure current does not fall significantly
with pulsewidth, which could be because the pulses
Current: 50 A per Division
are still short enough that most of the heat dissipation
happens before 10 ns. During the initial rise time of
the pulse, injection of the opposite carrier type has not
yet modulated the conductivity of the diode, and larger
power is dissipated compared to the power dissipation
later in the pulse when diode conductivity has been
reduced due to opposite carrier modulation. At pulse-
FIG 3 Current (blue) and voltage (violet) pulses 10 ns long,
widths above 250 ns, when the diode is in a low-conduc- measured during the forward-surge operation of an SiC diode.
tivity state only for a small fraction of the pulsewidth, The pulse driver signal (yellow) of the tester is also shown.
failure current reduces with the pulsewidth in such a
way that measured energy dissipation density is fairly
constant (Figure 4) [4]. This behavior, shown across mul-
250
tiple device current ratings at both the 600- and 1,200-V
range, indicates an inverse proportionality between
200
heat/power generation (higher surge current) and time
Failure Current (A)

period (longer surge pulse).

In PFC circuits, inrush current is typically in the range 150
of 100 ns to 10 ms [5]. We show that the energy density
for device failure is approximately constant in that range. 100
The length of surge pulses depends on the power quality 5 A, 600 V
of the input as well as on whether the circuit uses effective 50 6 A, 600 V
8 A, 1,200 V
surge-­detection relays and bypass diodes. Manufacturers
typically report maximum surge current (I f sum) at 8.3 or 0
10 100 1,000 10,000
10  ms (with the half-sine period at 50 or 60  Hz), which
Pulsewidth (µs)
is often longer than the duration of inrush currents that (a)
engineers typically anticipate in their designs. However,
the broad relationship in Figure 4 between the energy-
Failure Energy Density (mJ/mm2)

dissipation density at the failure and pulsewidth allows 1,000

us to arrive at broad design guidelines. In forward surge
and at pulsewidths 2250 ns, diode voltage is high enough
and conductive in p-i-n junctions long enough to disregard
transient effects and knee voltage and to assume Vf a I f . 100
Thus, energy-dissipation density for the same device is
proportional to I 2f # Ts, where Ts is the surge pulsewidth 5 A, 600 V
6 A, 600 V
and is 2500 ns. Then, the inrush current and pulsewidth 8 A, 1,200 V
follows the design guideline:
10
10 100 1,000 10,000
I 2
f surge Tsurge = I 2
f sm T f sm .(1) Pulsewidth (µs)
(b)

The value T f sum is either 8.3 or 10  ms in most data- FIG 4 The variations of (a) surge current and (b) energy density
sheets. Additionally, I f sum is often reported as a half-sine with the pulsewidth.

March 2019 z IEEE Power Electronics Magazine 37

 I 2f surge rms Tsurge = I 2f sm rms # T f sm . (2) impact of inrush current on the power system could
be  severe. Such standards as IEC61000-3-3 limit the maxi-
mum inrush current that can be drawn, for which ­further
For specifically a half-sine pulse at 8.3 ms, schemes are necessary.

I 2f sm 8.3 ms
I 2f surge rms Tsurge = # 8.3 ms. (3) Negative Temperature Coefficient Resistance
2
Inrush typically happens when the system is turned on
Such a design rule, with an appropriate margin, can be after a hiatus and, hence, is cold. So a series resistance
used to adapt the forward-surge-current limits reported (Figure 5) with a negative temperature coefficient (NTC)
in datasheets while selecting an SiC diode for a given PFC of resistance can reduce the total inrush current while
circuit design problem. However, when designing for fast adding little parasitic resistance during normal “hot” oper-
pulses with 1100 -ns pulsewidth or ation. NTC resistance can then be
even 1-ns- range electrostatic dis- designed for the constraint in (4).
charge (ESD) events, the circuit de­­ However, NTC resistance alone will
signer might reasonably impose only The challenge of not prevent high inrush current in
a current density limit, as shown in improving both the case of an off–on toggle when the
Figure  4. In the absence of specific NTC resistance is still hot while sub-
measurements using transmission line
efficiency and surge jected to inrush current:
pulses, an SiC diode can be designed performance in diodes V
for a 1-ns- long human body model I Surge Max NTC = R ac .(4)
ESD event to restrict the current den-
is just one part of the NTC Cold

sity to the limit at 10 ns, which is spec- problem of designing

ified in the datasheet.
a robust PFC converter.
Circuit Improvements
for SiC Diodes
The challenge of improving both effi-
ciency and surge performance in diodes is just one part of
the problem of designing a robust PFC converter. Another
challenge is to find additional circuit elements that can
reduce inrush current or divert it from the SiC diode [5]. To
avoid interfering with normal operations, such circuit ele-
ments distinguish the inrush condition from any normal
operation. The commonly used techniques for this are
given next.
Bypass Diode
Inrush current spikes the voltage across the boost induc-
tance (Figure 1), which forward biases the bypass diode
and shunts inrush current going through it. However, in
normal conditions, high Vdc holds the bypass diode in
reverse bias and prevents it from adding capacitance to the
switching process. Such protection might be enough for
the circuit to survive this inrush current. However, the
iac Dp
L Dpfc
vac
RNTC I(L)
S1
ac Source Rectifier Boost PFC Filter Load
FIG 5 A diagram showing a PFC boost converter with circuit
elements for surge protection.
Relay Shunted NTC Resistor
NTC resistance in Figure 5 can be
further shunted by a switch or relay
controlled by the output voltage
Vout such that when C is charged up
in normal operation, the resistance is shorted out from
the circuit. In this case, the highest possible inrush cur-
rent will occur in an off–on toggle situation where the
output voltage has been sufficiently reduced in the off
state to cause a current surge but not enough (Vdc trigger)
to trigger the switch to stop shunting the inrush-limiting
resistance. In such a case, the surge current through the
NTC resistance can be designed as in (5) to be less than
the maximum allowed:
Vac - Vdc trigger
I Surge Max NTC Shunt = R NTC Hot 1 I Surge Max NTC .(5)
Potential Circuit Improvement
In a particular PFC application using a 650-V, 10-A SiC
diode, the 220-V ac input voltage produced a 250-A (25×
rated current) triangular surge inrush current pulse last-
ing 3 ms after a cold turn on, which requires a specialty
diode capable of handling high surges. However, by add-
ing a bypass diode, NTC resistor, and relay, this surge
current through an SiC diode was reduced to 1100 A, and
the PFC converter circuit would be made more robust.
+ This circuit improvement allowed the use of a cheaper
C
RL Vdc and lower static loss SiC diode rated for lower surge cur-
– rent (100 A versus 250 A) to maintain an overall robust-
ness at a higher circuit efficiency. In  this example, the
codesign of an SiC diode and circuit techniques allowed a
cheaper overall circuit bill of materials than separate
designs would at the device or circuit levels.

38 IEEE Power Electronics Magazine z March 2019

Switch in PFC Circuit
Another critical active element of a PFC converter is the
semiconductor switch. Over the last decade, many PFC
designs have replaced older Si MOSFETs and IGBTs with
Si superjunction MOSFETs [2], which have a lower
capacitance and, hence, lower switching loss. After SiC
MOSFETs entered the fast power switch market, studies
considered the advantages of using these devices as PFC
switches  [6]. However, challenges with the SiC MOS
channel limit their performance vis-à-vis cost at the 650-V
range. Since SiC devices have a thinner drift region and,
therefore, higher specific capacitance than Si devices, a
substantial reduction in chip area is desired to reduce
capacitance. On-state voltage is higher, and the ratio of
gate-source to gate-drain capacitance is  lower in an SiC
MOSFET. Therefore, they also need ­different gate drivers
than what are used for Si trench ­s uperjunction MOS-
FETs. However, if the intense research efforts currently
underway improve the gate oxide quality and reliability
of SiC MOSFETs, then both conduction and switching
losses in PFC circuits can be reduced, especially when
operating at higher junction temperatures than currently
possible with Si devices. GaN switches are also a rapidly
maturing technology. These switches, being ­lateral
devices, can be monolithically integrated with gate driv-
ers, thus providing a more robust high-frequency switch
at 650 V [6].
Summary
This review of the successful adoption of SiC Schottky
diodes in PFC converter circuits focused on the impact of
SiC diode design in relation to how well the circuit stands
up to inrush surge currents. We showed from device-level
data that the designs for surge immunity depend on the
surge-current pulse characteristics. A simultaneous optimi-
zation of device and circuit design improvements can make
circuits more robust while achieving the higher efficiency
promised by SiC devices. Depending on efficiency targets
and the exposure to surge currents, a beneficial tradeoff
between these design parameters can be made. Specifically,
improvements to the PFC circuit while using an SiC device
of medium surge performance might provide higher overall
efficiency at less cost than simply replacing Si devices with
the most robust SiC device. Finally, we anticipate SiC MOS-
FETs with expected performance improvements to soon be
a viable PFC switch.
About the Authors
Rahul Radhakrishnan Potera (rahulrad@gmail.com)
received his B.Tech. degree from the National Institute of
Technology Calicut, India, in 2004 and his Ph.D. degree in
solid-state electronics from Rutgers University, New Jersey,
in 2012, both in electrical engineering. He has more than
10  years of experience working on power semiconductor
devices and is currently a device engineer with the Global
Power Technologies Group. He has authored 10 peer-
reviewed journal and conference articles and three patents
(pending and granted). He has previously worked on power-
­integrated circuit design and protection at Texas Instru-
ments, Dallas, and power-circuit breakers at Larsen & Tou-
bro, Mumbai, India.
Timothy Junghee Han (jhhan@gptechgroup.com)
received his B.S. and M.S. degrees in electrical engi-
neering from Busan National University, South Korea,
and his Ph.D. degree in electrical engineering from the
Korea Advanced Institute of Science and Technology
Daejeon. He is a senior manager of the Global Power
Technologies Group. He has 25 years of experience in
semiconductor devices, silicon carbide power devices
and packaging, optical components and packaging, and
simulation of power electronics modules and systems.
He has recently been involved in designing and develop-
ing advanced power electronics modules and subsys-
tems using silicon carbide devices for next-generation
hybrid electric vehicles and the alternative energy
industry. He has authored 23 technical journal papers
and 12 patents and given 14 presentations at prestigious
international conferences.
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March 2019 z IEEE Power Electronics Magazine 39