Radio Frequency DC-DC Power Conversion PDF

Radio Frequency dc-dc Power Conversion
by
Juan Rivas
B.S., Monterrey Institute of Tech.(1999)
S.M., Massachusetts Institute of Tech.(2003)
Submitted to the Department of Electrical Engineering and Computer Science

in partial fulfillment of the requirements for the degree of
Doctor of Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
September 2006
@ Massachusetts Institute of Technology, MMVI. All rights reserved.
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S epartment of Electrical Engineering and Computer Science

September 29, 2006
Certified by.
7/ David J. Perreault
-----manuel E. Landsman Associate Professor
Thesis Supervisor
Accepted by
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Arthur C. mit
Chairman, Department Committee on Graduate Stude s
MASSACHUSETTS INSTITUTE
OF TECHNOLOGY
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Radio Frequency dc-dc Power Conversion
by
Juan Rivas
Submitted to the Department of Electrical Engineering and Computer Science

on September 29, 2006, in partial fulfillment of the
requirements for the degree of
Doctor of Science
Abstract
T HIS THESIS addresses the development of system architectures and circuit topologies
for dc-dc power conversion at very high frequencies. The systems architectures that
are developed are structured to overcome limitations associated with conventional designs.
In particular, the new architectures described here structure the energy processing and
control functions of the system in such a manner that high efficiency can be achieved across
wide load range while regulating the output. Moreover, these architectures are amenable to
circuit designs operating at fixed frequency and duty ratio, considerable easing the circuit
design.
The thesis also develops new circuit designs that are well suited to these new architectures.
As part of this, two new gate drives and control methods are introduced that greatly reduce
gating loss at VHF frequencies for fixed frequency, fixed duty ratio operation. One of these
gating schemes provides near theoretical minimum loss by resonantly wave shaping the
gate voltage to have a trapezoidal drive voltage. This waveshaping approach is then taken
a step further, yielding a new class of dc-dc converter that archives a significant reduction
in peak switch voltage stress, requires small passive components with low energy storage,
and provides the capability for extremely rapid startup and shutdown. This new class of
converter is well adapted to the architectures and gate drive methods proposed in the thesis.
It is expected that the new architectures and circuit designs introduced here will contribute
to the development of power converter having greatly reduced size and improved transient
performance.
Thesis Supervisor: David J. Perreault

Title: Emanuel E. Landsman Associate Professor
Acknowledgements
I want to thank Prof. David J. Perreault, my thesis advisor, for his guidance, patience, and
support during the course of this journey. He is and outstanding engineer and educator.
My thanks go to my thesis committee: Prof. John Kassakian, Prof. Steve Leeb, and Prof.
Charlie Sullivan for their support, advice and direction.
Thanks to the sponsors of my work: DARPA, General Electric, and The MIT Automotive
Consortium.
I want to acknowledge the contributions and all things learned from other members of my
research group, all excellent individuals and good friends: Yehui Han, Olivia Leitermann,
Joshua Phinney, Anthony Sagneri, Robert Pilawa, Jackie Hu, David Jackson, James Warren,
Riad Wahby and John Shaffran.
I'm also grateful for all the help provided by my colleagues and staff from LEES: Dr.
Thomas Keim, Gary DesGroseilliers, Vivian Mizuno, and Wayne Ryan.
I would also like to thank the students that took 6.334 during the Spring semester of 2002,
2003 and 2005.
This work is also dedicated to my friends that have support me during my graduate studies:
In Boston: to my friends Antonio Lay6n, Ernesto Arroyo, Rachel Holley, Song-Hee Paik,
Catarina Bjelkengren, Dasha Lymar. In Mexico: Antonio Monterrubio, Edgar Matamoros,
Dr. Javier Elguea, Saul G6mez, Pilar Burguete, Tere Burguete, and Tofio Burguete.
I owe my deepest gratitude to my parents Carlos and Leticia, my siblings (also Carlos and
Leticia). Without their love and support I would not be where I am today.
-5-
The nature of Engineering
Reflection on the engineering practice:
"It is a great profession. There is the fascination of watching a

figment of the imagination emerge through the aid of science to a
plan on paper. Then it moves to realization in stone or metal or
energy. Then it brings jobs and homes to men. Then it elevates
the standards of living and adds to the comforts of life. That is the
engineers high privilege".
Years of Adventure, 1874 - 1920. President Herbert Clark Hoover (1874-1964)
-7-
Contents
1 Introduction 23
1.1 Challenges of High-Frequency Power Converter Design . ........... 24
1.2 Radio-Frequency Power Amplifiers . .................. .... 25
1.3 Thesis Objectives and Contributions . ................ . ... . 26
1.4 Organization of the Thesis ............................ 27
2 New Architectures for VHF Power Conversion 29

2.1 New Converter Architectures .......................... 29
2.1.1 Vernier-Regulated Architecture . .................. .. 30
2.1.2 Cell-Modulation-Regulated Architecture . ............... 32
2.1.3 Related Architectures .......................... 34
2.2 100 MHz Unregulated Cell Design ....................... 35
2.2.1 Class E Resonant Inverter .. . ...... ........ .... .. . 35
2.2.2 Self-Oscillating Gate Driver . .................. .... 36
2.2.2.1 Phase shift/feedback network . ................ 37
2.2.2.2 On/off and startup circuit . ................. 38
2.2.3 Matching Network and Rectifier . .................. . 39
2.2.4 Experimental Results .......................... 41
2.3 A Vernier-Regulated System ......................... 44
2.3.1 Converter Implementation ................... ..... 44
2.3.2 Experimental Results .......................... 45
2.4 A Cell-Modulation-Regulated System . .................. ... 48
2.5 Discussion on the Directions and Emerging Opportunities . ......... 49
2.5.1 RF Circuit Topologies .......................... 50
-9-
Contents
2.5.2 D evices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 53
2.5.3 Application Areas and Future Development . ............. 55
2.6 Conclusion ................... ............... .. 56
3 Design Considerations for VHF dc-dc Converters 57

3.1 System Structure and Control .................. ....... 57
3.1.1 Background ............ .................. .. 57
3.1.2 Converter System Structure . . . . . . . ......... .... 58
3.2 Self-Oscillating Multi-Resonant Gate Drive . ................. 61
3.3 Resonant Radio-Frequency Rectifier . . . . . . . . . . . . . . . . . ...... . . 68
3.4 Experimental Results and Evaluation . . . . . . . . . . . . . . . . . ...... . . 70
3.5 Conclusion .................................... 78
4 An Advanced Resonant Inverter Topology 81

4.1 Background .................................... 81
4.2 A New Class-4 based Inverter Topology . .................. . 83
4.2.1 The Class-) 2 Inverter .......................... 84
4.3 Design procedure for the 4I2 Inverter . .................. ... 85
4.3.1 General Overview ............................ 85
4.3.2 Tuning Procedure ............................ 86
4.3.2.1 Component Selection of the Reactive Interconnect Xs . .. 86
4.3.2.2 Initial Sizing of the elements of ZMR . . . . . . . . . . . . 87
4.3.2.3 Achieving the Important Characteristics of Zd, . . . . . . . 88
4.4 Practical Design of a 30 MHz P2 inverter . .................. 89
4.4.0.4 Importance of the Relative Impedances ratio at the Funda-
mental and Third Harmonic . ................ 94
4.4.0.5 Summary of the Inverter Design . .............. 95
4.5 42 Inverter Implementation ........................... 96
4.5.1 Inverter Implementation ......................... 96
4.5.1.1 Placement of resonant elements . .............. 98
4.5.1.2 Verification of the impedance Zds . ............. . 99
- 10 -
Contents
4.5.1.3 Implementation of the Gate Drive . ........ . . 100

4.5.2 Experimental Performance of the inverter . ........... 101
4.5.3 Output Power Measurements and Performance . ........ 107
5 A 'P2 Dc-Dc Converter 109

5.1 Background ............................ . . . . . . . . 109
5.2 A New P2 dc-dc Converter ................... .. . . . .. . 110
5.3 Alternative Implementations of P2 -Based dc-dc Converters . . . . . . . . . 111
5.4 Example design of a Class ( dc-dc converter . . . . . . . . . . . . . . . . . 113
5.4.1 Resonant Rectifier Design ................ ........ 114
5.4.2 %2 Inverter Design .................... . .. . . . .. 116

5.4.3 Summary of the design and expected performance . . . . . . . . . . 119
5.4.4 On the Expected Transient Performance of the ( 2 -Based dc-dc converter 121
5.5 2 dc-dc Converter Implementation .............. . . . .. . . . 125
5.5.1 Gate Drive Implementation . .............. . . . . . . . . 127
5.5.2 Summary of Component Values . ............ . . . . . . . . 129
5.6 Experimental Performance of the (2 dc-dc Converter ..... . . . . . . . . 130
6 Summary and Conclusions 133

6.1 Thesis Summary ................................ 133
6.2 Thesis Conclusions ............................... 134
6.3 Future Work .................................. 135
A Low Order Lumped Network derivation 137

A .1 D erivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
B 100 MHz dc-dc converter PCB layout 141
C Trapezoidal gate-drive PCB layout 147
D Trapezoidal start-up PCB layout 153
- 11 -
Contents
E (2 Inverter PCB layout 157

E.1 RF Load PCB .................................. 162
F 52 Dc-Dc Converter PCB layout 165
G PSPICE files 175

G.1 42 Inverter ........ ............................ 175
G.2 42 dc-dc Converter .... ............................ 180
G.3 Measurement sub-circuits ............................ 185
G.4 Sub-circuit Library .... ............................ 188
Bibliography 197
- 12 -
List of Figures
1.1 The Class E Inverter (a) and the Class E Rectifier (b) can operate with good
efficiency at RF frequencies. .......................... 26
2.1 A block diagram illustrating the Vernier-regulated converter architecture. . 30

2.2 An activation scheme for unregulated cells. Unregulated cells are activated
or deactivated based on the load on the regulating cell. U is the incremental
loading change when an unregulated cell is activated or deactivated. B is
the minimum load on the regulating cell, below which an unregulated cell is
deactivated. H is a hysteresis value to prevent chattering at boundaries. . . 31
2.3 A low Th6venin impedance at the regulating cell provides a tight regulation
of the output. A high Thevenin impedance in the unregulated cells result in
proper current sharing ............................. 32
2.4 A block diagram illustrating the cell-modulation-regulated converter archi-
tecture ...................................... 33
2.5 A simplified model of the Class-E resonant inverter. . ........... . 35
2.6 Idealized vds(t) and its fundamental (dotted line). The gate signal is also
shown. The phase angle between the fundamental component of the drain
voltage and the idealized gate signal is 1630. . ................ . 36
2.7 Simplified phase shift/feedback network. . .................. . 37
2.8 Magnitude and Phase of the transfer function - (w) for the proposed feed-
back network ... ............ .. ... .. ...... ..... ... 38
2.9 Self-oscillating resonant gate driver circuit. . .................. 39
2.10 Unregulated 100 MHz switching dc-dc power converter cell. Component val-
ues and important parasitics are enumerated in Table 2.1. .......... . 41
2.11 Cell performance as a function of supply voltage into a 5.1 V load. ...... 42
2.12 A photograph of the unregulated cell circuit board. . .............. 42
2.13 Measured drain-source voltage under nominal operating conditions at VI =
11V................... ..................... 43
- 13 -
List of Figures
2.14 Attenuated drain-source voltage during turn-on and turn-off transients. In

both cases, the command occurs at t = 0. The drain-source voltage was mea-
sured via an attenuator network that reduced DC voltage by approximately
a factor of 38; AC voltages are attenuated somewhat further. . ...... . 43
2.15 Simplified schematic of the Vernier cell and system controller. ......... 44
2.16 Efficiency versus output power of the Vernier-regulated system for Vin = 11 V.
In this experiment, the load was swept from 25 Q to 1 Q and then back to
25 Q, demonstrating the hysteretic characteristic of the controller. ...... 46
2.17 Efficiency versus output power of the Vernier-regulated system for Vin = 16 V,
25 2 2> Rload 2 0.46 S1. The theoretical efficiency expected under the same
conditions when utilizing a low-power control circuit in place of the tested
implementation is also shown ................... ........ 47
2.18 Dynamic performance of the Vernier-regulated converter with Vin = 11 V
under a load step from 1000 Q to 3 Q£ ...................... 47
2.19 Improved self oscillating gate driver with fast on/off control. ......... . 48
2.20 Transient behavior of the cell-modulation-regulated system under a step
change in load (27 2 to 13.5 R, Vin = 16 V). . .............. . . 49
2.21 Efficiency vs. output power of the Cell-modulation-regulated system at
Vin =11V and 16V.................... ............ 50
2.22 Efficiency vs. input voltage of the Cell-modulation-regulated system at Pout =2W. 51
3.1 A block diagram illustrating the structure of a high frequency dc-dc converter. 58
3.2 Schematic of a 100 MHz dc-dc converter. . ................... 59
3.3 Schematic of the multi-resonant gate drive. The input impedance ZIN, when
properly tuned, peaks in the vicinity of the fundamental and the third har-
monics and has low impedance at the second harmonic. . ........ . . 62
3.4 Simple multiresonant network. ......................... 63
3.5 Input impedance vs. frequency of the simple multiresonant structure shown
in Fig. 3.3 when the reactive elements follow the relations given in Equation 3.4. 64
3.6 Gate to source voltage at input of the main MOSFET of the converter. . .. 65
3.7 Simplified schematic circuit of the startup control strategy. . ......... 65
3.8 Simulated input impedance at the drain of the auxiliary switch of Fig. 3.7.
This simulation accounts for parasitics in the PCB and assumes linear de-
vice capacitances and 0.7 nH lead inductance in series with the gate of the
main LDMOSFET. Notice that the phase-shift network does not significantly
change the impedance at the frequencies of interest (fundamental, 2 nd and
3 rd harmonic). .................................. 66
- 14 -
List of Figures
3.9 Simulated magnitude and phase of the transfer function Vgate/Vdrain of the
auxiliary LDMOSFET. At the switching frequency (100 MHz), the phase
shift is -180 . .. .................... ... ........... 67
3.10 Simulated gate voltages at the gates of the main and auxiliary switches. The
switching frequency f,=102.2 MHz ........................ 68
3.11 Resonant rectifier connected to a constant output voltage. The resonant
capacitance Cr is the sum of the diode capacitance CD and an (optional)
external capacitance CEXT. CEXT may also be placed directly in parallel
with the diode. ................................. .. 69
3.12 Rectifier input voltage and input current, when driven by a sinusoidal current
source IIN at a frequency of 100 MHz. The resonant rectifier is delivering
6.2 W to a 12 V output .................... .......... 70
3.13 Power stage of the prototype 100 MHz dc-dc power converter. ........ . 71
3.14 Drain to source voltage and gate to source voltage of the prototype converter.
Also shown is the voltage at the input of the transformation stage. Values
are shown for a dc input voltage of 11 V and dc output voltage of 12 V. . . 74
3.15 Output voltage ripple and modulation control signal during steady state op-
eration. VOUT,DC = 12 V, POUT = 10 W, VIN = 16 V. . . . . . . . . . . . . 75
3.16 Schematic of the hysteretic controller. . .................. .. 76
3.17 Output voltage ripple and modulation control signal during a load step.
POUT is changed from 4W to 8W. ....................... 76
3.18 Drain to source voltage and control signal during startup and shut down of
the converter in on/off control. VIN=11 V, VOUT=12 V. The cell is fully on
in 600 ns and turns off in about 600 ns. .................... 78
3.19 Efficiency vs. input voltage at different output power levels. Vot=12 V. . . 78
4.1 Class E inverter (left) and 2nd harmonic Class E inverter (Right). Inductor
L 1 in the 2 nd harmonic Class E is a resonant element; this reduces the energy
storage requirements and achieves a faster transient response compared to a
conventional class E RF inverter. . .................. ..... 82
4.2 (a) Simple low-order lumped network. Example of IZINI vs. frequency is
shown in (b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . 84
4.3 Class 4D2 inverter .................................. 85
4.4 Model at the fundamental frequency used to size the components of the
reactive interconnect network ................... ........ 87
- 15 -
List of Figures
4.5 Magnitude of the impedances ZMR, ZL and Zd, the Class )2 inverter (at
an intermediate point in the tuning process). Zd, is equal to ZMRIIZL. For
this example CF=20 pF, LF=625.4 nH, CMR=18. 7 5 pF, LMR=375.26 nH.
Ls=257 nH, Cs=4 nF, Cp=75.42 pF (35.4 pF remaining from the switch
plus 40 pF external capacitance) ................... ...... 91
4.6 (a) Plot of the impedance Zd, vs. frequency. (b) Drain to Source voltage.
VIN=160 V, f,=30 MHz. For this example LF=625.4 nH, CMR=18.75 pF,
LMR=3 7 5. 2 6 nH. Ls=257 nH, Cs=4 nF, Cp=40 pF .............. 92
4.7 Magnitude of the impedances ZMR, ZL and Zd, the Class OI2 inverter. For
this example CF=20 pF, LF=270 nH, CMR= 1 8 .7 5 pF, LMR=375. 2 6 nH.
Ls=257 nH, Cs=4 nF, Cp=75.42 pF (35.4 pF remaining from the switch
plus 40 pF external capacitance). Notice that the peaks in ZMR are now at
a higher frequency. ...................... .......... 92
4.8 (a) Shows the magnitude and phase of Zd, vs. frequency. (b) Shows a
transient simulation of Vd, of the #2 inverter. Here, VIN=160 V, f,=30 MHz.
Components values are: LF=270 nH, CMR=18.75 pF, LMR=-3 7 5 . 26 nH. Ls=257 nH,
Cs=4 nF, Cp=40 pF. The MOSFET capacitance is modelled as C,,, = Co/(1+
2&)m with values that change dynamically as follows: Co = 2478 pF, '00 =
1.088 V, m-0.6946 for 0 < vds(t) < 14.5 V and Co = 2478 pF, b0 = 0.38 V, m-
0.6285 for 14.5 < vd,(t) • 500 V. Parasitic components for the time-domain
simulation also include parasitic inductances in the MOSFET (1.5 nH at the
drain, 1 nH at the source)............................ 93
4.9 (a) Shows the magnitude of Zds vs. frequency for different tuning having
the same impedance magnitude at the fundamental frequency, but different
impedance magnitudes at the third harmonic. these things were achieved by
selecting different values for Cp and keeping the impedance magnitude at the
fundamental constant by adjusting LF. (b) shows how Vd,(t) changes as the
impedance ratio between the magnitude at the fundamental and the third
harmonic is varied. The thicker line highlights the actual design selected for
the prototype system . ..... ............... .......... 94
4.10 Schematic of the (2 Inverter. .......................... 96
4.11 Magnitude and phase impedance of a 250 V 1lF ceramic capacitor Cbias.
This capacitor is used as CBIAS and as part of CIN in Fig 4.10. ....... . 97
4.12 Experimental Class 42 inverter. . .................. ...... 100
4.13 Experimental Class 12 inverter. The capacitor CBIAS provides dc isolation
and allows biasing of the ARF521 MOSFET to obtain the impedance plots
necessary for tuning ............................... 101
4.14 RF Load. ..................................... 102
4.15 Drain to Source Impedance vs. Frequency when VIN=160 V . . . . . . . . 103
- 16 -
List of Figures
4.16 Gate drive circuit schematic. In this prototype, RG,DC=10 kM LG,DC=568 nH

and CG,RF=5 nF. The RF source is a 50 l-output power amplifier. ...... 103
4.17 Experimental Class )2 inverter connected to the RF Load. . ......... 104
4.18 Bench setup of the Class @2 inverter connected to the RF Load. The signal
generator output is amplified by the RF Power Amplifier which drives the
gate of the RF MOSFET in the 42 Inverter. . .................. 104
4.19 Drain to source and gate voltage with VIN=160 V . . . . . . . . . . . . . . 105
4.20 Drain to source voltage for 160 V• VIN <200 V. The peak drain voltage to
input voltage ratio is N2.4 ............................ 105
4.21 Comparison between experimental measurements and simulation: (left) Drain
to source voltage ,(Right) Load voltage. Both plots at VIN=160 V. .... .. 106
4.22 Magnitude and phase vs. frequency of the impedance of the RF load con-
nected to two parallel 75 Q coaxial cables of the same length. ........ . 107
4.23 Load voltage when VIN=180 V. The table shows the harmonic content of the
waveform . .................... ................. .. 108
4.24 Output power and drain efficiency vs. input voltage for the class @2. ..... 108
5.1 (a) Shows the Class E inverter. (b) shows the )2 resonant inverter, in which
the passive elements are all resonant. . .................. ... 110
5.2 High-frequency resonant dc-dc converter. ................... . 110
5.3 Dc-dc converter implementing using an autotransformer. . ........... 112
5.4 Dc-dc converter providing electrical isolation. The magnetizing inductance of
the transformer provides the needed dc current path and is utilized to tune
the rectifier. The leakage inductance of the transformer forms part of the
reactive network that controls the amount of power delivered to the rectifier 112
5.5 Dc-dc converter with an alternative rectifier ................... 113
5.6 Dc-dc converter implementing synchronous rectification. . ......... . 113
5.7 CSD10030 diode capacitance vs. bias voltage. The figure compares measured
values to the model used for the design. . .................. . 114
5.8 Resonant rectifier ................................ 115
5.9 (a)Rectifier voltage and its fundamental component. (b) Fundamental com-
ponent of the input voltage and input current. POUT = 200 W. f, = 30 MHz,
LR=75 nH, QL=160. The equivalent resistance of the rectifier under this con-
dition is 8.4 . .................................. 116
- 17 -
List of Figures
5.10 Rectifier impedance magnitude and phase (at the fundamental) as a func-
tion of the output power. For this implementation f,=30 MHz, LR=75 nH,
QL=160. C, is entirely provided by the device capacitance of two paral-
leled CSD10030 SiC Diodes. Over a wide output power range, the equivalent
impedance of the resonant rectifier can be considered as being purely resistive.117
5.11 Simulated efficiency vs. output power of the resonant rectifier. For this
implementation f,=30 MHz, LR=75 nH, QL=160. . ............. . 118
5.12 Simulated drain to Source voltage and Converter performance over the op-
erating input range 160 V < VIN < 200 V . .................. 120
5.13 Simulated semiconductor and magnetic losses of the dc-dc converter over the
operating input range 160 V _< VIN 5 200 V. . ............... . 121
5.14 Fundamental component of the voltage and the current at the input of the
resonant rectifier of the dc-dc converter over the operating input range 160 V
_ VIN 200 V .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.15 Simulated drain to source voltage at turn-on for the example design of Sec-
tion 5.4 Here, VIN = 160 V. The low energy stored in the passive components
permits fast transient response. With the components of Table 5.1, Vd,(t)
reaches steady state within 10 switching cycles. . ................ 123
5.16 Components CSdamp and RSdamp in Fig. 5.3 damp the low frequency oscil-
lations occurring every time the dc-dc converter is activated. (a) Shows the
voltage vds(t) when the damping components are omitted and (b) shows
Vds(t) with RSdamp = 10 Q1 and CSdamp=1 2 pF. . . . . . . . . . . . . . . . . 123
5.17 Simulated energy loss per modulation cycle vs. VIN. The modulating fre-
quency which reduces the converter efficiency by 1% is 666 KHz. ...... . 124
5.18 Schematic of the D2 dc-dc converter. Component values listed in Table 5.1. 125
5.19 Photograph of the prototype D2 dc-dc Converter showing the heat sinks
attached to the semiconductors......................... .. 126
5.20 (2 dc-dc Converter and 33 V dc load ..................... 127
5.21 Prototype 42 dc-dc Converter. ......................... 128
5.22 Drain to Source Impedance vs. Frequency when VIN=160 V . . . . . . . . 128
5.23 Experimental MOSFET drain to source and gate voltage at VIN=160 V. . . 130
5.24 Experimental drain-to-source voltage Vd, for 160 V< VIN •200 V. The peak
drain voltage to input voltage ratio is -2.35. . ................. 131
5.25 Experimental startup transient response (to application of the gate drive) of
the #2 converter at VIN=160 V. Vd,(t) reaches periodic steady-state in less
than 300 ns. .................................. 132
- 18 -
List of Figures
5.26 Experimental output power and drain efficiency vs. input voltage for the
prototype dc-dc converter ............................. 132
A.1 Simple low-order lumped network . . . . . . . . . . . .. . . . . . . . . . . 137

A.2 IZFI, IZMRI and IZINI vs. frequency for the low-order network shown in
Fig. A.1 and tuned to have impedance poles at f=100 MHz and f=300 MHz
and zero impedance at f=200 MHz .................. .... . 138
B.1 100 MHz dc-dc PCB Schematic. ........................ 141

B.2 100 MHz dc-dc PCB Board. .......................... 142
B.3 100 MHz dc-dc PCB Board. Top copper layer. . .............. . 142
B.4 100 MHz dc-dc PCB Board. Top silkscreen layer. . ............. 143
B.5 100 MHz dc-dc PCB Board. Top cream layer. . .............. . 143
B.6 100 MHz dc-dc PCB Board. Top stop layer. . ............... . 144
B.7 100 MHz dc-dc PCB Board. Bottom copper layer. . ............ . 144
B.8 100 MHz dc-de PCB Board. Bottom silkscreen layer. . .......... . 145
B.9 100 MHz dc-dc PCB Board. Bottom stop layer. . ............... 145
B.10 100 MHz dc-dc PCB Board. Bottom cream layer. . ............ . 146
C.1 Trapezoidal gate-drive PCB SchemaLtic. ................... .. 147

C.2 Trapezoidal gate-drive PCB Board. .. . . .. . . .. . . . .. . . .. . . . 148
C.3 Trapezoidal gate-drive PCB Board. Top copper layer. . ............ 148
C.4 Trapezoidal gate-drive PCB Board. Top silkscreen layer. . .......... 149
C.5 Trapezoidal gate-drive PCB Board. Top cream layer. . ............ 149
C.6 Trapezoidal gate-drive PCB Board. Top stop layer. . ............. 150
C.7 Trapezoidal gate-drive PCB Board. Bottom copper layer. . .......... 150
C.8 Trapezoidal gate-drive PCB Board. Bottom stop layer. . ........... 151
C.9 Trapezoidal gate-drive PCB Board. Bottom stop layer. . ........... 151
D.1 Start-up PCB Schematic. ............................ 153

D.2 Start-up PCB Board. .............................. 154
D.3 Start-up PCB Board. Top copper layer. . .................. . 154
D.4 Start-up PCB Board. Top silkscreen layer. . .................. 154
- 19 -
List of Figures
D.5 Start-up PCB Board. Top cream layer. ..... . ....... 155
D.6 Start-up PCB Board. Top stop layer ....... . ....... 155
D.7 Start-up PCB Board. Bottom copper layer. . .. ..... 155
D.8 Start-up PCB Board. Bottom silkscreen layer. . . . . . . . 156
D.9 Start-up PCB Board. Bottom stop layer. ... . . . . . . . 156
D.10 Start-up PCB Board. Bottom cream layer. .. . . . . . . . 156
E.1 Inverter PCB Schematic. ............................ 157

E.2 Inverter PCB Board. .............................. 158
E.3 Inverter PCB Board. Top copper layer ...................... 158
E.4 Inverter PCB Board. Top silkscreen layer . .................. 159
E.5 Inverter PCB Board. Top cream layer . .................... . 159
E.6 Inverter PCB Board. Top stop layer . ..................... . 160
E.7 Inverter PCB Board. Bottom copper layer .................... 160
E.8 Inverter PCB Board. Bottom silkscreen layer. . ................ 161
E.9 Inverter PCB Board. Bottom stop layer. . ................... 161
E.10 RF Load PCB. .................................. 162
E.11 RF Load PCB: top copper layer. ........................ 163
E.12 RF Load PCB: top silkscreen layer. . .................. ... 163
E.13 RF Load PCB: bottom copper layer. ..................... 164
E.14 RF Load PCB: bottom silkscreen layer. ................... . 164
F.1 Dc-Dc Converter PCB Schematic. . . . . . . . . . . . . . . . . . . . . 165

F.2 Dc-Dc Converter PCB Board. ................ ....... 166
F.3 Dc-Dc Converter PCB Board. Top copper layer . . . . . . . . . . . . 167
F.4 Dc-Dc Converter PCB Board. Top silkscreen layer. .... . . . . . . . 168
F.5 Dc-Dc Converter PCB Board. Top cream layer . . . . . . . . . . . . 169
F.6 Dc-Dc Converter PCB Board. Top stop layer . . . . . . . . . . . . . 170
F.7 Dc-Dc Converter PCB Board. Bottom copper layer. .... . . . . . . . 171
F.8 Dc-Dc Converter PCB Board. Bottom silkscreen layer. . . . . . . . 172
F.9 Dc-Dc Converter PCB Board. Bottom stop layer. .... . . . . . . . 173
- 20 -
List of Tables
2.1 Component values in the unregulated cell. . ................... 40

2.2 Some Commercial 65 V/70 V Lateral Diffused MOSFETs and their figures of
merit. Note: Because some of these devices are intended for use in inefficient
amplifier classes, they are sometimes provided in rather unwieldy packages.
Also some recent devices require more sophisticated gate drivers for switched-
mode operation, such as the multi-resonant driver used in [1] and discussed
in a subsequent chapter .................... .......... 54
3.1 Equivalent impedance of the rectifier of Fig. 3.11. . ............... 71

3.2 Components used in 100 MHz dc-dc converter of Fig. 3.2. . .......... 72
3.3 Components used in the self-oscillating multi-resonant gate drive of Fig. 3.7. 73
3.4 Components used in the on-off controller board and auxiliary power supply
of Fig. 3.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.1 List of components for the 30 MHz, (2 inverter. The model of the Mos-
FET capacitance changes dynamically depending on voltage according to the
relations shown below ............................... 95
4.2 List of components for the 30 MHz, 160 V to 200 V O2 Prototype inverter. 99
5.1 List of components for the 30 MHz, #2 dc-dc converter. . ........... 119
5.2 List of components for the 30 MHz, 160 V to 200 V input 33 V output D2
prototype dc-dc converter ................... .......... 129
- 21 -
Chapter 1
Introduction
A SIGNIFICANT part of the cost and volume of modern electronic equipment is due
to the energy-conversion and energy-storage systems that they require. A challenge
of particular importance, and the subject of this work, is the miniaturization of power elec-
tronic circuits. Miniaturization of these systems is difficult because the power conversion
process requires passive elements with significant energy storage. Thus, design and man-
ufacturing methods that reduce energy storage requirements are very valuable in reducing
the size of power converters.
An important means for reducing the size of power circuits is through increases in switch-
ing frequency. The numerical value of the energy storage elements (e.g., inductors and
capacitors) needed to achieve a given conversion function varies inversely with switching
frequency (see, e.g., [2, Chapter 6]). Moreover, the increase in control bandwidth achiev-
able at higher switching frequencies often enables reductions in bulk energy storage at the
converter output. Increases in switching frequency, rising from tens of kilohertz in the early
1970's into the megahertz range today, have been responsible for remarkable reductions in
size and cost of switching power converters. The advances in operating frequency have been
achieved both through new devices and materials better suited to high-frequency operation
(e.g., power MOSFETs and new ferrite magnetic materials) and through circuit and com-
ponent designs that reduce losses associated with high-frequency switching (e.g., [3-23]).
Still much further increases in switching frequencies are needed to achieve miniaturization
and integration of power electronic circuits. Nevertheless, even though semiconductor de-
vices capable of operating ag gigahertz frequencies are available, switching frequencies in
power converters today remain well below 10 MHz. This fact poses a distinct challenge in
developing improved power electronics
This thesis will explore new architectures for dc-dc power conversion that enable dra-
matic increases in switching frequencies, into the Very High Frequency (VHF) range of
30-300 MHz. In addition to improvements in miniaturization and integration, these in-
creases in switching frequency hold promise for unprecedented improvements in control
bandwidth and transient performance.
- 23 -
Introduction
1.1 Challenges of High-Frequency Power Converter Design
Switched-mode power converters make use of passive energy storage elements (capacitors
and inductors) and semiconductor switches (MOSFETS, BJTs, etc.) to process electric
power efficiently. Not only do the passive elements provide intermediate energy storage, but
they also attenuate the ripple occurring at the switching frequency. Particularly, inductors
circulate energy through the circuit at low loss and also reduce the rapid variations in current
which are consequence of the high frequency switching. Generally, energy storage elements
are bulky and contribute to the large size and cost of conventional power electronic systems
and make miniaturization and integration difficult. Improving the size and performance
of power converters demands substantial increases in frequency. A number of factors in
switching power electronics make this a challenging goal. We begin by outlining some of
the dominant challenges to be overcome.
Modern applications demand power converters capable of maintaining voltage regulation

when confronted with rapid changes in the input voltage and load. Moreover, switching
conversion systems must operate efficiently over load ranges that can span two orders of
magnitude or more. While circuit designs exist that can achieve high efficiency at high
frequencies, they do not typically meet these requirements. In particular, Zero-Voltage
Switching (ZVS) allows converters to operate at frequencies reaching tens of megahertz
and beyond, but proves most effective at full load (e.g., [24-271). When operating at light
load, the resonant losses of these converters become comparable to the available output
power, severely reducing efficiency. Furthermore, gating losses become considerable as the
switching frequency of the converter is increased, further reducing light-load efficiency.
The influence that frequency-dependent losses exert on the size of magnetic components
is among the causes limiting the operating frequencies in conventional designs. At high
frequencies, it is not energy storage but power loss that often determines the size of the
magnetic components. This is particularly important in magnetics with large ac flux com-
ponents (e.g. transformers and inductors), since core loss rises rapidly with frequency. For
typical MnZn ferrite materials, flux derating of the core may be required as frequencies
exceed a few MHz, which halts the benefit that increasing the switching frequency has
on the overall size of the system [28]. Air-core magnetics do not incur in magnetic-core
loss, but the lack of high permeability material requires operation at even higher switching
frequencies where the inductance needed can be constructed without a core. Significant
reductions in the size of power converters necessitates either designs of passive components
which incur much smaller frequency-dependent losses or new architectures that enable a
substantial increases in the switching frequency which allows an effective use of air-core
magnetic elements.
- 24 -
1.2 Radio-Frequency Power Amplifiers
Regulating the output voltage presents additional challenges in converter designs at very
high operating frequencies. Because of gating loss and timing constraints, conventional
pulse-width modulation becomes untenable with available devices. Frequency control meth-
ods (e.g. [3,10,15]) and phase-shift control methods are capable of achieving efficiency reg-
ulation, but only over a very constrained range of loads. Difficulties in implementing the
control circuitry, and the complexity of the control dynamics impose additional limits in
applying these approaches in the VHF range. This thesis introduces systems architectures,
circuit topologies, and control methods that can overcome the control limitations associated
with VHF operation.
1.2 Radio-Frequency Power Amplifiers
Some of the system architectures and circuit topologies discussed in this thesis incorpo-
rate circuit structures and principles employed in tuned radio-frequency power amplifiers
(e.g., [16,18,29,30]), but apply them in manners that overcome their limitations in conven-
tional dc-dc converter architectures. Here we review some of the characteristics of tuned
radio-frequency power circuits.
Switched-mode rf amplifiers (inverters) utilize resonant circuit operation to achieve ZVS

of the semiconductor devices. To minimize driving losses and achieve high power gains,
multistage amplifier designs are often used. In a multi-stage design, amplifiers are chained
together such that each amplifier efficiently drives the gate(s) of a higher-power amplifier;
the last amplifier in such a chain drives the output. Using these techniques, tuned inverters
can be designed to operate with good efficiency into the gigahertz range, and in some cases
can be completely integrated (e.g., [29,31]). Similar (including dual) circuits can be used
for efficient high-frequency rectification (e.g., [9,11,13]). Figure 1.1 shows the schematic of
the Class E inverter (a) and the Class E rectifier (b) which are examples of power amplifiers
conventionally used in RF power conversion.
Both inverter and rectifier circuits of this type exhibit important limitations. First, they
only operate with good efficiency over a relatively narrow load range, both because of the
continuous resonating losses described above and because the load greatly affects the oper-
ating waveforms. Second, the controllability of these designs (e.g., to compensate for load
or input variations) is very limited, and becomes more challenging at higher frequencies and
in multi-stage amplifiers. Thus, the practical use of these circuits in dc-dc power conversion
(e.g., [3, 7, 10-12, 15]) has been limited to relatively low frequencies (<30 MHz), as previ-
ously described. Furthermore, traditional single switch Power Amplifiers, like the Class E,
- 25 -
Introduction
Cr
Introduction
impedance
(a) Class E Inverter (b) Class E Rectifier
Figure 1.1: The Class E Inverter (a) and the Class E Rectifier (b) can operate with good
efficiency at RF frequencies.
have high peak switch voltages that can reach more than 4 times the input. This requires
the use of comparatively high break-down voltages with poor conduction loss performance.
1.3 Thesis Objectives and Contributions
This thesis addresses the development of system architectures and circuit topologies for dc-
dc power conversion at very high frequencies. The systems architectures that are developed
are structured to overcome the previously described limitations associated with conventional
designs. In particular, the new architectures described here structure the energy processing
and control functions of the system in such a manner that high efficiency can be achieved
across a wide load range while regulating the output. Moreover, these architectures are
amenable to circuit designs operating at fixed frequency and duty ratio, considerably easing
the circuit design.
The thesis also develops new circuit designs that are well suited to the new architectures.
As part of this work, new gate drives and control methods are introduced that greatly
reduce gating loss at VHF frequencies for fixed frequency, fixed duty ratio operation. One
of these gating schemes provides near theoretical minimum loss by resonantly wave shaping
the gate voltage to have a trapezoidal waveform. This waveshaping approach is then taken
a step further, yielding a new class of dc-dc converter that archives a significant reduction
in peak switch voltage stress, requires small passive components with low energy storage,
and provides the capability for extremely rapid startup and shutdown. This new class of
converter is well adapted to the architectures and gate drive methods proposed in the thesis.
It is expected that the new architectures and circuit designs introduced here will contribute
to the development of power converters having greatly reduced size and improved transient
performance.
- 26 -
1.4 Organization of the Thesis
1.4 Organization of the Thesis
Chapter 2 describes the general attributes of two converter architectures suitable for radio
frequency power conversion. After describing their operating and control characteristics,
both architectures are experimentally demonstrated and evaluated in a multi-cell prototype
with "cells" operating at 100 MHz.
Chapter 3 explores design techniques for implementing dc-dc converter cells amenable to
operation at frequencies in the VHF range. In particular, it describes a trapezoidal resonant
gate drive and a resonant rectifier. These techniques are then applied to the design of a dc-
dc converter operating at 100 MHz switching frequency that achieves significant increases
in power density and transient performance as compared to the design implemented in
Chapter 2.
The VHF converter designs of Chapters 2 and 3 are based on the well-established Class E
inverter topology. Chapter 4 introduces an advanced resonant inverter topology that sig-
nificantly reduces semiconductor stress, requires smaller passive components, and provides
faster transient response than is possible with the Class E inverter. It also outlines a de-
sign procedure for tuning the new inverter (which we term the (2 resonant inverter) and
discusses relevant implementation issues. The chapter concludes by demonstrating the ex-
perimental performance of a 30 MHz %2 inverter that delivers 275 W of AC power and that
achieves a drain efficiency of 93%.
Chapter 5 describes a VHF dc-dc converter based on the 42 inverter of Chapter 4. A 200 W
prototype implemented using this topology shows an excellent transient response and good
dc-dc conversion (82.5% - 87.5%) efficiency over the input voltage range (160 V to 200 V).
Finally, Chapter 6 summarizes the thesis and suggests directions for continued work in this
area.
- 27 -
Chapter 2
New Architectures for VHF Power

Conversion
T HIS CHAPTER proposes two new architectures for switched-mode dc-dc power con-
version. These architectures enable dramatic increases in switching frequency while
preserving features critical in practice, including regulation of the output across a wide load
range and high light-load efficiency. This is achieved in part by how the energy conversion
and regulation functions are partitioned. The structure and control approach of the new
architectures are described, along with representative implementation methods. The design
and experimental evaluation of prototype systems with cells operating at 100 MHz are also
described.
2.1 New Converter Architectures
As described in Chapter 1, conventional power converter designs are subject to a number

of constraints that limit their practical operating frequency, and in turn limit the degree of
miniaturization and integration that can be achieved. Here we propose new power conver-
sion architectures that overcome these constraints. The architecture of most conventional
systems is straightforward: a single power stage of a particular topology, regulated using
a switching control technique such as pulse-width modulation or frequency modulation.
Here this basic architectural approach is expanded to systems incorporating multiple power
stages and new hybrid control techniques. The new system architectures relax the operating
requirements on the individual power stages, enabling the sought-after increase in switching
frequencies. These architectures take advantage of the high-frequency performance of tuned
rf amplifier circuits while circumventing their limitations through the manner in which the
energy conversion and regulation functions are partitioned. Two primary architectures are
introduced: a Vernier-regulated architecture and a cell-modulation-regulated architecture.
We also consider some of the variants of these approaches.
- 29 -
New Architectures for VHF Power Conversion
2.1.1 Vernier-Regulated Architecture
The Vernier-regulated cellular architecture (VRCA) is a type of cellular power converter. As

shown in Fig. 2.1, this architecture comprises a number of unregulated converter cells along
with a regulating converter cell, all of which supply the output in parallel. The unregulated
cells each comprise an rf inverter, a transformation stage, and a rectifier, along with filtering
and ancillary circuitry. The unregulated cells are structured such that they may be activated
or deactivated (turned on or off). The regulating converter cell-or Vernier cell-may be
a switched-mode converter, a linear regulator, or some combination thereof, and need only
be rated for a small fraction of the total system power. We term the regulating cell a
Vernier cell by analogy to the Vernier scale on a caliper (named after its designer, Pierre
Vernier). The Vernier scale provides incremental measurements between the discrete marks
on a caliper's main scale; likewise, the Vernier cell provides the incremental power between
the discrete power levels that can be sourced via the unregulated cells.
Figure 2.1: A block diagram illustrating the Vernier-regulated converter architecture.
Operation of the proposed architecture is as follows: The regulating cell is controlled to

regulate the output at the desired level. As the load varies, unregulated cells are activated
or deactivated to keep the regulating converter within a specified load range while ensuring
that the active unregulated cells run at or near their ideal operating points. One activation
scheme that meets these requirements is illustrated in Fig. 2.2. In steady state, the unregu-
- 30 -
lated cells deliver a portion of the total power (in discrete increments), while the regulating
cell provides whatever remaining power is needed to regulate the load voltage.
C"
€-c
.- 2
Load on Regulating Cell
Figure 2.2: An activation scheme for unregulated cells. Unregulated cells are activated
or deactivated based on the load on the regulating cell. U is the incremental loading
change when an unregulated cell is activated or deactivated. B is the minimum load on the
regulating cell, below which an unregulated cell is deactivated. H is a hysteresis value to
prevent chattering at boundaries.
This architecture has a number of advantages. First, the unregulated cells only run under
a narrow range of loading conditions. Second, the only control required for the unregulated
cells is a simple on/off command. These characteristics facilitate the use of VHF multi-
stage amplifier designs for the unregulated cells. Furthermore, because inactive cells do not
incur loss, and unregulated cells are only activated as needed to support the load, efficient
light-load operation can be achieved'. Finally, the proposed architecture inherits a number
of advantages of more conventional cellular converter architectures, including the dispersal
of heat generation in the circuitry and the potential for fault tolerance [33].
In any power converter system that processes power through multiple channels, it is im-
portant that each channel stably carry the appropriate amount of power in order to avoid
circulating losses and the possible destructive overload of individual channels (see [33-35]
and references therein). In the Vernier-regulated architecture, it is particularly important
to ensure that the unregulated cells share power in the desired manner. Furthermore, the
unregulated cells should not interfere with the output control function of the regulating cell.
1We note that varying the number of active cells in a parallel converter system to maintain light load
efficiency has been exploited before (e.g. [32]), albeit in the context of very different design and control
methods.
- 31 -
One method of achieving these control goals is to appropriately shape the output impedances
of the individual cells. For a given operating point, the cells are modelled as Thivenin
equivalent voltages and impedances that drive the output filter and load [33). For the
regulating cell, the Thivenin source is equal to the reference voltage, while the Thevenin
(output) impedance depends on both the power stage and control loop design. For the
unregulated cells, the Thevenin model parameters depend on the input voltage, the cell
power stage design, and the cell switching frequency. To achieve the desired output control,
the regulating cell is designed to have low output impedance at low frequencies (down to dc),
while the unregulated cells are designed to have relatively high output impedances (and thus
act as current sources)(Fig. 2.3). High dc output impedance is achievable with appropriate
rectifier design (see, e.g., [9]), and can also be used to ensure that the unregulated cells
share power (and current) correctly via their "droop" characteristics [33-38]. Under these
conditions, the small-signal control dynamics of the system are dominated by the regulating
cell. Thus, through appropriate design, the control requirements of the proposed Vernier-
regulated architecture can be met.
Regulating Multiple Output

Cell Unregulated Load
Cells
II--------------------------
I Zu2 Z
I I I
I I
I 1 V iul Zul i V,, i Vu +
......... I --I ...-
~---------
---------------------- L--------I
Figure 2.3: A low Thivenin impedance at the regulating cell provides a tight regulation of
the output. A high Th6venin impedance in the unregulated cells result in proper current
sharing.
2.1.2 Cell-Modulation-Regulated Architecture
The previous architecture uses a Vernier cell operating at variable load to provide the
difference between the quantized power levels delivered by the unregulated cells and that
needed to regulate the output. By contrast, the cell-modulation-regulated architecture uses
only unregulated cells to supply the output, as illustrated in Fig. 2.4. As with the previous
architecture, the unregulated cells are engineered to have high output impedance (such that
they may be treated as current or power sources) and to admit on/off control. To provide
the proper average power to regulate the output, the number of unregulated cells that are
- 32 -
Figure 2.4: A block diagram illustrating the cell-modulation-regulated converter architec-

ture.
activated is modulated over time, and an energy buffer (e.g., a capacitor, ultracapacitor,
battery, etc.) at the converter output is used to filter the resulting power pulsations.
A variety of modulation strategies are compatible with this approach. Perhaps the simplest
is hysteretic control of the output voltage. If the output voltage falls below a specified
minimum threshold, the number of activated cells is increased (e.g., in a clocked or staggered
fashion) until the output voltage returns above the minimum threshold (or until all cells are
activated). If the output voltage rises above a specified maximum threshold, the number of
activated cells is decreased until the output voltage returns below the maximum threshold
(or until all cells are deactivated). In the case where a single cell is used, this corresponds to
bang-bang control of the output [39]. With multiple cells this approach might be considered
a form of multi-level pulse-width modulation of power (or current). The system control can
be formulated as a sigma-delta modulator [40] or other discrete pulse modulation technique.
Clearly, there are many other similar control strategies that will likewise provide a desired
average output voltage.
The cell-modulation-regulated architecture exhibits a number of the advantages of the pre-

vious architecture. The unregulated cells only need to operate under on/off control over
a narrow power range. This facilitates the use of VHF power converter cells having small
size and high efficiency, and enables high light-load efficiency to be achieved. The efficiency
benefit at light loads is similar to that achieved with "burst" or "sleep" mode operation in
- 33 -
conventional designs, e.g. [41,42]. Moreover, because the cells can be run at fixed frequency
and duty ratios, the use of high-order tuned circuits to improve efficiency and power density
(e.g. Amplifer classes F, F - 1 , E/F, etc. [43-47]) becomes possible. However, the considera-
tions involved in sizing input and output filters for this architecture are different than that
of the previous one. In the Vernier architecture, the size of the output filter (e.g. output
capacitor) needed depends primarily on the bandwidth of the regulating (Vernier) cell, and
only secondarily on the startup speed of the unregulated cells, if at all. By contrast, in
the cell-modulation-regulated architecture, the energy storage requirement and size of the
output filter capacitor depends on the rate at which the unregulated cells can be modulated
on and off--typically more than an order of magnitude slower than the switching frequency
of the cells themselves. Consequently, the VHF operation of the cells enables dramatic
reductions in size of power stage components (e.g., inductors, capacitors, and transform-
ers), but it does not benefit the input and output filter components to the same extent.
Nevertheless, in many applications, significant energy storage is provided at one or both
converter ports (e.g. for holdup), so this is often acceptable. It may be concluded that
the cell-modulation regulated architecture enables high efficiency across load and tremen-
dous reductions in power stage component size, but does not provide the same degree of
improvement for input and output filters.
2.1.3 Related Architectures
The architectures proposed above enable dramatic increases in switching frequency as com-
pared to conventional designs, with consequent benefits. It should be appreciated that there
are many variants that offer similar advantages. For example, if one is willing to accept
regulation of the output to discrete levels, one can utilize a set of unregulated cells without
the need for a Vernier cell or time-domain modulation to interpolate between levels. The
use of unregulated cells having different power ratings (e.g., a geometric 2N progression)
would facilitate this approach, though it would perforce increase the design effort. (Note
that the use of non-uniform cell sizing can benefit the above architectures as well.)
The underlying characteristic of all such approaches is that they structure the energy con-
version and regulation functions in manners that are compatible with the effective use of
ultra-high frequency circuit designs and techniques. Limiting the drive requirements and
operating conditions of activated cells by partitioning energy processing and regulation -as
done here- is one means of achieving this. It is hoped that the recognition of this gen-
eral strategy will lead to the emergence of additional circuit architectures having similar
advantages.
- 34 -
2.2 100 MHz Unregulated Cell Design
The proposed architectures admit a wide range of unregulated cell designs. The principle
requirements are that the cells should operate efficiently for at least a narrow specified
operating range, have high output impedances, and be amenable to on/off control. These
requirements are fulfilled by many rf circuit topologies, and permit cell designs having
switching frequencies far higher than those reached in conventional dc-dc converters. To il-
lustrate this, we present the design and experimental evaluation of a converter cell operating
at 100 MHz that achieves >75% efficiency over its operating range.
The unregulated cell consists of a high frequency inverter, an impedance matching network,
and a resonant rectifier. The inverter is driven by a self-oscillating gate driver at a free
running frequency of 100 MHz. The converter operates with 11 V< Vi <•16 V and it is
designed to deliver up to 7.5 W to a constant 5 V load.
2.2.1 Class E Resonant Inverter
The front end of the unregulated cell consists of a Class E resonant inverter (Fig. 2.5).
The inverter provides the desired Zero-Voltage Switching, and admits the use of relatively
slow gating waveforms without undue loss. In conventional rf design, the loaded Q (QL)
of the converter is usually chosen to be large, resulting in waveforms with high spectral
purity. For power conversion, however, the requirements on QL are different, since the
goal is to maximize power transfer with minimum loss. A low value of QL results in less
energy resonated in the tank, which further implies reduced conduction loss in the parasitic
elements of the inverter; Equations for the design of Class E rf inverters with low Q can be
found in [48]. The nominal loaded Q in the prototype design was set to QL= 3 .4 .
I LI~
("r
v·
DC
impedance
Figure 2.5: A simplified model of the Class-E resonant inverter.
- 35 -
Under optimal ZVS conditions, inverter output power is proportional to the capacitance
in parallel with the switch. For the intended range of output power in the prototype cell
implementation, the required capacitance was provided entirely by the parasitic drain-source
capacitance associated with the switch.
The device selected for the main switching element is a Silicon N-channel Laterally Dif-
fused MOSFET (LDMOSFET). This semiconductor device offers the required characteristics
needed to operate at high frequencies: it presents an acceptable drain to source capacitance
and a low gate capacitance that allows for small gating loss.
2.2.2 Self-Oscillating Gate Driver
Gating losses in power converters grow with switching frequency. In traditional topologies,
these losses often become the limiting factor for high frequency operation. To mitigate
these losses and recover some of the energy required to operate the semiconductor switch,
a resonant gate driver may be used. A resonant gate drive often implies sinusoidal gate
signals, a feature commonly found in cascaded power amplifiers.
Figure 2.6: Idealized Vd,(t) and its fundamental (dotted line). The gate signal is also shown.
The phase angle between the fundamental component of the drain voltage and the idealized
gate signal is 1630.
- 36 -
A low-cost, efficient method of selectively driving the inverter is of great importance to

the proposed design. To achieve this goal while maintaining the cell's simplicity, a self-
oscillating gate driver making use of the drain-source voltage vds(t) of the LDMOSFET
was implemented. A resonant feedback network is used to extract and phase shift the
fundamental component of the drain voltage to generate a sinusoidal gating signal capable
of sustaining oscillation at the desired frequency.
Figure 2.6 shows the inverter's drain to source voltage Vd,(t) as well as its fundamental
component. These waveforms are referred in phase to the required gate voltage, vg,(t). The
phase difference between the fundamental component of vds(t) and the required gate signal
was found to be 1630 (as depicted in Fig. 2.6).
2.2.2.1 Phase shift/feedback network
A linear circuit structure, including the internal parasitics of the LDMOS gate, provides
the appropriate frequency selection and phase shift to attain sustained oscillation at the
desired frequency. Figure 2.7 shows a simplified circuit which feeds back the voltage Vd,(t)
MOSFET Gate
+ I
Vgs I
- I
Figure 2.7: Simplified phase shift/feedback network.
and provides the required phase shift. The fundamental of Vd,(t) is also attenuated to a
value that ensures proper gate drive while remaining below the gate breakdown voltage
(vgs,max = 20 V).
Figure 2.8 shows the frequency response of the drain to gate transfer function (w)); at
100 MHz the phase is the required 1630. By properly adjusting the damping resistor >fb
it
- 37 -
Magnitude and Phase of the Transfer function Vgdrain

g drain
Frequency [MHz]
Figure 2.8: Magnitude and Phase of the transfer function •: (w) for the proposed feedback
network.
is possible to set the magnitude and the precise frequency of oscillation by changing the Q
of the resonant structure.
The function of Ld2r and Rd2r is to damp the second resonance apparent in the transfer
function of Fig. 2.8; higher frequency oscillations (;2 GHz) might otherwise result.
The input impedance of the self-oscillating structure is dominated by the value of the
feedback capacitor Cfb at the operating frequency. This capacitor is selected such that the
impedance looking into the structure is much higher than the impedance looking into the
resonant tank of the Class E inverter, ensuring that the frequency characteristics of the
tank circuit are not substantially altered.
2.2.2.2 On/off and startup circuit
The proposed gate driver requires a simple method to start and stop cell operation. This
can be achieved with a slight modification to the phase shift/feedback network previously
described. This is illustrated in Fig. 2.9.
- 38 -
Figure 2.9: Self-oscillating resonant gate driver circuit.
When transistor Qon/off is on, the gate is pulled low and the inverter is shut off. When
Qon/off turns off, Cd, charges through Rfb. With a properly chosen logic supply voltage
(3.3 V in Fig. 2.9), the gate is driven above threshold, turning on the MOSFET and starting
oscillation through the phase shift/feedback network. A digital signal can thus be used to
activate or inhibit converter operation.
During operation, Cdc remains biased close to the MOSFET threshold voltage, helping to
keep the duty ratio near 50%. Cdc is selected for minimal impact on the transfer function
Y: (w). When Q0on/ of is off, the junction capacitance of Don/off appears in series with the
output capacitance of Qon/off; this minimizes loading on the phase shift/feedback network.
The RC circuit formed by Rfb and Cdc introduces a delay between the command signal and
inverter startup; it is this delay which limits the speed at which the cell can be turned on.
2.2.3 Matching Network and Rectifier
The rectifier is implemented as a balanced pair of single-diode rectifiers. The rectifier

network is structured such that it appears resistive in a describing function sense. This
rectifier is connected to the inverter tank by a simple L-section matching network [49].
Figure 2.10 shows the implemented cell design, with component values and part numbers
enumerated in Table 2.1. Important circuit board parasitics are also described. Layout
information for the cell is presented in Appendix B.
- 39 -
Table 2.1: Component values in the unregulated cell.

Circuit element Nominal Value Part number
Lchoke 538 nH Coilcraft 132-20SMJ
Cfb 2 pF CDE MCO8CA020C
Cpm 1.15 pF Measured circuit board parasitic
Lfb 27 nH Coilcraft 1812SMS-27NG
Rf 2.2 k2 Standard SMD
Cdc 2.2 nF COG Ceramic, 50 V
Rb 100 kQ Standard SMD
Ld2r 2.5 nH Coilcraft A01TJ
Rd2r 15 Q Standard SMD
Cpds 5.9 pF Measured circuit board parasitic
Lr 68 nH Coilcraft 1812SMS-SMS-68N
Cr 57 pF (47 pF+10 pF) CDE MC12FA470J
CDE MC08CA100D
Cm 47 pF CDE MC12FA470J
Cpm 2.4 pF Measured circuit board parasitic
Lm 12.5 nH Coilcraft A04TJ
Cn 100 pF CDE MC12FA101J
Lc, 22 nH Coilcraft 1812SMS-22NG
Lshl 12.5 nH Coilcraft A04TJ
Lsh2 12.5 nH Coilcraft A04TJ
Cin 4 x 47 nF X7R Ceramic, 50 V
Cout 9 x 47 nF X7R Ceramic, 50 V
C3.3 2 x 47 nF X7R Ceramic, 50 V
LDMOSFET PD57018S
D 1, D 2 MBRS1540T3
Don/off BAS70
Qon/off BC847
- 40 -
Figure 2.10: Unregulated 100 MHz switching dc-dc power converter cell. Component values
and important parasitics are enumerated in Table 2.1.
2.2.4 Experimental Results
Cell efficiency and output power were measured over the supply voltage range 11 to 16 V
with a constant-voltage load comprising fifteen 5.1 V, 1 W Zener diodes in parallel with two
15 pF Tantalum capacitors. Output power ranged from approximately 2.5 to 6 W, with an
average efficiency greater than 77.5%. Figure 2.11 illustrates measurements from a typical
cell. A photograph of one cell is shown in Fig. 2.12. The schematic and mask files used to
make the PCB of the prototype are shown in Fig. B.
Figure 2.13 shows measured drain-source voltage under nominal conditions; turn-on and
turn-off transients are depicted in Fig. 2.14 (the command occurs at t = 0 in both cases).
The incremental output impedance of the unregulated cell design at Vout = 5 V ranged
from 30 Q (Vin = 11 V) to 3 fl (Vin = 16 V).
The unregulated cell switching frequency, 100 MHz, is significantly higher than those found
in conventional dc-dc converter designs, while maintaining an acceptable efficiency level.
Moreover, as discussed in section 2.5, substantially higher switching frequencies (to sev-
eral hundreds of megahertz), power densities, and efficiencies are possible with the general
approach taken here.
- 41 -
Cell Efficiency and Output Power vs. Input Voltage
Input Voltage [V]
Figure 2.11: Cell performance as a function of supply voltage into a 5.1 V load.
Figure 2.12: A photograph of the unregulated cell circuit board.
- 42 -
11
Drain to Source Voltage (VIN= V)
0 5 10 15 20 25 30
Time [ns]
Figure 2.13: Measured drain-source voltage under nominal operating conditions at V, =

11V.
Turn on delay time

r^n
V. OIr
0.6
0 .4 . .... ..... .......
>0.
.2
0 5 10 15 20 25 30
Time[gls]
Turn off delay time
0.81 :
0.
>0. - Drain-.
in-Source Voltage
-Control signal
0 2 4 6 8
Time[lis]
Figure 2.14: Attenuated drain-source voltage during turn-on and turn-off transients. In
both cases, the command occurs at t = 0. The drain-source voltage was measured via an
attenuator network that reduced DC voltage by approximately a factor of 38; AC voltages
are attenuated somewhat further.
- 43 -
2.3 A Vernier-Regulated System
2.3.1 Converter Implementation
To demonstrate the fundamental operation of a Vernier-regulated converter (section 2.1.1),

we designed and constructed a prototype system comprising eight unregulated cells of the
type in section 2.2, a Vernier cell, and a clocked controller of the type pictured in Fig. 2.2.
In this implementation an LM7805 linear regulator was used for the Vernier cell. Chief
among the reasons for this decision are its suitability to the task (as discussed in sec-
tion 2.1.1) and its simplicity. Other benefits of a linear regulator are that it maintains
constant (though low) efficiency down to almost zero load and that it provides well-behaved
output control dynamics. Moreover, the use of an otherwise extremely inefficient regulator
in this system demonstrates the efficiency potential of the Vernier-regulated architecture
despite regulating cell loss.
The controller, pictured in simplified form in Fig. 2.15, consists of a current sensor, two
comparators, and two four-bit bi-directional shift registers. When the Vernier cell output
current exceeds a predefined upper threshold, a command is sent to the shift registers which
activates one additional unregulated cell. Likewise, when the lower threshold is crossed,
the resulting command causes one unregulated cell to be turned off. Note that the shift
register outputs are inverted to produced the appropriate active-low control signals to the
unregulated cells.
10kHz
Figure 2.15: Simplified schematic of the Vernier cell and system controller.
To prevent oscillation, it is necessary that the difference between the upper and lower
switching thresholds be larger than the maximum unregulated cell output current. In a
- 44 -
binary weighted system, the difference between the switching thresholds is determined by the
minimum size cell. If this were not the case, upon exceeding the upper threshold and giving
an activation command the Vernier cell output current would immediately fall below the
lower threshold, causing a subsequent deactivation command and restarting the limit cycle.
On the other hand, too large a hysteresis band underutilizes the unregulated cells, costing
converter efficiency. As is clear from Fig. 2.11, unregulated cell output current is a rather
strong function of input voltage. Thus, were a static upper hysteresis threshold chosen
(necessarily accommodating the output current at Vin = 16 V), substantial underutilization
of the unregulated cells would occur at lower supply voltages. To mitigate the consequent
losses, the upper hysteresis threshold is instead made a function of Vin via a Zener diode
and a resistive attenuator.
2.3.2 Experimental Results
The Vernier architecture converter performed as expected over the full supply and load
ranges, achieving over 68% peak efficiency.
Figures 2.16 and 2.17 show measured efficiency versus load at Vin = 11 V and Vin = 16 V,
respectively. When an unregulated cell is switched on, power processing shifts from the
low-efficiency regulating cell to the high-efficiency unregulated cell. This causes a sudden
jump in converter efficiency, resulting in the sawtooth pattern apparent in both figures.
The hysteretic nature of the control strategy employed in this converter gives rise to the
possibility of two distinct operating configurations for the same load condition. In the ex-
periment of Fig. 2.16, the load was swept from nearly zero to maximum and then back.
During the upward sweep, cell activation lagged the increasing load, resulting in the utiliza-
tion of only the minimum number of cells necessary to power the load. On the downward
sweep, cell deactivation lagged the changing load; as a result, during some portions of the
downward sweep more power was processed by the high-efficiency unregulated cells than
during the upward sweep.
Conversion efficiency suffers at light load because of the power drawn by the controller.
In this prototype converter, the control circuitry draws 80 mA of quiescent current from
the supply, resulting in substantial loss, especially under light load conditions. Figure 2.17
shows the theoretical efficiency impact of an implementation utilizing a low-power controller.
Such a controller could be readily implemented through a variety of means.
Static line regulation was measured at 25 W across the supply range of the converter; over
this range the output voltage varied by 75 mV, or less than 1.5%. Static load regulation was
- 45 -
Efficiency versus Output Power (Vin = 11V)
. .
.............. . . f .. .......
......
.. ii.
.....
................
aa
IY
.............
........... -
A
a)
9
w
...... - Downward Load Sweep (1a to 259)

- - -Upward Load Sweep (251 to 1Q)
-- -- --
5 10 15 20 25
Output Power [W]
Figure 2.16: Efficiency versus output power of the Vernier-regulated system for Vin = 11 V.
In this experiment, the load was swept from 25 Q to 1 2 and then back to 25 (2, demon-
strating the hysteretic characteristic of the controller.
better than 0.8% at Vin = 11 V and 2.4% at Vin = 16 V. Measured output voltage ripple
was less than 200 mV at Vin = 11 V, Rload = 1 Q and less than 300 mV at Vin = 16 V,
Rload = 0.46 Q.
The Dynamic performance of the Vernier system is illustrated in Fig. 2.18. At Vin = 11 V,
the load was stepped from 1000 Q to 3 (, resulting in the activation of the first three
unregulated cells. The delay between cell activations is determined by the controller clock
frequency, 10 kHz.
In order to better match the power throughput of the unregulated cells, three of the eight
cells were minimally trimmed to compensate for component variation. At maximum load
with Vin = 16 V, individual cell output currents were matched to within ±6.5% of aver-
age. This is certainly sufficient for practical purposes, and it is expected that with tighter
component tolerances or more extensive trimming much better load sharing is possible.
- 46 -
Efficiency versus Output Power (Vin = 16V, 2M2 to 0.46Q)
Output Power [W]
Figure 2.17: Efficiency versus output power of the Vernier-regulated system for Vin = 16 V,
25 >_ Rload > 0.46 Q. The theoretical efficiency expected under the same conditions when
utilizing a low-power control circuit in place of the tested implementation is also shown.
Load Step, 1000Q to 30, Vin=l 1V
0.6 . . . .
0.4-
• Cell 1 Cell 2 Cell 3
0.2..........
SO ... .. •
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35

Time [ms]
Figure 2.18: Dynamic performance of the Vernier-regulated converter with Vin = 11 V

under a load step from 1000 •0 to 3 02.
- 47 -
2.4 A Cell-Modulation-Regulated System
This section provides experimental verification of the architecture described in section 2.1.2.
In the prototype developed here, a single 100 MHz dc-dc cell is modulated, through its on/off
control input, with a hysteretic controller which keeps the output voltage within predefined
boundaries. Thus, the cell operates at an output voltage at which its efficiency is maximized.
For our particular experimental implementation the hysteresis is implemented using a simple
voltage comparator (LM311), and limits the voltage swing to be between 5.0 and 5.2 V. The
unregulated cell is provided with an output capacitance of 16.5 pF (Formed by 5 3.3 ~iF
tantalum capacitors in parallel).
In order to reduce the size of the capacitor needed at the output of the system, an improved
self oscillating gate drive circuit was utilized. The modified self oscillating gate drive with
on/off control is shown in Fig. 2.19. This implementation achieves faster cell turn on
than the circuit described in section 2.2.2 and enables activation/deactivation (modulation
frequency) rates in excess of 70 kHz to be obtained.
Figure 2.19: Improved self oscillating gate driver with fast on/off control.
Figure 2.20 shows the transient response of the cell-modulated architecture when a step
change in the load is applied. In particular, the step change takes the converter from
almost no load to half the rated output power (27 Q2to 13.5 f2, Vin = 16 V). Under such
a step change, the output voltage remains within the predefined limits. The same figure
shows that the input current pulsates with a frequency depending on the input voltage, the
output capacitance, and load, and that it rapidly reaches steady state conditions.
- 48 -
2.5 Discussion on the Directions and Emerging Opportunities
Input and Output Current (Load Step 27Q to 13.5 Q)
Output Voltage (Load Step 27Mto 13.5 9)
F:----:-....... ... .... ... ... ..
]
...
..
.........
...
. .....
......
.....
...
...
. I I I I
-900 -400 -300 -200 -100 0 100 200 300 400
Time[us]
Figure 2.20: Transient behavior of the cell-modulation-regulated system under a step change
in load (27 Q to 13.5 0, Vin = 16 V).
The performance of the architecture is shown in figures 2.21 and 2.22. Fig. 2.21 shows the
efficiency plotted as a function of the output power and Fig. 2.22 the efficiency plotted as
function of the input voltage. Both figures demonstrate that the overall efficiency of the
system is high over the entire input voltage range and across the output power range.
As can be seen from the prototype system and results, the high cell switching frequency
allows reduction in the power stage component sizes. However, the frequency of the input
and output waveforms depends on the time modulation of the cell, and have much lower
frequency content. Nevertheless, it is anticipated that the use of higher operating frequencies
permitted by this architecture (e.g. to >1 GHz), the use of more cells, and design and control
of cells for more rapid startup and shutdown will together enable substantial improvements
in the input and output ripple performance of this architecture.
2.5 Discussion on the Directions and Emerging Opportuni-

ties
The rf power converter cell design of Section 2.2, as applied in the architectures of the
previous two sections, demonstrates the feasibility of power converters operating at very
- 49 -
Efficiency vs. Output Power (Vn=l 1,16V Vout=5.1V)

Io . .............. ...... ... ........ ...... •. ... ..... ..... ..... ..... ..... ..... ..... ..... ................
............... . ........ ............. . ....................... :................ = at 16V

ata11V
74
73 . . ... .. ... .. ...
-.. ... .. ... .. ... .. ... .. i.. .. ... ... ... .. ... .. ...!.... .. .... .. .. ... ... .. .. .. ... ... .. ...
72
o 71
.......................
.... ... ............ .......................
........................ ............ .......
. .... ..........
.at . . .. ................... ...............
16V
I.. . .r i.
*
] 69 -
68
. . . . . . . . . . . . . ..•. . . . . . . .. . . . .. . . . .. .. . . . . . . .. . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . .:.. . . . . . . . . . . . ..
67 ...............
i................. .. ......................i...
......................
..............
•
66
a0r
0.5 1 1.5 2
Output Power [W]
Figure 2.21: Efficiency vs. output power of the Cell-modulation-regulated system at

Vin =11V and 16V.
high frequencies. The dramatic reduction in passive component values and the elimination of
magnetic materials also points towards the possibility of greatly increased integration (e.g.,
integration of the passive components as part of the printed circuit board). Nevertheless,
the cell power density (-0.5 W/cm3 ) and efficiency (-77%) of this first prototype are low
compared to many conventional designs 2 . In this section we outline circuit design strategies
and emerging device technologies that greatly increase the achievable power density and
efficiency of rf power converters, and which will enable the benefits of the architectures
described here to be more fully exploited.
2.5.1 RF Circuit Topologies
The design strategy described in this chapter takes advantage of circuit topologies and tech-
niques employed in radio-frequency power amplifiers. While power density and efficiency
are important concerns in rf power amplifiers, they are often secondary to other consider-
2
Partly this is because maximizing power density and efficiency was not a focus in our first-pass design. We
have subsequently developed VHF converters based on similar principles that provide far higher performance
(e.g., see [1,50,51] and subsequent chapters).
- 50 -
Efficiency vs. Input Voltage (Pout=2W, Vout-5.1V)
74.5 . . . . ......
. i.................... ..................... .................... ,.................. .
74
73.5
............ . . . ................... :....... 7....7 ......... :..... .................................
73
72.5
72 . . . . . . . . . .i . .. ..... ... ... ....i.... ... ...... ... ... . .. ..... ... .... .. ... . .. ... .... ....
71.5
.... . . . . ..... . . . . . . . . . . . . . . . . . . . . . . . ........ ....... ..... .......

70.5
_/n
12 13 14 15 16
Input Voltage [V]
Figure 2.22: Efficiency vs. input voltage of the Cell-modulation-regulated system at

Pout =2W.
ations (e.g., linearity and spectral purity). Consequently, there is substantial opportunity
for developing improved rf circuits that are much better adapted to the demands of switch-
ing power electronics. Here we point out two circuit design techniques - waveshaping and
parasitic absorption - that can lead to greatly improved power density and efficiency in rf
power converters. These strategies are briefly described here and pursued in more detail in
Chapters 4.
The class E inverter selected for the prototype system has many desirable attributes: it
provides soft switching, is tolerant of slow gate-drive waveforms, requires only a single,
ground-referenced switch, and its design is very well understood. One limitation of this
topology is its very high device stresses. The waveforms of the class E inverter are treated
in [16,48, 52], [53, Chapter 15], and reveal a peak switch voltage V,,of approximately 3.6
times the dc input voltage and a peak switch current I,, of approximately 1.7 times the
magnitude of the ac load current. To compare the stresses of the class E inverter to other
topologies, consider the per-switch stress factor PSSF, defined as:
PSSF =
Po,8 w
- 51 -
where Po,8 w is the output power per switch of the inverter. (This definition is the same as
the stress factor defined in [2, chapter 6] and the inverse of the normalized power handling
capability defined in [46,53], except that we normalize to the power per switch, to better
capture the limits of multi-switch topologies.) With reference to [46, 52, 53], the class E
inverter has a PSSF a 10.2, which is substantially higher than that of the class D resonant
inverter, which has a PSSF - 6.25.
Clearly, the power density and efficiency of the systems proposed here would benefit from
rf topologies having lower device stresses. One route towards realizing such improvements
is waveshaping. By designing the rf power stages with additional resonant tunings near
the harmonics of the fundamental, the converter waveforms can be shaped for lower stress.
For example, the class F inverter (see, e.g., [44] [53, Chapter 15] [54, Chapter 5]) and
its variants [45-47] incorporate one or more additional resonances to shape the switch
voltage to approximate a square wave (V,,. 2Vin), yielding a single-switch topology with
a reduced PSSF ; 6.25 (approximately 39% below a class E inverter, and matching that of
a class D inverter). The necessary multi-resonant networks can be realized using lumped
elements, transmission lines, or integrated LC elements [44], [45], [53, Chapter 15], [46].
The dual strategy of reshaping switch current via the resonant network is also effective for
improving efficiency and power density (e.g., as accomplished in the class F- 1 and related
topologies [43], [53, Chapter 15], [55]), and there is good reason to expect that shaping
both voltage and current together will be even more beneficial. Note that while achieving
high efficiency with such multi-resonant topologies constrains inverter operation (e.g., to
fixed duty ratio and frequency), the system architectures introduced in this chapter are
not hampered by these constraints, as regulation is achieved through other means. We
thus conclude that designs incorporating waveshaping can offer substantial improvements
in performance over that demonstrated in our first prototype system.
A further means to improving efficiency and power density is through absorption of the de-
vice parasitic capacitance. While the class E topology incorporates the device capacitance
as part of the resonant network (C in Fig. 2.5), output power is proportional to both this
capacitance and to the switching frequency [52]. Consequently, for a given semiconductor
device there is an upper bound on switching frequency before inverter output power - and
the corresponding switch conduction losses - become too high and cause unacceptable re-
ductions in efficiency. This coupling between device capacitance, minimum output power,
and conduction loss is a limitation of the class E topology. However, some of the multi-
resonant topologies described above can absorb device capacitance into the network in a
manner that partly decouples device capacitance from output power (e.g., see [43,44,47]).
Absorbing the parasitic capacitance in this manner allows the use of increased switching
frequencies (improving power density) and/or device sizes (improving efficiency) as com-
pared to a class E converter. Based on these considerations, it is reasonable to expect that
- 52 -
substantial improvements in performance can be achieved by better exploiting existing rf

circuit topologies and techniques. Moreover, it is apparent that there exists substantial
opportunity to develop new rf circuits that are better adapted to the demands of switch-
ing power electronics, yielding further improvements in performance. Subsequent chapters
of the thesis introduce new inverter topologies that, by using a lumped approximation of
a quarter-wavelength transmission line, implement voltage waveshaping and of parasitic
absorbtion. These techniques will be demonstrated experimentally.
2.5.2 Devices
The attainable performance of radio-frequency power converters is also advancing quickly

due to the ongoing development of improved rf power semiconductor devices. The demands
of the communications sector are driving rapid improvements in rf power devices. Here we
illustrate some of these ongoing developments, and describe how they impact the circuit
architectures described above.
There is a close tie between the attainable performance of a radio-frequency power converter
and the characteristics of its power semiconductor device(s). For example, consider the
performance of a class E inverter based on a lateral diffused MOSFET (e.g. as utilized
in the prototype system described here). If the operating frequency f is sufficiently high
that the device output capacitance Co,, forms the entire shunt resonant capacitor (C in
Fig. 2.5), the inverter power is approximately proportional to f and Co,,, (optimally evaluated
at the dc input voltage) [50, 52, 56]. With resonant gating, loss for this device type is
heavily dominated by conduction loss 3 , which is proportional to the on-state resistance
Rds-on. Using these facts and following through the calculations developed in [50,52,56],
it can be shown that device dissipation normalized to inverter power is approximately
proportional to Rds-on*Cos, f. Thus, the product Rd,-on*Cos, is a good measure of device
performance in this circuit: a device with a lower figure of merit Rds-on*Coss provides a
proportionately lower device loss as a fraction of total power (yielding higher efficiency),
or enables a proportionate reduction in switching period at constant loss (yielding higher
frequency and power density).
Table 2.2 shows a number of recent LDMOS devices in the 65V/70V category (as used
in the converter of Section 2.2) along with the figure of merit for each device. The first
device, with a figure of merit of 15.1 l.-pF, is a slightly older device (datasheet from early
2003) and is the one utilized in the prototype converter demonstrated here. The remaining
3In many vertical MOSFETs, by contrast, gating loss can be a major loss mechanism even with resonant
gating, making analysis somewhat more complicated [56]. Other device types can likewise have different loss
considerations than the LDMOS devices considered here.
- 53 -
devices are more recent (datasheets from 2004 or 2005). As can be seen, devices providing
far better figures of merit (up to a factor of 5.4 better) are presently available, indicating
that similar designs having far higher power densities and efficiencies are achievable. As
an example of this, we subsequently developed a converter similar to the one presented in
section 2.2(again without an attempt to optimize power density) using the MRF373ALSR1
MOSFET [1]. The design was of similar switching frequency, size, and efficiency, but achieved
more than a factor of 4 increase in output power through the use of a better device (figure of
merit better by a factor of 2.25). Clearly, substantial further improvements in performance
are possible with presently available devices, even without resorting to improved circuit
topologies.
Table 2.2: Some Commercial 65 V/70 V Lateral Diffused MOSFETs and their figures of
merit. Note: Because some of these devices are intended for use in inefficient amplifier
classes, they are sometimes provided in rather unwieldy packages. Also some recent devices
require more sophisticated gate drivers for switched-mode operation, such as the multi-
resonant driver used in [1] and discussed in a subsequent chapter.
Device Rds-on'Coss (S7"pF)
ST Microelectronics PD57018 15.1
Cree UPF1030P 7.8
Cree UPF1010P 7.7
Freescale MRF373ALSR1 6.7
Freescale MRF6S9125NR1 5.0
Cree UGF9085P 4.3
Freescale MRF6S9060NR1 4
Agere AGR09030GUM 3.9
Agere AGR09180EF 2.8
In addition to the rapid evolution of silicon MOSFETs, the communications sector is driving
development and application of other materials and device types for rf power amplifiers.
For example, GaAs, SiC, A1GaN/GaN, and InGaP material systems are all in use for rf
power applications, in field effect (e.g., MOSFET, MESFET, HEMT) and bipolar (e.g.,
BJT, HBT) devices. (Models for some of these device types can be found in [57, Chapter
3] and references therein.) These devices can often offer improved power gain and efficiency
at extreme high frequencies. While it is possible in some cases to adapt these devices
to traditional switching power converters (see, e.g., [58]), their driving requirements and
optimization for rf operation makes their use significantly more favorable in the type of
architecture proposed here. We thus anticipate that the proposed architectures will continue
to benefit from the ongoing advances in microwave semiconductor device technology.
- 54 -
2.5.3 Application Areas and Future Development
Reasonable questions regarding the proposed architectures are: for what power and voltage
ranges and for what applications spaces are these approaches most suitable? While it is
too early in the development of these architectures to provide complete answers to these
questions, we introduce some current thoughts on these matters here.
While the proposed architectures can be realized effectively with conventional vertical power
MOSFETs (see, e.g., [50]), the use of radio-frequency power devices is particularly advanta-
geous. It is thus reasonable to estimate that initial applications of the proposed technology
will be at voltage levels for which good rf power devices are commercially available. Widely-
used dc bus voltages for rf communications include 7.5 V, 12.5 V, 28 V, and 50 V [59],
leading to rf power devices with typical rated blocking voltages of 25 V, 40 V, 65/70 V,
and 120/125 V. (For low-power systems, discrete transistors with blocking voltages down to
3 V are available [60].) These devices are largely intended for rf power amplifiers for com-
munications in the VHF band (30-300 MHz) through the UHF band (300 MHz - 3 GHz) 4,
and can be used with high efficiency in the proposed architectures at typical factors of 3-10
lower in frequency (i. e., to several hundred megahertz.) Similarly, (vertical, metal-gate)
rf power MOSFETs intended for HF (2-30 MHz) communications and Industrial, Scientific,
and Medical (ISM) band applications (e.g., plasma generation) are commercially available.
Devices of this type are available with blocking voltages in the range of 200 - 1000 V (see
the device comparison in [46]), and can be used with acceptable efficiency to frequencies
beyond 30 MHz [46,63-67]. It may be concluded that the proposed architectures can be
applied to applications spanning a wide range of input voltages and power levels. Based
on available devices and other design considerations, higher-voltage designs will likely be
implemented at lower switching frequencies and higher cell power levels.
We believe there is a wide applications space for the proposed design strategy. It is likely
that the proposed approaches will find easier use in applications typically addressed with
indirect [2, Chapter 6] converter topologies (e.g., Clik, SEPIC, buck/boost, Zeta), since
these topologies have relatively high stresses, and rf converter cells can easily be designed
to convert both up and down in voltage (e.g., [1]). Likewise, achieving isolation is relatively
straightforward in typical rf topologies due to their use of high-frequency intermediate
waveforms, so applications requiring isolation may be well matched to these architectures.
One present application area of interest to the authors is dc-dc converters for automotive
applications. This is an attractive area due to the high motivation to reduce cost (e.g., by
integrating passive components as part of a printed circuit board), and the fact that available
devices are well matched to the voltage requirements of automobile electrical systems [68].
4
See [61, 62] for a summary of the designation and utilization of the various frequency bands.
- 55 -
It is expected that continued development will further reveal the best applications for the
proposed architectures.
2.6 Conclusion
This chapter proposes new architectures for switched-mode dc-dc power conversion. The
proposed architectures promise to break the frequency barrier that has until now con-
strained the design of switched-mode power converters, while preserving features critical in
practice, including regulation of the output across a wide load range and high light-load
efficiency. This is achieved in part by how the energy conversion and regulation functions
are partitioned in these architectures. The structure and control approach of the new ar-
chitectures are described, along with representative implementation methods. The design
and experimental performance of prototype systems with cells operating at 100 MHz are
also described. It is anticipated that the proposed approaches will allow significant im-
provements in the size of switching power converters to be achieved, and, in some cases, to
permit their integrated fabrication.
An underlying characteristic of the design approaches presented here is that they structure
the energy conversion and regulation functions in manners that are compatible with the
effective use of ultra-high frequency circuit designs and techniques. It is hoped that the
recognition of this general strategy will lead to the emergence of additional circuit architec-
tures having similar advantages.
- 56 -
Chapter 3
Design Considerations for VHF dc-dc

Converters
T HIS CHAPTER describes several aspects relating to the design of dc-dc converters
operating at frequencies in the VHF range (30-300 MHz). Design considerations are
treated in the context of a dc-dc converter operating at a switching frequency of 100 MHz.
Gate drive, rectifier and control designs are explored in detail, and experimental measure-
ments of the complete converter are presented that verify the design approach. The gate
drive, a self-oscillating multi-resonant circuit, dramatically reduces the gating power while
ensuring fast on-off transitions of the semiconductor switch. The rectifier is a resonant
topology that absorbs diode parasitic capacitance and is designed to appear resistive at
the switching frequency. The small sizes of the energy storage elements (inductors and
capacitors) in this circuit permit rapid start-up and shut-down and a correspondingly high
control bandwidth. These characteristics are exploited in a high bandwidth hysteretic con-
trol scheme that modulates the converter on and off at frequencies as high as 200 kHz. The
design developed here achieves important increases in power density and performance over
the prototype converter presented in Section 2.4.
3.1 System Structure and Control
3.1.1 Background
Achieving high efficiency in dc-dc converters operating at very high frequencies necessitates
means to keep the switching loss to a minimum. In hard-switching converters some energy
is lost every time the semiconductor switches commutate, yielding a loss component that
is proportional to the switching frequency. Soft switching - and in particular zero volt-
age switching (ZVS) - reduces the switching loss by maintaining a low voltage across the
semiconductor device during the on/off transitions [20, 22]. Furthermore, ZVS operation
is beneficial because it reduces the electromagnetic interference (EMI) normally associated
with rapid transitions in hard-switched converters. However, the resonant methods used to
- 57 -
Design Considerationsfor VHF dc-dc Converters
RL
Inverter Transformation Rectifier

Stage
Figure 3.1: A block diagram illustrating the structure of a high frequency dc-dc converter.
realize ZVS operation tend to incur losses that do not scale back with load, making it dif-
ficult to achieve efficient light-load operation. A challenge, addressed by the architectures
introduced in Chapter 2, is to take advantage of the high-frequency capabilities of ZVS
topologies while still maintaining efficient operation at light load.
A further challenge in implementing VHF power converters is reducing the losses due to the
gating of the semiconductor devices. With conventional gate drives, gating loss is propor-
tional to switching frequency and rapidly becomes unacceptable as frequency is increased.
Recovering at least a portion of the energy delivered to charge the gate is thus an important
means for extending the achievable switching frequency range [3,24-27, 50,69-71].
Parasitic elements are another important consideration in RF converters, and become more
so with increasing switching frequency. In many RF circuit implementations, the size of
some circuit elements is comparable to the parasitics introduced by the devices, packages
and interconnections. For example, the parasitic capacitance of the semiconductor device is
typically an important consideration in RF converter design. To address this issue, and to
allow for even higher switching frequencies, topologies that absorb or utilize the component
parasitics (especially device capacitances) as an integral part of their operation are desirable.
This, however, leads to a tighter dependance of circuit performance on device parasitics than
is typical in conventional designs.
3.1.2 Converter System Structure
This chapter describes a design approach that can meet all the above requirements by
following the guidelines demonstrated in Chapter 2. In particular, a design implementing
"cell-modulation" or "on/off" control in conjunction with resonant switching and resonant
gating is used to achieve VHF operation while providing output control and good efficiency
across load. A block diagram of a system realizing this approach is shown in Fig. 3.1,
consisting of a radio-frequency resonant inverter, a transformation stage, and a resonant
rectifier, along with an appropriate control system (for cell-modulation control). Figure 3.2
- 58 -
3.1 System Structure and Control
Inverter Transforration Rctifier

Stage
-------------- -ir------------
L hojc CR LR CC1 Lcl I I -
iO
II I
+ I - 1'
+ I
Vi, GtDi "I . _ L C II

II _
I,
II
II
II
I
I
I
12
c iI I
Figure 3.2: Schematic of a 100 MHz dc-dc converter.
shows a simplified schematic of the prototype dc-dc converter implemented to demonstrate

this approach. Subsequent sections will focus on key system elements, and will present an
evaluation of the different functional blocks of the system.
An inverter at the system input transfers power from the input source to the subsequent
stages by transforming the dc input voltage into a VHF sinusoid. The inverter can be
implemented using any of a number of switched-mode RF power amplifier topologies that
provide the required ZVS (e.g., [16, 18, 29, 30, 45, 46]). For the particular implementation
presented here, the inverter utilized was a class E power amplifier operating with a low
loaded Q (QL) to deliver power efficiently'. Details on the design, characteristics, and
limitations of this class of power amplifiers can be found in [16, 48, 52], and [53, Chapter
15], and so will only be treated briefly here.
Inverter output power (under ZVS conditions) is proportional to the capacitance in parallel
with the switch. For the intended output power range in the practical implementation de-
scribed here, the required capacitance is provided by the nonlinear drain-source capacitance
of the MOSFET and 20 pF of external capacitance.
The device selected for the main switching element of the inverter is a lateral doubly-
diffused MOSFET (LDMOSFET) of the type typically used in cell phone base stations. This
semiconductor device offers the characteristics required to operate at high frequencies: it
presents an acceptably low output capacitance (Cros) as well as a low input capacitance
(Cis,), gate resistance (RG) and reverse transfer capacitance (Cras) that allow for a small
gating loss under resonant drive conditions.
'In conventional RF designs, the loaded Q of the inverter tank is usually chosen to be large, resulting in
waveforms with high spectral purity [16,67]. For power conversion, however, the requirements on QL are
different since the goal is to maximize power transfer with minimum loss. A low value of QL results in less
energy resonated in the tank, which implies reduced conduction loss in the parasitic elements of the inverter.
- 59 -
Design Considerations for VHF de-dc Converters
The system described in this chapter also incorporates a new low-loss gate driver that recov-
ers most of the energy used to control the gate of the semiconductor device. Furthermore, it
provides fast response times compatible with control schemes that achieve high bandwidth.
An important attribute of this gate drive is the trapezoidal wave-shaping of the gate volt-
age; this characteristic allows fast commutation of the switch, requires only small passive
components for its realization, and provides near-minimum loss. The design of this gate
driver is treated in detail in Section 3.2
As shown in Fig. 3.1, the inverter is followed by a transformation stage, which provides a
means of scaling the voltages and currents of the inverter to a level at which a set of balanced
resonant rectifiers can operate efficiently. This stage also provides resistance compression [1]
to mitigate the inherent sensitivity of the class E to variations in load. Design of this type
of circuit is treated in [1] so is not considered further here.
The next stage in the dc-dc structure is a resonant rectifier which transforms the interme-
diate RF ac waveforms back down to dc. Rectifier circuits having characteristics similar to
tuned resonant inverters can operate efficiently under certain conditions [9,11,13,72]. This
chapter introduces a resonant rectifier structure in which two single-diode resonant recti-
fiers deliver power to a constant voltage output. The effective input impedance of these
rectifiers at the switching frequency is desired to be resistive to ensure suitable operation
of the previous stages. Design methods for this rectifier are presented in Section 3.3.
The design of high efficiency dc-dc converters requires the implementation of output control
techniques compatible with all of the requirements described in Section 3.1.1. One suitable
technique is the "cell-modulation" or "burst-mode" modulation [39, 41] sometimes used
to obtain high efficiency in converters operating at light load. Moreover, some cellular
architectures, like the ones introduced in [70] and in Chapter 2, also allow for high efficiency
operation over wide load ranges. In the implemented converter, regulation of the output
voltage is achieved by modulating the converter on and off ("bang-bang" control), forcing
the voltage to comply with a ripple specification. The simplicity of this control scheme
overcomes the difficulty in efficiently controlling RF amplifiers through other means (e.g.
frequency modulation [3, 10, 15, 20]). The converter system developed here is regulated
with a hysteretic controller that maintains the output voltage within a 100 mV hysteresis
band through on/off or bang-bang control of the converter. Section 3.4 will evaluate the
performance of a 11.5 W dc-dc converter switching at a frequency of 100 MHz with closed-
loop voltage control.
- 60 -
3.2 Self-Oscillating Multi-Resonant Gate Drive
As discussed in the previous section, reducing gating loss is essential to operating at very
high switching frequencies. Conventional hard-switched gate drives dissipate all of the
energy delivered to the gate from the gate drive supply each cycle. This results in a frequency
dependent gate drive loss:
Pgate = Ciss ate f (3.1)
To achieve very high frequency operation while maintaining acceptable gating loss, a res-
onant energy recovery gate drive is necessary. Switch transitions are effected by ringing
charge on and off of the gate [3, 24-27, 50, 69, 70]. Under these conditions, most of the
energy stored on the gate is recovered and total loss is a fraction of what can be expected
if the device were hard gated.
One approach, previously used in the prototype evaluated in Section 2.2, is a sinusoidal gate
drive [3, 50, 69-71]. In this approach, a resonant network is used to ring charge on and off
the gate such that the gate voltage is sinusoidal (possibly with a dc offset). For switching
times much longer than a gate RC time constant, this can be an effective method, providing
a reduced loss of:
Pgate = 27r2 2. C2,s RG - VI,ac (3.2)
where Cis,, is the gate input capacitance, RG is the effective series resistance of the MOSFET
gate and drive circuit, and VG,ac is the peak amplitude of the sinusoidal ac gate voltage.
While a sinusoidal resonant drive is effective in some applications, it does have some im-
portant limitations. First, many of the commercially-available LDMOS devices suitable for
VHF power conversion incorporate a protection diode between the source and gate termi-
nals, preventing the use of gate drivers which impose negative voltage excursions on the
gate. Moreover, even when a sinusoidal gate drive can be used, the ac drive magnitude
often has to be larger than needed to fully enhance the device in order to provide a fast
gate drive transition time, increasing overall gate loss by a square law as in (3.2). The
negative excursions of the gate drive voltage also induce unnecessary gate loss.
The most efficient way to charge/discharge the gate capacitance Ci, for a specified tran-
sition time is a constant current source [73, Appendix A]. A trapezoidal drive voltage
waveform applied at the gate of the semiconductor switch will yield an approximately con-
stant current on the rising and falling edges of the gate voltage (for small gate resistance
RG), thus minimizing the power dissipated in the gate resistance. As shown in [74], the
power dissipated in RG of an MOS transistor driven by a trapezoidal waveform is:
- 61 -
Design Considerationsfor VHF dc-de Converters
Pgate =C s Vate RG. + f is (3.3)

where Vgate is the maximum voltage of the trapezoid, Ci,, is the input capacitance of the
LDMOS,and tr and t1 are the rise time and the fall time respectively of the drive waveform.
Consider driving the gate of a MRF373ALSR1 LDMOSFET (having Cis,=114 pF and

RG=0.3 Q) at a switching frequency f,=100 MHz with the three driving schemes described
above. Hard gating with a peak gate voltage Vgate= 10 V dissipates 1.17 W. By contrast,
the power dissipated by a sinusoidal gate drive with VG,ac=15 V (large enough to rapidly
enhance the device) is only 173.16 mW. A trapezoidal driving scheme with tr = tf=l ns and
Vgate=10 V yields a further reduced dissipation of only 78 mW. (Note that a sinusoidal drive
would not be permissible due to the presence of a protection diode in the MRF373ALSR1,
making the trapezoidal drive the only one of the three viable in practice).
Here we introduce an efficient gate drive using a simple multi-resonant structure to imple-
ment trapezoidal voltage wave shaping. This circuit, shown in Fig. 3.3, is a switched mode
driver incorporating wave shaping methods similar to those employed in class F power am-
plifiers and related circuits [44-47,75-81], [57, Chapter 7]. Unlike traditional class F power
amplifiers, the driver proposed here operates in switched mode, thus providing maximum
efficiency. Moreover, the circuit does not incorporate a bulk (rf choke) inductor, enabling
rapid startup and shutdown of the gate drive to be realized.
Figure 3.4 shows a simple low-order lumped passive network that is at the core of the gate
drive. The input impedance of the network (ZIN) has maxima at two frequencies (poles).
The impedance is zero at dc and at a frequency somewhere between the two maxima. The
components LMR and CMR are tuned to be series resonant close to the second harmonic
as viewed from the drain/source port of the auxiliary device. The resonant components
LF and CF are tuned in conjunction with LMR and CMR such that the input impedance
a 'ZIN
qi{
Q1Q
Figure 3.3: Schematic of the multi-resonant gate drive. The input impedance ZIN, when
properly tuned, peaks in the vicinity of the fundamental and the third harmonics and has
low impedance at the second harmonic.
- 62 -
Figure 3.4: Simple multiresonant network.
ZIN in Fig. 3.4 presents relatively high impedance at the switching frequency and the third
harmonic of the switching frequency. This is done in such a manner that the voltage
vg(t) in Fig. 3.3 can support approximately trapezoidal waveforms that contain a dominant
fundamental voltage component and a smaller third harmonic component. A good design
starting point for tuning the low-order lumped network is to start with impedance maxima
(poles) at the fundamental and third harmonic, and a low impedance (zero) at the second
harmonic of the switching frequency as shown in Fig. 3.5. Component values for tuning the
poles of ZIN in Fig. 3.4 at exactly the fundamental and third harmonic and placing the
zero at the second harmonic can be determined from the following equations (derived in
Appendix A), starting from a selected value for CF [77,82]:
1 1 15
LF- 9 , LMR - , and CMR -CF . (3.4)
9,7r2f,2CF I 1572f,2CF 5 16
Note that the component CF incorporates the output capacitance Coss of the auxiliary
switch and the gate capacitance Ciss of the main semiconductor switch. It is important
to minimize the stray inductance between the gate of the main MOSFET and the auxiliary
drain node, such that both Co,, of the auxiliary device, and the gate capacitance Ciss of
the main device can be considered connected in parallel. Because the inductor LF acts as a
resonant inductor, it has a very small numerical value and small energy storage.
When the gate drive auxiliary switch in Fig. 3.3 drives this structure at the switching
frequency with a duty ratio of somewhat less than 0.5, the voltage waveform at the gate
is roughly trapezoidal and offset so that it never swings negative. Moreover, the dynamic
characteristics provide zero voltage switching of the driver switch, such that energy delivered
to the gate capacitance is naturally returned to the gate drive supply. These conditions arise
as a result of the half-wave symmetry imposed by the impedance of the network [45-47]. A
simulation of the gate to source voltage of the main switch with a switching frequency of
approximately 100 MHz is shown in Fig. 3.6. One can easily appreciate that the trapezoidal
waveform and dc offset characteristics are achievable. Experimental results confirming
practical low-loss operation of this drive are presented in Section 3.4.
- 63 -
Design Considerationsfor VHF de-de Converters
ZINI vs. frequency (CF=117pF, LF=9.6nH, CMR=109.7pF, LMR=5. 8 nH)

1001
...........
,
Simulation I
........
..................
0 100 200 300 400 500

Frequency [MHz]
Figure 3.5: Input impedance vs. frequency of the simple multiresonant structure shown in
Fig. 3.3 when the reactive elements follow the relations given in Equation 3.4.
Controlled self-oscillation of the driver is achieved by using an appropriate feedback network

around the gate drive circuit. A fraction of the drain to source voltage of the gate drive
MOSFET is phase shifted and applied to its gate. Figure 3.7 shows the network that provides
the required phase shift along with a simplified schematic of the start up circuit. The start
up circuit is required to initiate the oscillation at the application of the gate-drive input
voltage. (As shown in Section 3.4, modulating this input on and off provides a means of
controlling the converter.)
Components LFB, CFB and LT provide a phase shift of -180' of the fundamental voltage
at the drain of the auxiliary device in order to achieve self-oscillation while at the same
time the components are selected to minimize loading that could significantly change the
impedance ZIN of the multiresonant network.
This section presents PSPICE simulations of the self-oscillating gate driver implemented in
the prototype described in Section 3.4. For this simulation, the gate of the main LDMOS-
FET (Freescale MRF373ALSR1) is modelled as a series RLC branch with LG,main=700 pH,
RG,main=0.3 Q and Ciss,main,=114 pF. Referring to Fig. 3.7, the values of the elements of the
low-order lumped network are: L 1=8.1 nH, LMR= 4 nH, CMR=150.56 pF. Coss,aux= 4 8 pF,
- 64 -
Gate Voltage (1st and 3rd Multi-resonant network)

I
-
PSPICE Simulation
n. r
.......
.........
n
†T
i.
I IT I
5 10 15 20 25 30 35 40
Time [ns]
Figure 3.6: Gate to source voltage at input of the main MOSFET of the converter.
which together with Ciss,main makes CF =162 pF. Figure 3.8 shows the magnitude of the
impedance ZIN at the drain of the auxiliary LDMOSFET. The phase-shift network responsi-
ble for the self-oscillation is also included in the simulation as well as the parasitic elements
present in the printed circuit board (PCB). The magnitude of ZIN at the switching fre-
Multi-
Power/Control Phase-shift
Startup network resonant
Signal network Network
-- ---L-------------------
--- i
I Il II I
rL
(RTI RT 2 II
FIB
DT; I
DTB F
), I
I
IIII
M~Jn
QI
•
CTga D iiI L.J toi
:I _
iI ii
I
ILBI II
CTI __CT
r
Figure 3.7: Simplified schematic circuit of the startup control strategy.

Figure 3.7: Simplified schematic circuit of the startup control strategy.
- 65 -
Design Considerationsfor VHF de-dc Converters
quency (approximately 100 MHz) is higher that than at the third harmonic as explained
above.
Simulated ZIN at drain of AUX. LDMOS
Ci
in
CD
"a
.A
0 100 200 300 400 500
Frequency [MHz]
Figure 3.8: Simulated input impedance at the drain of the auxiliary switch of Fig. 3.7.
This simulation accounts for parasitics in the PCB and assumes linear device capacitances
and 0.7 nH lead inductance in series with the gate of the main LDMOSFET. Notice that
the phase-shift network does not significantly change the impedance at the frequencies of
interest (fundamental, 2nd and 3rd harmonic).
The gate of the auxiliary MOSFET Q2 (a Polyfet L8829) is part of the phase shift network
and is modelled as series RLC branch with RG,aux=3 Q and Ciss,aux=30 pF. The gate
inductance LG,aux is not significant and is included in the value of LT. The values of the
elements comprising the phase shift network are: LFB=100 nH, CFB=56.8 pF, LB=100 nH,
CB=2 nF and LT=84 nH. The magnitude and phase of the transfer function (TF) of the
phase-shift network responsible for achieving self-sustained oscillation is shown in Fig. 3.9.
As described above, the figure shows that at the intended frequency of oscillation (100 MHz),
the phase-shift angle of the TF is -1800. The phase-shift network also provides filtering to
attenuate the third harmonic, as is demonstrated in the figure.
The mechanism for starting the oscillation (and thereby turning on the converter) is as
follows. Referring to Fig. 3.7, after the gate drive power supply is applied, a delay of
- 66 -
Transfer function: v(gate)/v(drain) of AUX. LDMOS
Frequency [MHz]
Figure 3.9: Simulated magnitude and phase of the transfer function Vgate/Vdrain of the
auxiliary LDMOSFET. At the switching frequency (100 MHz), the phase shift is -1800.
duration Th is provided to allow the voltage at the drain of the auxiliary device to settle.
After this interval (Th) a pulse of voltage of duration Tp is applied to the phase-shift
network. This momentarily drives down the drain to source voltage of the auxiliary switch.
At the end of the pulse, the drain to source voltage will naturally ring with the harmonic
characteristics of the network. This voltage, in turn, drives the gate of the main switch.
To stop the oscillations, the supply voltage to the multi-resonant gate driver is cut by a
logic control signal. The durations of the hold interval (Th) and the pulse interval (Tp) are
determined by the timing components RT1,CT1 and RT2, CT2 respectively. Diodes DT1 and
DT2 provide a low impedance path to rapidly discharge the timing capacitors to allow for
faster activation rates. Figure 3.10 shows the simulated voltage at the drain of the auxiliary
LDMOSFET (gate of the main switch) under self-oscillating conditions at f,=102.2 MHz.
When modulating the dc-dc converter on and off, the energy stored in the bypass capacitors,
the timing elements of the network, and the output tank is lost in each transition. This
energy loss, as well as the time required for the cell to achieve steady state operation, limits
the maximum modulation frequency. On the whole, the small size of the energy storage
components keeps this loss to a minimum and allows a relatively large control bandwidth
on the order of 200 kHz.
- 67 -
Design Considerations for VHF de-de Converters
Simulated gate voltage: VDRIVER=5

DRIVERs
V, f=100 MHz
1
a,
C)
0 5 10 15 20 25 30
Time [ns]
Figure 3.10: Simulated gate voltages at the gates of the main and auxiliary switches. The
switching frequency f,=102.2 MHz.
Section 3.4 will present component values and experimental results for the trapezoidal gate
drive developed here and used in the prototype. This gate driver utilizes less than 100 mW
at 100 MHz switching frequency (less than 10% of an equivalent hard-switched gate drive).
3.3 Resonant Radio-Frequency Rectifier
The high-frequency sinusoidal voltage at the output of the inverter in Fig. 3.2 generates
sinusoidal currents at the outputs of the transformation/compression stage. These currents
are rectified to provide dc power to the converter output.
As described in [1, 51] it is desirable for the fundamental voltages at the rectifier inputs to
be substantially in phase with the currents at the output of the transformation/compression
stage. Under this condition, the transformation/compression network will provide appro-
priate loading to the inverter to maintain the desired ZVS.
- 68 -
3.3 Resonant Radio-Prequency Rectifier
Figure 3.11 shows the schematic of the resonant rectifier investigated here, loaded with a
constant voltage at the output. The rectifier is driven by a sinusoidal current source of
magnitude IIN. A resonant capacitance Cr represents the sum of an external capacitor
CEXT and an equivalent diode capacitance CD. Resonant inductor LR provides a path
for the dc current and resonates with capacitance Cr so that the input looks resistive at
the fundamental frequency. A similar rectifier structure was presented in the literature
in [72] but for very different drive and loading conditions that are not applicable to the
cell-modulation converter system considered here.
---------
i Coh
Figure 3.11: Resonant rectifier connected to a constant output voltage. The resonant ca-
pacitance C, is the sum of the diode capacitance CD and an (optional) external capacitance
CEXT- CEXT may also be placed directly in parallel with the diode.
The conduction duty cycle of the diode depends on the component values. By adjusting
the net capacitance CR in parallel with the resonant inductor, it is possible to trade off
the length of the conduction interval and the peak reverse voltage across the diode. It is
convenient to have a conduction interval close to 50 percent, as this provides a good tradeoff
between peak diode forward current and reverse voltage. This additional capacitance can
either be added externally or can be solely provided by additional diode area, which can
have the added benefit of reducing the overall conduction loss in the rectifier. The value
of LR of the resonant rectifier is selected in conjunction with Cr to provide the desired
"resistive" input characteristics (fundamental rectifier input voltage in phase with rectifier
input current). Appropriate values can be found through straight parametric search using a
simulation tool (e.g. PSPICE or a piecewise linear simulator) by looking at the fundamental
component of the voltage vrec and minimizing the phase angle between the input current
and the fundamental component of the rectifier input voltage at a given nominal output
power.
Figure 3.12 shows the input current and voltage of a resonant rectifier (of the type shown in
2
Fig. 3.11) simulated using PSPICE. For the simulation shown, LR=18.8 nH, CEXT=3 pF,
- 69 -
Design Considerations for VHF dc-de Converters
CD is the non-linear device capacitance of the diode (Di, an MBRS260T3 Schottky diode),
VoUT=12 V, and the sinusoidal input current IIN=0. 6 7 A at a frequency of 100 MHz. The
average power delivered to the load under these conditions is 6.2 W. Note that Fig. 3.12
shows that the fundamental component of the input voltage and the current are nearly
in phase resulting in a rectifier with an equivalent resistance (only at the fundamental)
of approximately 29.8 Q2. The equivalent impedance at the fundamental frequency of the
Rectifier
Inputcurrent andInputvoltage
vs.Time -- Rectifier
inputcurrent andfundamental ofinputvoltage
vs.Time"-
,50 1 40
InputCurrent
- - - InputVoltage(fundamental)
0.5 20
c
C
* . a
r 2S 0
! , r 0
i
-0.5 -20
i _-ll
15 20 25 -0 5 10 15 20 25"
Time[ns] Time[nsl
(a) Time domain (b) Fundamental
Figure 3.12: Rectifier input voltage and input current, when driven by a sinusoidal current
source IIN at a frequency of 100 MHz. The resonant rectifier is delivering 6.2 W to a 12 V
output.
rectifier will change with the input current. Over the operating range of the rectifier, it is
desired that this equivalent input impedance remain substantially resistive. Table 3.1 shows
how the equivalent impedance of the rectifier changes as POUT changes from 4 W to 14.47 W
(i.e. with changes in the drive current magnitude at constant output voltage.). Notice how
even as the equivalent resistance changes over the operating range, the equivalent reactance
remains small.
The rectifier, a non-linear circuit, will generate an input voltage vrec with significant har-
monic content. For optimum operation of the implemented system, it is desirable to block
the effects of the harmonic components on the inverter current. This is accomplished as
part of the transformation stage and resistance compression network, as described in [1].
3.4 Experimental Results and Evaluation
This section evaluates the performance of a prototype dc-dc converter implementing the
techniques described in the previous sections. Figure 3.13 shows a photograph of the 11.5 W
- 70 -
Table 3.1: Equivalent impedance of the rectifier of Fig. 3.11.

POUT IZINI ZZIN Re{ZIN} ~Smn{ZIN}
[W] [Q] (degrees) [Q] [A]
4.000 38.52 21.6 35.81 14.18
5.398 32.87 7.2 32.61 4.12
6.554 28.61 0 28.61 0
7.621 25.33 -3.6 25.28 -1.59
8.643 22.73 -10.8 22.33 -4.26
9.634 20.62 -12.6 20.12 -4.50
10.611 18.87 -14.4 18.28 -4.69
11.583 17.40 -16.2 16.71 -4.85
12.549 16.16 -18.0 15.37 -4.99
13.509 15.10 -19.8 14.21 -5.11
14.470 14.17 -21.6 13.17 -5.22
converter operating at a switching frequency of approximately 100 MHz. Schematics and

component values for the power stage are provided in Figs. 3.2 and 3.7 and Tables 3.2 and 3.3
(Additional detals may be found in [51].). The input voltage range is from 11 V to 16 V
and the output voltage is 12 V with an output voltage ripple of 100 mV.
Figure 3.13: Power stage of the prototype 100 MHz dc-dc power converter.
Waveforms showing the operation of the inverter for Vin,dc = 11 V and Vout,dc = 12 V can
be seen in Fig. 3.14. In the top panel of the figure are the drain to source voltage and
the voltage at the input of the transformation stage in Fig. 3.2. It is clear from the figure
- 71 -
Design Considerationsfor VHF de-de Converters
that zero-voltage turn-on of the LDMOSFET is achieved, indicating a proper impedance

match. Shown at the bottom of the same figure is the gate to source voltage driving the
semiconductor switch. The total power dissipated by the gate driver, including the startup
Table 3.2: Components used in 100 MHz dc-dc converter of Fig. 3.2.
Component Nominal Manufacturer Part Measured
Name Value and Part Style Number Value
Ccl 18 pF CDE Chip- MC08EA180J 36.22 pF
+15 pF Mica 100 V MC08EA150J
Cc 2 56 pF CDE Chip- MC12FA560J 66.5 pF
+7 pF Mica 100 V MC08CA070C
Cextra 10 pF x 2 CDE Chip- MC08CA100D
Mica 100 V
Cin 2.2 IuF Tantalum 35 V PCT6225CT
+0.68 pF Tantalum 35 V PCT6684CT
+0.047 pF x 12 Ceramic 50 V Kemet
CR 82 pF CDE Chip- MC12FA8205
+2 pF Mica 100 V MC08CA020D
CR1, CR2 15 pF x 2 CDE Chip- MC08EA150J CR1=32.6 pF
Mica 100 V CR2=32 pF
Cout 0.1 pF x 19 Kemet C0805C104M5UAC
Ceramic 50 V
D1 , D2 Schottky ON Semi MBRS260T3
Power Diode 60V, 2.0A
L1 17.5 nH Coilcraft B06T6
Let 33 nH Coilcraft 1812SMS-33N 38.1 nH
LC2 68 nH Coilcraft 1812SMS-68N 69.9 nH
Lchoke 120 nH x 2 Coilcraft 1812SMS-R12G
LDMOS Freescale MRF373ALSR1
70 V (max Vds )
LR 12.5 nH Coilcraft A04TJ
+ Two-turn 18 AWG Approx.
magnet wire coil 22 nH
+8.9nH board parasitic
LR1, LR2 18.5 nH Coilcraft A05T LR1 =18.9 nH
LR2 =18.7 nH
- 72 -
Table 3.3: Components used in the self-oscillating multi-resonant gate drive of Fig. 3.7.
Component Nominal Manufacturer Part Measured
Name Value and Part Style Number Value
LF PCB trace 8.1 nH
CF 48 pF Coss,aux 162 pF
+114 pF Ciss,main
LMR PCB trace 4 nH
CMR 100 pF CDE Chip- MC12FA101J 150.56 pF
+47 pF Mica 100 V MC12FA470J
+4 pF MC08CA040D
LFB 100 nH Coilcraft 1812SMS-R10 L 100 nH
CB 2 nF Ceramic 50 V Kemet 2 nF
CFB 47 pF CDE Chip- MC12FA470J 56.8 pF
+5 pF Mica 100 V MC08CA050D
+3 pF MC08CA030D
LB 100 nH Coilcraft 1812SMS-R10 L 100 nH
LT 82 nH Coilcraft 1812SMS-82N L 84 nH
RT1 1 kQ Rohm, 0805, 1/8 W, 1 % MCR10EZHF1001 1 kO
CT1 100 pF Kemet, 0805, 50 V C0805C101J1GAC 325 pF
+220 pF Kemet, 0805, 50 V C0805C221J5GACTU
DT1 Diodes Inc. BAS70-7
RT2 2.43 kQ Rohm, 0805, 1/8 W, 1 % MCR10EZHF2431 2.43 kf
CT2 100 pF Kemet, 0805, 50 V C0805C101J1GAC 325 pF
+220 pF Kemet, 0805, 50 V C0805C221J5GACTU
DT2 Diodes Inc. BAS70-7
Rgst 100 ~11100 Q Rohm, 0805, 1/8 W, 1 % MCR10EZHF1000 50 0
Dgst Diodes Inc. BAS70-7
IC 1 National LLP-6 LM5115
IC 2 National LLP-6 LM5115
Auxiliary LDMOS Polyfet SO-8 L88219
- 73 -
Drain to Source Voltage and Inverter Voltage
Time [ns]
Gate to Source Voltage
0
,e,,
Time [ns]
Figure 3.14: Drain to source voltage and gate to source voltage of the prototype converter.
Also shown is the voltage at the input of the transformation stage. Values are shown for a
dc input voltage of 11 V and dc output voltage of 12 V.
circuitry, was measured to be less than 100 mW, which is more than an order of magnitude
less than the power that would be dissipated had the switch been driven with conventional
hard-switched gating (and lower than the 300 mW dissipation of an earlier implementation
of this gate drive [1]).
The output voltage ripple under closed-loop control is shown in Fig. 3.15 when VOUT,DC =
12 V, POUT = 10 W. Under these conditions, the controller modulates the converter on and
off at 83.3 kHz to provide the average power required to regulate the output. The control
signal modulating the converter system on and off is shown in the lower trace of Fig. 3.15.
This control signal commands the converter either to operate or to remain inactive depend-
ing on the conditions of the output voltage. The resulting output ripple is approximately
100 mV peak to peak, independent of load. In the figure, the 100 MHz switching ripple
(observed as the "hash" when the output voltage is rising) is under-sampled in the time
scale shown. While the modulating frequency is on the order of 100 kHz, most of the the
energy storage components in the converter are sized based on the 100 MHz switching fre-
quency. Only the input and output capacitors are sized based on the modulation frequency.
The modulation frequency is determined by the loading conditions, the allowed hysteresis
- 74 -
band around the nominal output voltage, and the size of the output filter capacitor. In
the implemented design, the maximum modulation frequency was in excess of 200 kHz.
Figure 3.16 shows the schematic for the hysteretic modulation controller and the switched-
Output Voltage Ripple [ VOUT,DC=12 V, Put10 W,fts100 MHz, fmod=83.3 kHz ]

1UU
E
50 . . . . . . . .
.......... · · ·· · · .
·.
·.
:·.··
· ·
-50 ... .. .... ... .. .. .. ..

...
......
0 _11nn
-5 0 5 10 15 20 25 30
Time [its]
E
0,
C
E
E
0
0
Time [Ls]
Figure 3.15: Output voltage ripple and modulation control signal during steady state op-
eration. VOUT,DC = 12 V, POUT = 10 W, VIN = 16 V.
mode regulator that provides power to the self-oscillating gate drive and start-up circuitry.
Table 3.4 lists all the components used in the design of the controller and the auxiliary
power supply which provides power to the gate drive. This auxiliary supply is a switched
mode supply that is rated to provide the power for the controller and the gate drive.
As described in Section 3.1, the on/off control scheme and the small values of the reactive
components allow for fast dynamic response of the converter. This is evident in Fig. 3.17
which shows the output voltage during a step change in load going from 4 W to 8 W: no
substantive change in output voltage is observed. The figure also shows the change in the
modulation control signal due to the load change.
As described in Section 3.2, the small sizes of the energy storage elements used in the design
of the dc-dc converter allows for fast modulation rates. Figure 3.18 shows the modulation
control signal and the drain to source voltage of the main MOSFET when the cell is switched
- 75 -
Design C
UT-,
UT-1
Figure 3.16: Schematic of the hysteretic controller.
Load Step from 4 Wto 8 W [VIN=11 V VOUT=11. 95 V]
)0
Time [RLs]
)0
Time [gls]
Figure 3.17: Output voltage ripple and modulation control signal during a load step. POUT
is changed from 4W to 8W.
- 76 -
Table 3.4: Components used in the on-off controller board and auxiliary power supply of
Fig. 3.16.
Component Nominal Manufacturer Part
Name Value and Part Style Number
R1 510 kf2 Rohm, 0805, 1/8 W, 1 % MCR10EZHF5103
R2 150 kOf Rohm, 0805, 1/8 W, 1 % MCR10OEZHF1503
R3 7.5 k2 Rohm, 0805, 1/8 W, 1 % MCR10EZHF7501
R4 3.9 kQ Rohm, 0805, 1/8 W, 1 % MCR10EZHF3901
R5 100 kQ Rohm, 0805, 1/8 W, 1 % MCR10EZHF1003
R6 3 kf2 Rohm, 0805, 1/8 W, 1 % MCR10EZHF3001
C1 10 pF TDK, 1210, 16 V C3225X5R1C106M
C2 1 ILF TDK, 0805, 16 V C2012X5R1C105K
C3 0.1 IF KEMET, 0805, 50 V C0805C104M50AC
C4 10 pF KEMET, 0805, 100 V C0805C100J1GAC
C5 22 pF TDK, 1210, 10 V C3225X5R1A226M
C6 1 IF TDK, 0805, 16 V C2012X5R1C105K
C7 0.1 1iF KEMET, 0805, 50 V C0805C104M50AC
C8 0.1 pF KEMET, 0805, 50 V C0805C104M50AC
C9 0.1 pF KEMET, 0805, 50 V C0805C104M50AC
C 10 100 pF KEMET, 0805, 100 V C0805C101J1GAC
C 11 2 pF CDE, 0805, 100 V MC08CA020D
U1 Texas Instruments, QFN16 TPS6211
U2 Texas Instruments, SOT23-6 TLV3501
U3 Analog Devices, TSOT23-5 AD392
on and off. The converter reaches steady state operation in approximately 600 ns at turn-on
and also 600 ns at turn-off.
Figure 3.19 shows the efficiency of the dc-dc converter when operating under closed loop
control. The figure plots the efficiency as the input voltage is varied over the operating range
(11 V to 16 V), parameterized in output power Pout. While the efficiency of this prototype
design is not particularly high, our ongoing design work indicates that substantially higher
efficiencies are achievable using the design methods proposed here.
- 77 -
1
E Turn-on transient NVIN=1
V,VOUT-12
V] E V]
Turnoff transient[Vm=11V,VOUT12
1601
1 40 .... .....
80 20 .........
0 ........
0 0.2 0A 0.6 0.8 1 0 0.1 0.2 0. OA 0.5 0.6 0.7
Time [pA] Time [p~]
10. 10
10:7.......
5
-
.................
0.2
---
0.4A
Time [p]
0.6
-
0.8 0 0.1 0.2 0.3 0.4
Tine [p1]
0.5 0.6 0.7
(a) On (b)Off
Figure 3.18: Drain to source voltage and control signal during startup and shut down of
the converter in on/off control. VIN=11 V, VOUT= 1 2 V. The cell is fully on in 600 ns and
turns off in about 600 ns.
3.5 Conclusion
This chapter describes methods and circuits suitable for the design of dc-dc converters
operating at very high frequencies. These methods are applied in the design of a dc-dc
Converter Efficiency vs Input Voltage at Various Loads
S-- -
0.74 U./O
i
i W
I ~Pout=11.5
- ~ VVWI
~W-'UUL= f~AJ
lU
0.74 . .... *-. Pout=8 W
0.74 . . ..
:: : - Pout=6 W
**... Pout=4W
>, 0.72 . ...... .. ... . ................. .............. ...............
..
w
0.7 •:
............ ...........
... .......
..... ..... .:-
....
0 0.68
I:,
..
-,
.......
........................:.
.... ..
. ...
..
0.66 ............I .......... • . .. . . . . . . . . . . .. ......................
:,, "I . , I It
I I
n IA
11 13 14
Input Voltage [V]
Figure 3.19: Efficiency vs. input voltage at different output power levels. Vout=12 V.
- 78 -
3.5 Conclusion
converter operating at a switching frequency of 100 MHz. Gate drive, rectifier and control
designs are explored in detail, and experimental measurements of the complete converter
are presented that verify the design approach. The gate drive, a self-oscillating trapezoidal
circuit, dramatically reduces the gating power while ensuring fast on-off transitions of the
semiconductor switch. The rectifier is a resonant topology that absorbs diode parasitic
capacitance and is designed to appear resistive at the switching frequency. The small sizes
of the energy storage elements (inductors and capacitors) in this circuit permit rapid start-
up and shut-down and a correspondingly high control bandwidth. These characteristics are
exploited in a high-bandwidth hysteretic control scheme that modulates the converter on
and off at frequencies as high as 200 kHz. It is anticipated that the guidelines and techniques
presented here will facilitate the development of power supplies with switching frequencies
in the VHF range and beyond that meet the emerging demands for high performance power
electronics.
- 79 -
Chapter 4
An Advanced Resonant Inverter Topology
T HERE IS an interest in power electronic systems that achieve a greater degree of minia-
turization and meet more stringent transient specifications than present-day designs.
As described in Chapter 2, this can be achieved through system architectures and designs
that enable the use of greatly increased switching frequencies and associated reductions in
internal converter energy storage. This chapter presents a new switched-mode resonant
inverter, which we term the #2 inverter, that is well suited to operation at Very High
Frequencies and to rapid on/off control.
4.1 Background
Some high frequency dc-dc converters, such as the ones described in previous chapters of this
thesis, use a resonant inverter to efficiently generate high frequency sinusoids, a transformer
or matching network to provide voltage transformation, and a rectifier to convert back to
dc [1, 10, 13, 50, 69, 70, 83-85].
The designs of dc-dc converter cells presented in sections 2.2 and [1], make use of the class E
inverter topology (shown in Fig. 4.1 (a)). While the Class E inverter topology has many
merits, it also has some limitations for the VHF designs considered here. These limitations
include a tight tie between device capacitance and output power, and the need for a bulk
inductor (an "rf choke").
Among the undesirable characteristic of the class E topology ,in power-converter applica-
tions, is the high voltage stress imposed on the switch. The peak switch voltage stress in an
ideal class E circuit is about 3.6 times the input voltage [16, 52] (idealized operation using
linear passive components, ideal switch, 50% duty cycle). In practical implementations,
with operating frequencies reaching into the VHF range, the capacitance C1 of the class E
circuit of Fig. 4.1(a) is oftentimes solely provided by the semiconductor drain-to-source ca-
pacitance. The non-linear variation of the device capacitance with drain voltage can further
increases the voltage stress across the semiconductor, reaching a value of almost 4.4 times
the input voltage [86] for this circuit. Some radio-frequency power amplifiers, such as class F
- 81 -
and variants use resonant harmonic peaking of the input or output network [44,57,75,78-81]
to reduce the peak voltage on the switch. However, most practical rf amplifier designs of
this type operate with significant overlap of device voltage and current (i.e. not fully in
"switched mode"), thus providing unacceptable efficiency for our purposes.
A switched-mode variant of the class F inverter that can be made highly efficient is the so-
called class D inverter. This approach, proposed in [45,46], uses a transmission-line network
or a high-order lumped simulating network at its input to provide waveform shaping that
reduces peak device stress, without the need for a bulk rf choke. Unlike most practical
class F designs, the Class 5 inverter operates entirely in switched mode (at duty ratios
below 50%). This yields high efficiency and provides reduced device stress and improved
energy storage requirements as compared to traditional inverters. However, these inverters
utilize high-order resonant structures with many energy storage components and/or modes
and relatively high complexity.
In converter architectures relying on on/off control of the converter circuit to regulate

the output (such as those in [70, 77]), it is desirable to achieve fast transient response
for start up and shut down. In this type of system, traditional class E converter circuits
have the disadvantage of a large value of the input inductor. This results in a relatively
large energy stored which in turn increases the time for the converter to reach steady state
(e.g., during startup or shutdown). Some less familiar inverter topologies, like the "second
harmonic Class E" [87,88] shown on the right of Fig. 4.1(b), reduce the bulk energy storage
requirement compared to the class E, but do not reduce the peak device voltage stress.
L,
(a) Class E (b) 2nd Harmonic Class E
Figure 4.1: Class E inverter (left) and 2 nd harmonic Class E inverter (Right). Inductor
L 1 in the 2 nd harmonic Class E is a resonant element; this reduces the energy storage
requirements and achieves a faster transient response compared to a conventional class E
RF inverter.
Both the class E and the second harmonic class E inverters also share the disadvantage of
having a tight link between the output power and the drain-to-source capacitance of the
switch. For the class E inverter POUT = 27r2 f, - VI2N . C,while POUT = 2".f, VI2N. C1
for the second harmonic class E. This implies that at high operating frequencies the power
- 82 -
4.2 A New Class-D based Inverter Topology
amplifiers are bounded to a minimum output power that may be higher than the desired
output power. Running at a design power greater than desired hurts efficiency, making this
limitation a significant consideration. Of these two designs, the second harmonic class E
has a higher allowable frequency limit for a given power throughput and device capacitance.
However, both designs suffer from this tight tie between output power, capacitance, and
efficiency.
In light of the above issues, there is need for improved topologies that enable VHF operation,
provide low device stress and loss, and require a reduced number and size of energy storage
components. This chapter introduces a new design that addresses these issues. This circuit
topology is based on a simplified "Class-4" inverter which attenuates second harmonic
voltage to provide waveform symmetry. The basic structure of this inverter is the same
as the one used in the trapezoidal gate drive introduced in section 3.2, but used here as
an efficient high-frequency power stage. Furthermore, the design of this topology permits
a degree of absorbtion of device capacitance into the waveshaping network. This breaks
the tight link between the output power and output device capacitance, providing more
flexibility for designs over wider frequency and power range.
4.2 A New Class-D based Inverter Topology
This section introduces a new Class-4 based inverter topology, in which a passive network
having multiple critical frequencies is periodically excited to provide voltage conversion
through resonant action. The network is tuned to obtain a voltage across the main switch
with low peak amplitude, and to allow switched-mode operation and low loss by achieving
near zero voltage at turn-on and turn-off. By proper tuning, one can also obtain zero dv/dt
at switch turn on, which is also a desirable condition for operating at frequencies in the
VHF-UHF range.
Figure 4.2 shows the simple passive low-order lumped network at the core of the topology.
The driving point impedance of the network (ZIN) has maxima at two frequencies. The
impedance is zero at DC and at a frequency somewhere between the two maxima. By
incorporating an appropriate controllable switch and a reactive connection network, an
inverter can be designed that delivers high frequency ac power efficiently to a resistive load.
- 83 -
va. Frequency
IZmI
KI
Frequency [MHz]
(a) Low Order Network (b) IZINI vs. freq.
Figure 4.2: (a) Simple low-order lumped network. Example of IZIN I vs. frequency is shown
in (b)
4.2.1 The Class-4 2 Inverter
Figure 4.3 shows the new (2 inverter topology. The inverter incorporates the low order
passive network of Fig. 4.2, and by controlling the impedance at the first few harmonics of
the switching frequency, achieves a significant reduction of the peak drain voltage across
the switch. To better understand the working principles behind the operation of the the
Class (2 inverter, the circuit in Fig. 4.3 has been divided in two parts: One part, formed
by the controllable switch and the low-order lumped network has an impedance ZMR when
the switch is "off".' This portion of the network provides a crude approximation to the
impedance and waveform symmetrizing characteristics of a shorted quarter-wave trans-
mission line [45-47,89]. The other part is a load network, having an impedance ZL and
comprising the resistance RLOAD, a reactive interconnect (Xs in the figure), and a shunt
capacitance Cp. The total impedance seen looking into the drain-source port of the power
MOSFET (or other switching device) is given by Zd, = ZMRIIZL.
A characteristic feature of the (2 inverter is that components LMR and CMR are tuned
to be series resonant near the second harmonic of the switching frequency. This condi-
tion imposes a low impedance across the switch at the second harmonic and prevents the
drain voltage Vd, (t) from having a significant second harmonic component. The rest of the
components (forming the reminder of ZDS) are tuned to provide relatively high impedance
1
We use the subscript MR for the components forming a "multi-resonant network". LMR and CMR
form the second harmonic series resonator, which produce a Zero in the impedance of the drain node. As
demonstrated in the Foster's reactance theorem (Corollary 2) [49] there is always a zero between adjacent
maxima in reactive networks with "Multiple Resonances".
- 84 -
4.3 Design procedure for the 42 Inverter
VLOAD
Figure 4.3: Class I2 inverter.
at the fundamental and the third harmonic of the driving frequency. Because the switch
imposes a constant voltage when it is on, and the network impedance dominantly supports
fundamental and third harmonic components of voltage, the overall drain-source voltage
waveform is approximately trapezoidal. The exact shape of the drain voltage is determined
by the impedance of the drain-source port, which is selected as part of the tuning process
to secure the zero-voltage switching conditions that allow high frequency switched-mode
operation. Since the performance of the inverter depends heavily on tuned components, the
42 inverter operates most effectively at a fixed frequency and duty ratio.
Plotting the impedances ZMR and ZL vs. frequency (for the equivalent circuit when the
switch is "off") and the resulting impedance Zd, is useful for tuning the inverter to achieve
the desired waveshaping of the drain node (e.g. see Fig. 4.5). During the operation of the
inverter, and for the interval in which the switch is "on", energy flows from VIN and is
stored in the inductor LF. Also during this interval, energy is circulated (at two times the
switching frequency) in the resonant leg formed by LMR-CMR. The state of these passive
elements at the end of "on" interval becomes the initial conditions of the resultant circuit
when the MOSFET is off. It is during this interval that the drain to source voltage of the
inverter rings with a characteristic determined by the impedance of the drain node.
4.3 Design procedure for the (2 Inverter
4.3.1 General Overview
The design of the 12 inverter begins by structuring the resonant tank (formed by Xs and
RLOAD in Fig. 4.3) to deliver appropriate power to the resistive load from the trapezoidal
drain to source voltage. Then, the components that comprise the impedance Zd, are tuned
- 85 -
to achieve the desired waveform shape. As will be shown, the appropriate drain-source
impedance Zd, characteristics are:
* An impedance null at the second harmonic of the switching frequency.
* An inductive impedance at the fundamental, with a phase angle between 200 and 500.
* An impedance at the 3 rd harmonic of the switching frequency with a magnitude that

between 4 and 10 dB below that at the fundamental switching frequency.
There are many ways to achieve this goal, but here we consider one route towards it.
4.3.2 Tuning Procedure
4.3.2.1 Component Selection of the Reactive Interconnect Xs
Components Ls and Cs are part of the output tank that connects the drain to the load
resistor RLOAD. This reactive interconnect (labelled Xs in Fig. 4.3) performs multiple
functions: It provides dc blocking, and also forms an impedance divider that controls the
ac power delivered to the resistive load. Moreover, the output tank forms part of the total
impedance Zd, and thus is also involved in the waveshaping of the switch voltage.
To determine the component values of the interconnect, we begin by assuming that the
drain voltage Vd,(t) is a trapezoid, which can be further approximated by a square wave to
simplify the design. This square wave has 50% duty cycle, an average voltage equal to VIN,
and swings between 0 and 2 VIN. Further, we assume that the all the ac power is delivered
to the load only at the fundamental of the switching frequency. Hence, we can represent
the output tank of the (2 inverter with the equivalent circuit shown in Fig 4.4. Here, Vdsl
represents the fundamental of ds,(t) which has an amplitude Vd8 =4 . VIN. Xs can be
implemented to either look capacitive or inductive at the fundamental: both possibilities
are viable, but yield differences in the way harmonic components are handled.
Consider how the reactance Xs in Fig. 4.3 can be obtained. As mentioned above, Xs forms
part of a reactive divider that sets the output power delivered to RLOAD. By reference
to Fig. 4.4, one can determine for a given output power, Vloadl,RMS = VPOUT " RLOAD-
Knowing that the effective value of the fundamental component of Vd,(t) (approximated by
a square wave) is Vdsl,RMS = -4 - VIN one can obtain the desired reactance Xs as:
- 86 -
4.3 Design procedure for the D2 Inverter
Vdl1 VLOAD1
Figure 4.4: Model at the fundamental frequency used to size the components of the reactive
interconnect network.
2
( Vloadl,RMS
RMS )
Xs = RLOAD" -1Vloadl, (4.1)
Ls and Cs are then selected to provide this desired reactive magnitude (with inductive or
capacitive phase) and a desired frequency selectivity.
4.3.2.2 Initial Sizing of the elements of ZMR
The next step in the tuning procedure of the b, inverter is selecting the components that
form the impedance ZMR in Fig. 4.3. The elements forming ZMR are part of the low-order
network of Fig. 4.2(a), and play a major role in shaping of the voltage Vd, into a trapezoid.
One possible starting point is to tune the network represented by Fig. 4.2 (a) such that
the impedance maxima of ZIN (or ZMR in Fig. 4.3) are at the fundamental and the third
harmonic of the switching frequency. Component values for tuning the poles of Fig. 4.2 at
exactly the fundamental and third harmonic and placing the zero at the second harmonic
can be determined starting from a selected value for CF [57, 82]:
1 1 15
LF = 2
, LMR = 2
, and CMR= -CF- (4.2)
91r fSCF 157r f22CF 16
These relations are derived in appendix A.
Notice that in the )2 inverter of Fig. 4.3, the capacitance of the semiconductor switch and
the capacitor CFEXTRA in ZMR form the capacitor CF in the network of Fig. 4.2 (a). The
value of the capacitor CF used to obtain the other components of ZMR can be solely the
semiconductor capacitance, a fraction of it, or a larger value. The specific value chosen can
be used as a design handle that has a significant impact on the performance of the inverter.
- 87 -
Using larger values of CF in Eq. 4.2 will shift the impedance magnitude of Fig. 4.2 down,
and because the drain impedance Zd, = ZMRIIZL, reducing the magnitude of ZMR may
be a necessary step in applications in which the impedance ZL heavily loads the drain
impedance Zds. In some other applications, a smaller value of CF may be a better choice,
because it increases the impedance of the rest of the components of ZMR, and thus reduces
the circulating currents throughout the network. On the other hand, using a really small
or large value of CF results in unreasonable values for the rest of the components of the
network. Then, the choice of the value of CF is a trade off between the allowable resonating
losses (due to the Q of the components) and the output power delivered to ZL.
Eq. 4.2 gives good starting point for the value of LF, but extra tuning may be required.
The detailed tuning of LF is accomplished to obtain desirable waveform characteristics at
the switch terminals. These characteristics may include zero-voltage switching (ZVS) of the
semiconductor switch and zero dv/dt across the switch at switch turn on (It is recognized
that highest efficiency operation may occur for other tuning objectives, however.)
4.3.2.3 Achieving the Important Characteristics of Zd,
The next step in the tuning process is selecting Cp, which includes any capacitance of the
semiconductor not used as part of CF in the previous tuning step. In a design in which
the reactance Xs is positive (inductive tuning), the impedance of Cp dominates the high
frequency portion of the impedance ZL in Fig. 4.3(e.g. see Fig. 4.5). In this case, the
impedance ZL will look capacitive at low frequencies (for 0 < w < 1 ), inductive near
the fundamental of the switching frequency (< <
- w < 1r), and capacitive again
somewhere in between the fundamental and the third harmonic. Increasing Cp reduces the
impedance ZL (and Zds) at the third harmonic .
Looking into the drain node of the '2 inverter, the relative magnitudes of the impedance
Zd8 at the fundamental and the third harmonic of the switching frequency determine how
large these components are going to be in the drain to source voltage Vd,(t). Thus, the ratio
of these impedance magnitudes has a direct impact on the maximum voltage across the
semiconductor. Alternatively, the impedance ratio can be varied by making changes to the
impedance at the fundamental of the driving frequency. For typical designs, the impedance
at this frequency is determined by the parallel combination of jwLF and jXs + RLOAD.
The zero-voltage turn-on condition on the MOSFET occurs when the net impedance Zd,
is inductive at the fundamental (having somewhere between 20 and 50 degrees of phase).
Because the proposed initial tuning of ZMR peaks at the fundamental (ideally, at w = w,
IZMRI - 00), the impedance ZL dominates Zd, at this frequency. Although Xs is designed
- 88 -
4.4 Practical Design of a 30 MHz (2 inverter
to look inductive at this frequency, the phase angle of Xs may be too small to achieve ZVS.
The phase angle of Zd, at the fundamental, can be increased by reducing LF, an action
that will also increase the frequency at which ZMR peaks. Moreover, reducing the value of
LF will speed the transient response of the converter, but this consideration is secondary to
the tuning process. Note that Cp and LF may be adjusted iteratively to achieve the desired
characteristics.
In the proposed (2 inverter of Fig. 4.3, LF acts as a resonant inductor. At driving frequencies
in the VHF range, LF has a very small numerical value and low energy storage as compared
to the rf choke found in many inverters such as the traditional class E inverter [16,52].
To summarize, the steps in the tuning process of a %2 inverter are:
1. Select the reactance Xs to deliver the desired output power. For the case in which Xs is
inductive, Cs only provides dc blocking.
2. Starting with a suitable value for CF use Eq. 4.2 to obtain values for CMR, LMR, and
LF. With these values ZMR will peak at the fundamental and third harmonic of the
switching frequency and will have a null impedance at the second harmonic.
3. Cp is selected to attenuate the impedance Zd, at the third harmonic, to achieve a ratio
between the fundamental and the third harmonic of 4 to 10 dB. This ratio has a direct
impact on the maximum drain to source voltage during operation of the inverter.
4. If necessary, LF is reduced from its nominal value found using Eq. 4.2, to increase the
phase angle of Zd, at the fundamental. A phase angle between 20 and 500 results in ZVS.
Reducing LF increases circulating currents in the network and can have and adverse effect
in the performance of the inverter.
4.4 Practical Design of a 30 MHz 42 inverter
To show the trade offs involved in the design of the %2 inverter, this section describes the
tuning process of a 30 MHz O2 inverter designed to deliver 275 W to a 33.3 11 resistive
load. A subsequent section will present details on the experimental implementation of the
inverter designed here, and will show measurement of the performance of the prototype.
For the design presented here the input voltage ranges between 160 V and 200 V.
The semiconductor switch selected for this design is a 500 V vertical MOSFET (APT521)
which has an Rds,ON = 1~ and an Coss=55.42 pF at VDS = 160 V. Details on the modelling
of the semiconductor in the simulation results presented here can be found in [90].
- 89 -
We begin by calculating the value of the components forming Xs. In this design, Xs will be
designed to look inductive at the switching frequency. For an output power of 275 W when
VIN=160 V, with RLOAD= 3 3.3 Q, we use Eq. 4.1 and set Xs = 2r.f, -Ls. With this choice,
and at a switching frequency of 30 MHz, Ls=199 nH. The value of Cs is selected to provide
dc blocking and to have a low impedance when compared to the the series combination of
Ls and RLOAD. This can be achieved with a capacitor Cs=4 nF. (Note that making the
value of Cs excessively large can have a detrimental impact on the transient response of the
inverter in certain applications.)
The elements comprising ZMR are initially tuned according to equation 4.2 to peak at the
fundamental and third harmonic and to have a zero in impedance at the second harmonic
of the switching frequency. To minimize the circulating current throughout the resonant
elements of the inverter, we calculate the value of the components of ZMR assuming a
value of CF=20 pF, which for a switching frequency of 30 MHz results in LF=625.4 nH,
LMR=3 7 5 .2 6 nH and CMR=18.75 pF.
Figure 4.5 shows the simulated magnitude of the impedances ZL, ZMR and the resultant
drain impedance Zd, as a function of frequency. Here, Cp includes the remainder of the
MOSFET capacitance and 40 pF of external capacitance needed to achieve the desired at-
tenuation at the third harmonic of fs. Notice that while the magnitude of the impedance
ZMR peaks at 30 MHz and 90 MHz, it has a null at 60 MHz. Because Zd, = ZMRIIZL, the
maxima of the magnitude of Zd, will not necessarily correspond to the maxima of either
ZMR or ZL, so the designer has to be aware of the impact that changes on each component
can have in the overall impedance Zds.
To better appreciate the resulting impedance looking into the drain node of the inverter
Fig. 4.6(a) shows the magnitude and phase of the impedance Zd8 of this example. It shows
that at the fundamental of the switching frequency, Zd, has a magnitude of 37.23 dBQ and
2.770 of phase. Although the phase angle is positive, 2.770 of phase is not inductive enough
to ensure ZVS. This can clearly be seen in Fig. 4.6(b) which shows a transient simulation
of a (2 inverter with the values obtained so far. Notice that the drain voltage is near 125 V
right before the MOSFET turns on.
Reducing the value of LF from the value selected initially shifts the first peak of ZMR to a
higher frequency, this makes the net Zd, looks more inductive at the fundamental. Reducing
LF in this manner is a way to achieve the ZVS operation of the 4(2 inverter. Figure 4.7
shows the impedances ZL, ZMR and the drain impedance Zd, of the inverter when the
value of LF is reduced from 625.24 nH to 270 nH. Notice that the impedance peaks of the
magnitude of ZMR are no longer at the fundamental and third harmonic of the switching
frequency, but are significantly higher in frequency.
- 90 -
4.4 Practical Design of a 30 MHz 42 inverter
Impedance Magnitude vs. Frequency

100 ............... ................
80......................... ..... ..... .... ........................... ............ ds
a 60 -
.40 . ... . . ....
-20
10 100 1000
Frequency [MHz]
Figure 4.5: Magnitude of the impedances ZMR, ZL and Zd, the Class 42 inverter (at
an intermediate point in the tuning process). Zd, is equal to ZMRIIZL. For this exam-
ple CF=20 pF, LF=625.4 nH, CMR=18. 7 5 pF, LMR=37 5 .2 6 nH. Ls=257 nH, Cs=4 nF,
Cp=75.42 pF (35.4 pF remaining from the switch plus 40 pF external capacitance).
The effects of the reduction in the value of LF can be better appreciated in Fig4.8(a), which
shows that with a smaller value of LF, the phase angle of the impedance at the fundamental
is now 40.60, with a magnitude of 34.8 dBf2. Under this conditions ZVS is achieved as can
clearly be seen in the transient simulation of Fig. 4.8(b). The models in the simulation
results include parasitic elements in most of the components, which are responsible for the
high frequency oscillations on Vd,(t) when the MOSFET is on. Furthermore, the simulation
accounts for the non-linear capacitance of the semiconductor device (ARF521 MOSFET)
chosen for the design.
- 91 -
30
Impedance
Magnitude
vs. Frequency Drainto Source Voltage(1f= MHz,VIN=160
V
i• !
i" PMagnitude
has e ..
i .I
. .
Ir
....: ...tA 3
....
....
.... !i i \
i ;
iI
"•:
iL
•'I:
i
= i,
: •
: : : '- a
"" I ' ; ; i i i ~---'----' i'·-
Frequency
[MHz] Time[ns]
(a) Impedance plot (b) Time domain
Figure 4.6: (a) Plot of the impedance Zd, vs. frequency. (b) Drain to Source voltage.
VIN=160 V, fs=30 MHz. For this example LF=625.4 nH, CMR=18.75 pF, LMR=375.26 nH.
Ls=257 nH, Cs=4 nF, Cp=40 pF
0'
'I
Frequency [MHz]
Figure 4.7: Magnitude of the impedances ZMR, ZL and Zds the Class 12 inverter. For this
example CF=20 pF, LF=270 nH, CMR=18.75 pF, LMR=375. 2 6 nH. Ls=257 nH, Cs=4 nF,
Cp=75.42 pF (35.4 pF remaining from the switch plus 40 pF external capacitance). Notice
that the peaks in ZMR are now at a higher frequency.
- 92 -
4.4 PracticalDesign of a 30 MHz 42 inverter
ImpedanceMagnitude
va Fequency (t=30 MHz,Vi=160 V)
Drainto SoumeVoltage
-- ---
3 1 db ! "---7 Phan
-.
40
348117db4SOM2
CaW
R
w .... 1
..............
............
.. . . . C
20
a
..... ...... , | ·
:. ..............•-50
:_ : 1
i !10i
10 100
Frequency
[MHz] Time[rn]
(a) Impedance plot (b) Time domain
Figure 4.8: (a) Shows the magnitude and phase of Zd, vs. frequency. (b) Shows a transient
simulation of Vd, of the 42 inverter. Here, VIN=160 V, f,=30 MHz. Components values
are: LF=270 nH, CMR=18.75 pF, LMR= 3 7 5 .2 6 nH. Ls=257 nH, Cs=4 nF, Cp= 4 0 pF.
The MOSFET capacitance is modelled as Co,, = Co/(1 + 2)m with values that change
dynamically as follows: Co = 2478 pF, 0i= 1.088 V, m-0.6946 for 0 < Vds(t) < 14.5 V and
Co = 2478 pF, 0po = 0.38 V, m-0.6285 for 14.5 < vd,(t) < 500 V. Parasitic components for
the time-domain simulation also include parasitic inductances in the MOSFET (1.5 nH at
the drain, 1 nH at the source).
- 93 -
4.4.0.4 Importance of the Relative Impedances ratio at the Fundamental and

Third Harmonic
The ratio between the magnitude at the fundamental and third harmonic Zd, has a direct
impact in the shape of the drain voltage. In particular, this ratio determines the peak
voltage across the MOSFET. For the simulation results shown in Fig. 4.8(a), this ratio is
4.75 dB.
To demonstrate the effects that the impedance ratio has on the performance of the 12
inverter, we simulated the inverter presented in the previous subsection with different values
of capacitance Cp and inductance LF. By varying Cp, we lower the impedance at the third
harmonic, while keeping the impedance at the switching frequency constant by adjusting
the value of LF. Figure 4.9 summarizes the results of this process. Figure 4.9(a) shows
the magnitude of the drain impedance when Cp is 0, 40 pF and 80 pF. LF here is 400 nH,
270 nH, and 200 nH respectively. Figure 4.9(b) shows the resulting Vd,(t). Notice how the
relative impedance magnitudes relate to the peak voltage at the drain.
•.l vs Frequency Drl o SourcVolage(f30 MHz,VeIlO0V)
--. p pF,270r InH ---Cz40pF,

270nH
xwwmCp=4OpF.L1e
nH 400
.....
.....
i.
..€ '-•?l -.-.cPso pF,L-.OnH
350
I . ..... .....
3200 .......... ····
250 ......
.. ...
.....
I-
1200
20..........
1" ........... .
..
..
......
... ...............
.... ... ........
o.. . " ..
......
.... .
.............. 00
1.
·· ··
....................
II..i...
a[..................
i..........
......
i..
.... ..................
.........
...
......
! 50
o ...
..
.....
..
....
.....
..
-10 10-oa• 0 15 2 0 2 0 4
"10 100 WOO a 5 10 15 20 25 30 35 40

Frequercy
[MHz] Tirm
niml
(a) Impedance magnitude (b) Time domain
Figure 4.9: (a) Shows the magnitude of Zd, vs. frequency for different tuning having
the same impedance magnitude at the fundamental frequency, but different impedance
magnitudes at the third harmonic. these things were achieved by selecting different values
for Cp and keeping the impedance magnitude at the fundamental constant by adjusting
LF. (b) shows how Vds(t) changes as the impedance ratio between the magnitude at the
fundamental and the third harmonic is varied. The thicker line highlights the actual design
selected for the prototype system.
- 94 -
4.4 PracticalDesign of a 30 MHz 42 inverter
4.4.0.5 Summary of the Inverter Design
Table 4.1 shows a summary of the designed of the 30 MHz, 160 V to 200 V #2 inverter.
Table 4.1: List of components for the 30 MHz, '2 inverter. The model of the MOSFET
capacitance changes dynamically. depending on voltage according to the relations shown
below.
Component Value
LF 270 nH
CF 20 pF (assumed)
MOSFET ARF521
C08 8 =
Co = 2478 pF, 0o = 1.088 V, m=0.6946, for 0 < vd,(t) < 14.5 V

Co = 2478 pF, 1o = 0.38 V, m=0.6285, for 14.5 V < vd,(t) • 500 V
LMR 375.26 nH
CMR 18.75 pF
Cp 40 pF
Cs 4 nF
Ls 257 nH
- 95 -
4.5 (2 Inverter Implementation
Section 4.2 introduced a new circuit topology -the "(2" resonant inverter - which pro-
vides low device stresses, eliminates the need for a bulk input inductor, and provides a
greater degree of design flexibility than conventional designs such as the Class E resonant
inverter. This section describes the implementation of the inverter designed in section 4.4
and briefly describes the method used to drive the gate. Furthermore, it evaluates the in-
verter performance and highlights the potential of the (2 inverter in practical applications.
4.5.1 Inverter Implementation
Section 4.3 sketched a method of obtaining component values for the passive elements of
the class t2 inverter (shown again in Fig. 4.10). The design procedure focuses on shaping
the impedance seen by the semiconductor switch, such that the network is able to support
voltages across the switch with fundamental and third harmonic components, and suppress
any component at the second harmonic of the switching frequency (via a zero near the
second harmonic).
VIN VLOAD
Figure 4.10: Schematic of the 42 Inverter.
The prototype inverter was constructed on a printed circuit board (PCB) (2-layer, 1 oz.
copper, FR4 material) while a 33.3 D RF RLOAD capable of dissipating 450 W (using the
appropriate heatsink) was constructed on a second circuit board. The masks of both PCB's
can be found in Appendix E.
Of particular importance during the fabrication of the prototype is the accurate determina-
tion of the drain impedance Zd,. This measurement is done using an impedance analyzer
connected to the drain node (through an SMA connector) and in series with a DC blocking
capacitor CBIAS (such that the drain node can be biased to an appropriate voltage). The
impedance analyzer is calibrated to compensate for the introduction of a 6 in., 50 Q coaxial
- 96 -
4.5 42 Inverter Implementation
cable between the instrument head and the PCB under study. The calibration offers an
accurate measure of the impedance up to a frequency of about 400 MHz.
The nonlinear dependance of the MOSFET's drain to source capacitance with voltage re-
quires a way of biasing the drain node to the nominal input voltage when measuring the
impedance. The input voltage of the inverter (160 V• VIN _ 200 V) exceeds the bi-
asing limits of the impedance analyzer available (Agilent 4395A, with ±40 V dc range.).
Therefore, to allow for dc bias and protection of the analyzer, it is necessary to add a ca-
pacitor CBIAS between the analyzer and the drain node. The role played by this capacitor
is twofold: it prevents the dc voltage from reaching the measuring test point of the analyzer
and holds the voltage across CBIAS constant though out the measurement. It is essential
the impedance of CBIAS be negligible when compared to the impedance of the drain node
at a biased point. The length of the frequency sweep interval of the impedance analyzer is
selected to be short enough so that no significant drop in bias voltage is observed.
The impedance Zd, of the 42 inverter design developed in Section 4.4 has the frequency
dependance shown in Fig. 4.8(a). In the light of the above considerations, the impedance
of CBIAS is chosen to be 10 times smaller that the #2 design at 30 MHz and 90 MHz. The
impedance magnitude at these frequencies is 34.81 dBQ and 30.06 dB92 respectively. A
250 V, 1pF ceramic capacitor (CKG57NX7R2E105M) meets these requirements as shown
in the impedance plot of Fig. 4.11. Although the impedance of the capacitor looks inductive
for frequencies higher than 3 MHz, is low enough to be used for CBIAS. Furthermore, this
type of capacitor also proves to be an excellent choice for the input capacitance CIN.
Impedance vs. Frequency

20 ,__. 100
- Magnitude
. - Phase
•:tA-
I 00
m
o.
0
0 Ca
0
o 0 C
V
-C
cc
0 -20 --to100o
E
E
E
004% i~! • i iii i~ii
T1.i 1 10 100
Frequency [MHz]
Figure 4.11: Magnitude and phase impedance of a 250 V 1pF ceramic capacitor Cbias. This
capacitor is used as CBIAS and as part of CIN in Fig 4.10.
- 97 -
The values of resonant inductor LF, LMR, and Ls (shown in Table 4.1) are small and
can be implemented with few turns of magnet wire. The air-core inductors built for this
inverter have quality factors QL larger that those assumed in the design of section 4.2.1.
To ensure mechanical stability and repeatability, the inductors were wound on threaded
Teflon® cylinders.
4.5.1.1 Placement of resonant elements
The first step in the construction of the prototype was the placement of the second harmonic
resonator (formed by CMR and LMR). These components were tuned to resonate at the
second harmonic of the switching frequency. Inductor LMR was fabricated with 9 turns of
AWG16 magnet wire on a 3/8 in. diameter Teflon @ rod with 14 turns/in threads. Then,
we added a CMR= 1 6 . 3 pF capacitor in series with the inductor. The series network formed
by LMR and CMR was found resonant at a frequency of 61.3 MHz. Hence, the effective
value of LMR is 414 nH. An important consideration in the layout of the PCB is the peak
voltage across capacitor CMR, which can reach 1.25 KV at VIN=200 V. Therefore, CMR
was implemented by connecting three 500 V porcelain capacitors in series. To avoid adding
parasitic capacitance here, no ground plane was placed (on the other side of the board)
below the midpoint connection of the CMR- LMR tank.
Once the second harmonic leg was in place, the MOSFET and the rest of of the passive
components were placed on the PCB. Throughout the placement of the resonant components
of the inverter, the ARF521 gate and source were shorted using a low inductance connection.
Hence, measurement of the drain-source impedance Zd, included switch capacitance Co,,.
Table 4.2 shows the measured values of all passive components of the inverter.
Figure 4.12 shows a photograph of the prototype with all the inverter components in place.
In order to keep the loop area of the input to a minimum, the inductor LF was placed across
the top of the ARF521.
A close up view of the drain node is shown in Fig. 4.13. The photograph shows the SMA
connector for the impedance analyzer, and capacitor CBIAS. Both components were located
right on top of the drain node to minimize parasitic inductance. Kapton @ tape was used
to insulate the high voltage connections.
The (2 inverter delivers power to a resistor implemented by paralleling three 100 Q RF

power resistors, each rated to 150 W. Figure 4.14 shows the PCB of the load network with
the resistors placed symmetrically. The connection between the inverter stage and the RF
- 98 -
4.5 (2 Inverter Implementation
Table 4.2: List of components for the 30 MHz, 160 V to 200 V I2 Prototype inverter.
Part Measured Value Q Part number
LF 306 nH 194 8 turns of AWG 16 wire
on a 3/8 in. diam. Teflon® rod
with 14 turns/in, threads
CF Device capacitance ARF521
LMR 414 nH 280 9 turns AWG 16 wire
with 14 turns/in. threads
CMR 16.29 pF (porcelain) 10 K 2x56 pF ATC100B560JW
10 K 1x39 pF ATC100B390JW
Cp 28.065 pF Parasitic drain
capacitance
Cs 2 nF 3K 2x1 nF MC22FD102J-F
Ls 193 nH 190 4 turns AWG 16 wire
on a 5/8 in. diam. Teflon @ rod
with 12 turns/in. threads
RLOAD ; 33.3 Q 3 parallel 100 2
RA1000-150-4X
Cbias 1 pF CKG57NX7R2E105M
CIN 4 pF (250 V Ceramic) 4x CKG57NX7R2E105M
Load was made using two 75 2 coaxial cables in parallel. A subsequent section shows a
detailed characterization of the load across frequency, and at the operating temperature.
4.5.1.2 Verification of the impedance Zd,
With the voltage of capacitor CBIAS held to VIN, we proceed to compare the measured
impedance Zd, to the one obtained by simulation using PSPICE with the values obtained
in Table. 4.2. Figure 4.15 shows the magnitude of Zd, when VIN is 160 V. The difference
between measurement and simulation in the frequency range between 70 MHz and 80 MHz
is due to the gate to drain capacitance Cgd and the gate-to-source inductance. Cgd is not
included separately in the PSPICE model of the MOSFET but is rather treated as part of
the device output capacitance Coss.
- 99 -
Figure 4.12: Experimental Class '12 inverter.
4.5.1.3 Implementation of the Gate Drive
The inverter operates with a constant duty cycle of approximately 0.3. The gate of the
ARF521 MOSFET used here is driven sinusoidally by an RF power amplifier having 50 Q
output impedance (Amplifier Research 150A100B) with a dc offset on the gate voltage.
Figure 4.16 shows a schematic of the gate drive circuit where VG,DC is a dc voltage that
controls the duty cycle. Capacitor CG,RF=5 nF presents a low impedance to the RF signal
coming from the power amplifier. The inductor LG,DC= 56 8 nH and RG,DC=10 kQ prevent
the RF signal from reaching the auxiliary supply VG,DC.
The impedance between gate and source of the ARF521 is modelled as a series resonant
circuit, with RG=0.116 Q, Ci,,=920 pF, and LG=2.6 nH. The measurement accounts for
the gate and source lead inductances.
When a sine wave is used to drive the gate of the MOSFET, the power lost in the gate is
(ideally) PGATE = 27r 2 . f 2 . V2 ac C2ss RG. For Vg,ac=1 2 V, the power lost at the gate is
just PGATE= 2 5 1 mW, which is negligible compared to the output power of the inverter.
- 100 -
4.5 4)2 Inverter Implementation
Figure 4.13: Experimental Class I)2 inverter. The capacitor CBIAS provides dc isolation and
allows biasing of the ARF521 MOSFET to obtain the impedance plots necessary for tuning
4.5.2 Experimental Performance of the inverter
The inverter and load were each mounted to appropriate heat sinks. In particular, the RF
load was mounted on an aluminum heat-sink with two fan-cooled copper heat-sinks (type
Zalman F CNPS7700-Cu) also mounted to it to improve heat transfer. In thermal steady
state, the net thermal impedance seen by the resistive load was found to be 0.2 oC/W.
The inverter MOSFET was mounted on a fan-cooled aluminum heat-sink with a thermal
resistance of 0.5 OC/W (Cooler-Master® HAC-L82). This heat-sink was deliberately heavily
over-sized to ensure acceptable temperature rise on the inverter board even if the inverter
did not operate as desired. The prototype inverter and load are shown in Fig. 4.17.
Figure 4.18 shows the inverter test setup with connections to the measurement equipment.
The figure shows the main power supply as well the auxiliary power supply powering the
heat-sinks' fans. A second output of this supply controls the DC offset on the gate drive to
adjust the duty cycle of the inverter.
The measured drain to source voltage Vds(t) of the 4P2 inverter is shown in Fig. 4.19 as well as
the voltage at the MOSFET's gate (with VIN=160 V). The figure clearly shows ZVS condition
and the expected waveshaping outlined in section 4.2.1. Figure 4.20 shows experimental
measurements of Vds(t) as the input voltage is varied over the 160 V<VIN : 200 V range
The peak voltage across the switch is significantly smaller than the voltage obtained by
- 101 -
Figure 4.14: RF Load.
conventional circuits (Class E, second harmonic Class E). The peak Vds(t) to VIN ratio
measured is approximately 2.4 over the entire input range.
Figure 4.21 illustrates the excellent agreement that exists between measurement and PSPICE
simulation for the case when VIN=160 V. Vd,(t) is shown on the left of the figure, while the
load voltage Vload(t) is shown on the right.
- 102 -
4.5 k2 Inverter Implementation
Drain to Source Impedance (Magnitude) at VIN=1 6 0V
10 100
Frequency [MHz]
Figure 4.15: Drain to Source Impedance vs. Frequency when VIN=160 V.
Figure 4.16: Gate drive circuit schematic. In this prototype, RG,DC=10 kQ LG,DC=568 nH
and CG,RF=5 nF. The RF source is a 50 P-output power amplifier.
- 103 -
Figure 4.17: Experimental Class 42 inverter connected to the RF Load.
Figure 4.18: Bench setup of the Class 'D2 inverter connected to the RF Load. The signal
generator output is amplified by the RF Power Amplifier which drives the gate of the RF
MOSFET in the b2 Inverter.
- 104 -
4.5 (D2 Inverter Implementation
gatee (VI=160
ds Vgat
Vds and IN V, f=30
S MHz)
12
Time [ns]
Figure 4.19: Drain to source and gate voltage with VIN=160 V.
Measured Drain Voltage

- @V IN=160V
-...- - @V IN=170V
....... @V IN=180V
N=190V
V I.@V
@V N=2 00V
)0
Time [ns]
Figure 4.20: Drain to source voltage for 160 V< VIN •200 V. The peak drain voltage to
input voltage ratio is -2.4
- 105 -
30
VdwMeasuredand Simulated(VIN=160 V, fL=30MHz) VloadMeasuredand Simulated
(VIN=160V, f= MHz)
Time[ns] Time[ns]
(a) Vd, (b) Vload
Figure 4.21: Comparison between experimental measurements and simulation: (left) Drain
to source voltage ,(Right) Load voltage. Both plots at VIN=160 V.
- 106 -
4.5 P2 Inverter Implementation
4.5.3 Output Power Measurements and Performance
Measuring ac power at 30 MHz is difficult in RF systems, especially at impedance levels

different from 50 Q. To accurately measure the power delivered to the load, we obtained the
frequency components of the voltage across the RF load and computed the power delivered
at each harmonic frequency. To do this this, we measured the impedance of the RF load
across frequency and temperature. A plot of the load impedance in the frequency range
between 1MHz and 400 MHz ( at 250C) is shown in Fig. 4.22. The measured value of the
static thermal coefficient of the load was 4.2306 m2/oC. We scaled the real part of the
load impedance to account for the temperature increase of the load during operation of the
inverter. We made the simplifying assumption that the effect of the thermal coefficient was
constant with frequency.
A•
"^
#]m ~ ' ""' 1ýffI
Magnitude
u4 - - - Phase
S
..... : : . I
32 . .........
: : : : ! [ ! ! ! ,=
<n
co
a,,
'
...
'i i~i"i... . ...
. ? I !'" 'I,
0 rrrrrr-r~s .·riC* i it i i: i '

C 0)
.
0 -
a,-30
0Z
0a C
Co
E
(D
-0
0o
-1
cl.2
0) E
E 28t -10-
Frequency [MHz]
Figure 4.22: Magnitude and phase vs. frequency of the impedance of the RF load connected
to two parallel 75 Q coaxial cables of the same length.
Figure 4.23 shows the voltage across the RF resistive load, and the magnitude and phase of
the first 9 harmonic components. With the harmonic content, the impedance of the load,
and the load temperature, the output power can be estimated with reasonable accuracy.
The output power and drain efficiency of the converter over the input voltage range are
shown in Fig. 4.24. All the voltage measurements were made when the temperature of the
- 107 -
MeasuredVd (Vfei180V)
Harmonic Amplitude [V] Phase

00 s
190.7836 1
9.3254 216.19370 2nd
3 rd 9.6288 -76.41640
4t h 3.5710 113.87630
5 0.9197 205.34070
6 0.8111 -9.24730
7h 0.4374 114.40410
.............
...............
............
S............. ............
............. 8h 0.0157
........................... 146.08460
h
-U 0 10 20 30 40 0 60 70 80 9 t 0.2094 96.50120
Time[n]j
Figure 4.23: Load voltage when VIN=180 V. The table shows the harmonic content of the
waveform.
load resistor reached 100 0C. The drain efficiency is over 92 % over the operating range2 .
The performance of the prototype (D2 inverter demonstrates experimentally many of the
advantages that the topology has over conventional designs. In particular, it demonstrates
the significant reduction in the voltage stress achieved by this topology.
,,,'
Inverter Performance vs. Input Voltage
500 . . . . .
480 94
4%
460
440 93 Lo
L 420
OUT 92 =
0
o
91
- EiEfficiency
141" I -U I
160 165 170 175 180 185 190 195 20"

Input Voltage [V]
Figure 4.24: Output power and drain efficiency vs. input voltage for the class (2*
2
Subsequent measurements on this converter made by colleagues at the University of Colorado at Boulder
yielded efficiencies improvements of several percent with an improved gate drive.
- 108 -
Chapter 5
A tP
2 Dc-Dc Converter
T HE I2 inverter introduced in chapter 4 operates efficiently at frequencies in the VHF

range when driven with a constant frequency and duty ratio. Moreover, all the el-
ements of the 12 inverter are resonant and of small value, which is beneficial in modern
applications requiring rapid transient responses. By replacing the resistive load by a res-
onant rectifier, a dc-dc converter is formed with characteristics that are compatible with
the architectures introduced in Chapter 2. This chapter describes the design of a ' 2-based
dc-dc converter and presents experimental results demonstrating its operation.
5.1 Background
The RF dc-dc converters described in Chapters 2 and 3 use a conventional class E inverter
to obtain a high frequency ac waveform (Fig. 5.1 (a)). A resonant rectifier connected to
the inverter via a matching network forms a dc-dc converter that delivers power efficiently
when operating at a constant switching frequency and duty ratio. It is customary, in
designing a class E inverter, to have a large inductor at the input port to reduce the
input current ripple. When a class-E-based dc-dc converter is operating under the cell-
modulation regulated architecture (Section 2.4), the large choke inductor of the inverter
limits the maximum modulating frequency. The rate at which the dc-dc cell is turned on
and off (to keep the output voltage constant) determines the value and size of the energy
storage elements needed to keep the output voltage steady during the time period in which
the dc-dc cell is off. The benefits of increasing the modulating frequency are twofold: it
allows a reduction in the overall size of the converter (by reducing input and output bulk
capacitance requirements), and improves the control bandwidth, which is very promising in
applications requiring fast transient response.
In the I2 inverter introduced in Chapter 4 (shown again in Fig. 5.1 (b)) all the passive
elements are resonant and hence possess small energy storage requirements. Furthermore,
this topology reduces the voltage stress on the semiconductor, and reduces the ties between
frequency, capacitance and output power of the Class E inverter. These features make the
- 109 -
A 42 Dc-Dc Converter
(2 an attractive candidate in the development of high performance, high frequency dc-dc

power converters.
VLOAD
(a) Class E (b) 12 Inverter
Figure 5.1: (a) Shows the Class E inverter. (b) shows the D2 resonant inverter, in which
the passive elements are all resonant.
5.2 A New (2 dc-dc Converter
The advantages offered by the the 42 inverter can be utilized in the design of advance reso-
nant dc-dc power converters. This can be done by simply replacing RLOAD (in Fig. 5.1(b))
with a tuned resonant rectifier having the same equivalent resistance RLOAD at the fun-
damental frequency. Figure 5.2 shows the schematic dc-dc converter incorporating these
ideas.
Figure 5.2: High-frequency resonant dc-dc converter.
Note that while this circuit has some topological elements in common with the conventional
SEPIC converter [28, Chapter 6] and its resonant variants [20,91], the design, component
values, stresses, and operational characteristics are quite different.
As with the inverter, the proposed converter operates with a fixed frequency and duty cycle.
Hence, control of the average converter output (voltage, current, or power) can be obtained
by on/off control of the converter cell, which makes it suitable for systems architectures like
the ones described in section 2 and in [39,50,70,77].
- 110 -
5.3 Alternative Implementations of I2-Based de-dc Converters
The first step in the design of the converter is to realize a rectifier with the desired be-
havior at the fundamental frequency (e.g., see [77], and Section 3.3). Once the equivalent
impedance of the resonant rectifier (at a given output power and voltage) is known, it can
be used in the design of the 42 inverter.
The next step is to design the '2 inverter (e.g. following the tuning process in Section. 4.3)
using the equivalent resistance of the rectifier as the nominal load. However, due to the
nonlinear behavior of the rectifier and its interaction with the inverter, additional tuning of
the design may be required to achieve maximum efficiency and/or ZVS and/or zero dv/dt
switching characteristics.
The rectifier topology used in the dc-dc converter of Fig. 5.2 comprises a single diode feeding
a constant (capacitively filtered) output voltage, a resonant inductor LR that provides a dc
path to ground, and a resonant capacitor CEXT in parallel with the resonant inductor. This
capacitor may equivalently be placed in parallel with the diode and effectively absorbs the
diode capacitance CD to form a total capacitance CR. In some implementations CR may
comprise only diode capacitance.
This topology offers significant advantages over previous designs. It provides efficient dc-
dc conversion at very high frequencies, with few small-valued passive components and low
device stresses. Due to the small values and energy storage of the passive components,
the transient response can be very fast compared to conventional designs. Moreover, in
many implementations the dependance of operating power on input voltage is reduced as
compared to conventional resonant converter designs.
5.3 Alternative Implementations of # 2-Based dc-dc Convert-

ers
It will be appreciated that there are a range of possible variants to the design of Fig. 5.2. For
example, different reactive connection networks can be used to provide more sophisticated
adjustment of the equivalent rectifier loading. Likewise, different configurations of the
rectifier may be useful in certain applications.
Of special interest for further discussion in subsequent sections is a slight variation of the
topology shown in Fig. 5.3. This variant achieves higher efficiency by taking advantage
of the impedance transformation provided by an autotransformer. Subsequent sections of
this chapter will present detailed design considerations and experimental validation of this
topology. Notice that the autotransformer forms part of both the resonant rectifier and the
- 111 -
reactive interconnect of the inverter. CSdamp and RSdamp in Fig. 5.3 are components used to
damp transient oscillations occurring during the start-up of the converter but do not have
a significant impact during steady-state operation of the circuit.
Figure 5.3: Dc-dc converter implementing using an autotransformer.
Figure 5.4 shows an implementation in which electrical isolation is achieved by using a

transformer to couple the rectifier to the high frequency inverter. This strategy can result
in higher efficiency and design flexibility by virtue of the impedance transformation provided
by the transformer. Furthermore, the magnetizing inductance of the transformer can be
used as the resonant inductor for the rectifier, while the leakage inductance forms part of
the reactive interconnection network thus reducing the number of components.
Fig. 5.5 shows another possible implementation in which the rectifier diode has its anode
terminal connected to ground. In this configuration, the capacitance CR comprises the
device capacitance CD and any external capacitance CEXT required to tune the rectifier.
The implementation shown in Fig. 5.5 facilitates the implementation of "synchronous rec-
tification", in which an active switch may also carry the rectifier current, thus reducing the
Figure 5.4: Dc-dc converter providing electrical isolation. The magnetizing inductance of
the transformer provides the needed dc current path and is utilized to tune the rectifier.
The leakage inductance of the transformer forms part of the reactive network that controls
the amount of power delivered to the rectifier
- 112 -
5.4 Example design of a Class 1 dc-dc converter
Figure 5.5: Dc-dc converter with an alternative rectifier.
conduction losses. A dc-dc converter implementing "synchronous rectification" is shown in

Fig. 5.6.
Figure 5.6: Dc-dc converter implementing synchronous rectification.
5.4 Example design of a Class (Ddc-dc converter
To demonstrate the performance of the new l 2-based dc-dc topology, we present the design
of a dc-dc converter using the topology variant of Fig. 5.3 and operating at a switching
frequency of 30 MHz. The input voltage range is from 160 V to 200 V and the output
voltage is held constant at VOUT = 33 V. The designed output power when VIN=160 V is
200 W. The required inductor values are small enough to be implemented in air-core.
As was the case with the inverter design implemented in Chapter 4, the semiconductor
switch is a vertical RF MOSFET ARF521 (Advanced Power Technologies) with a 500 V
drain to source breakdown limit. Note that the breakdown limit of the selected device rules
out the use of class E derived topologies for this design. The diode for this design is realized
as a paralleled pair of 300 V silicon carbide Schottky diodes (Cree CSD10030).
- 113 -
A (D2 Dc-Dc Converter
The parameters that describe the nonlinear diode capacitance were obtained by measuring
the diode capacitance (CKA =548 pF, 163 pF, and 119 pF , at f,=1 MHz) at three different
bias voltages (VKA=O, 11 V, and 23 V respectively) and solving for Vj and m in the
equation: CKA = Cjo/(1 + VA_)m. For the CSD10030 diode: Cjo = 548.3 pF, Vj = 0.78 V,
and m=0.45 for 0 _< vKA < 100 V. The CSD10030 datasheet indicates that for VKA > 100 V
the diode capacitance is constant (CKA = 62.6 pF). Figure. 5.7 compares measured values
of the capacitance to values obtained with model used for the design. In addition to the
capacitance, the SPICE model of the diode incorporates 6 nH of lead inductance (between
lead and the back of the TO-220 package), and 0.15 f of equivalent series resistance. The
forward characteristic of diode are modelled as a constant forward drop (Vd,ON=50 7 mV)
in series with a resistor (Rs=89.7 mR).
Capacitance vs. bias voltage at fs =1 MHZ

bb(l
* Measurement
- Model
C.....................
=548.3115 pF
• 350
V=0.78062 V,m=0.44631
VAK =11 V, C1=163 pF
g 300 ............
.......... =119 pF
ESR=0.14625 9
E 250 .....
..............
............
............
ESL=6.006 1nH
200
150 . . . . . . . .
..
...................................
100
rn -
0 5 10 15 20 25 30 35
VA [V]
Figure 5.7: CSD10030 diode capacitance vs. bias voltage. The figure compares measured
values to the model used for the design.
5.4.1 Resonant Rectifier Design
As described above, the rectifier is designed to appear resistive and fundamental frequency
at the desired output power'. For design purposes the rectifier can be modelled as illustrated
1Alternatively, if the rectifier is tuned to appear appropriately reactive at the switching frequency, reso-
nance between the interconnect network and the rectifier network can be used to provide voltage gain from
the input to the output.
- 114 -
5.4 Example design of a Class D de-de converter
in Fig. 5.8. Figure 5.8 shows the schematic of the resonant rectifier loaded with a constant
voltage at the output. The rectifier is modelled as being driven by a sinusoidal current
source of magnitude IIN. A resonant capacitance CR represents the sum of an external
capacitance CEXT and an equivalent diode capacitance CD. The resonant inductor LR
provides a path for the DC current and resonates with the capacitance CR. This resonance
can be selected such that the input looks nearly resistive at the fundamental frequency
(That is, the fundamental of the voltage v, is in phase with the drive current irec.). The
input current amplitude is selected to provide the desired output power. The output voltage
is assumed to be constant for the description that follows.
r-- ------
VOUT
Figure 5.8: Resonant rectifier.
The amplitude and conduction angle of the diode current depend on the component values.
By adjusting the net capacitance CR in parallel with the resonant inductor, it is possible to
trade off the length of the conduction interval and the peak reverse voltage across the diode.
In some implementations it is convenient to have a conduction angle close to 50 percent,
as this provides a good tradeoff between peak diode forward current and reverse voltage.
This additional capacitance can either be added externally or can be solely provided by
additional diode area, which can have the added benefit of reducing the overall conduction
loss in the rectifier.
Appropriate tuning can also be accomplished by adjusting the inductance LR and the the
magnitude of the sinusoidal current source IIN of Fig. 5.8. For the proposed design, two
silicon carbide diodes (CSD10030) were connected in parallel and the corresponding capac-
itance Cr is solely composed of the non-linear capacitance of the devices (An approximate
model of the capacitance for a single diode is shown in Fig. 5.7). In silicon carbide Schottky
diodes, the forward conduction thermal coefficient is positive, which allows the paralleling
of multiple devices. It is often desirable that all of the capacitance needed by the rectifier
be provided by device capacitance, since this results in lower forward conduction drop when
the diode is conducting and avoids resonances between the capacitors and device package
inductance.
- 115 -
Figure 5.9 (a) shows a PSPICE simulation of the rectifier shown in Fig. 5.8 when it is tuned
to appear resistive at the fundamental frequency. For the conditions shown in the figure,
La=75 nH, f, = 30 MHz and IIINJ= 7.15 A. The output power POUT delivered to the
33 V load is 200 W. Figure 5.9 (b) shows the sinusoidal input current, and the fundamental
component of the input voltage, from which the an equivalent resistance of approximately
8.4 Df can be extracted.
Rectifier voltageand fundamental
vs. time (PouT=200W, VoUT=33V) Rectifier
Voltage(fundamental)
and Rectifier
current
100
Rectifier voltage
-- - Fundamental
.....
... 20
50 40 ........
.. 60 80 100
5.
0···
0 20 40 60 80 100
Time[ns] Time [ns]
(a) a (b) b
Figure 5.9: (a)Rectifier voltage and its fundamental component. (b) Fundamental compo-
nent of the input voltage and input current. POUT = 200 W. f, = 30 MHz, LR=75 nH,
QL=160. The equivalent resistance of the rectifier under this condition is 8.4 Q.
Figure 5.10 shows how the magnitude of and the phase of the equivalent impedance of
the rectifier changes as the output power is varied over a a wide range (by varying IIIN).
The figure shows that the phase angle between the fundamental component of the voltage
and the rectifier current remains small across the whole operating range. The simulated
efficiency of the resonant rectifier remains high as the output power changes between 200 W
and 350 W as shown in Fig. 5.11.
Due to the transforming action of the 1:1 autotransformer (Fig. 5.3), the equivalent impedance
of the rectifier at the input of the autotransformer will be 4 - Req= 3 3.6 Q.
5.4.2 42 Inverter Design
To select the values of (2 inverter of Fig. 5.1 (b), we follow the same tuning procedure
outlined in Section. 4.3. For designing the inverter, RLOAD= 3 3 ~2 which is the equivalent
impedance of the rectifier (4 x 8.2 Q) as seen at the input of the autotransformer. The
impedance transformation due to the autotransformer is advantageous in this case because
- 116 -
Impedance Magnitudevs. Output Power(LR=75 V)

nH, VOUT=33 ImpedancePhasevs. Output Power(LR=75nH,VOT.=33 V)
Rn
U 7.5
7S
... ........ .. ..................
.................
2 6.5
. ...
.....
..
..
...... .................................
6
E5.5 ............................ .......................
5
I
250 300 250 300
Output Power[W] Output Power[W]
(a) Magnitude (b) Phase
Figure 5.10: Rectifier impedance magnitude and phase (at the fundamental) as a function of
the output power. For this implementation fs=30 MHz, LR=75 nH, QL=160. Cr is entirely
provided by the device capacitance of two paralleled CSD10030 SiC Diodes. Over a wide
output power range, the equivalent impedance of the resonant rectifier can be considered
as being purely resistive.
it reduces the loading effect that impedance ZL (on Fig. 4.3) has on ZMR. For the 200 W
design example considered here, and using 20 pF as the starting value of CF, we obtain the
following component values for the inverter: CL=385 nH, CMR=18.7 5 pF, LMR= 3 7 5 nH,
Ls=175 nH, Cs=4 nF, and Cp=30 pF.
- 117 -
A #2 Dc-Dc Converter
Efficiency vs. Output Power (LR=75 nH, VOUT= 33 V)

952
95 . ........................... ........................... · · · · · ·.........

· ..
· · ·... .. .. . .. .
94.8
94.6 ....
............ ...................
....... .........
.. . . . . . .. . . . . . .
94.4
SD 94.2
...
....... ·-.......
.... · ·.. .......
.. .···-·. ..........
··...........
........
...... ....
94 -...................... ... *...
93.8
.·..
93.6 .................................................................................·
250 300
Output Power [W]
Figure 5.11: Simulated efficiency vs. output power of the resonant rectifier. For this
implementation fs=30 MHz, LR=75 nH, QL= 16 0.
- 118 -
5.4.3 Summary of the design and expected performance
Table 5.1 shows the components values of the 30 MHz, 160 V to 200 V %2dc-dc con-
verter. This converter uses an inverter design similar to the one presented in Section 4.2.1,
but tuned to deliver approximately 200 W to the equivalent resistance of the rectifier at
VIN=160 V (design presented in Section 5.4.1) replacing RLOAD. For this design, we se-
4
lected CSdamp= nF and RSdamp=1 0 . Section. 5.4.4 will elucidate the functions of these
components and how these elements improve the transient response of the converter when
modulating it on and off.
Table 5.1: List of components for the 30 MHz, 42 dc-dc converter.

Component Value
LF 345 nH
LMR 375nH
CMR 18.75 pF
Cp 30 pF
Cs 4 nF
Ls 215 nH
CSdamp 15 nF
RSdamp 10 IQ
LR 75 nH
N (autotransformer) 1
MOSFET ARF 521
Diodes 2x CSD10030
CD Device capacitance
Figure 5.13 (a) displays the simulated drain to source voltage of the dc-dc converter as
the input voltage changes over the 160 V < VIN < 200 V range. The simulation result
clearly indicates the drain to source voltage remains within the semiconductor operational
limits. Moreover, the peak drain voltage to input voltage ratio is 2.04< Vda < 2.34. This
represents a significant reduction in voltage stress as compared to some other conventional
topologies (Class E, 2 nd harmonic Class E) in which Vd,,•a --4. The performance predicted
by the simulation is shown in Fig. 5.13 (b), which shows that the dc-dc converter efficiency
remains high and (between 83% and 88%) over the entire operating range. Another char-
acteristic worth noticing is the sub-linear dependance of the output power versus the input
voltage, which is in contrast with the quadratic dependence in power in many conventional
converters (e.g., [1]).
- 119 -
A O2 De-Dc Converter
Drain to Source Voltage, VouT=33

V, f=30 MHz Output Power and Efficiency, vs. Input Voltage
500 ..... ... ........
. .......... ....• =160 V
iP
- - V =VINf180
V
SVIN=190 V
2
- VIN=00 V 300
84
'S
%..........
..........
...........
........... .. .. .
. . . .. .. . .. .. .. .
,oo
18 1 1757 17 15 190 196 20

Time [ns] VINMLJ
(a) Vds VS. VIN (b) Performance
Figure 5.12: Simulated drain to Source voltage and Converter performance over the oper-
ating input range 160 V < VIN • 200 V
The expected loses can also be extracted from the simulation and are shown in Fig. 5.13(a).
The semiconductors models used in the simulation account for their main loss mecha-
nisms and also include reasonable parasitic elements. In particular, the SPICE model of
the ARF521 MOSFET models includes 1.5 nH of parasitic inductance at the drain, and
1 nH at the source terminal. The model of the SiC diode incorporates 6 nH of lead induc-
tance. Moreover, the assumed value for the MOSFET RDSON was estimated by measurement
and assuming high temperature operation of the device (125 0 C). Also modelled in the simu-
lation is the series resistance of the output capacitance Co
0 s which was found to significantly
contribute to the conduction losses. Figure. 5.13(b) shows the losses within the magnetic el-
ements of the converter. Here all the inductor are assumed to have a quality factor QL=160
at f,=30 MHz, and a dc resistance RL,dc=5 mQ.
Previous sections described how the resonant rectifier was designed to appear resistive at
the fundamental frequency, and showed how the resistive behavior was maintained over a
wide operating range when the rectifier was being driven by a sinusoidal current source.
Figure 5.14 shows that in the dc-dc converter simulation, the fundamental components of
both the rectifier voltage and current remain almost in phase over the whole operating
range, validating the assumption used in the design.
- 120 -
5.4 Example design of a Class o dc-dc converter
3
Semiconductor
Powerlossvs VIN,f= 0 MHz Inductorlossvs VIN,f-30 MHz
40
Switch
*-Diodes ....... 4.5
-LF
- -LMR
...!........i.. ....
,.......... '.......... .......... ...
0
,..
35
-- LS
4
30
3.5 .
........ .. . .. .
25 .. ... * . Ne .... : Nd
.......... .......... !.• = . ... .......... ... . • ........... ! ............
20
5 2.5
..... ...
i~~~ .. . . . .. .. .. . .. : .. .
C. 2 ..
.....
.. ..
.....
......
......
. ....
..
. .. .....,....
..
i ......i ........ ...... ......
... .. ........ ..... ... ...
15
1.5
........
.......
...........
...
10 ...
..
...
.....
..
. ..
...
.
,I
.. .........
........
...
...
..
...........
..
..
...
...
.......
........ ....
.. ...
...
...
.....
...
...
................
..
...... ...
... ...
...
... .. ..
.
...
..
5
0.5
Y 15 170 175 180 185 190 195 200 Y60 165 170 175 180 185 190 195 200
VIN[V VINM
(a) Semiconductor Loss (b) Loss in magnetic components
Figure 5.13: Simulated semiconductor and magnetic losses of the dc-dc converter over the
operating input range 160 V < VIN < 200 V.
5.4.4 On the Expected Transient Performance of the D2-Based dc-dc con-

verter
The small energy storage requirements of the passive elements of the D2 converter allows for
a rapid transient response. Figure 5.15 shows the simulated voltage Vd,(t) of the converter
described in Section 5.4.3 when the gate signal is applied to the power MOSFET. Once the
converter is activated, steady state operation is reached within 10 switching cycles. The
simulation shows the drain voltage exceeding the rating of the MOSFET (500 V) during
the first switching period of the transient response. This situation is not expected to be a
problem in practical applications because of the low energy associated with the single peak.
Alternatively, a clamping device can be used to limit the voltage across the device.
The schematic circuit of the 42 dc-dc converter shown in Fig. 5.3 shows CSdamp and RSdamp
connected parallel to Cs. These components form a damping leg to damp the low fre-
quency oscillations resulting from the series resonant looped formed by Cs and the series
combination of inductors LF, Ls, L1ea and (1 + N 2) x LR (which accounts for the effective
transformation action of the autotransformer) [92]. Figure 5.16(a) shows the voltage vd (t)
under transient conditions when CSdamp and RSdamp are not connected. Figure 5.16(b)
shows the same voltage but now with CSdamp=1 2 pF and RSdamp= 10 1.
The proposed 42 dc-dc converter, like the other converters introduced in this thesis, is
designed to operate at a fixed frequency and duty ratio, and as part of a system imple-
menting on-off control of the converter. If the 42 dc-dc converter presented here is used
in cell-modulated architecture system using a single cell (see Chapter 2), it is important to
- 121 -
A O2 Dc-Dc Converter
Rectifier Voltageandcurrent(fund)at PoUT=201.1501

W Rectifier Voltageandcurrent(fund)at POUT=370.1821
W
9nn
SVoltage
- - -Current
100Fi 5 -
E 5
C
> -100
0 2 40 60 80
-2(w 10
0 20 40 60 80 100
Time [na] Time[ns]
(a) Rectifier at VIN = 160 V (b) Rectifier at VIN = 200 V
Figure 5.14: Fundamental component of the voltage and the current at the input of the
resonant rectifier of the dc-dc converter over the operating input range 160 V < VIN 5
200 V.
evaluate the amount of energy lost every time the converter undergoes an on-off cycle. This
energy loss will set a limit on the maximum frequency at which the D2 can be modulated
on and off. Figure 5.17 shows the expected energy loss per modulation cycle as the input
voltage is varied over all the operating range. The energy lost per modulation cycle at
VIN= 160 V is 3 /tJ. We can use this result to determine that for a 2 W loss (1 % of the
output power), the maximum modulating frequency at which the cell can turn on and off
is 666 KHz.
- 122 -
5.4 Example design of a Class 4 de-de converter
Vds(t) at turn on , VIN= 160 V, fs30 MHz
)0
Time [ns]
Figure 5.15: Simulated drain to source voltage at turn-on for the example design of Sec-
tion 5.4 Here, VIN = 160 V. The low energy stored in the passive components permits fast
transient response. With the components of Table 5.1, Vd,(t) reaches steady state within
10 switching cycles.
vd(t) at tum on, with no damping v (t) at tum on, C=--4 nF, Csdamp=12 nF, FRsmp=lO0
450 -- . .. .
..... ..............
AM .................11. ....
350.......
250 .............
2000 ...... ..................
..............
......
150 ....
100
50
0
-1 -0.5 0 0.5 1 1.5 2
Time [ps] Time [jls]
(a) With no damping leg (b) Optimized damping
Figure 5.16: Components CSdamp and RSdamp in Fig. 5.3 damp the low frequency oscilla-
tions occurring every time the dc-dc converter is activated. (a) Shows the voltage Vd,(t)
when the damping components are omitted and (b) shows vd,(t) with RSdamp = 10 ~2 and
CSdamp=12 pF.
- 123 -
A 42 De-Dc Converter
Energy loss per modulation cycle vs. VIN
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .} . . . . . . . . . .
. . . . . . . . . . : . . . . . . . . . . :.. . . . . . . . . . . . . . . . . . . . .:. . . . . . . . . . . . . . . . . . . . . ! . . . . . . . . . . . . . . . . . . . .
i · · · · · i · .· ..· .· ·..··.· .·.

· · · · · ·.
..............................
.................
.. ....................
..................................
........
............
........... ......
.................... ...·.·...............
.·
'60 165 170 175 180 185 190 195 200

Input Voltage [V]
Figure 5.17: Simulated energy loss per modulation cycle vs. VIN. The modulating frequency
which reduces the converter efficiency by 1% is 666 KHz.
- 124 -
5.5 42 dc-dc Converter Implementation
To implement the I2 dc-dc converter (shown again in Fig. 5.18), presented in Section 5.3,
similar impedance measurement techniques as applied in the construction of the 12 inverter
of Section 4.5 were used. The dc-dc converter was constructed on a printed circuit board
(PCB) (2-layer, 4 oz. copper, FR4 material). The masks of the PCB can be found in
Appendix F.
Figure 5.18: Schematic of the #2 dc-dc converter. Component values listed in Table 5.1.
Figure 5.19 displays a photograph of the prototype, with all components mounted on the
PCB. As with the prototype of the I2 inverter of Section 4.5, the ARF521 MOSFET was
mounted on a fan-cooled aluminum heat sink with a thermal resistance of 0.5 OC/W (Cooler-
Master @ HAC-L82). The two silicon carbide diodes were soldered on the PCB, and a water-
cooled heat sink (Tide Water CL-W0052 from Thermaltake) was attached to the bottom
side of the board. A heat-pad (Bergquist, p/n CPU 1.375X1.375) was placed between the
surface of the diode heat sink and the bottom layer of the PCB. Both heat sinks were
substantially over-sized for purposes of initial testing.
To evaluate and measure the steady state performance of the converter, a 33 V de load
was constructed by paralleling 14 50-W Zener diodes (NTE5269A). The Zener diodes were
mounted on a 0.33 O/W (Natural Convection) heat sink (Wakefield engineering p/n 392-
300AG) with two muffin fans attached at its ends. Figure 5.20 shows a photograph of the
>2 converter connected to the 33 V dc load. The photograph in Fig. 5.21 provides a closer
view of the dc-dc converter and indicates the location of the semiconductors.
The first components placed on the prototype board were CMR and LMR which introduce a
null at the second harmonic of the switching frequency. LMR was constructed by winding 9
turns of AWG16 magnet wire on a 3/8 in. diameter Teflon® rod (with 14 turns/in threads) 2 .
2
My colleague Yehui Han designed and constructed the inductors and the autotransformer used for this
prototype.
- 125 -
Figure 5.19: Photograph of the prototype 4)2 dc-dc Converter showing the heat sinks at-
tached to the semiconductors.
CMR was implemented by connecting 3 (two 56 pF and one 39 pF) porcelain capacitors in
series. A direct measurement of drain impedance placed the resonant frequency of the
LMR-CMR combination at 61 MHz.
The auto-transformer used for this implementation was also built on a Teflon @ rod (9/16 in.
diameter, with 12 turns/in threads). The primary winding consists of 3 turns of AWG16
magnet wire, while the secondary has 2 turns. The secondary winding was placed on top
of the primary to maximize coupling. Parameter extraction was performed by standard
short and open-circuit impedance measurements. These measurements were made with the
auto-transformer placed on the PCB to account for board parasitic inductances. We used
a cantilever model for the transformer, with leakage inductance in the primary, and the
magnetizing inductance (which takes the role of LR in the rectifier) in the secondary. The
measured value of LLEAK= 84 .8 nH, LA=78.5 nH, and the effective turns ratio is N=0.83.
The leakage Lleak contributes part of the 257 nH needed for the reactive interconnect.
Once all the components were mounted on the PCB, we applied a dc bias across the semi-
conductors and measured the drain to source impedance Zd, with the impedance analyzer
(Agilent 4395A). The impedance was measured with 33 V bias at the output and with the
input biased to 160 V. Figure 5.22 shows a measurement of the Zds and compares it with
SPICE simulation in which the parameters were extracted from measurements on the PCB.
This step was made to verify and account for as many parasitic capacitance as was deemed
possible.
- 126 -
Figure 5.20: '12 dc-dc Converter and 33 V dc load.
5.5.1 Gate Drive Implementation
For the test results presented here, the gate was driven form a 50 Q power amplifier. In
order to reduce the impact of the 50 Q output impedance of the power amplifier (Amplifier
Research 150A100B) used, a 4:1 (in impedance) bifilar RF transformer (Pulse Engineering
p/n CX2024) was connected as a transmission-line transformer (autotransformer) to the
input of the gate drive in Fig. 4.16. Reducing the effective impedance at the input of the
gate drive circuit allows for a higher gate voltage and a better enhancement of the ARF521
MOSFET.
- 127 -
Figure 5.21: Prototype 12 dc-dc Converter.
Drain to Source Impdeance (Magnitude) at VIN=160 V

oU
- Measured
- - - Simulated ............
i i i ii !
............... • • • :......... . . ..... ..... ......
40 .......... ......... ............... -
30
........
.. -
..
.......... ·
...............
.....
...... I...............
. ... . ..........
Frequency [MHz]
Figure 5.22: Drain to Source Impedance vs. Frequency when VIN=160 V.
- 128 -
5.5 42 dc-de Converter Implementation
5.5.2 Summary of Component Values
Table 5.2 shows measured values of the components in the prototype.
Table 5.2: List of components for the 30 MHz, 160 V to 200 V input 33 V output 12
prototype dc-dc converter.
Part Measured Value Q Part number
CIN 4 ~tF (250 V Ceramic) 4x CKG57NX7R2E105M
LF 384 nH (off-board 197 9 turns of AWG 16 wire
measurement) on a 3/8 in. diam. Teflon® rod
MOSFET ARF521 APT Inc.
LMR 414 nH 185 9 turns AWG 16 wire
CMR 16.3 pF (porcelain) 10 K 2x56 pF ATC100B560JW
10 K 1x39 pF ATC100B390JW
Cp 28 pF Parasitic drain
capacitance
Cs 4 nF 3K 4x1 nF MC22FD102J-F
CSdamp 10 nF 15 nF C3225COG2E153J
RSdamp 10 Q2 (SMD1012) ERJ-S14F10ROU
Ls 175 nH 195 5 turns AWG 16 wire
Auto-transformer N=0.83 Primary: 2 turns AWG 16 wire
LLEAK= 84 .8 nH Secondary: 3 turns AWG 16 wire
L,=78.5 nH on a 9/16 in. diam. Teflon @ rod
Diode 2x CSD10030 Cree Inc.
COUT 4 pF (250 V Ceramic) 4x
- 129 -
A (2 Dc-Dc Converter
5.6 Experimental Performance of the 4D2 dc-dc Converter
Figure 5.23 shows the drain voltage Vd,(t) and the gate voltage vg,(t) of the MOSFET
when VIN=160 V. The desired trapezoidal drain waveforms with ZVS switching is achieved
(c.f. 5.12(a)). The drain-gate capacitance Cr,, is responsible for the distortion in the gate
waveform. It is expected that an improved gate driver will result in a gate voltage with
larger amplitude that will better enhance the MOSFET.
160
Vd, and Vt (VN= V, f=30 MHz)
400 40
300 30
200 20
100
0 , I SI
I I 0
-100 -10
-Drain Voltage
- - -Gate Votage
0 20 40 60 80
Time [ns]
Figure 5.23: Experimental MOSFET drain to source and gate voltage at VIN=160 V.
Experimental measurements of Vds(t) over the entire operating input voltage range (160 V
to 200 V), portrayed in Fig. 5.24, demonstrate that the peak voltage across the power
MOSFET is at most 2.35 times the input voltage.
The low internal energy storage of the '2 converter offers a means to achieve fast transient
response. This is illustrated in the experimental measurements in Fig. 5.25. The figure
demonstrates that vds(t) reaches steady state in less than 300 ns after the gate signal is
applied. This results are in line with the transient response predicted in the simulation and
presented in Fig. 5.15.
The output power and the drain efficiency of the converter is presented in Fig. 5.26 over
the input voltage range. The figure demonstrates that the 42 dc-dc converter can achieve
- 130 -
5.6 Experimental Performance of the '2 dc-dc Converter
Measured Drain Voltage

- @V IN=160V
-- @VIN=170V
- @V N=200V
Time [ns]
Figure 5.24: Experimental drain-to-source voltage vds for 160 V< VIN <200 V. The peak
drain voltage to input voltage ratio is ý-2.35.
high efficiency over the entire input range (82.5% to 8.7%). The results obtained in this
prototype demonstrates the high degree of performance achievable with this topology.
- 131 -
A 42 De-Dc Converter
Vds(t) and v s(t)

5ULConverSer
Dc-Dc
A(T•2
40C .1'' 1' 'r'.'''l.''

a A ''''''
30C
20C
10
-1tn
0
-'50 0 50 100 150 200 250 300 350 400
Time [ns]
10
-10 -Gate oltag

-02T--aeot~\I'\i''"V 'f'\"~;i'
-50 0 50 100 150 200 250 300 350 400

Time [ns]
Figure 5.25: Experimental startup transient response (to application of the gate drive) of
the 42 converter at VIN=160 V. Vd,(t) reaches periodic steady-state in less than 300 ns.
Dc-Dc Converter Performance vs. Input Voltage
Input Voltage [V]
Figure 5.26: Experimental output power and drain efficiency vs. input voltage for the
prototype dc-dc converter.
- 132 -
Chapter 6
Summary and Conclusions
THIS THESIS introduces system architectures and topologies which enable tremendous
increases in the switching frequency as compared to conventional power converter
designs. This thesis demonstrated that switching frequencies in the VHF ranges are viable.
6.1 Thesis Summary
Chapter 1 outlines the benefits of increasing switching frequency in dc-dc power converters,
and discusses the practical considerations that constrain the operating frequencies of con-
ventional designs. Switching loss, magnetic loss, and gating loss are among the mechanisms
that have limited the switching frequency in most conventional power electronic systems to
only few megahertz. It is also argued that while resonant converters and RF power ampli-
fiers (like the Class E) achieve high efficiency operation at high frequencies by Zero-Voltage
switching, their performance is typically sensitive to changes in the load, and input voltage
and output voltage, limiting their efficacy in many applications.
Chapter 2 introduces cellular dc-dc converter architectures that separate the power process-
ing from the regulation of the output voltage to overcome the aforementioned limitations.
In these designs parameters that are commonly used to control the output voltage (i.e. fre-
quency and duty cycle) remain constant in these new architectures. With this, resonant
techniques commonly used in RF power amplifiers can be exploited to process power ef-
ficiently. The Vernier architecture and the cell-modulated architecture are introduced as
means to achieve high efficiency operation even at light load using switching cells operating
in the VHF range.
Chapter 3 treats in detail the design and performance of a regulated dc-dc converter using
the simplest form of the cell-modulated architecture: a sing VHF cell with on-off "bang-
bang" control. The designed cell incorporates a class E inverter followed by a set or resonant
rectifiers an connected through a "resistance compression network" (RCN). RCN are de-
scribed in [1] and allow a class E inverter to operate over wider voltage ranges. This
chapter also introduces a new trapezoidal gate-drive circuit which operates near-maximum
- 133 -
efficiency and that forms the basis for the design of advanced resonant topologies covered
in Chapter 4.
Chapter 4 introduces an inverter topology (the 42 inverter) that uses a passive network
with multiple resonances to shape the drain voltage. The drain impedance when the switch
is "off" has a zero at the second harmonic on the switching frequency and higher impedance
at the fundamental and third harmonic. By controlling the ratio between the impedance
at fundamental and third harmonic component, the peak switch voltage can reduced sig-
nificantly as compared to conventional designs. This voltage shaping is achieved resonantly
resulting in elements requiring minimum energy storage. The benefits of low energy storage
is twofold: it allows startup response times of only a few cycles of the switching frequency,
and achieve greater power densities through miniaturization of the passive components.
The chapter also presents a method for selecting the passive components needed to achieve
the required drain impedance. Finally, chapter 4 presents an example design of a 30 MHz
O2 inverter and evaluates its performance experimentally. The measured drain efficiency of
this prototype is in excess of 90%.
Chapter 5 utilizes the advanced resonant inverter introduced in Chapter 4 to develop a a

dc-dc converter topology suitable for operation at frequencies in the VHF range. It details
the designed and construction of a prototype D2 dc-dc converter( also switching at 30 MHz)
The converter delivers in excess of 200 W from an input voltage of 160 V to 200 V to a
33 V dc load. The efficiency of the (2 dc-dc converter implemented ranges between 83%
and 87% across the input voltage range.
6.2 Thesis Conclusions
Over the past years, there has been substantial improvements in power semiconductor that
have dramatically reduced conduction losses (by reducing Rds,on). Likewise, important
breakthroughs in semiconductor packaging have facilitated increases in the power densities
of dc-dc converters. Nonetheless, conventional power converters still have the switching
frequencies limited to just few megahertz.
Dramatic improvement in the switching frequency of power converters offers the opportu-
nity of greater miniaturization and better dynamic performance. Operating at switching
frequencies that are more than an order of magnitude higher than conventional designs
requires addressing the switching, magnetic, and gating losses which grow as the driving
frequency increases. The work presented in this thesis addresses these limitations through
the development of new circuit topologies and system architectures.
- 134 -
6.3 Future Work
6.3 Future Work
The architectures and topologies introduced in this thesis open opportunities for further
development and research. For example, they can lead to designs that can achieve even
higher operating frequencies than those implemented here. In low voltage applications such
increase in switching frequency can lead to designs in which all the passive components
integrated on the die or within the device package.
Ongoing research in new power semiconductor technologies (i.e. Gallium Nitride and Silicon
Carbide) promise devices with conduction and switching characteristics that outpace those
of conventional Si devices. Available and emerging devices in these material systems, (such
as MESFETS, JFETS, HEMTS, etc.) are often tested at RF operation and are not amenable
to conventional drive strategies. It is worth exploring the use of some of the resonant
topologies discussed here on the realm of these new semiconductor technologies and less
conventional device types. All converters evaluated here used RF MOSFETS but there are
other switching devices amenable for power conversion in the VHF range. For example, the
higher switching performance of devices such as GaAs MESFETs can be employed to enable
even higher driving frequencies.
Most commercial power devices are not optimized for switching operation at VHF frequen-
cies. This offers many opportunities for innovation. Improvements in device parameters
like the resistance in series with Co,, is particulary important to achieve high efficiency in
the VHF converters introduced here. The packaging of semiconductors is oftentimes the
limiting factor in the operating frequency in commercial devices. Commonly used semi-
conductor packages, like the TO-220 or TO-247, have lead inductances in the order of
ten's of nanohenries, that confine their maximum driving frequencies (even using advanced
topologies like the (2 inverter) to just few megahertz.
Adapting the advanced resonant techniques presented in Chapter 4 and 5 to converters

operating at very low output voltage is another area of research with opportunities for
further development. Synchronous rectification applied to converters similar to the 42 can
have an important role in the design of Point Of Load (POL) converters for future micro-
processors. By increasing the bandwidth of POL regulators using some of the techniques
explored here, it is possible to reduce the large number of output capacitors required in those
systems today. Additionally, still better performance can be expected if the waveshaping
methods presented here can also be used to reduce the stresses in the rectifier.
Higher power densities and important size reduction can be obtained by using high-frequency
magnetic materials (i.e. Zn-Fe). These materials, even though their relatively low permeabil-
ity, have low losses up to few hundred's of Megahertz. More advanced anisotropic materials
- 135 -
can be used to make inductive structures having higher quality factors, and thus reducing
their size. The use of relatively high-permeability magnetic materials can ameliorate the
EMI and electromagnetic compatibility issues resulting from switching in the VHF range.
- 136 -
Appendix A
Low Order Lumped Network derivation
A.1 Derivation
Figure A.1 shows the low order lumped network presented in the converter introduced in
Chapter 4.
Low-order lumped Network
Figure A.1: Simple low-order lumped network.
This appendix will show how to determine the value of the circuit parameters of the network
of Fig. A.1 that, for a given value of CF, result in a transfer function with a magnitude
having a zero at the second harmonic of the switching frequency and poles at both the
fundamental and third harmonic of the switching frequency [57, 82].
The input impedance of the network is ZIN = ZFIIZMR where:
1 sLF 1 1 + S2 LMRCMR
ZF = LFII 1 LFF and ZMR = sLMR +
SCF 1 + S2LFCF SCMR SCMR
(A.1)
Expressing the ZIN in terms of ZF and ZMR is convenient way of understanding the impact
that changes in the value of the components has on the magnitude of the impedance.
Figure A.2 shows the magnitude ZF and ZMR of the network of Fig. A.1 when CF = 100
- 137 -
Low Order Lumped Network derivation
pF and properly tuned. The figure also shows that asymptotically ZIN can be seen as the
lowest impedance between ZF and ZMR. The poles in IZINI occur when IZFI and IZMRI
intersect.
IZFI, IZMRI and IZINI vs. Frequency
·.· · · ·.· · ·. · ·. · ·.. ·. ·
i'
i··r
~r
rY
r.
··
00
Frequency [MHz]
Figure A.2: IZFI, JZMRI and IZINI vs. frequency for the low-order network shown in Fig. A.1
and tuned to have impedance poles at f=100 MHz and f=300 MHz and zero impedance at
f=200 MHz.
Using the expression for ZF and ZMR in Eq. A.1 we can write ZIN as:
(SLF) (1 + S2LMRCMR)
1 + S 2 (LFCF + LMRCMR + LFCMR) + (A.2)
84 (LFCFLMRCMR)
and the magnitude of the transfer function can be written as:
ZIN = 1 - (WLF)2W2 (A.3)

1 MM]
MW]
+ 1 7
.M + u).2 UJFF(7m
where:
1 1 1
WFF = w = and OFM = (A.4)
NITI/F LMRCMR ' and WFM
- 138 -
A.1 Derivation
By setting WMM = 2ws = 47rfs, where f, is the switching frequency of the converter, we
introduce a zero in the transfer function at the 2nd harmonic of the switching frequency.
The poles of the transfer functions occur when:
1 -w 2 w + + [ 0 (A.5)
1:F M w),FM WFF MM
Solving the two positives roots of the quartic we find:
W1,3
ý1aIV --I
Ta[ (A.6)
where,
=W [FW ] [ + ;M ]
±MF
(A.7)
Ot -- -- -J- 032 M
and,
(A.8)
I-FF +[ WMM WM
W
Setting the condition to have poles at the fundamental and third harmonic of the switching
frequencies (wl = ws and W3 = 3ws), we arrive to the following conditions:
a = 5w2 , p = 9W2
195 '
(A.9)
The conditions of the impedance transfer function are then:
3
WFF Ws WMM = 2W8s , WFM = s • (A.10)
We can now find expressions for the different elements of the low-order lumped network of
Fig.A.1 in terms of the capacitor CF:
1
LF-= ' LMR
$9r2g• =
1
1 , and CMR = -CF1
15
(A.11)
15r2 2f2CF 16
- 139 -
Appendix B
100 MHz dc-dc converter PCB layout
Figure B.1: 100 MHz dc-dc PCB Schematic.
- 141 -
Figure B.2: 100 MHz dc-dc PCB Board.
L.E.E.S. @ MIT (C)2004

O Juan Pivas, Piad Wahby,
Shafran, Olivia Leitermann,
John
Prof. David Perreault
2004/02/18
T
A: 0
0 0
Figure B.3: 100 MHz dc-dc PCB Board. Top copper layer.
- 142 -
$C2
i
L.E.E.S. @ MIT (C)2004
Juan Rivas, Riad Wahby,
John Shafran, Olivia Leitermann,
Prof. David Perreault
2004/02/18
Figure B.4: 100 MHz dc-dc PCB Board. Top silkscreen layer.
0 0
"1 1 "//
D~i~g~
UMR
o 0
Figure B.5: 100 MHz dc-dc PCB Board. Top cream layer.
- 143 -
. 7Z , . 7
Io: " . " -Zi .
.
"V,•
Figure B.6: 100 MHz dc-dc PCB Board. Top stop layer.
I
C
Figure B.7: 100 MHz dc-dc PCB Board. Bottom copper layer.
- 144 -
O O
ET3 E3
o 0
layer.
PCB Board. Bottom silkscreen
Figure B.8:100 MHz dc-dc
Figure B.8: 100 MHz dc-dc PCB Board. Bottom silkscreen layer.
K
6Y 6'
:I:s··?r~ ~i
':~
IF
"-~~
:'"·*
i? mTa
ir-··~-:·~·:·s
•,
Figure B.9: 100 MHz dc-dc PCB Board. Bottom stop layer.
- 145 -
o0
O O
Figure B.10: 100 MHz dc-dc PCB Board. Bottom cream layer.
- 146 -
Appendix C
Trapezoidal gate-drive PCB layout
IOUNT.-HOLE3.3
'
W U04
NTHOL
373AL..S
X1-"
X1--
I~9l~;jlJNI··H'.I~~3.3
IOUNT
- +,1LE3.3
TITLE: M1I3SO1OOM_v2_Thesis
Document Number: REU:
Date: 7/26/2006 10:03:02p Sheet: 1/1
Figure C.1: Trapezoidal gate-drive PCB Schematic.
- 147 -
C f
r~3 0
>C,10
ý_
QLOl
ml..
Cdlr
PE~/
Figure C.2: Trapezoidal gate-drive PCB Board.
0 -1 0
o o
Figure C.3: Trapezoidal gate-drive PCB Board. Top copper layer.
- 148 -
-r h
JU fF"
LII
C3
41 M rig
O
M> LO
WO~
J- L. 1
xi IL i
2I
Figure C.4: Trapezoidal gate-drive PCB Board. Top silkscreen layer.
oo 0
Q ©iizzzp
OWN=
Figure C.5: Trapezoidal gate-drive PCB Board. Top cream layer.
- 149 -
Figure C.6: Trapezoidal gate-drive PCB Board. Top stop layer.
Figure C.7: Trapezoidal gate-drive PCB Board. Bottom copper layer.
- 150 -
Ln X
K- N
%>73 {KY-
Figure C.8: Trapezoidal gate-drive PCB Board. Bottom stop layer.
fiI 0N>,,
K" -
Ln /
Figure C.9: Trapezoidal gate-drive PCB Board. Bottom stop layer.
- 151 -
Appendix D
Trapezoidal start-up PCB layout
Figure D.1: Start-up PCB Schematic.
- 153 -
Figure D.2: Start-up PCB Board.
r rI
((c) 2005 MIT
Figure D.3: Start-up PCB Board. Top copper layer.
EU
] (
Juan Rivas (c) 2005 MIT
Figure D.4: Start-up PCB Board. Top silkscreen layer.
- 154 -
-za
(c) 205 IT
(C) 2005 MIT
Figure D.5: Start-up PCB Board. Top cream layer.
Li7 D
Li
(c)25 M IT
(c) 20095 MIIT
Figure D.6: Start-up PCB Board. Top stop layer.
C3) TI
(c) 2005 MIT
Figure D.7: Start-up PCB Board. Bottom copper layer.
- 155 -
I
IIT
(c) 2005 MIT
Figure D.8: Start-up PCB Board. Bottom silkscreen layer.
b,\\
(C) 2G05 MIT
Figure D.9: Start-up PCB Board. Bottom stop layer.
(c) 2005 MIT
Figure D.10: Start-up PCB Board. Bottom cream layer.
- 156 -
Appendix E
42 Inverter PCB layout
-- t------i--- -------------- 1
1 - Eaft~~l P - - Q(ItI
- - - - - - - - -C--
rotI lrzI r~)n I

C432
Uf
-10 --
- - -
- -
-- --
-- - -
---
--- -
---- J
- -- - - LCNN2-ze~z ouricy 5c CA0"i
I ' PPC313
~n~LF~t· L U _1 _tte rai-_ ndC Sia Circuit
r-------------------------------,--a-------------
Tuce ..
.........
....
........
.....
...... .............
.............
[......T
:.I ., ....
CCA
I h .....
•...... n.
.......
..
..........
T..............................
.... 5 pr_ PFXY PFUo
........
il...............
-.....................
......................
.........
...........
.................
.... ~~ ........
lRi·vI
TpF~
Juan Pivas, Olivia Leitermann

Yehui Han, Prof. David Perreault (C) M.I.T. 2
(C) M.I.T. 20
rTITLE: INU
IIl " Massachusetts
Document Number: REU:
Institute of
TechnologyI 12 0 3
IDate: 5/17/2006 : :00p jSheet: 1/1
Figure E.1: Inverter PCB Schematic.
- 157 -
'2 Inverter PCB layout
------------------------------------
Ci~
1inch
LFigure E.2: Inverter PCB Boar-----------------------------d.
Figure E.2: Inverter PCB Board.
------------------------------------ 1
S 0
0
I
0
0
0
o0
0o
0o
0o
O 1 inch I
Figure E.3: Inverter PCB Board. Top copper layer.

Figure E.3: Inverter PC13 Board. Top copper layer.
- 158 -
------------------------------------
~
SO
i Phi-2 (Poiato) Inverter
O -
II6 6
< (©I
SIP
II
1- Juan Pivas, Olivia Leitermann

101 Yehui Han, Prof. David Perreault
-- (C) 2006 LEES MIT
L ,---,,----------------------------
Figure E.4: Inverter PCB Board. Top silkscreen layer.
r-------------- --------------------- I
I I
I0 0
L- igu----------- ePBB - d.Tpe------------

--- ----
Figure E.5: Inverter PCB Board. Top cream layer.
Figure E.5: Inverter PCB Board. Top crearm layer.
- 159 -
b2 Inverter PCB layout
------------------------------------ I
I 'I
1 inch
Lveter
Figure E.6: PC oad. Top stop l-----------------------------------ayer.
------------------------------------- 1
0 I~ -~
S 0
I0
0 1 inch O
Figure E.7: Inverter PCB Board. Bottom copper layer.

Figure E.7: Inverter PCB Board. Bottom copper layer.
- 160 -
r--------------------------------- ___1
I 0'
.xul*
L .
I -I
- 0
0
L ------------------
3O
O C
I 0
! 1 A "inch
L - - Bottom
Figure E.9: -----------------
Inverter PCB Board. - -
- -stop- layer. -- J
Figure E.9: Inverter PCB Board. Bottom stop layer.
- 161 -
O2 Inverter PCB layout
E.1 RF Load PCB
0
-u
O
_r
L6.
cE
0
(Y)
Juan Rivas, Olivia Leitermann 0512006

Yehui Han, Prof. David Perreault
S,0, L.E.E.S. @ MIT (C) 2006
Figure E.10: RF Load PCB.
- 162 -
E. 1 RF Load PCB
Figure E.11: RF Load PCB: top copper layer.
4ý I
A
1inch RFC
RFC3 75Ohms FC4 750hms
R~~F~kmF
,, ,,
0I
B I-
CL3 j XNV4
vi
'.4u
UV4
Juan Rivas, Olivia Leitermann 05/2006

Yehui Han, Prof. David Perreault
L.E.E.S. @ MIT (C) 2006
Figure E.12: RF Load PCB: top silkscreen layer.
163 -
(2 Inverter PCB layout
0 U U\ n
0000
0 0 0 0
0 0 0 0
0 0
Figure E.13: RF Load PCB: bottom copper layer.
0 0
SI I I
I I
Figure E.14: RF Load PCB: bottom silkscreen layer.
- 164 -
Appendix F
1)2 Dc-Dc Converter PCB layout
-
Massachusetts
T , ,÷II f - - - - - - - - - - - - -
acs.
,F1;152
6i•NG I
---- ---------------------------
"I
I"!" POWMOLEX2PM
COPi CB
22 ic3P3 70"4 CITSP5
C_ 6, I
L n Filer
. ~-i - -C/
GLt nd Bias Circuit
r----------------------------- -I-----
....
ucc , , .. ......
............
...........
I If
!CI1RZ
L i
Te
I 4 . ......
.
P,i2 Po or Skage
L--------------------------------------------------------------------I
rmr
I Lco co2 a ca2L Cort Cor c CC22

r14
Ti7
T T T T T T - Yehui Han, Juan Rivas

I -V 1T22 Olivia Leitermann, Prof. David Perr&,u I.T. 2E 36
rt C0 2oTr _OJT
T J6
C2
o cI TITLE: CONUERTERLU1FINAL817
.. .. .. Document Number: REU:

Date: 8/17/2006 10:37:12a Sheet: 1/1
Figure F.1: Dc-Dc Converter PCB Schematic.
- 165 -
12 Dc-Dc Converter PCB layout
------------------- -----------
8 8 8
ii'
LFigure F.2: Dc-----------Dc
Converter PC--------------B
Board.
Figure F.2: Dc-Dc Converter PCB Board.
- 166 -
-----------------------------
I O O O I
I
ij~'I
0 0 0
Figure F.3: Dc-Dc Converter PCB Board. Top copper layer.

Figure F.3: Dc-Dc Converter PCB Board. Top copper layer.
- 167 -
(2 Dc-Dc Converter PCB layout
--z-------------~~~-~ indNI IdlfO
8
ii
LFigure F.4: Dc-Dc Converter PCB Board. Top silk---------------------screen
l---------ayer.
Figure F.4: Dc-Dc Converter PCB Board. Top silkscreen layer.
- 168 -
- - - -- ------
F- ----------------- - -1
- ---
I o
K\\
'E,
B~
NMR
1M
MBL\lly
0>,
L -------- ---------------
---
Figure F.5: Dc-Dc Converter PCB Board. Top cream layer.
- 169 -
42 Dc-Dc Converter PCB layout
-------------------------------- 1
- L £&ALt>
rt~"xr~i7~rJt~.~s~J~31~;~,Y~ma~~F~z~ru~r
L-------------------------------
K - - -, 1K
J
Figure F.6: Dc-Dc Converter PCB Board. Top stop layer.
- 170 -
0 0 0-----------------------------
O O O
L
0 0
1K'
0
I
JI.:D-
Figure F.7: Dc-Dc Converter PCB Board. Bottom copper layer.
- 171 -
(2 Dc-Dc Converter PCB layout
F -----------------------------
0 I
r7
LJ
I
yu I
/YY
....... -I
II
< >
I /
Figure F.8: Dc-Dc Converter PCB Board. Bottom silkscreen layer.
- 172 -
------------------ -----------
I I
... (•. •7 p I
' os
aVQ1,
0 -O
.A..
'
@©o ©© @
©~~
8
G"i
8 8
8~/(/8i3ii?
8 O :b 89
I!
6s
I 2
HEJ
L -----------------------------
Figure F.9: Dc-Dc Converter PCB Board. Bottom stop layer.
- 173 -
Appendix G
PSPICE files
G.1 42 Inverter
*** CIRCUIT FILE TO SIMULATE THE ***

*** THE NEW PHI-2 (POTATO) INVERTER ***
*** TRANSIENT SIMULATION

*** WRITTEN BY: JUAN RIVAS, M.I.T. ***
*** CAMBRIDGE,MA 04/20/2006 ***
* SIMULATION CONTROL *
*---STEP COMMAND
.STEP PARAM VIN LIST 160 200
*---TRANSIENT COMMAND
.tran 35p 1Ou 9u 35p uic
*---AC FREQUENCY SWEEP COMMAND
*.ac dec 3k IMEG 500MEG
.PROBE
*** LIST OF LIBRARIES ***
.LIB "THESIS.lib"
**** OPTIONS TO AVOID CONVERGENCE PROBLEMS ***
.OPTIONS ABSTOL=1OnA
+ GMIN=10p
+ ITLI=6000
- 175 -
PSPICE files
+ ITL2=4000
+ ITL4=5000
+ RELTOL=0.005
+ VNTOL=O.O6mV
.OPTION STEPGMIN
*******************************************
*** OPTIONS TO KEEP A SMALL OUTPUT FILE ***

*******************************************
.OPTIONS
+ NOPAGE
+ NOBIAS
+ NOECHO
+ NOMOD
+ NUMDGT=8
.WIDTH OUT=132 ;TO PRINT MORE COLUMNS
********************************************
*** SPECIAL PARAMETERS AND CONSTANTS ***

*******************************************
*******************************************
.PARAM:
+ PI=3.14159265358979 ;GUESS WHAT
*---CONVERTER PARAMETERS
.PARAM:
+FS=30MEG ;SWITCHING FREQUENCY
+VIN=200 ;INPUT VOLTAGE
+DUTY=0.3 ;DUTY CYCLE
***************************
*LOW ORDER LUMPED NETWORK *

****************************
*---LF LEG
VDULF N01 N02 0
XLF N02 N03 LCHQC
+ PARAMS:
+ L=306.19NH ;LF INDUCTOR
+ QL=190
+ FQ={FS}
+ RDC=5M
+ ICL=O
+ EPC=.001P
+ ICC=O
- 176 -
G.1 42 Inverter
+ EPR=1OMEG
VIN N03 0 {VIN}
*---MR LEG
VDUMR N01 N05 0
XCMR N05 N06 CQL

+ PARAMS:
+ C=16.29PF ;CMR CAPACITOR
+ QC=3K
+ FQ={FS}
+ ICC=O
+ ESL=1P
+ ICL=O
XLMR N06 0 LQCR
+ PARAMS:
L=414n
QL=190
FQ={FS}
EPC=. 1P
EPR=10OMEG
ICL=O
ICC=O
*---DUMMY SOURCE TO MEASURE THE IMPEDANCE OF

* THE LOW ORDER LUMPED NETWORK
VDUZMR NT NOi 0
*SEMICONDUCTOR SWITCH *
VDUSMOS N01 N07 0 ;DUMMY SOURCE TO MEASURE

;THE DRAIN SWITCH CURRENT
XSIMOS GATE N07 0 ARF475FLD-v5
+ PARAMS:
+ RDSON=1
+ RG=lOm
+ CGS=.IP
+ LG=.1P
+ LD=1.5N
+ LS=1N
- 177 -
PSPICE files
+ RCOUT=O.3
*IDEALIZED GATE DRIVER*
*---GATE DRIVE PARAMETER

.PARAM:
+TR={1/(100*FS)} ;RISE TIME
+PWIDTH={(DUTY/(FS))-TR-TR} ;PULSE WIDTH
VGATE GATE 0 PULSE(-25 25 0 {TR} {TR} {PWIDTH} {1/FS})
*RESONANT LOAD SECTION *
*---DUMMY TO MEASURE RESONAN*T LOAD

VDUZL NT M01 0
VDUCP M01 M02
XCP M02 0 CQL
+ PARAMS:
+ C= 28.065P
+ QC=3K
+ FQ={FS}
+ ICC=O
+ ESL=1P
+ ICL=O
VDUCS M01 M03
XCS M03 M04 CQL
+ PARAMS:
+ C=2N
+ QC=10K
+ FQ={FS}
+ ICC=O
+ ESL=1P
+ ICL=O
XLS M04 M05 LQCR
+ PARAMS:
*+ L= 200N
+ L=192.5N
+ QL=192.3
+ FQ={FS}
+ EPC=1P
+ EPR=10MEG
- 178 -
G.1 (2 Inverter
+ ICL=O
+ ICc=O
RLOAD M05 0 33.2
*AC SOURCE *
*---ThIS SECTION IS COMMENTED WHEN RUNING A TRANSIENT

* SIMULATION
* OTHERWHISE CAN BE USED TO OBTAIN THE IMEDANCE OF
* THE DRAIN NODE NT
* IT INCLUDES THE 1UF CAPACITOR USED TO BIAS THE DRAIN
*VT NT 0 {VIN} AC 1
*vZIN ZT 0 AC 1
*XCZT ZT 0 CQL
*+ PARAMS:
*+ C=lu
*+ QC=3K
*+ FQ={FS}
*+ ICC=O
*+ ESL=7.5n
*+ ICL=O
***SUBCIRCUITS TO MEASURE PERFORMANCE ***
.FUNC LORC(FS) {I00/(2*PI*FS)} ;FUNCTION THAT PLACES THE FILTER

;COMPONENT OF THE MEASURMENT
;CIRCUITS TWO DECADES BEFORE THE
;SWITCHING FREQUENCY
*-----INPUT POWER MEASUREMENT

EPI PIN01 0 VALUE={V(N03)*(-I(VIN))}
LPI PIN01 PIN {LORC(FS)}
CPI PIN 0 {LORC(FS)}
RPI PIN 0 1
*-----OUTPUT POWER MEASUREMENT
EPO PO01 0 VALUE={v(MO5)*I(VDUCS)}
LPO PO01 POUT {LORC(FS)}
CPO POUT 0 {LORC(FS)}
RPO POUT 0 1 ;OUTPUT POWER
*---- EFFICIENCY
- 179 -
PSPICE files
EEFF EFF 0 VALUE={IF(TIME<100N,O,V(POUT)/v(PIN))}

*---RMS OF DRAIN VOLTAGE
ERMS1 RMS1 0 VALUE={V(NT)**2}
LRMS1 RMS1 RMS2 {LORC(FS)}
CRMS1 RMS2 0 {LORC(FS)}
RRMS1 RMS2 0 1 ;RMS OUTPUT VOLTAGE
ERMS2 VNTRMS 0 VALUE={SQRT(V(RMS2))}
RRMS2 VNTRMS 0 1
G.2 (2 dc-dc Converter
*********************************************************
*** CIRCUIT FILE TO SIMULATE THE

*** THE NEW PHI-2 (POTATO) INVERTER ***
*** ***
*** TRANSIENT SIMULATION **

*** WRITTEN BY: JUAN RIVAS, M.I.T. ***
*** CAMBRIDGE,MA 04/20/2006 **
**********************
* SIMULATION CONTROL *
*---STEP COMMAND
.STEP PARAM VIN LIST 160 200
*---TRANSIENT COMMAND
35
.tran 35p 20u 19.5u p uic
*---AC FREQUENCY SWEEP COMMAND

*.ac dec 3k iMEG 500MEG
.PROBE
*** LIST OF LIBRARIES ***

***** * ****** *
* ********* **
- 180 -
G.2 (2 dc-dc Converter
.LIB "THESIS.lib"
**** OPTIONS TO AVOID CONVERGENCE PROBLEMS ***
.OPTIONS ABSTOL=1OnA
+ GMIN=10p
+ ITLI=6000
+ ITL2=4000
+ ITL4=5000
+ RELTOL=0.005
+ VNTOL=O.O6mV
.OPTION STEPGMIN
*** OPTIONS TO KEEP A SMALL OUTPUT FILE ***
.OPTIONS
+ NOPAGE
+ NOBIAS
+ NOECHO
+ NOMOD
+ NUMDGT=8
.WIDTH OUT=132 ;TO PRINT MORE COLUMNS
*** SPECIAL PARAMETERS AND CONSTANTS ***
.PARAM:
+ PI=3.14159265358979 ;GUESS WHAT
*---CONVERTER PARAMETERS
.PARAM:
+FS=30MEG ;SWITCHING FREQUENCY
+VIN=200 ;INPUT VOLTAGE
+DUTY=0.3 ;DUTY CYCLE
*LOW ORDER LUMPED NETWORK *

#####**######*#######*****#
- 181 -
PSPICE files
*---LF LEG
VDULF N01 N02 0
XLF N02 N03 LCHQC

+ PARAMS:
+ L=345N ;LF INDUCTOR
+ QL=160
+ FQ={FS}
+ RDC=5M
+ ICL=O
+ EPC=.OO1P
+ ICC=O
+ EPR=1OMEG
VIN N03 0 {VIN}
*---MR LEG
VDUMR N01 N05
XCMR N05 N06 CQL

+ PARAMS:
+ C=18.75PF ;CMR CAPACITOR
+ QC=3K
+ FQ={FS}
+ ICC=O
+ ESL=IP
+ ICL=O
XLMR N06 0 LQCR

+ PARAMS:
+ L=375n
+ QL=160
+ FQ={FS}
+ EPC=.1P
+ EPR=10MEG
+ ICL=O
+ ICC=O
*---DUMMY SOURCE TO MEASURE THE IMPEDANCE OF

* THE LOW ORDER LUMPED NETWORK
- 182 -
G.2 t2 dc-dc Converter
VDUZMR NT N01 0
*SEMICONDUCTOR SWITCH *
VDUSMOS N01 N07 0 ;DUMMY SOURCE TO MEASURE

;THE DRAIN SWITCH CURRENT
XSIMOS GATE N07 0 ARF475FLD_v5

+ PARAMS:
+ RDSON=1I
+ RG=lO0m
+ CGS=. .P
+ LG=. 1P
+ LD=1.5N
+ LS=1N
+ RCOUT=0.3
*IDEALIZED GATE DRIVER*
*---GATE DRIVE PARAMETER

.PARAM:
+TR={1/(100*FS)} ;RISE TIME
+PWIDTH:={(DUTY/(FS))-TR-TR} ;PULSE WIDTH
VGATE GATE 0 PULSE(-25 25 0 {TR} {TR} {PWIDTH} {I/FS})
*RESONANT LOAD SECTION *

************ **** ** **
*---DUMMY TO MEASURE RESONANT LOAD
VDUZL NT M01 0
VDUCP M01 M02
XCP M02 0 CQL
- 183 -
PSPICE files
+ PARAMS:
+ C= 30P
+ QC=3K
+ FQ={FS}
+ ICC=O
+ ESL=1P
+ ICL=O
VDUCS M01 M03
XCS M03 M04 CQL

+ PARAMS:
+ C=4N
+ QC=IOK
+ FQ={FS}
+ ICC={VIN}
+ ESL=1P
+ ICL=O
XCSDAMP M03 MO3X CQ1

+ PARAMS:
+ C=15N
+ QC=IOK
+ FQ={FS}
+ ICC={VIN}
+ ESL=1P
+ ICL=O
RDAMP MO3X M04 4
XLS M04 M05 LQCR

+ PARAMS:
+ L=215N
+ QL=160
+ FQ={FS}
+ EPC=1P
+ EPR=10OMEG
+ ICL=O
+ ICc=O
- 184 -
G. 3 Measurement sub-circuits
* ----- RECTIFIER WITH CANTELIVER TRANSFORMER

VDUREC M05 R01 0
XTF1 R02x 0 R01 R02x 2WTRFCL_QCH

+ PARAMS:
+ N2 = i
+ RDCP=5M
+ RDCS=5M
+ LM= 75N
+ QP= 1.60
+ LL2= .01N
+ QS= 160
+ FQ = {FS}
+ IC = 0
VDUSEC RO2X R02 0 ;DUMMY SOURCE TO MEASURE

;SECONDARY CURRENT
XD1 R02 R03 CSD10030

XD2 R02 R03 CSD10030
VOUT R03 0 33
.inc "XF_MEAS.CIR"
G.3 Measurement sub-circuits
***MEASUREMENT CIRCUITS ***
- 185 -
PSPICE files
*JUAN RIVAS 030106
.FUNC LORC(FS) {100/(2*PI*FS)} ;FUNCTION THAT PLACES THE FILTER

;COMPONENT OF THE MEASURMENT
;CIRCUITS TWO DECADES BEFORE THE
;SWITCHING FREQUENCY
*-----INPUT POWER MEASUREMENT
EPI PIN01 0 VALUE={V(n03)*(-I(VIN))}
LPI PINOI PIN {LORC(FS)}
CPI PIN 0 {LORC(FS)}
RPI PIN 0 1
*-----OUTPUT POWER MEASUREMENT resistive load
EPO POO 0 VALUE={v(R03)*I(VOUT)}
LPO P001 POUT {LORC(FS)}
CPO POUT 0 {LORC(FS)}
RPO POUT 0 1 ;OUTPUT POWER
*---- EFFICIENCY
EEFF EFF 0 VALUE={IF(TIME<100N,O,V(POUT)/v(PIN))}
*HIGH Q BAND PASS FILTER ***
*---- PARAMETERS FOR THE BANDPASS FILTER

.PARAM
+ QBP=IO0
.FUNC CBPQ(FS,QBP) {1/(2*PI*FS*QBP)}
.FUNC LBPQ(FS,QBP) {QBP/(2*PI*FS)}
*-----FUNAMDENTAL OF THE RECT. VOLTAGE
EBPRV BPRV1 0 VALUE={V(RO1)}
LBPRV BPRV1 BPRV2 {LBPQ(FS,QBP)}
CBPRV BPRV2 BPRV {CBPQ(FS,QBP)}
RBPRV BPRV 0 1
*-----FUNDAMENTAL OF THE RECT. CURRENT
EBPRI BPRI1 0 VALUE={I(VDUREC)}
LBPRI BPRII BPRI2 {LBPQ(FS,QBP)}
CBPRI BPRI2 BPRI {CBPQ(FS,QBP)}
RBPRI BPRI 0 1
*POWER LOST IN THE INDUCTORS *

$#####################################
- 186 -
G.3 Measurement sub-circuits
**---POWER LOST IN LCHOKE

EPLLF PLLFI 0 VALUE={V(N2,NO3) * (I(VDULF)) }
LPLLF PLLFI PLLF {LORC(FS)}
CPLLF PLLF 0 {LORC(FS)}
RPLLF PLLF 0 1
*---POWER LOST LMR

EPLLMR PLLMRI 0 VALUE={V(NO5, NO6) * (I (VDUMR)) }
LPLLMR PLLMR1 PLLMR {LORC(FS)}
CPLLMR PLLMR 0 {LORC(FS)}
RPLLMR PLLMR 0
*---POWER LOST IN LS
EPLLS PLLSI 0 VALUE={V(N6) * (I(VDUCS)) }
LPLLS PLLSI PLLS fLORC(FS)}
CPLLS PLLS 0 {LORC(FS)}
RPLLS PLLS 0
**---POWER LOST IN LR
*EPLLR PLLRI 0 VALUE={V(ROI,O)*(I(VDULR))}
*LPLLR PLLR1 PLLR {LORC(FS)}
*CPLLR PLLR 0 {LORC(FS)}
*RPLLR PLLR 0 1
*---POWER LOST IN THE WHOLE SWITCH

EPLSW PLSW1 0 VALUE={V(N01)*I(VDUSMOS)}
LPLSW PLSW1 PLSW {LORC(FS)}
CPLSW PLSW 0 {LORC(FS)}
RPLSW PLSW 0 1
*---POWER LOST IN THE DIODES

EPLD PLD1 0 VALUE={V(R02,RO3)*I(VOUT)}
LPLD PLDI PLD {LORC(FS)}
CPLD PLD 0 {LORC(FS)}
RPLD PLD 0 I
*DERIVATIVE CALCULATION ***
*FUNC. FOR R OF THE DERIVATIVE SUBCIRCUIT
- 187 -
PSPICE files
*.PARAM: LDER=.O1U
*.FUNC RDER(LDER,FS) {3000*2*PI*FS*LDER}
*GDER 0 Di VALUE={V(NT)}
*LDER Di 0 {LDER}
*RDER D1 0 {RDER(LDER,FS)}
*EDER DER 0 VALUE={V(DI)/LDER}
*RDER2 DER 0 1K
G.4 Sub-circuit Library
*** SPCIE LIBRARY FOR CIRCUIT SIMULATION IN THE THE
*** BY: JUAN RIVAS, M.I.T.

*** CAMBRIDGE, MA 04-2006
*$
*MODEL: LQCR
* APPLICATION: INDUCTOR MODEL IN WHICH "Q" IS SPECIFIED
* AT A GIVEN FREQUENCY. PARALELL RESISTANCE *
* AND PARALLEL CAPACITANCE ARE INCLUDED
* LIMITATIONS: NONE
*PARAMETERS: *
*L : INDUCTANCE
*QL : SERIES RESISTANCE
*FQ : FREQUENCY AT WICHI THE INDUCTOR Q IS SPEC. *
*EPC : EQUIVALENT PARALLEL CAPACITNACE
*EPR : EQUIVALENT PARALLEL RESISTOR
*ICL : INITIAL CONDITION FOR THE INDCUTOR
*ICC : INITIAL CONDITION FOR THE CAPACITOR *
*NODES:
* LI: INDUCTOR INPUT
- 188 -
* LO: INDUCTOR OUTPUT
.SUBCKT LQCR LI LO
+ PARAMS:
+ L=100N
+ QL=160
+ FQ=30MEG
+ EPC=1P
+ EPR=1OMEG
+ ICL=O
+ ICC=O
.PARAM: PI=3.1416
.FUNC ESR(L,QL,FQ) {2*PI*FQ*L/QL}
R1 LI 101 {ESR(L,QL,FQ)} ;SERIES RESISTANCE
Li 101 LO {L} IC={ICL} ;SERIES INDUCTANCE
Ci LI LO {EPC} IC={ICC} ;PARALLEL CAPACITANCE
R2 LI LO {EPR} ;PARALLEL RESITANCE
.ENDS LQCR
*MODEL: CQL *
* APPLICATION: SIMPLE MODEL OF CAPACITOR WHICH INCLUDES *
AN EQUIVALENT SERIES RESISTANCE THAT IS *
* DESCRIBED IN TERMS OF THE "Q"AT A GIVEN *
* FREQUENCY. SERIES INDUCTANCE ALSO MODELED *
* LIMITATIONS: NONE
*PARAMETERS: *
*C : CAPACITANCE
*QC : Q OF THE CAPACITOR AT A GIVEN FREQUENCY
*FQ : FREQUENCY AT WHICH THE Q IS EVALUATED
*ICC : INITIAL CONDITION *
*ESL : EQUIVALENT SERIES INDUCTANCE
*ICL : INITIAL CONIDTION OF THE INDUCTOR
*NODES:
* CI: CAPACITOR TERMINAL I
* CO: CAPACITOR TERMINAL 0
.SUBCKT CQL CI CO
- 189 -
PSPICE file8
+ PARAMS:
+ C=IOOP
+ QC=3K
+ FQ=30MEG
+ ICC=O
+ ESL=IP
+ ICL=O
.PARAM PI=3.1416
.FUNC ESR(C,QC,FQ) {i/(2*PI*FQ*C*QC)}
Cl CI 101 {C} IC={ICC} ;SERIES RESISTANCE
Ri i01 102 {ESR(C,QC,FQ)} ;SERIES CAPACITANCE
L1 102 CO {ESL} IC={ICL} ;SERIES INDUCTANCE
.ENDS CQL
*$
*MODEL: LCHQC *
* APPLICATION: SIMPLE MODEL THE CHOKE INDUCTOR IN WHICH
THE DC RESISTANCE (RDC) AND THE AC
RESISTANCE ARE SPECIFIED, THE AC RES.
IS SPECIFIED BY ITS Q AT A GIVEN FREQUENCY*
EQUIVALENT PARALLEL CAPACITANCE AND RESIS-*
TANCE ARE ALSO SPECIFIED
* LIMITATIONS: NONE
*PARAMETERS: *
*L : INDUCTANCE
*QL : SERIES RESISTANCE
*FQ : FREQUENCY AT WICHI THE INDUCTOR Q IS SPEC.
*RDC : DC RESISTANCE
*ICL : INDUCTOR INITIAL CONDITION *
*EPC : EQUIVALENT PARALLEL CAPACITANCE *
*ICC : CAPACITOR INITIAL CONDITION *
*EPR : EQUIVALENT PARALLEL RESISTOR
*NODES: *
* LI: INDUCTOR INPUT
* LO: INDUCTOR OUTPUT *
.SUBCKT LCHQC LI LO
- 190 -
+ PARAMS:
+ L=100N
+ QL=160
+ FQ=30MEG
+ RDC=5M
+ ICL=O
+ EPC=1P
+ ICC=O
+ EPR=1OMEG
.PARAM:
+ PI=3.1416
+ OMEGA.O={2*PI*FQ/100}
*DC RESISTANCE AND BYPASS CAPACITOR
RDC LI 101 {RDC} ;DC RESISTANCE
*AC RESISTANCE AND BYPASS INDUCTOR
RAC 101 102 {ESR(L,QL,FQ)-RDC} ;AC RESISTANCE
LBP 101 102 {(ESR(L,QL,FQ)-RDC)/OMEGA.0} IC={ICL}
L1 102 LO {L} IC={ICL} ;CHOKE INDUCTANCE
Ci LI LO {EPC} IC={ICC}
Ri LI LO {EPR}
.ENDS LCHQC
*MODEL: ARF521FLD_v5
* APPLICATION:
* SIMPLIFIED MODEL OF THE APT DEVICE USING A SWITCH
* AND A NONLINEAR CAPACITOR
* VERSION 0.0
* LIMITATIONS:
* 13 apr 06
* PARAMETERS:
* RDSON: ON RESISTANCE
* RG: GATE RESISTANCE
* CGS: LINEAR GATE TO SOURCE CAPACITANCE
* COUT: LINEAR DRAIN TO SOURCE CAPACITANCE
* RCOUT: RESISTANCE IN SERIES WITH D-S CAPACITANCE
* RSHUNT: DRAIN TO SOURCE RESISTANCE TO ACCOUNT FOR OFF
* CURRENT
- 191 -
PSPICE files
*NODES:
* GATE: GATE OF THE MOSFET
* DRAIN: DRAIN OF THE MOSFET
* SOURCE: SOURCE OF THE MOSFET
* NOTES:
* MODEL BASED ON MEASUREMENTS MADE ON 04/05/06
* THE NON-LINEAR CAPACITANCE MODEL WAS SELECTED TO FIT
* THE MEASUREMTS AT VOLTAGES HIGHER THAN 16v
* BACK DIODE MODEL WITH DATE FROM APT SPICE MODELS
.SUBCKT ARF475FL_Dv5 GATE DRAIN SOURCE

+ PARAMS:
+ RDSON=0.580 ;NOT FIXED YET
+ RG=0.116 ;measurement added 6apr
+ CGS=780P ;NOT FIXED YET
+ RCOUT=0.410 ;measurement added 6 apr
+ RSHUNT=12MEG
+ CJO=2478.06P ;;measurement added 5 apr
+ VJ1=1.0883 ;;measurement added 5 apr
+ M1=0.6946 ;;measurement added 5 apr
+ VJ2=.37951 ;;measurement added 5 apr
+ M2=.62852 ;;measurement added 5 apr
+ Vbreak=14.5 ;;approximation added 5 apr
+ LD=1.5n ;;measurement added 6 apr
+ LS=1.ln ;;measurement added 6 apr
+ LG=1.3n ;;measurement added 6 apr
LD DRAIN DRAINL {LD}

Ron DRAINL DMAIN {RDSON}
RSHUNT DRAIN SOURCEI {RSHUNT}
LSOURCE SOURCE1 SOURCE {LS}
SW DMAIN SOURCE1 GMAIN 0 SWIDEAL
.MODEL SWIDEAL VSWITCH (RON=0.001 ROFF=1.3MEG VON=2.6 VOFF=2.3)
*---NONLINEAR CAPACITANCE EVALUATED AS A CONTROLLED CURRENT

* SOURCE
GCNL Ni01 DRAINL VALUE={IF((V(DMAIN)-V(N101))<O,CJO*V(201)*(1/LDER),
+ IF ((V(DMAIN)-V(NIOI))<Vbreak,
- 192 -
+ V(201)*(1/LDER)*(CJO/((1+((V(DMAIN)-V(NI01))/VJi))**M1)),
+ V(201)*(1/LDER)*(CJO/((I+((V(DMAIN)-V(N101))/VJ2))**M2))))}
RCOUT N101 SOURCE1 {RCOUT}
DBACK NiO1DRAINL DSUB
.MODEL DSUB D (IS=41.5N N=1.5 rs=lu BV=2000 TT=500N)
LGATE GATE GATE1 {LG}
RG GATE1 GMAIN {RG}
CGS GMAIN 0 {CGS}
****SUBCIRCUIT TO EVALUATE THE DERIVATIVE***
*PARAMETERS AND DEFINITION FOR THIS SUBCIRCUIT
.PARAM:
+ LDER=.IU ;INDUCT FOR THE DERIVATIVE SUBCIRCUIT
+ PI=3.1416
*--FUNC. FOR R OF THE DERIVATIVE SUBCIRCUIT

.FUNC RDER(LDER,FS) {3000*2*PI*FS*LDER}
GY 0 201 VALUE={V(N101)-V(DMAIN)}
L1 201 0 {LDER}
Ri 201 0 {RDER(LDER,FS)}
.ENDS ARF475FL_D_v5
*MODEL: CSD10030
• APPLICATION: MODEL OF A DIODE MODELED WITH A NON LINEAR*
* PARALLEL CAPACITANCE CHARACTERISTIC, AND
* AND TAKING INTO ACCOUNT THE DIODE FORWARD DROP
* AND A SERIES REISTANCE
* CREE SiC PART CSD10030, 10A, 300V TO-220
*PARAMETER:
* + ESRC: RESIST. IN SERIES WITH NON-LIN CAPACITOR
* + ESL: EQ. SERIES INDUCTANCE
* + VDON: DIODE FORWARD DROP
* + RON: ON SERIES RESISTANCE
* + CJO:
* + VJ:
*+ M:
* + FS: OPOERATING FREQUENCY
* + VCCAP: VOLTAGE AT WHICH DEVICE CAP. REMAINS CONSTANT*
* + FC: FORWARD-BIAS DEPLECTION CAPACITANCE COEFFICIENT *
- 193 -
PSPICE files
* EXTERNAL NODES:
* A: ANODE
* K: CATHODE
.SUBCKT CSD10030 A K
+ PARAMS:
+ ESRC=0.146250HMS ;RESIST. IN SERIES WITH NON-LIN CAPACITOR
+ ESL=6.0061NH ;EQ. SERIES INDUCTANCE.
+ VDON=506.9MV ;DIODE FORWARD DROP
+ RON=89.655MOHMS ;ON SERIES RESISTANCE
+ CJO=548.3115PF
+ VJ=0.78062V
+ M=0.44631
+ FS=30MEG ;OPOERATING FREQUENCY
+ VCCAP=100V ;VOLTAGE AT WHICH DEVICE CAP. REMAINS CONSTANT
+ FC=0.5 ;forward-bias depletion capacitance coefficient
*PARASITIC LEAD INDUCTANCE

LLEAD A 101 {ESL} IC=O
*IDEAL DIODE MODEL

DIDEAL 101 102 DIDEAL
.MODEL DIDEAL D(N=0.001)
*FORWARD VOLTAGE DROP MODEL

VDON 102 103 {VDON}
RON 103 K {RON}
*NONLINEAR CAPACITANCE EVALUATED AS A CONTROLLED CURRENT
*SOURCE
RC 101 104 {ESRC}
GCNL K 104 VALUE={
+IF((V(K)-V(104))<=(-FC*VJ),V(201)*(1/LDER)*(CJO*((1-FC)**(-(1+M)))*(1-(FC*(1+M))
+-((M/VJ)*(V(K)-V(104))))),
+IF((V(K)-V(104))< (VCCAP),V(201)*(1/LDER)*(CJO/((1+((V(K)-V(104))/VJ))**M)),
+V(201)*(1/LDER)*(CJO/((I+((VCCAP)/VJ))**M))))}
****SUBCIRCUIT TO EVALUATE THE DERIVATIVE***
*PARAMETERS AND DEFINITION FOR THIS SUBCIRCUIT
- 194 -
.PARAM:
+ LDER=IU ;INDUCT FOR THE DERIVATIVE SUBCIRCUIT
+ PI=3.14159265
*FUNC. FOR R OF THE DERIVATIVE SUBCIRCUIT
.FUNC RDER(LDER,FS) {3000*2*PI*FS*LDER}
GY 0 201 VALUE={V(K)-V(104)}
Li 201 0 {LDER}
Ri 201 0 {RDER(LDER,FS)}
.ENDS CSDIO030
MODEL: 2WTRFCLQCH
APPLICATION: 2 WINDING TRANSFORMER CANTELIVER MODEL
THE 2 WINDING ARE UNCOMMITED
+ PRIMARY TURNS = i
+ MODELS QUALITY FACTORS OF THE WINDINGS
+ ALSO MODEL THE DC RESISTANCE
* PARAMETERS:
+N2 = SECOND WINDING
+RDCP = DC RESISTANCE PRIMARY
+RDCS = DC RESISTANCE SECONDARY
+LM = MAGNETIZING INDUCTANCE (PRIMARY)
+QP = Q OF THE PRIMARY
+LL2 = LEAKAGE IN THE SECONDARY
+Q02 = Q OF THE SECONDARY (LL2+(LM*(N2**2)))
+FQ = FREQUENCY AT WHICH Q IS MEASURED
+IC = INITIAL CONDITIONS
* Nodes:
+PID = PRIMARY ONE DOTTED TERMINAL
+PIND = PRIMARY ONE NON-DOTTED TERMINAL
+SID = SECONDARY ONE DOTTED TERMINAL
+SIND = SECONDARY ONE NON-DOTTED TERMINAL
* MODEL HISTORY:
* 02/28/2006 MODEL DEVELOPED
* 03/04/2006 WINDINGS Q'S AND DC RESISTANCE
- 195 -
PSPICE files
.SUBCKT 2WTRFCLQCH PiD PIND SiD SiND

+ PARAMS:
+ N2 = 1
+ RDCP=IM
+ RDCS=IM
+ LM= 1OM
+ QP= 300 ;PRIMARY Q
+ LL2= IN
+ QS= 300
+ FQ = 100MEG
+ IC = 0
*RELATIONS FOR CANTELIVER VOLTAGE RELATIONS
.PARAM:
+ PI=3.14159265
+ OMEGA_0={2*PI*FQ/100}
*FUNCTIONS TO CALCULATE ESR
*CANTELIVER CIRCUIT DESCRIPTION
*---PRIMARY DESCRIPTION
RDCP PID Pi {RDCP} ;PRIMARY DC RESISTANCE
RACP Pi P2 {ESR(LM,QP,FQ)-RDCP}
LBPP Pi P2 {(ESR(LM.OP.FO)-R DCP)/0MEGA 0} TIC=ITC
L11 P2 PIND {LM} IC={IC} ;MAGNETIZING INDUCTANCE
Gil PIND P2 VALUE={(N2*I(ET2))} ;DEPENDANT CURRENT SOURCE
*---SECONDARY DESCRIPTION
ET2 Si SIND VALUE={(N2*V(P2,PIND))}
L02 Si S2 {LL2} IC={IC}
RACS S2 S3 {ESR((((N2*N2*LM)+LL2)),QS,FQ)-RDCS}
LBPS S2 S3 {(ESR((((N2*N2*LM)+LL2)),QS,FQ)-RDCS)/OMEGAO} IC={IC}
RDCS S3 SID {RDCS}
.ENDS 2WTRFCL_QCH
- 196 -
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Radio Frequency dc-dc Power Conversion

Submitted to the Department of Electrical Engineering and Computer Science

MASSACHUSETTS INSTITUTE OF TECHNOLOGY

@ Massachusetts Institute of Technology, MMVI. All rights reserved.

S epartment of Electrical Engineering and Computer Science

APR 3 0 2007 ARCHIVES

Submitted to the Department of Electrical Engineering and Computer Science

Thesis Supervisor: David J. Perreault

Reflection on the engineering practice:

"It is a great profession. There is the fascination of watching a

2 New Architectures for VHF Power Conversion 29

3 Design Considerations for VHF dc-dc Converters 57

4 An Advanced Resonant Inverter Topology 81

4.5.1.3 Implementation of the Gate Drive . ........ . . 100

5 A 'P2 Dc-Dc Converter 109

5.4.2 %2 Inverter Design .................... . .. . . . .. 116

5.6 Experimental Performance of the (2 dc-dc Converter ..... . . . . . . . . 130

6 Summary and Conclusions 133

A Low Order Lumped Network derivation 137

B 100 MHz dc-dc converter PCB layout 141

C Trapezoidal gate-drive PCB layout 147

D Trapezoidal start-up PCB layout 153

E (2 Inverter PCB layout 157

F 52 Dc-Dc Converter PCB layout 165

G PSPICE files 175

2.1 A block diagram illustrating the Vernier-regulated converter architecture. . 30

2.14 Attenuated drain-source voltage during turn-on and turn-off transients. In

4.16 Gate drive circuit schematic. In this prototype, RG,DC=10 kM LG,DC=568 nH

A.1 Simple low-order lumped network . . . . . . . . . . . .. . . . . . . . . . . 137

B.1 100 MHz dc-dc PCB Schematic. ........................ 141

C.1 Trapezoidal gate-drive PCB SchemaLtic. ................... .. 147

D.1 Start-up PCB Schematic. ............................ 153

E.1 Inverter PCB Schematic. ............................ 157

F.1 Dc-Dc Converter PCB Schematic. . . . . . . . . . . . . . . . . . . . . 165

2.1 Component values in the unregulated cell. . ................... 40

3.1 Equivalent impedance of the rectifier of Fig. 3.11. . ............... 71

1.1 Challenges of High-Frequency Power Converter Design

Modern applications demand power converters capable of maintaining voltage regulation

1.2 Radio-Frequency Power Amplifiers

Switched-mode rf amplifiers (inverters) utilize resonant circuit operation to achieve ZVS

1.3 Thesis Objectives and Contributions

1.4 Organization of the Thesis

New Architectures for VHF Power

2.1 New Converter Architectures

As described in Chapter 1, conventional power converter designs are subject to a number

2.1.1 Vernier-Regulated Architecture

The Vernier-regulated cellular architecture (VRCA) is a type of cellular power converter. As

Figure 2.1: A block diagram illustrating the Vernier-regulated converter architecture.

Operation of the proposed architecture is as follows: The regulating cell is controlled to

Load on Regulating Cell

Regulating Multiple Output

......... I --I ...-

2.1.2 Cell-Modulation-Regulated Architecture

Figure 2.4: A block diagram illustrating the cell-modulation-regulated converter architec-

The cell-modulation-regulated architecture exhibits a number of the advantages of the pre-

2.1.3 Related Architectures

2.2 100 MHz Unregulated Cell Design

2.2.1 Class E Resonant Inverter

Figure 2.5: A simplified model of the Class-E resonant inverter.

2.2.2 Self-Oscillating Gate Driver

A low-cost, efficient method of selectively driving the inverter is of great importance to

2.2.2.1 Phase shift/feedback network

Figure 2.7: Simplified phase shift/feedback network.