Strunz R, Toal D, McGowan C.

A SOFTWARE / HARDWARE DIGITAL BASED FUNCTIONAL

IC TESTER

R. Strunz, D. Toal , C. Mc Gowan,

Department of Electronics,
University of Limerick,
Limerick , Ireland.

ABSTRACT

This paper describes the implementation of a low cost PC - based logic system suitable for either
small scale chip or printed circuit board testing. The system incorporates a flexible graphical user interface
(GUI) which permits users with little or no programming expertise to generate tests and operate the system
quickly and efficiently. System cost is of the order of £1,000 which makes it very attractive to SME's.

1 INTRODUCTION

In any manufacturing industry there are continuous efforts to effect cost reductions, upgrade quality
and improve overall efficiencies. In the electronics industry, with the dramatic increase in circuit complexity
and the need for higher levels of reliability, a major contributory cost of any product can be in the testing.
However, in the real world we have to recognise that no process can be perfect, so that testing, and in
particular, automatic testing, will be an essential part of production for the foreseeable future.
In this paper the development of a prototype digital functional IC tester is described. The test system
has been designed so that the end user has total control over how testing of IC's is to be carried out. The
end user will have the ability to change or redefine pin connections of any IC within the data bank, alter test
vectors previously defined, specify the master clock period, carry out simulated testing, check the contents
of the data base and obtain information on the PC 8255 I/O Card set-up.
The test system has been developed to allow for a more detailed examination of how IC's operate for
particular functional tests. To date all test systems on the market (except for extremely expensive ATE)
only inform the end user whether the device under test (DUT) has passed or failed their own predefined
test. This gap in the market has called for this prototype tester.
One objective of improved test equipment would be an increase in throughput by providing a better
test. However this prototype test system has not been designed to carry out exhaustive tests. The
application of 2n test vectors to a device with n inputs is effective if n was small. However because the
number of tests, 2n , grows exponentially with n, the number of tests required increases rapidly. For n
inputs the truth table contains 2n lines; if we work through the table at 1 test/µs, this would take 18 min
for n = 30, 13 days for n = 40 , & 36 years for n = 50. Quiet obviously this method of exhaustive testing is
unacceptable for end of line testing. An alternative approach is based on the observation that ,' in a device,
any particular input test vector will usually cover a significant number of faults' ref[1]. Any random
selection of tests of reasonable size, therefore can be expected to achieve reasonable fault coverage.
Strunz R, Toal D, McGowan C.

R.D Eldner ref[2] advocated creating specific tests for faults most likely to occur . This method has become
the standard approach to developing tests for digital logic IC's.
An analysis of statistical methods that estimate the quality of a test set based on probabilities of
detecting faults with random vectors is beyond the scope of this paper. For further information relating to
this area refer to Abramovici et al, ref[3].

1.1 Test System Overview

Tester circuitry

DUT

Fig. 1 Test System Topology

The test system is based around a low cost personal computer. It is user friendly and quick in
operation. The tester system is interfaced to the PC using an 8255 I/O Card. The entire operation of the
system is controlled by an IBM compatible computer, which also has the task of collecting and evaluating
the test results. The test system is concerned with logic testing of devices. Testing of digital logic involves
the application of stimuli to a device under test and evaluation of the response to determine whether the
device is functioning correctly. In this paper these stimuli are referred to as test vectors. The test system
topology is shown in Fig .1. The tester hardware and software are described in part 3.
Electrical/Electronic testing breaks down into a large number of areas :- full functional testing,
accelerated life testing, in process testing, etc. The tester described here falls into the in-process testing
category. It is designed to be used in-line on the production process. It may find applications in areas such
as testing of IC's after IC fabrication or after the encapsulation process of the IC's. Alternatively the test
system can be used for goods inwards testing of device just received from a supplier. Finally the test
system has the possibility of being used for testing digital based circuit boards

2 OPERATION OF TESTER

The operation of the digital functional IC tester can be subdivded into two modes of operation. These
are the learn and test mode, each of which will be individually described.

2.1 Learn Mode

In the learn mode the user is allowed to add to the existing data base the characteristics relating to a
new IC. This learning process can be broken down into four individual stages.
Strunz R, Toal D, McGowan C.

Stage 1: The user defines the name, series name and IC pin count for the new IC as seen in Fig .2.

Fig 2. Device Description Screen.

Stage 2:- The user is presented with a window containing a menu box and a IC drawing. The menu
box contains nine options. Each option may be individually used to define connections to pins of the new
IC as seen in Fig .3. Having finished specifying the IC's configuration the option of making changes is
available to the user.

Fig .3. IC Pin-Out Definition Screen.

Stage 3:- All switching of test vectors takes place in synchronisation with a master clock. The
clock period and number of clock cycles are defined during this stage.
Strunz R, Toal D, McGowan C.

Stage 4:- The specification of test vectors to be applied to the DUT take place during this next stage.
The user is presented with a graphic screen as shown in Fig .4. Specification of test vectors for either input,
output , clock or input/output pins are defined for pins of the new IC if such pins exist. It is important to
note that only 25 clock cycles of the master may be displayed on the screen at any one time (as shown on
Fig .4.). For this reason a 'page-on & page-back' option has been included in this graphic's section of the
package. It essentially allows the end user to page through the master clock cycles in windows of 25 (clock
cycles), hence generating a scrolling effect. In addition a 'page-up & page-down' facility is also available to
the end user. It allows the package to scroll vertically up or down if more than 12 pins are defined to be of
the same type for a particular device. The user also has to his or her availability an edit option. This option
gives the user the freedom to highlight a pulse stream and either copy or cut the highlighted section.This
action means that the end user can also paste the pulse stream somewhere else as desired at some later
stage.
Finally, once all test vectors have been defined for this new IC the user is given the option of either
saving or discarding the IC characteristics.

Fig .4. Test Vector Input Screen.

2.2 Test Mode

Permission will only be granted to enter the test mode if a file relating to the IC to be tested exists
within the main data bank. Assuming a file does exist for the IC to be tested, then the data relating to this
IC is retrieved from the data bank. After the user has clamped the device under test in place, the software
will automatically instruct the circuitry to power up the DUT. The 8253 (timer tick) is reprogrammed to
enable switching of test vectors to take place in synchronisation with the master clock. This all takes place
during the installation of the interrupt service routine (covered in section 3).
During each clock period the circuitry will present to the DUT the appropriate test vectors previously
defined for each pin that relates to the particular clock period in question. The response to these test
vectors are read from the DUT and are compared to the ideal responses expected for the applied input test
vectors (which will have been specified, during stage 4 above, as expected output vectors). If the response
for the input test vectors are not correct, then the pin number and clock period at which the error was
Strunz R, Toal D, McGowan C.

encountered is noted. The next test vectors are applied to the DUT and so on, until all test vectors have
been applied.
Finally the results for the DUT are displayed on screen. The package will point out which pins were
in error and over which clock periods these errors occurred. Otherwise, if the IC meets or passes the
functional test a success message is displayed on the screen as shown in Fig .5.. (A more detailed look at
the individual elements of the tester circuitry is covered in section 4)

Fig .5. Test Results Display Screen.

3 MASTER CLOCK GENERATION

It is necessary to carry out switching of test vectors to the DUT in synchronisation with a high
resolution master cycle. The C - Programming language however, only allows time delays in the order of
1ms which causes great problems when timing is of crucial importance. The only other alternative in
achieving a master clock which could operate in conjunction with both the IC Tester's software & hardware
whilst still maintaining a high degree of accuracy, was to reprogram the PC's own system clock.
Unfortunately reprogramming the PC's clock is made difficult by the lack of information currently available
and by the fact that Microsoft & IBM have not published many of the details concerning the
reprogramming of system support chips.
Strunz R, Toal D, McGowan C.

Reprogramming of the PC's system clock was accomplished through the development of an Interrupt
Service Routine (ISR). The ISR requires that the PC's 8259 Programmable Interrupt Controller (PIC) and
the 8253 Programmable Interval Timer (timer tick) be reset to the particular users needs.

Main Program

Display test GUI

Screen
Interrupt vector
Power up DUT Table
Save orignal timer
tick Handler (08H) Get address
Interrupt vector
stage 1 Initialise ISR Re-route interrupt Table
vector to new ISR
Handler 08H Store address

stage 2 Mask 8259 reset interrupt sources

stage 3 Reprogram reset register for .1ms tick interval

8253

stage 4 Start timer New ISR for the timer tick on IRQ 0
stage 5. - Disable Interrupts
Test DUT & - Save registers and flag contents
use ISR for high resol. - Increment interrupt count
timing requirements
IRQ 0 - Check if system time or date need
incrementing
no IC every .1ms - Signal IRET.
test finished - Enable interrupts
?
yes stage 6.
Reset timer system clock reset to 18.2 ticks per second

stage 7.
Reset old 08H system will crash if not done
Handler for ISR

Display results

return to main
program

Fig .6. ISR Flow Diagram.

Initially when the PC is powered up , the BIOS configures the 8259 internally to correspond to it's
physical connections on the PC system board . In order to reprogram the timer tick (i.e. the PC system
clock) it is required that the 8259 must first have its interrupt request lines masked. Once this is
accomplished the timer tick can be reprogrammed with the requested number of clock ticks per sec.
Strunz R, Toal D, McGowan C.

Masking and reprogramming of the system support chip is done straight after the ISR is installed and must
be reset once the program terminates.
The ISR is responsible for ensuring that the PC 's systems time and date are not effected in any way
by the reprogramming of the 8253 clock. At present the ISR allows for timing delays in the order of 0.1ms
but may be reprogrammed to give even smaller time delays. Fig.6. shows a general flow diagram of the ISR
implementation.

4 HARDWARE AND SOFTWARE

In this section the tester hardware and software is explained. However a brief look at the hardware /
software interface is first given.

4.1 Hardware/Software Interface

An 8255 I/O Card has been used to provide an interface between the PC (which is IBM Compatible)
and the digital IC functional tester. The 8255 I/O Card is a programmable peripheral interface device,
designed for use in computer systems. It's function is that of a general purpose I/O component to interface
peripheral equipment to the micro computer system bus. The functional configuration of the 8255 I/O Card
are programmed by the system software so that normally no external logic is necessary to interface
peripheral devices or structures. The 8255 I/O Card contains three 8-bit ports which can be configured for
a wide variety of functional characteristics by the system software. Each port has its own special features
or 'personality' to further enhance the power and flexibility of the card.

CURRENT AUTO POWER POWER

FOLD BACK CONNECTION DISPLAY
PROTECTION CIRCUITRY UNIT
CIRCUITRY
VDU LOGIC 1
SWITCHING
8255 MATRIX
IMB SAMPLING
PC I/O DUT
CIRCUITRY
CARD LOGIC 0
SWITCHING
MATRIX

POWER UP RESET GROUND PIN

CIRCUITRY CONNECTION
MATRIX

Fig .7. Hardware block diagram

Strunz R, Toal D, McGowan C.

4.2 Digital Switching Matrices

The digital switching matrix is composed of serial to parallel 8-bit shift registers, D-type latches,
buffers and Analog Device's 7511 dielectrically isolated analogue CMOS switches. The 7511 switches are
TTL controlled CMOS switches with a maximum voltage rating of 25V. Each individual matrix has been
designed to be seen as a single entity. The matrices serve the sole purpose of connecting pins of the DUT
(device under test) to either logic 1, logic 0 or ground. The maximum 'on' resistance of the CMOS
switches is 75Ω. There is a question as to what is the maximum 'on' resistance that can be tolerated
between a TTL pin and ground so that the IC continues to operate as specified.
When any input pin of a digital IC is grounded about 1.6ma of current has to flow through the
ground lead. If an attempt is made to ground the input through a resistance (i.e. such as the 75Ω on
resistance of the CMOS switch) there will be a voltage drop across the switch resistance, and the emitter
will not be pulled close enough to ground to let the gate operate reliably. The maximum permissible low
state input voltage is 0 - 0.8volts. At any input above that the gate will either lose noise immunity or stay in
it's active region and possibly oscillate.
Thus, any resistance connected to ground should be less than 500Ω ref [4]. Therefore it can be seen
that the Analog Devices 7511 dielectrically isolated analogue CMOS switches are more than adequate for
the application intended.

4.3 Power Up Reset Circuitry

When the tester circuitry is initially powered up, all D-type flip flops & shift registers are reset to a
known state. This is to avoid false connections being made to the zero force insertion socket where the
DUT is to be inserted. A reset time constant of 2ms has been selected as the power up reset time. This reset
interval is controlled via a resistor capacitor combination. The voltage developed across the capacitor (Vc)
is connected to the input of a Nand gate and after 2ms has elapsed Vc will have reached the TTL switching
threshold. This causes the Nand gates output to switch state which has the effect of triggering the reset
circuitry. As a result of this, further resetting of the tester circuitry is now carried out under software
control.

4.4 Device Auto Power Supply Connection Circuitry

Before testing of a device may commence it must be powered up. The auto power supply connection
circuitry is responsible for making a supply voltage connection to the power pins of the DUT. The supply
voltage automatically connected to these pins can be either +5v,+15v or -15v, depending on the DUT
requirements. Opto isolators have been used to connect supply voltages to power pins of the DUT as
analog CMOS switches have low current handling capabilities(typically 20ma). This current limitation
increases their chance of being damaged when all output gates of the DUT are operating at their maximum
allowable fan out.
Strunz R, Toal D, McGowan C.

4.5 Short Circuit Protection Circuitry

Logic 1 connections to different pins of the DUT are liable to become short circuited to ground if the
DUT is faulty. This short circuit possibility would cause a substantial current to be drawn through the
analog CMOS switches which have a maximum current capability of 20ma. If the maximum current rating
is exceeded the tester circuitry will become damaged. As a result of this possibility some form of short
circuit protection must be implemented. Foldback protection is a method of protecting against damage
caused by excessive current and has been include in the tester circuitry to overcome the problem.The
foldback characteristics of Fig .8. shows how the current is reduced as the voltage drops to zero because of
a short circuit.

Limit Limit
V V

I I
(a)
(b)
Protection system. A simple protection system behaves as shown in (a), with
the current limited, but passing enough current to keep the dissipation high.
A foldback system (b) will reduce the amount of current to lower than the
maximum when a short circuit occurs.
Fig.8. Short Circuit Protection.

4.6 LED Power Supply Display Circuitry

It is possible to automatically power up the DUT. But Vdd(supply voltage) which may be either +5v
or +15v must be manually selected. As a result a LED display unit has been incorporated into the tester.
This enables the end user to clearly see what supply voltage will be connected to the DUT.

4.7 Sampling Circuitry

The sampling circuitry has been developed from a decoder unit and a number of analog switches. The
circuitry has been configured so that each output pin of the DUT may be sampled under software control as
requested. In addition input protection circuitry has been added to the 8255 input port . This is to avoid
Strunz R, Toal D, McGowan C.

problems if by chance a voltage greater than 7Volts was to make its way into the 8255 input port and
possibly damage it.

4.8 Software

The code for the package has been written in C and it provides the end user with a graphical based
windows interface to the digital IC functional tester. The software has been broken up into 73 individual C
files, all of which are linked together at run time via a project file and linker. The software is responsible for
the entire circuitry control and operation and communicates with the hardware via the 8255 I/O Card. Test
vectors and IC characteristics for each individual device are stored in separate files within a data bank on
the hard disk.
The package allows for re-editing of individual features of any device currently stored within the
data bank. This includes making changes or alterations to an IC's configuration, deleting or changing test
vectors previously specified for the device, or alternatively deleting an IC completely from the data bank.
In addition the software also allows the end user to view the devices currently stored within the data
bank, obtain information on the 8255 port setup and simulate the IC test which is carried out when the
hardware is not connected.

5 CONCLUSIONS

A low cost digital IC test system developed at the University of Limerick has been described. The
system uses an IBM-PC (or IBM compatible) connection via a programmable peripheral interface to a
dedicated test system and could be implemented for less than £1000.
The test system has been designed to enable people with little or no programming experience to
generate tests and operate the system quickly and efficiently. The inclusion of a modification option in the
package allows for test vectors previously defined for a device to be re-edited by the end user. This means
that once test vectors have been specified the end user will not be required to re-enter the same vectors
again if modifications are required to the test patterns.
The flexibility and ease of implementation offered by this approach makes it very attractive,
particularly for smaller manufacturers operating under tight budget constraints.

REFERENCES

[1] B.R.Wilkins, Testing Digital Circuits, Van Nostrand Renihold(UK) Co.Ltd 1986.
ISBN 0-442-31748-4. (Random testing pg 166 ).

[2] Alexander Miczo, Digital Logic Testing And Simulation, John Wiley & Sons, USA, 1986.
ISBN 0-471-60365-1. (Approaches to testing pg15).
Strunz R, Toal D, McGowan C.

[3] Abramovici.M et al, Digital System Testing And Testable Design, AT&T Bell Laboratories &
Freeman + Company, USA, 1990. ISBN 0-7167-8179-4.

[4] Lancaster D, TTL Cookbook, Sam's & Mac Millan Inc., UK, 1990.