Lakshmi Narain College of Technology &

Science, Bhopal

Department of
Electronics and Communication Engineering

VLSI CIRCUITS AND SYSTEMS

(EC-6004)
Lab Report
For III Year VI Sem ECE
0157EC161039

Prepared By Guided By
Mr. Gaurav Singh Dr. Bhanu Pratap Singh

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 XILINX ISE OVERVIEW
The Integrated Software Environment (ISE™) is the Xilinx® design software suite that allows you to take
your design from design entry through Xilinx device programming. The ISE Project Navigator manages and
processes your design through the following steps in the ISE design flow.

Design Entry: -

Design entry is the first step in the ISE design flow. During design entry, you create your source files based
on your design objectives. You can create your top-level design file using a Hardware Description Language
(HDL), such as VHDL, Verilog, or ABEL, or using a schematic. You can use multiple formats for the lower-level
source files in your design.

Note: If you are working with a synthesized EDIF or NGC/NGO file, you can skip design entry and synthesis and
start with the implementation process.

Synthesis: -

After design entry and optional simulation, you run synthesis. During this step, VHDL, Verilog, or mixed
language designs become netlist files that are accepted as input to the implementation step.

Implementation: -

After synthesis, you run design implementation, which converts the logical design into a physical file format
that can be downloaded to the selected target device. From Project Navigator, you can run the implementation
process in one step, or you can run each of the implementation processes separately. Implementation processes
vary depending on whether you are targeting a Field programmable Gate Array (FPGA) or a Complex
programmable Logic Device (CPLD).

Verification: -

You can verify the functionality of your design at several points in the design flow. You can use simulator
software to verify the functionality and timing of your design or a portion of your design. The simulator interprets
VHDL or Verilog code into circuit functionality and displays logical results of the described HDL to determine
correct circuit operation. Simulation allows you to create and verify complex functions in a relatively small
amount of time. You can also run in-circuit verification after programming your device.

Device Configuration: -
After generating a programming file, you configure your device. During configuration, you generate
configuration files and download the programming files from a host computer to a Xilinx device.

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ISE 8.1i Quick Start Tutorial

The ISE 8.1i Quick Start Tutorial provides Xilinx PLD designers with a quick overview of
the basic design process using ISE 8.1i. After you have completed the tutorial, you will understand how to create,
verify, and implement a design.

Note: This tutorial is designed for ISE 8.1i on Windows.

 This tutorial contains the following sections:

• “Getting Started”

• “Create a New Project”

• “Create an HDL Source”

• “Design Simulation”

• “Create Timing Constraints”

• “Implement Design and Verify Constraints”

• “Reimplement Design and Verify Pin Locations”

• “Download Design to the SpartanTM-3 Demo Board”

.
Create a New Project: -
Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit
demo board.

To create a new project:

1. Select File > New Project... The New Project Wizard appears.

2. Type tutorial in the Project Name field.

3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created
automatically.

4. Verify that HDL is selected from the Top-Level Source Type list.

5. Click Next to move to the device properties page.

6. Fill in the properties in the table as shown below:

• Product Category: All

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 • Family: Spartan3

• Device: XC3S200

• Package: FT256

• Speed Grade: -4

• Top-Level Module Type: HDL

• Synthesis Tool: XST (VHDL/Verilog)

• Simulator: ISE Simulator (VHDL/Verilog)

• Verify that Enable Enhanced Design Summary is selected.

• Leave the default values in the remaining fields.

7. Click Next to proceed to the Create New Source window in the New Project Wizard. At
the end of the next section, your new project will be complete.

Create an HDL Source: -

In this section, you will create the top-level HDL file for your design. Determine the language that you
wish to use for the tutorial. Then, continue either to the “Creating a VHDL Source” section below, or skip to the
“Creating a Verilog Source” section.

Creating a VHDL Source: -

Create a VHDL source file for the project as follows:
1. Click the New Source button in the New Project Wizard.
2. Select VHDL Module as the source type.
3. Type in the file name counter.
4. Verify that the Add to project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information.
 Click Next, then Finish in the New Source Information dialog box to complete the new source file template.
 Click Next, then Next, then Finish.

The source file containing the entity/architecture pair displays in the Workspace, and the counter displays
in the Sources tab.

Checking the Syntax of the New Counter Module: -

When the source files are complete, check the syntax of the design to find errors and typos.

1. Verify that Synthesis/Implementation is selected from the drop-down list in the Sources window.

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2. Select the counter design source in the Sources window to display the related processes in the Processes
window.

3. Click the “+” next to the Synthesize-XST process to expand the process group.

4. Double-click the Check Syntax process.

Note: You must correct any errors found in your source files. You can check for errors in the Console tab of the
Transcript window. If you continue without valid syntax, you will not be able to simulate or synthesize your
design.
5. Close the HDL file.

Design Simulation: -
Verifying Functionality using Behavioral Simulation: -
Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter
module. The test bench waveform is a graphical view of a test bench.

Create the test bench waveform as follows:

1. Select the counter HDL file in the Sources window.

2. Create a new test bench source by selecting Project →New Source.

3. In the New Source Wizard, select Test Bench waveform as the source type, and type
counter_tbw in the File Name field.

4. Click Next.

5. The Associated Source page shows that you are associating the test bench waveform
with the source file counter. Click Next.

6. The Summary page shows that the source will be added to the project, and it displays
the source directory, type and name. Click Finish.

7. You need to set the clock frequency, setup time and output delay times in the Initialize
Timing dialog box before the test bench waveform editing window opens.

The requirements for this design are the following:

 The counter must operate correctly with an input clock frequency = 25 MHz.

 The DIRECTION input will be valid 10 ns before the rising edge of CLOCK.

 The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK.

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  The design requirements correspond with the values below.

Fill in the fields in the Initialize Timing dialog box with the following information:

 Clock Time High: 20 ns.

 Clock Time Low: 20 ns.

 Input Setup Time: 10 ns.

 Output Valid Delay: 10 ns.

 Offset: 0 ns.

 Global Signals: GSR (FPGA)

 Initial Length of Test Bench: 1500 ns.

Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically.
Leave the default values in the remaining fields
8. Click Finish to complete the timing initialization.

9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the Input Setup Time in the
Initialize Timing dialog box. Toggle the DIRECTION port to define the input stimulus for the counter design as
follows:

 Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the counter will
count up.

 Click on the blue cell at approximately the 900 ns to assert DIRECTION high so that the counter will
count down.

10. Save the waveform. In the Sources window, select the Behavioral Simulation view to see that the test bench
waveform file is automatically added to your project.

11. Close the test bench waveform.

Simulating Design Functionality: -

Verify that the counter design functions as you expect by performing behavior simulation as follows:
1. Verify that Behavioral Simulation and counter_tbw are selected in the Sources window.

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2. In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process and double-click the Simulate
Behavioral Model process.
3. The ISE Simulator opens and runs the simulation to the end of the test bench.
4. To view your simulation results, select the Simulation tab and zoom in on the transitions.
5. Verify that the counter is counting up and down as expected.
6. Close the simulation view. If you are prompted with the following message, “You have
an active simulation open. Are you sure you want to close it? “, click Yes to continue.

Implement Design and Verify Constraints

Implement the design and verify that it meets the timing constraints specified in the
previous section.

Implementing the Design

1. Select the counter source file in the Sources window.

2. Open the Design Summary by double-clicking the View Design Summary process in the Processes tab.
3. Double-click the Implement Design process in the Processes tab.
4. Notice that after Implementation is complete, the Implementation processes have a green check mark next to
them indicating that they completed successfully without Errors or Warnings.
5. Locate the Performance Summary table near the bottom of the Design Summary.
6. Click the All Constraints Met link in the Timing Constraints field to view the Timing Constraints report. Verify
that the design meets the specified timing requirements.
7. Close the Design Summary.

Assigning Pin Location Constraints

Specify the pin locations for the ports of the design so that they are connected correctly on the Spartan-3
Startup Kit demo board.

To constrain the design ports to package pins, do the following:

1. Verify that counter is selected in the Sources window.

2. Double-click the Assign Package Pins process found in the User Constraints process group. The Xilinx Pinout
and Area Constraints Editor (PACE) opens.

3. Select the Package View tab.

4. In the Design Object List window, enter a pin location for each pin in the Loc column using the following
information:

 CLOCK input port connects to FPGA pin T9 (GCK0 signal on board)

 COUNT_OUT<0> output port connects to FPGA pin K12 (LD0 signal on board)

 COUNT_OUT<1> output port connects to FPGA pin P14 (LD1 signal on board)

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  COUNT_OUT<2> output port connects to FPGA pin L12 (LD2 signal on board)

 COUNT_OUT<3> output port connects to FPGA pin N14 (LD3 signal on board)

 DIRECTION input port connects to FPGA pin K13 (SW7 signal on board)

5. Select File →Save. You are prompted to select the bus delimiter type based on the synthesis tool you are using.
Select XST Default <> and click OK.

6. Close PACE.

Notice that the Implement Design processes have an orange question mark next to them,
indicating they are out-of-date with one or more of the design files. This is because the UCF
file has been modified.

Download Design to the SpartanTM-3 Demo Board

This is the last step in the design verification process. This section provides simple instructions for downloading
the counter design to the Spartan-3 board.

1. Connect the 5V DC power cable to the power input on the demo board (J4).

2. Connect the download cable between the PC and Spartan-3 board (J7).

3. Select Synthesis/Implementation from the drop-down list in the Sources window.

4. Select counter in the Sources window.

5. In the Processes window, click the “+” sign to expand the Generate Programming File processes.

6. Double-click the Configure Device (iMPACT) process.

7. In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG).

8. Verify that Automatically connect to a cable and identify Boundary-Scan chain is

selected.

9. Click Finish.

10. If you get a message saying that there are two devices found, click OK to continue. The devices connected to
the JTAG chain on the board will be detected and displayed in the impact window.

11. The Assign New Configuration File dialog box appears. To assign a configuration file to the xc3s200 device
in the JTAG chain, select the counter.bit file and click Open.

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12. If you get a Warning message, click OK.

13. Select Bypass to skip any remaining devices.

14. Right-click on the xc3s200 device image, and select PROGRAM... The programming
Properties dialog box opens.

15. Click OK to PROGRAM the device.

 When Programming is complete, the PROGRAM Succeeded message is displayed.

 On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running.

16. Close impact without saving.

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 VERILOG PROGRAMMING
LANGUAGE

1. INTRODUCTION
The complexity of hardware design has grown exponentially in the last decade. The exponential growth is fueled
by new advances in design technology as well as the advances in fabrication technology. The usage of Hardware
Description Language (HDL) to model, simulate, synthesize, analyze, and test the design has been a cornerstone
of this rapid development. Verilog HDL is a Hardware Description Language. A Hardware Description Language
is a language used to describe a digital system: for example, a network switches, a microprocessor or a memory
or a simple flip-flop. HDL allows the design to be simulated earlier in the design cycle in order to correct errors
or experiment with different architectures. Designs described in HDL are technology-independent, easy to design
and debug, and are usually more readable than schematics, particularly for large circuits. One may describe a
digital system at several levels. For example, an HDL might describe the layout of the wires, resistors and
transistors on an Integrated Circuit (IC) chip, i.e., the switch level. Or, it might describe the logical gates and
flip flops in a digital system, i.e., the gate level. An even higher level describes the registers and the transfers of
vectors of information between registers. This is called the Register Transfer Level (RTL). Verilog supports all
of these levels.

1.1 WHAT IS VERILOG?

Verilog is one of the two major Hardware Description Languages (HDL) used by hardware designers in industry
and academia. VHDL is the other one. The industry is currently split on which is better. Many feel that Verilog
is easier to learn. Verilog is very C-like and liked by electrical and computer engineers as most learn the C
language in college. VHDL is very Ada-like and most engineers have no experience with Ada.

Verilog was introduced in 1985 by Gateway Design System Corporation, now a part of Cadence Design Systems.
Until May, 1990, with the formation of Open Verilog International (OVI), Verilog HDL was a proprietary
language of Cadence. Cadence was motivated to open the language to the Public Domain with the expectation
that the market for Verilog HDL-related software products would grow more rapidly with broader acceptance of
the language.

Verilog HDL allows a hardware designer to describe designs at a high level of abstraction such as at the
architectural or behavioral level as well as the lower implementation levels (i.e., gate and switch levels) leading
to Very Large-Scale Integration (VLSI) Integrated Circuits (IC) layouts and chip fabrication. A primary use of
HDLs is the simulation of designs before the designer must commit to fabrication.

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1.2 WHY USE VERILOG HDL?

Digital systems are highly complex. At their most detailed level, they may consist of millions of elements, i.e.,
transistors or logic gates. Therefore, for large digital systems, gate-level design is dead. For many decades, logic
schematics served as the bridge language of logic design, but not anymore. Today, hardware complexity has
grown to such a degree that a schematic with logic gates is almost useless as it shows only a web of connectivity
and not the functionality of design.
Since the 1970s, Computer engineers and electrical engineers have moved toward hardware description languages
(HDLs). The most prominent modern HDLs in industry are Verilog and VHDL. Verilog is the top HDL used by
over 10,000 designers at such hardware vendors as Sun Microsystems, Apple Computer and Motorola. The
Verilog language provides the digital designer with a means of describing a digital system at a wide range of
levels of abstraction and at the same time provides access to computer-aided design tools to aid in the design
process at these levels. Verilog allows hardware designers to express their design with behavioral constructs,
deterring the details of implementation to a later stage of design. An abstract representation helps the designer
explore architectural alternatives through simulations and to detect design bottlenecks before detailed design
begins. Computer-aided-design tools, i.e., programs, exist which will “compile” programs in the Verilog notation
to the level of circuits consisting of logic gates and flip flops. One could then go to the lab and wire up the logical
circuits and have a functioning system. And, other tools can “compile” programs in Verilog notation to a
description of the integrated circuit masks for very large scale integration (VLSI). Verilog also allows the
designer to specific designs at the logical gate level using gate constructs and the transistor level using switch
constructs. Verilog allows engineers to optimize the logical circuits and VLSI layouts to maximize speed and
minimize area of the VLSI chip.

1.3 HIERARCHICAL MODELING CONCEPTS

Before we discuss the details of the Verilog language, we must first understand basic hierarchical modeling
concepts in digital design.

Design Methodologies

There are two basic types of digital design methodologies: a top-down design methodology and a bottom-up
design methodology. In a top-down design methodology, we define the top-level block and identify the sub-
blocks necessary to build the top-level block. We further subdivide the sub-blocks until we come to leaf cells,
which are the cells that cannot further be divided. Figure 1-1 shows the top-down design process.

Figure 1-1. Top-down Design Methodology

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In a bottom-up design methodology, we first identify the building blocks that are available to us. We build bigger
cells, using these building blocks. These cells are then used for higher-level blocks until we build the top-level
block in the design.

Figure 1-2. Bottom-up Design Methodology

Typically, a combination of top-down and bottom-up flows is used. Design architects define the specifications of
the top-level block. Logic designers decide how the design should be structured by breaking up the functionality
into blocks and sub-blocks. At the same time, circuit designers are designing optimized circuits for leaf-level
cells. They build higher-level cells by using these leaf cells. The flow meets at an intermediate point where the
switch-level circuit designers have created a library of leaf cells by using switches, and the logic level designers
have designed from top-down until all modules are defined in terms of leaf cells.

List of Experiments
List of Experiments
Design and implementation of the following CMOS digital/analog circuits using Cadence/
Mentor Graphics/ Synopsys/ GEDA/Equivalent CAD tools. The design shall include Gate-level
design. Transistor –level design, Hierarchical design, Verilog HDL/VHDL design, Logic synthesis, Simulation
and verification, scaling of CMOS inverter for different technologies,
study of secondary effects (temperature, power supply and process corners), circuit optimization with respect to
area, performance and/or power, Layout Extraction of parasitic and back annotation, modifications in circuit
parameters and layout consumption, DC/ transient analysis, Verification of layours (DRC, LVS)

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E-C AD programs:
Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and
performance testing may be done using pattern generator (32 channels) and logic analyzer apart from
verification by simulation with any of the front-end tools.
1. HDL code to realize all the logic gates
2. Design of 2-to-4 decoder
3. Design of 8-to-3 encoder (without and with parity)
4. Design of 8-to-1 Multiplexer/ Demultiplexer

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1. Simulation using all the modeling styles and Synthesis of all the logic gates using Verilog HDL
Objective: Implement and verify the functionality of basic gates using Xilinx ISE
Scope:
a) To realize the logical operation of the basic gates using Verilog and implement the same on Xilinx
FPGA

Electronic Design Automation Tools and Apparatus required:

 Xilinx Spartan 3 FPGA

 Xilinx ISE Simulator tool
 Xilinx XST Synthesis tool
 Xilinx Project Navigator 8.1i
 JTAG cable
 Adaptor 5v/4A

Theory
Logic gates:
A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs and
one output. At any given moment, every terminal is in one of the two binary conditions low (0) or high (1),
represented by different voltage levels.
a) AND Gate: The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A
dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB

Boolean expression of AND gate is given as Y = (A· B)

AND gate - Truth Table
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

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Verilog program for AND gate:

module andg (A, B, Y);

input A, B;
output Y;
assign Y = A & B;
endmodule

Simulation Results:
Verilog test bench program for AND gate:
module andg_tb;
reg A, B;
wire Y;
andg andgate(.A(A), .B(B),.Y(Y));
initial begin
A =1'b0;B= 1'b0;
#10 A =1'b0;B= 1'b1;
#10 A =1'b1;B= 1'b0;
#10 A =1'b1;B= 1'b1;
#10
$finish;
end
always @(Y)
$display( "time =%0t \tINPUT VALUES: \t A=%b B =%b \t output value Y =%b",$time,A,B,Y);
endmodule
Wave Form:

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 b) OR Gate: The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are
high. A plus (+) is used to show the OR operation.

Boolean expression of OR gate is given as Y = (A+B)

OR gate - Truth Table
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

Verilog program for OR gate:

module org (A, B, Y);

input A, B;
output Y;
assign Y = A | B;
endmodule

Simulation Results:
Verilog test bench program for AND gate:
module org_tb;
reg A, B;
wire Y;
andg andgate(.A(A), .B(B),.Y(Y));
initial begin
A =1'b0;B= 1'b0;
#10 A =1'b0;B= 1'b1;
#10 A =1'b1;B= 1'b0;
#10 A =1'b1;B= 1'b1;
#10
$finish;
end
always @(Y)
$display( "time =%0t \tINPUT VALUES: \t A=%b B =%b \t output value Y =%b",$time,A,B,Y);
endmodule
Wave form:

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 c) NOT Gate: The NOT gate produces an inverted version of the input at its output. It is also known as
an inverter. If the input variable is A, the inverted output is known as NOT A. This is also shown as A',
or A with a bar over the top, as shown at the outputs.

Boolean expression of NOT gate is given as A = A’

NOT gate - Truth Table

A A’
0 1
1 0

Verilog program for NOT gate:

module not_g (A, B, Y);
input A;
output Y;
assign Y = ~ A ;
endmodule
Simulation Results:
Verilog testbench program for NOT gate:
module notg_tb;
reg A;
wire Y;
notg norgate(.A(A),.Y(Y));
initial begin
A =1'b0;
#10 A =1'b1;
#10
$finish;
end
always @(Y)
$display( "time =%0t \tINPUT VALUES: \t A=%b output value Y =%b",$time,A,Y);
endmodule
Wave Form:

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 d) NAND Gate: NAND gate is NOT-AND gate which is equal to an AND gate followed by a NOT gate.
The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a
small circle on the output. The small circle represents inversion.

Boolean expression of NAND gate is given as Y = (A·B)’

OR gate - Truth Table

A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Verilog program for NAND gate:
module nandg (A, B, Y);
input A, B;
output Y;
assign Y = ~(A & B);
endmodule

Simulation Results:
testbench program for nand gate:
module nandg_tb;
reg A, B;
wire Y;
nandg nandgate(.A(A), .B(B),.Y(Y));
initial begin
A =1'b0;B= 1'b0;
#10 A =1'b0;B= 1'b1;
#10 A =1'b1;B= 1'b0;
#10 A =1'b1;B= 1'b1;
#10 $finish;
end
always @(Y)
$display( "time =%0t \tINPUT VALUES: \t A=%b B =%b \t output value Y =%b", $time,A,B,Y);
endmodule
Wave Form:

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 e) NOR Gate: NOR gate is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The
outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small
circle on the output. The small circle represents inversion.

Boolean expression of NOR gate is given as Y = (A+B)’

NOR gate - Truth Table
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

Verilog program for NOR gate:

module norg (A, B, Y);
input A, B;
output Y;
assign Y = ~(A | B);
endmodule

Simulation Results:
Verilog teshbench program for NOR gate:
module norg_tb;
reg A, B;
wire Y;
norg norgate(.A(A), .B(B),.Y(Y));
initial begin
A =1'b0;B= 1'b0;
#10 A =1'b0;B= 1'b1;
#10 A =1'b1;B= 1'b0;
#10 A =1'b1;B= 1'b1;
#10
$finish;
end
always @(Y)
$display( "time =%0t \tINPUT VALUES: \t A=%b B =%b \t output value Y =%b",$time,A,B,Y);
endmodule
Wave Form:

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 f) XOR Gate : The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of
its two inputs are high. An encircled plus sign () is used to show the EOR operation.

Boolean expression of XOR gate is given as Y= A.B’ + A’.B

NOR gate - Truth Table

A B Y
0 0 0
0 1 1
1 0 1
1 1 0

Verilog program for XOR gate:

module xorg_dataflow (A, B, Y);
input A, B;
output Y;
assign Y = A ^ B ;
endmodule
Simulation Results:
Verilog teshbench program for XOR gate:
module xorg_tb;
reg A, B;
wire Y;
xorg xorgate(.A(A), .B(B),.Y(Y));
initial begin
A =1'b0;B= 1'b0;
#10 A =1'b0;B= 1'b1;
#10 A =1'b1;B= 1'b0;
#10 A =1'b1;B= 1'b1;
#10
$finish;
end
always @(Y)
$display( "time =%0t \tINPUT VALUES: \t A=%b B =%b \t output value Y =%b",$time,A,B,Y);
endmodule
Wave Form:

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 g) XNOR Gate: The 'Exclusive-NOR' gate circuit does the opposite to the EXOR gate. It will give a low
output if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle
on the output. The small circle represents inversion.

Note:
The NAND and NOR gates are called universal functions since with either one the AND and
OR functions and NOT can be generated.
A function in sum of products form can be implemented using NAND gates by replacing all
AND and OR gates by NAND gates.
A function in product of sums form can be implemented using NOR gates by replacing all
AND and OR gates by NOR gates.

XNOR gate - Truth Table

A B Y
0 0 1
0 1 0
1 0 0
1 1 1

Verilog program for XNOR gate:

module xnorg_dataflow (A, B, Y);
input A, B;
output Y;
assign Y = ~(A ^ B) ;
endmodule
Simulation Results:
Verilog testbench program for XNOR gate:
module xnorg_tb;
reg A, B;
wire Y;
xnorg xnorgate(.A(A), .B(B),.Y(Y));
initial begin
A =1'b0;B= 1'b0;
#10 A =1'b0;B= 1'b1;
#10 A =1'b1;B= 1'b0;
#10 A =1'b1;B= 1'b1;
#10
$finish;
end
always @(Y)

21
$display( "time =%0t \tINPUT VALUES: \t A=%b B =%b \t output value Y =%b",$time,A,B,Y);
endmodule
Wave Form:

Viva Questions:
1. An AND gate and OR gate are given inputs X & 1 , what is expected output?
2. An XOR gate and XNOR gate are given inputs X & 1 , what is expected output?
3. How do you convert a XOR gate into NOT gate?
4. How do you convert a XOR gate into buffer?
5. How do you make a NAND gate out of an AND gate using inverters (NOT gates)?
6. How do you make a NOR gate out of a NAND gate using inverters (NOT gates)?
7. How do you make an AND gate out of an OR gate using inverters (NOT gates)?
8. What does connect together the inputs of NAND and NOR gates do?
9. What is the difference between wire and reg?
10. What are the uses of user defined primitives (UDP) in Verilog?
11. What are applications of XOR and XNOR gates?
12. What is VLSI Design?
13. What do you mean by HDLs? Give examples.
14. What do you mean by universal gate?

22
2. Design of 2-to-4 decoder using Verilog HDL
Aim: To design the 2x4 decoder using Verilog and simulate the design
Objective: To develop the source code 2-to-4 decoder using Verilog HDL in order to obtain the simulation,
synthesis, place and route to implement into FPGA.
Scope:
a. To understand the design using procedural level coding and structural level coding of decoder using
Verilog.
b. To verify wave form viewer against the truth table of decoder
c. To implement the decoder on FPGA development board

Electronic Design Automation Tools and Apparatus required:

 Xilinx Spartan 3 FPGA

 Xilinx ISE Simulator tool
 Xilinx XST Synthesis tool
 Xilinx Project Navigator 8.1i
 JTAG cable
 Adaptor 5v/4A
THEORY:
As a decoder is a combinational circuit takes an n-bit binary number and produces an output on one of

2n output lines.

In a 2-to-4 binary decoder, two inputs are decoded into four outputs hence it consists of two input lines

and 4 output lines. Only one output is active at any time while the other outputs are maintained at logic 0

and the output which is held active or high is determined the two binary inputs A1 and A0. The figure

below shows the truth table for a 2-to-4 decoder. For a given input, the outputs D0 through D3 are active

high if enable input EN is active high (EN = 1). When both inputs A1 and A1 are low (or A1= A0= 0), the

output D0 will be active or High and all other outputs will be low.

When A1 = 0 and A0 = 1, the output D1 will be active and when A1 = 1 and A0 = 0, then the output D2 will

be active. When both the inputs are high, then the output D3 will be high. If the enable bit is zero then all

the outputs will be set to zero. This relationship between the inputs and outputs are illustrated in below truth

table clearly.

23
Block diagram:

a) Verilog coding for 2 to 4 decoder using dataflow model

module decoder_2_to_4_df(EN, A0, A1, D0, D1, D2, D3);

input EN, A0, A1;
output D0, D1, D2, D3;
assign D0 =(EN & ~A1 & ~A0);
assign D1 =(EN & ~A1 & A0);
assign D2 =(EN & A1 & ~A0);
assign D3 =(EN & A1 & A0);
endmodule

b) Verilog code 2 to 4 decoder using case statement (behavior level-procedural)

module decoder_2_to_4_beh(EN, A0, A1, D0, D1, D2, D3);
input EN, A0, A1;
output D0, D1, D2, D3;
reg D3, D2, D1, D0;
always @(A0 or A1 or EN) begin
if (EN == 1'b1)
case ( {A1, A0} )
2'b00: { D3, D2, D1, D0} = 4'b0001;
2'b01: { D3, D2, D1, D0} = 4'b0010;
2'b10: { D3, D2, D1, D0} = 4'b0100;
2'b11: { D3, D2, D1, D0} = 4'b1000;
default: {{ D3, D2, D1, D0} = 4'bxxxx;
endcase
if (EN == 0)
{ D3, D2, D1, D0} = 4'b0000;
end
endmodul

24
 c) Verilog code for 2 to 4 decoder using structural level

module decoder_2_to_4(EN, A0, A1, D0, D1, D2, D3);

input EN, A0, A1;
output D0, D1, D2, D3;
wire x,y;
not u1(y,A1);
not u2(x,A0);
and u3(D0,EN,y,x);
and u4(D1,EN,A0,y);
and u5(D2,EN,x,A1);
and u6(D3,EN,A0,A1);
endmodule

Simulation Results:
Verilog testbench code for 2 to 4 decoder
module decoder_2_to_4_tb;
reg EN, A0, A1;
wire D0, D1, D2, D3;
decoder_2_to_4 decoder(.EN(EN), .A0(A0), .A1(A1), .D0(D0), .D1(D1), .D2(D2), .D3(D3));
initial begin
EN=1'b0; A1 =1'bX ; A0 =1'bX;
#10 EN=1'b1; A1 =1'b0 ; A0 =1'b0;
#10 EN=1'b1; A1 =1'b0 ; A0 =1'b1;
#10 EN=1'b1; A1 =1'b1 ; A0 =1'b0;
#10 EN=1'b1; A1 =1'b1 ; A0 =1'b1;
#10$stop;
end
always @(D0, D1, D2, D3)
$display( "time =%0t \tINPUT VALUES: \t EN=%b \tA1 =%b \t A0 =%b \t output value D3 D2 D1 D0 =
%b%b%b%b",$time,EN,A1, A0, D3,D2, D1, D0);
endmodule
Expected waveform:

25
Viva Questions:
1. What is the difference between Verilog and VHDL?
2. Differentiate between Simulation and Synthesis?
3. What are the differences between continuous and procedural assignments?
4. Why RTL synthesis is important?
5. What is the difference between $display and $monitor?
6. List out the applications of decoder?
7. Convert 2 to decoder into Half adder?
8. What is a "parallel" case statement?
9. Write the Verilog code for 3 to 8 decoder?
10. What is the function of a decoder's enable input?
11. Explain working of a Decoder
12. List all the system tasks and their purpose?
$display
$strobe
$monitor
$reset
$stop
$finish
$time, $stime, $realtime
$scope
$showscopes
$fopen
fclose
$fdisply,
$fstrobe

26
3. Design of 8-to-3 encoder (without and with priority) using Verilog HDL

Objective: To realize 8x3 encoder (without and with priority) using Verilog HDL in order to obtain the simulation,
synthesis, place and route to implement into FPGA.
Scope:
a. To understand the design using procedural level coding (using case statement) and structural level coding
of encoder and priority encoder using Verilog.
b. To verify wave form viewer against the truth table of encoder
c. To implement the encoder on FPGA development board and verify the same.

Electronic Design Automation Tools used

 Xilinx Spartan 3 FPGA

 Xilinx ISE Simulator tool
 Xilinx XST Synthesis tool
 Xilinx Project Navigator 8.1i
 JTAG cable
 Adaptor 5v/4A
THEORY:
An encoder is a combinational logic circuit that essentially performs a “reverse” of decoder functions. An

encoder has 2^N input lines and N output lines. In encoder the output lines generate the binary code corresponding

to input value. An encoder accepts an active level on one of its inputs, representing digit, such as a decimal or

octal digits, and converts it to a coded output such as BCD or binary. Encoders can also be devised to encode

various symbols and alphabetic characters. The process of converting from familiar symbols or numbers to a

coded format is called encoding. An encoder has a number of input lines, only one of which input is activated at

a given time and produces an N-bit output code, depending on which input is activated.

For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2 are:

Y0 = I1 + I3 + I5 + I7

Y1= I2 + I3 + I6 + I7

Y2 = I4 + I5 + I6 +I7

27
Circuit Diagram, Block diagram and Truth Table:

Verilog program for 8x3 encoder structural:

module encoder_8_to_3(input [7:0] I,output reg [2:0] Y );
or(Y[2],I[4],I[5],I[6],I[7]);
or(Y[1],I[2],I[3],I[6],I[7]);
or(Y[0],I[1],I[3],I[5],I[7]);
endmodule
Verilog program for 8x3 encoder behavioral:
module encoder_8_to_3(input [7:0] I,output reg [2:0] Y );
always@(*)
begin
case(I)
8'b00000001: Y<= 3'b000;
8'b00000010: Y <= 3'b001;
8'b00000100: Y <= 3'b010;
8'b00001000: Y <= 3'b011;
8'b00010000: Y <= 3'b100;
8'b00100000: Y <= 3'b101;
8'b01000000: Y <= 3'b110;
8'b10000000: Y <= 3'b111;
default: Y<= 3'bxxx;
endcase
end
endmodule
Verilog testbench program for 8x3 encoder behavioral:
module encoder_8_to_3_tb;
reg [7:0] I;
wire [2:0] Y;
encoder_8_to_3 encoder(.I(I),.Y(Y));
initial begin
28
I= 8'b00000001;
#10 I=8'b00000010;
#10 I=8'b00000100;
#10 I=8'b00001000;
#10 I=8'b00010000;
#10 I=8'b00100000;
#10 I=8'b01000000;
#10 I=8'b10000000;
#10$stop;
end
always @(Y)
$display("time =%0t \tINPUT VALUES: \t I=%b \t output value Y = %b ",$time,I, Y);
endmodule

Simulation Results:

29
Viva Questions:
1. How do I choose between a case statement and a multi-way if-else statement?
2. How do I avoid a priority encoder in an if-else tree?
3. What are the differences between if-else and the (“?:”) conditional operator?
4. What is the importance of a default clause in a case construct?
5. What is the difference between full_case and parallel_case synthesis directive?
6. What is the difference in implementation with sequential and combinatorial processes, when the final
else clause in a multiway if-else construct is missing?
7. What is the difference in using (== or !=) vs. (=== or !==) in decision making of a flow control
construct in a synthesizable code?
8. Explain the differences and advantages of casex and casez over the case statement?
9. How does an encoder differ from a decoder?
10. How does a priority encoder differ from an ordinary encoder?
11. What is the function of a decoder's enable input?

30
4. Design of 8-to-1 multiplexer and 1-to-8 Demultiplexer
Objective: To realize 8-to-1 multiplexer and 1-to-8 Demultiplexer using Verilog HDL in order to obtain the
simulation, synthesis, place and route to implement into FPGA.
Scope:
a. To understand various abstract level of coding coding of 8-to-1 multiplexer and 1-to-8 Demultiplexer
using Verilog.
b. To verify wave form viewer against the truth table of 8-to-1 multiplexer and 1-to-8 Demultiplexer.
c. To implement the 8-to-1 multiplexer and 1-to-8 Demultiplexer on FPGA development board and verify
the same.

Electronic Design Automation Tools and Apparatus required:

 Xilinx Spartan 3 FPGA

 Xilinx ISE Simulator tool
 Xilinx XST Synthesis tool
 Xilinx Project Navigator 8.1i
 JTAG cable
 Adaptor 5v/4A

Theory:
An 8-to-1 multiplexer consists of eight data inputs D0 through D7, three input select lines S2 through S0
and a single output line Y. Depending on the select lines combinations, multiplexer decodes the inputs.
The below figure shows the block diagram of an 8-to-1 multiplexer with enable input that enable or disable
the multiplexer. Since the number data bits given to the MUX are eight then 3 bits (23=8) are needed to select
one of the eight data bits.

31
 The truth table for an 8-to1 multiplexer is given below with eight combinations of inputs so as to

generate each output corresponds to input.

For example, if S2= 0, S1=1 and S0=0 then the data output Y is equal to D2. Similarly the data outputs D0 to

D7 will be selected through the combinations of S2, S1 and S0 as shown in below figure.

From the above truth table, the Boolean equation for the output is given as

From the above Boolean equation, the logic circuit diagram of an 8-to-1 multiplexer can be implemented by

using 8 AND gates, 1 OR gate and 7 NOT gates as shown in below figure. In the circuit, when enable pin is set

to one, the multiplexer will be disabled and if it is zero then select lines will select the corresponding data input

to pass through the output.

32
Verilog code for 8 to 1 mux – Gate level realization:
module mux8_1_gate(input D0,D1,D2,D3,D4,D5,D6,D7, input [2:0]S,output Y);
wire inv0, inv1, inv2; // Inverter outputs.
wire a0, a1, a2, a3, a4, a5, a6, a7 ; // AND gates outputs.
not not_0 (inv0, S[0]); //// Inverters.
not not_1 (inv1, S[1]);
not not_2 (inv2, S[2]);
and and_0 (a0, inv2, inv1, inv0,D0); //// 3-input AND gates.
and and_1 (a1, inv2, inv1, S[0],D1);
and and_2 (a2, inv2, S[1], inv0,D2);
and and_3 (a3, inv2, S[1], S[0],D3);
and and_4 (a4, S[2], inv1, inv0,D4);
and and_5 (a5, S[2], inv1, S[0],D5);
and and_6 (a6, S[2], S[1], inv0,D6);
and and_7 (a7, S[2], S[1], S[0],D7);
or or_0(Y, a0, a1, a2, a3, a4, a5, a6, a7); //// 8-input OR gate.
endmodule

Simulation Results:

Verilog testbench code for 8 to 1 mux:

module mux8_1_tb;
reg D0,D1,D2,D3,D4,D5,D6,D7;
reg [2:0] S;
wire Y;
mux8_1 mux(.D0(D0),.D1(D1),.D2(D2),.D3(D3),.D4(D4),.D5(D5),.D6(D6),.D7(D7), .S(S),.Y(Y));
initial begin
{D0,D1,D2,D3,D4,D5,D6,D7}=$random%8;
#10 S= 000;
{D0,D1,D2,D3,D4,D5,D6,D7}=$random%8;
#10 S= 001;
{D0,D1,D2,D3,D4,D5,D6,D7}=$random%8;
#10 S= 010;
{D0,D1,D2,D3,D4,D5,D6,D7}=$random%8;
#10 S= 011;
{D0,D1,D2,D3,D4,D5,D6,D7}=$random%8;
#10 S= 100;
{D0,D1,D2,D3,D4,D5,D6,D7}=$random%8;
#10 S= 101;
{D0,D1,D2,D3,D4,D5,D6,D7}=$random%8;
#10 S= 110;
{D0,D1,D2,D3,D4,D5,D6,D7}=$random%8;
#10 S= 111;
{D0,D1,D2,D3,D4,D5,D6,D7}=$random%8; #10$stop;
end
always @(Y)
$display("time =%0t \tINPUT VALUES: \t D0 D1 D2 D3 D4 D5 D6 D7=%b%b%b%b%b%b%b%b \t S = %b \t
output value Y = %b ",$time,D0,D1,D2,D3,D4,D5,D6,D7,S, Y);
endmodule
33
Expected Wave form:

34
Demultiplexor
A demultiplexer is a combinational logic circuit that receives the information on a single input and
transmits the same information over one of 2n possible output lines.. The action or operation of a demultiplexer
is opposite to that of the multiplexer. As inverse to the MUX , demux is a one-to-many circuit. With the use of a
demultiplexer , the binary data can be bypassed to one of its many output data lines. Demultiplexers are mainly
used in Boolean function generators and decoder circuits.
The below figure shows the block diagram of a 1-to-8 demultiplexer that consists of single input D, three
select inputs S2, S1 and S0 and eight outputs from Y0 to Y7.
It is also called as 3-to-8 demultiplexer due to three select input lines. It distributes one input line to one of 8
output lines depending on the combination of select inputs.

The truth table for this type of demultiplexer is shown below. The input D is connected with one of the
eight outputs from Y0 to Y7 based on the select lines S2, S1 and S0.

35
For example, if S2S1S0=000, then the input D is connected to the output Y0 and so on.
From this truth table, the Boolean expressions for all the outputs can be written as follows.

From these obtained equations, the logic diagram of this demultiplexer can be implemented by using
eight AND gates and three NOT gates as shown in below figure. The different combinations of the select lines ,
select one AND gate at given time , such that data input will appear at a particular output.
Applications of Demultiplexer
Since the demultiplexers are used to select or enable the one signal out of many, these are extensively
used in microprocessor or computer control systems such as
 Selecting different IO devices for data transfer
 Choosing different banks of memory
 Depends on the address, enabling different rows of memory chips
Enabling different functional units.

Other than these, demultiplexers can be found in a wide variety of application such as
Synchronous data transmission systems
 Boolean function implementation
 Data acquisition systems
 Combinational circuit design
 Automatic test equipment systems
 Security monitoring systems (for selecting a particular surveillance camera at a time), etc.

36
Verilog code for 1 to 8 Demux – Gate level realization:
module demux_8_1_gate(input D, input [2:0]S,output Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7);
wire inv0, inv1, inv2; // Inverter outputs.
// Inverters.
not not_0 (inv0, S[0]);
not not_1 (inv1, S[1]);
not not_2 (inv2, S[2]);
// 3-input AND gates.
and and_0 (Y0, inv2, inv1, inv0, D );
and and_1 (Y1, inv2, inv1, S[0], D );
and and_2 (Y2, inv2, S[1], inv0, D );
and and_3 (Y3, inv2, S[1], S[0], D );
and and_4 (Y4, S[2], inv1, inv0, D );
and and_5 (Y5, S[2], inv1, S[0], D );
and and_6 (Y6, S[2], S[1], inv0, D );
and and_7 (Y7, S[2], S[1], S[0], D );
endmodule

Simulation Results:

Verilog testbench for 1 to 8 Demux – using assign statement:

module demux_8_1_gate_tb;
reg D;
reg [2:0] S;
wire Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7;
demux_8_1_gate demux(.D(D),.S(S),.Y0(Y0),.Y1(Y1),.Y2(Y2),.Y3(Y3),.Y4(Y4),.Y5(Y5),.Y6(Y6),.Y7(Y7));
initial begin
D=$random;
S= 000;
#10 S= 001;
D=$random;
#10 S= 010;
D=$random;
#10 S= 011;
D=$random;
#10 S= 100;
D=$random;
#10 S= 101;
D=$random;
#10 S= 110;
D=$random; 25

37
#10 S= 111;
D=$random;
#10$stop;
end
always @(*)
$display("time =%0t \tINPUT VALUES: \t D =%b \t S = %b \t output value Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 =
%b%b%b%b%b%b%b%b ",$time,D,S,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7);
endmodule

Expected Waveform:

38
Questions:
1. What logic is inferred when there are multiple assign statements targeting the same wire?
2. What do conditional assignments get inferred into?
3. What is the logic that gets synthesized when conditional operators in a single continuous assignment are
nested?
4. What value is inferred when multiple procedural assignments made to the same reg variable in an
always block?
5. Why should a non-blocking assignment be used for sequential logic, and what would happen if a
blocking assignment were used? Compare it with the same code in a combinatorial block.
6. What are the different approaches of connecting ports in a hierarchical design? What are the pros and
cons of each?
7. What is difference between Verilog full case and parallel case?
8. Explain the working of 4:1 MUX with block diagram.
9. State some applications of MUX.
10. How is the 4-to-2 encoder different from a 4-to-1 multiplexer?
11. Explain the difference between a DEMUX and a MUX.
12. True or False: The circuit for a DEMUX is basically the same as for a decoder.
13. Draw the logic diagram of 2-bit comparator using gates.
14. Write Verilog codes for Decoder, Encoder, MUX and DEMUX.
15. Write syntax of module if there are two inputs (A and B) and one output (C).

39