10/5/2015

Outline
• FF: Characterization Table and Equation
– RS, D, JK and T Flip flop
Sequential Logic Design • Register
(FF & Register) – Parallel Load, Parallel out : (PIPO)
– Serial Load, Wrap around load, Serial out
(SISO)
– PISO, SIPO Register
• Multifunction Register : How to design?

Master Slave J‐K Flip Flop J‐K Flip Flop

• To synthesize a D flip‐flop, simply set K equal to
the complement of J.
J
S S
Q’
• The JK flip‐flop is a universal flip‐flop
– Because it can be configured to work as any FF
C C – T flip‐flop or D flip‐flop or SR flip‐flop.
J=T K=T Q+ J=D K=D’ Q+ J=S K=R Q+
Q Q
K 0 0 Qt 0 0 Qt 0 0 Qt
R R
0 1 0 0 1 0 0 1 0
Q+= K’Q + JQ’ 1 0 1 1 0 1
1 0 1
1 1 Qt’ 1 1 Qt’
1 1 Qt’

Toggle Flip‐Flop: T FF 4 Types of Flip‐Flops

S R Q+ J K Q+
• J=K=1, Q+= Q’
0 0 Qt 0 0 Qt
J T 0 1 0 0 1 0
Q Q
T JK T 1 0 1 1 0 1
Flip Flop Flip Flop 1 1 U 1 1 Qt’
K

C C
D Q+ T Q+
0 0 0 Qt
1 1 1 Qt’

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Given a D FF: Construct JK FF Given a D FF: Construct T FF
J J K D K’Q+JQ’ T D TQ’+T’Q
D Q 0 0 Q 1Q+0Q’ D Q 0 Q 0Q’+1Q
J
K 0 1 0 0Q+0Q’ 0 Q’ 1Q’+0Q
CLK C Q
Q’ 1 0 1 1Q+1Q’ CLK C Q
Q’
1 1 Q’ 0Q+1Q’

D= K’Q + JQ’ D= TQ’ + TQ

Characteristic Equations Characteristic tables
• The tables that we’ve made so far are called
characteristic tables.
• A descriptions of the next‐state table  – They show the next state Q(t+1) in terms of the current
of a flip‐flop state Q(t) and the inputs.
• Constructing from the Karnaugh
Constructing from the Karnaugh map 
map – For simplicity, the control input C is not usually listed.
– Again, these tables don’t indicate the positive edge-
for Qt+1 in terms of the present state  triggered behavior of the flip-flops that we’ll be using.
and input J K Q+
0 0 Qt D Q+ T Q+
0 1 0
0 0 0 Qt
1 0 1
1 1 1 Qt’
1 1 Qt’

Characteristic equations Characteristic equations
• We can also write characteristic equations, 
• We can also write characteristic equations, 
where the next state Q(t+1) is defined in terms 
where the next state Q(t+1) is defined in terms 
of the current state Q(t) and inputs.
of the current state Q(t) and inputs.
J K Q+ Q+=  J’K’Q+JKQt’+JK’ T Q+
D Q+ Q+=D
0 0 Qt =  J’K’Q+JKQ’+JK’Q’+JK’Q 0 0 0 Qt
0 1 0 =  J’K’Q+JK’Q + JKQ’+JK’Q’ Q(t+1) = D
1 Qt’
1 1
= (J+J’)K’Q+J(K+K’)Q’
1 0 1 Q+= T’Q+TQ’ = T ⊕ Q
Q+= K’Q + JQ’ Q(t+1) = T’Q(t) + TQ’(t)  = T ⊕ Q(t)
1 1 Qt’
Q(t+1)= K’Q(t) + JQ’(t)

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FF with Asynchronous Inputs

Characteristic equations • S‐R, D and J‐K inputs are synchronous inputs
SR
– As data on these inputs are transferred to the flip‐
flop’s output 
Flip Flop  Characteristic 
Type Equation – Only on the triggered edge of the clock pulse.
SR Q+= S +R’Q   (SR=0)
( ) • Asynchronous inputs affect the state of the flip‐
Q flop independent of the clock
JK Q+= JQ’+K’Q
• Example: 
D Q+=D
– Preset (PRE) and clear (CLR) 
Q+= S + R’Q    (SR=0) T Q+=TQ’+T’Q=T⊕Q
– or direct set (SD) and direct reset (RD)

FF with Asynchronous Inputs Asynchronous Inputs

• When PRE=HIGH, Q is immediately set to HIGH. ƒ A J‐K flip‐flop with active‐LOW preset and clear 
inputs.
• When CLR=HIGH, Q is immediately cleared to  CLK
LOW. PRE
Q PRE
• Flip‐flop in normal operation mode when both  J
C
PRE and CLR are LOW.
PRE and CLR are LOW K Q' CLR

CLR Q
Preset Toggle Clear
J = K = 1

Registers I0 D Q A0 Registers
I0 D Q A0
R CLK
• Group of D Flip‐Flops I3 R
I1 D Q A1
• Synchronized (Single Clock) I2 I1 D Q A1
• Store Data R I1
R
I2 A2 I0
D Q
A3 I2 D Q A2
R
A2 R
I3 D Q A3 A1
I3 D Q A3
CLK A0
R CLK
Reset Note New data has to go in
Note: R
with every clock Reset
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See carefully:  Input at the dotted will  be reflected  to output : Just before rising edges

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Registers with Parallel Load Registers with Parallel Load
• Control Loading
Loading the Register with New Data • Should we block the “Clock” to keep the “Data”?
I0 D Q A0
D7 R Q7 D7 R Q7
D6 E Q6 D6 E Q6
D5 G Q5 D5 G Q5 I1 D Q A1
D4 Q4 LD Q(t 1)
Q(t+1) D4 Q4
I Q3
I Q3
D3 D3
D2 S Q2
0 Q(t) D2 S Q2 I2 D Q A2
D1 T Q1 1 D D1 T Q1 Delays
the Clock
D0 E Q0 D0 E Q0
I3 A3
D Q
LD R LD R Load
CLK
19 20

Registers with Parallel Load Shift Registers
• Circulate the “old data”
• Register (Set of FFs)
• 4‐Bit Shift Register (Example)  
I0 MUX
I0 I1 S
Y D Q A0 • Serial in Serial Out (SISO)
I0 MUX
Y D Q A1
I1 I1 S

I0 MUX
Y D Q A2
I2 I1 S

I0 MUX
Y
I3 I1 S D Q A3
21
Load CLK

Shift Register Shift Register
• Right Shift Example  (Left shift is similar) Register contents
1 1 0 1
before shift right
– Move each bit one position right 0
– Shift in 0 to leftmost bit
Q: Do four right shifts on 1001, showing value  0 1 1 0
Register contents
after each shift after shift right
A
A:  1001 ( i i l)
1001 (original) Register contents
1 1 0 1
before shift right • Implementation: Connect flip-flop output
0100  0 to next flip-flop’s input
0010  Register contents
0 1 1 0 shr_in
0001  after shift right

0000  23

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Shift Registers Shift Registers (SISO)
Q3 Q2 Q1 Q0
• 4‐Bit Shift Register   SI D Q D Q D Q D Q SO

• Serial in Serial Out (SISO)
Serial SI SO CLK
D Q D Q D Q D Q
p
Input Se a
Serial
Output CLK
SI
CLK Q3
Q2
Q1
Q0
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Shift Register with Control Shift Register with Control
• To allow register to either shift or retain, use 2x1  Shift Control=1, Do one right shift per cycle 
muxes Serial In Bit
– Shift Control: shr: 0 means retain, 1 shift Shift Control 1   0  1   0  1   0  1   0 

– shr_in: value to shift in  : May be 0/1, or right most bit
Serial In Bit S i l O t Bit
Serial Out Bit  D D D D
Serial Out Bit 
Shift Control 1   0  1   0  1   0  1   0 
Q Q Q Q
D D D D

Q Q Q Q

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Shift Register with Control
Shift Control=0, No change to Data
Serial In Bit

Shift Control 1   0  1   0  1   0  1   0 

D D D D
Serial Out Bit  Thanks
Q Q Q Q