IET Power Electronics

Research Article

ISSN 1755-4535
New cascade boost converter with reduced Received on 5th April 2015
Revised on 14th November 2015
losses Accepted on 22nd November 2015
doi: 10.1049/iet-pel.2015.0240
www.ietdl.org

Mohammad Lotfi Nejad 1 ✉, Behzad Poorali 2, Ehsan Adib 2, Ali Akbar Motie Birjandi 1
1
Department of Electrical and Computer Engineering, Shahid Rajaee Teacher Training University, Tehran, Iran
2
Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran
✉ E-mail: M.Lotfi@srttu.edu

Abstract: To enhance the gain of conventional boost converters in applications such as fuel cells and photovoltaic
systems, cascade boost converters are normally applied. In this study, a new cascade boost converter topology with
reduced conduction losses is proposed. This converter shows reduced root-mean-square currents of the circuit
elements and reduced conduction losses. The proposed converter is analysed and compared with the conventional
circuit topology. The proposed converter has all the advantages of cascade boost converter with the advantage of
reduced conduction losses. Finally, simulation and experimental results of a 200 W laboratory prototype are presented.

1 Introduction 2 Proposed converter topology

In recent years, researchers have paid attention to new energy sources
such as fuel cells and photovoltaic (PV) systems [1–3]. A high step-up
converter is an essential part in these systems which increases the low
output voltage of the fuel cells or PV panels [4–6]. Thus, efficiency of
the high step-up converter is very important to increase the system
performance and reduce the total system cost [7]. There are many
methods to enhance the efficiency of boost converters [2]. Some
methods focus on the switching losses [8, 9]. Reducing conduction
losses is another method to improve the efficiency [10, 11]. On the
other hand, the conventional boost converter is unable to achieve high
voltage gains due to large efficiency drop at high operating duty
cycles. To solve this problem, isolated converters and converters with
coupled inductors can be employed [12, 13]. However, these
converters have high switch voltage stress and electromagnetic
interference issues due to voltage spikes across the switch caused by
leakage inductance [14]. Therefore, cascade boost converter is a better
solution when isolation is not necessary. Novel single-switch
converters are proposed in [15–17] which have high voltage but the
current stress of semiconductor devices are high. Cascade boost
converter has low voltage stress in the first stage and low current stress
in the second stage. Also, cascade boost converters can be employed
as two-stage power factor correction (PFC) converters [18], such that
the first converter is applied for power factor correction and the other
converter is applied to enhance the voltage gain and voltage
regulation. Interleaving of DC–DC converters is another method to
improve the efficiency. Interleaved boost converters have higher
efficiency compared with the conventional boost converter due to
lower conduction losses [19]. However, the voltage gain of an
interleaved converter is the same as basic converter. To solve this
problem, Chang et al. [20] have presented two interleaved
voltage-doubler boost converters with acceptable gain and low
conduction losses. However, these converters require four switches
and the control circuit is complicated which is not desirable in low
power applications [21].
In this paper, a new cascade boost converter is introduced and
analysed. The proposed converter has all the benefits of conventional
cascade boost converters such as high voltage gain and low voltage
stress of semiconductor devices with high current rating. In addition,
in the proposed converter, conduction losses are reduced. To
demonstrate the advantages of the proposed converter, comparison of
the conventional and the proposed cascade boost converters are
accomplished. Simulation and experimental results of a laboratory
prototype are presented which justify the theoretical analysis.
Fig. 1 shows the conventional cascade boost converter. This
converter is employed for high step-up and power factor correction
applications. Conduction losses of the inductors, especially L1
losses are considerable. To reduce the conduction losses, a new
circuit topology is proposed. The proposed converter schematic
diagram along with its switching method is illustrated in Fig. 2.
Furthermore, the proposed concept can be extended for series
connection of n-boost converters.
3 Performance analysis of the proposed converter
Considering the suggested switching method for the proposed
converter operating in continuous conduction mode (CCM), there
are three major intervals in each switching cycle (Fig. 3). In the
first interval, both switches are on and two inductors are charging.
Second interval starts when the switch M2 is turned off and L2 is
discharged into the output capacitor C2. In third interval, M1 is off
and M2 is on. The stored energy in L1 is transferred to capacitor
C1 through the diode Di1.
Voltage gain of the proposed converter can be obtained according
to switching method shown in Fig. 2b and using volt-second balance
for inductors. The voltage gain equation is expressed as
1
M (D) = (1)
(1 − D1 )(1 − D2 )
where D1 and D2 are duty cycles of M1 and M2, respectively. As it is
observed, the proposed converter voltage gain is the same as a
conventional cascade boost converter.
Block diagram of the proposed converter control circuit is shown
in Fig. 4. According to the proposed switching method, M2 is turned
on when M1 turns off. The pulse width modulation (PWM) control
units are just like the control units used in conventional converters.
4 Comparison of proposed and conventional
converters
In this section, voltage ripples of capacitors and current ripples of
inductors in the proposed and conventional converters are

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Fig. 1 Conventional cascade boost converter

Fig. 3 Operating intervals of the proposed converter in CCM condition

a First interval: both switches are on
b Second interval: M1 is on and M2 is off
c Third interval: M1 is off and M2 is on

the inductor L1 in the conventional and proposed converters can be

expressed as

Fig. 2 Proposed cascade boost converter and its switching method 1 V

IL1 =

 C2 (3)
a Proposed cascade boost converter 1 − D1 1 − D2 R
b Switching method for proposed converter

D1 VC2
IL1 = (4)
compared together. Theoretical loss equations are also presented in new
(1 − D1 )(1 − D2 ) R
order to compare two converter topologies.
Therefore, L1 current rating in the proposed converter is lower
4.1 Comparison of voltage and current ripples

Table 1 indicates a comparison between inductor current ripples and

capacitor voltage ripples in the conventional and proposed
converters.
In Table 1, VC1 and VC2 are steady-state voltages of the capacitors
C1 and C2, Io is the load current and Ts (Ts = 1/fs) is the switching
period.
As it can be observed in Table 1, the current ripple of L1 and the
voltage ripples of C1 and C2 are equal in both converters. However,
the current ripple of L2 (DiL2 ) in the proposed converter is smaller in
comparison to the conventional converter. Reduction of inductor
current ripple results in reduction of its size and conduction losses.

4.2 Comparison of losses

Average current of the inductor L2 in both converters are equal to

1 VC2
IL2 = (2)
(1 − D2 ) R

where R is the load resistance. On the other hand, average current of Fig. 4 Block diagram of the proposed converter control circuit

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Table 1 Inductor current ripples and capacitor voltage ripples in two converters
Conventional converter Proposed converter

First boost converter Second boost converter First boost converter Second boost converter

Vin VC2 − VC1 Vin (VC2 − VC1 ) − Vin

DiL1 = D T DiL2 = (1 − D2 )Ts DiL1 = D T DiL2 = (1 − D2 )Ts
L1 1 s L2 L1 1 s L2
IL IL
DvC1 = 2 D1 Ts DvC2 = Io D2 Ts DvC1 = 2 D1 Ts DvC2 = Io D2 Ts
C1 C1

compared with the conventional converter. This is due to the fact that Sum of the inductor currents IL1 and IL2 in the proposed converter
input current in the proposed converter is sum of the L1 and L2 is equal to the inductor current IL1 in the conventional converter.
currents. Considering Table 2, it can be concluded that conduction losses of
Converter losses are divided into three parts including switching L1 in the proposed converter is D21 times of that in the
losses (Psw), conduction losses (Pcon) and off-state losses [22–24]. conventional converter.
Off-state losses are low enough to be neglected. In a cascade boost
converter, conduction losses are normally higher in the first stage
while switching losses are dominant in the second stage. 5 Small signal analysis of the proposed converter
Comparison of losses of the conventional and proposed converters
is presented in Table 2. Losses associated with the gate drive State equations of the proposed converter topology can be obtained
circuits of switches are almost equal in both converters and can be using voltage and current balances and separating the variables into
neglected. DC and AC parts
In Table 2, D1′ and D2′ are ratios of off-time intervals of the ′
switches to the switching period Ts which can be expressed as D1 ∂il1 (t)
′
= 1 − D1 and D2 = 1 − D2. L1 = Vin − VC1 D′1 + vin (t) − vc1 (t)D′1 + VC1 d1 (t) (5)
∂t
Ton and Toff are transition times of the switches to on- and
off-state, respectively. Their values depend on characteristics of ∂il2 (t)
the switches and gate drives. Also, Won and Woff are dissipated L2 = Vin + VC1 D1 − VC2 D′2 + VC1 d1 (t) + VC2 d2 (t)
∂t
energies of the switches during turn-on and turn-off instants,
+ vin (t) + vc1 (t)D1 − vc2 (t)D′2 (6)
respectively.
Rds stands for the switch on-resistance (drain–source resistance) ∂vc1 (t)
and RonDi is the diode dynamic resistance. Also, Qrr and Vf are the C1 = −IL2 D1 + IL1 D′1 − IL2 d1 (t) − IL1 d1 (t) − il2 (t)D1
reverse recovery charge and the diode forward voltage drop, ∂t
respectively. + il1 (t)D′1 (7)

Table 2 Loss equations for both converters operating in CCM

Conventional converter Proposed converter

1 VC2 D1 V C2 1 V
IL1 = IL1 = , (IL1 + IL2 ) =

 C2
(1 − D1 )(1 − D2 ) R (1 − D1 )(1 − D2 ) R 1 − D1 1 − D2 R

1 V C2 1 V C2
IL2 = IL2 =
(1 − D2 ) R (1 − D2 ) R
   
DiL21  2 Di 2
L1
PconM1 = RdsM1 D1 IL21 + PconM1 = RdsM1 D1 IL1 + IL2 +
12 12
   
DiL22 Di 2
L2
PconM2 = RdsM2 D2 IL22 + PconM2 = RdsM2 D2 IL22 +
12 12
   
DiL21 DiL21
PL1 = RL1 IL21 + PL1 = RL1 IL21 +
12 12
   
DiL22 Di 2
L2
PL2 = RL2 IL22 + PL2 = RL2 IL22 +
12 12
PSwM1 = (Won1 + Woff1 ) fs PSwM1 = (Won1 + Woff1 ) fs
Won1 = 0.5IL1 VC1 Ton1 Won1 = 0.5(IL1 + IL2 )VC1 Ton1
Woff1 = 0.5IL1 VC1 Toff1 Woff1 = 0.5(IL1 + IL2 )VC1 Toff1
PSwM2 = (Won2 + Woff2 ) fs PSwM2 = (Won2 + Woff2 ) fs
Won2 = 0.5IL2 VC2 Ton2 Won2 = 0.5IL2 VC2 Ton2
Woff2 = 0.5IL2 VC2 Toff2 Woff2 = 0.5IL2 VC2 Toff2
   
′ ′ DiL21   ′ ′
 2 Di 2
L1
PconDi1 = V f 1 IL1 D1 + RonDi1 D1 IL21 + PconDi1 = V f 1 IL1 + IL2 D1 + RonDi1 D1 IL1 + IL2 +
12 12
   
′ ′ DiL22 ′ ′ Di 2
L
PconDi2 = V f 2 IL2 D2 + RonDi2 D2 IL22 + PconDi2 = V f 2 IL2 D2 + RonDi2 D2 IL22 + 2
12 12
PswDi1 = VC1 Qrr1 fs PswDi1 = VC1 Qrr1 fs
PswDi2 = VC2 Qrr2 fs PswDi2 = VC2 Qrr2 fs

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Table 3 Simulation parameters of the conventional and proposed
converters

Conventional converter Proposed converter

L1 = 450 μH L2 = 1.3 mH L1 = 450 μH L2 = 1 mH

RL1 = 0.15 V RL2 = 0.2 V RL1 = 0.15 V RL2 = 0.17 V
C1 = 220 μF C2 = 22 μF C1 = 220 μF C2 = 22 μF
fs = 50 kHz Vin = 40 V fs = 50 kHz Vin = 40 V
Di1:MUR880 Di2:MUR860 M1:IRF640 M2:IRF740
D1 = 0.6 D2 = 0.66 D1 = 0.6 D2 = 0.66
R = 450 Ω R = 450 Ω

Fig. 5 Output voltage waveforms of the conventional and proposed

converters

∂vc2 (t) VC ′ v (t) ′

C2 = − 2 + IL2 D2 − IL2 d2 (t) − c2 + il2 (t)D2 (8) Fig. 6 Inductor current waveforms of the conventional and proposed
∂t R R converters
a Current waveforms of the inductor L1
where D1, D2, IL1 , IL2 , VC1 , VC2 and Vin are the corresponding b Current waveforms of the inductor L2
steady-state DC values while d1(t), d2(t), il1(t), il2(t), vc1(t), vc2(t)
and vin(t) are their small signal variations.
Transfer function of d2 to VC2 can be expressed as (see (9)) converter. The lower inductance results in smaller winding
resistance.
Zeros of the transfer function can be calculated as Fig. 5 illustrates the output voltage waveforms of the conventional
 and proposed converters. According to this figure, the proposed
D1 − 1 converter shows higher voltage gain under identical conditions due
Z1,2 = +j (10) to lower losses. Fig. 6 shows the current waveforms of the
C1 L 1 inductors in two converters. It can be observed that average
current of the inductor L1 in the proposed converter is 0.6 times of
According to (10), zeros of the transfer function are on the imaginary that in conventional converter. Efficiencies of two converter
axis. This matter not only increases the response speed of the topologies are depicted in Fig. 7 under different output powers. It
converter but also increases its output voltage overshoot. is obvious that losses of both converters increase when output
power increases. However, the proposed converter has better
efficiency especially at high operating power.
6 Simulation results

In this section, simulation results of the conventional and proposed
converters using PSPICE software are presented. Simulation
parameters are summarised in Table 3.
The converters have been designed such that both converters have
the same inductor current ripples and capacitor voltage ripples.
Choosing proper current ripples for inductors ensures operation of
the converters in CCM. Assuming equal current ripples for
inductors in both converters, inductance of L2 in the proposed
converter is obtained smaller compared with the conventional
7 Experimental results
To verify performance of the proposed converter and accuracy of the
theoretical analysis, a 200 W laboratory prototype to convert 40 V
input voltage to 300 V is implemented. In addition, a prototype of
the conventional cascade boost converter is also implemented to
experimentally compare performance of two converter topologies.
Table 4 shows important parameters of the implemented
prototypes. The converters are designed such that the capacitor C1

 ′
 ′
 ′ 
VC2 (s) −I2 s(D21 L1 + D12 L2 ) + s3 C1 L1 L2 + D2 D12 + s2 C1 L1 V2
H2 (s) = =
′ 2 
′ 2 

′  (9)
d2 (s) D2 D1 + s2 C1 L1 + (1/R) + sC2 s(D21 L1 + D12 L2 ) + s3 C1 L1 L2

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Fig. 7 Efficiencies of two converter topologies
Fig. 9 Photographs of the implemented prototypes
a Conventional cascade boost converter
Table 4 Main parameters of the implemented prototypes b Proposed converter
Parameter Value

Conventional converter Proposed converter voltage becomes 100 V. For this, operating duty cycles of the
switches M1 and M2 are obtained as 0.6 and 0.66, respectively.
Vin 40 V Fig. 8 illustrates schematic of the implemented proposed converter
Vo 300 V
fs 50 kHz
and its control circuit. According to this figure, the control circuit
M1 IRF640 uses two PWM controllers and an optocoupler (as a NOT gate). It
Di1 MBR20150 should be noted that the voltage sources Vcc1 and Vcc2 can be
L1 450 μH generated from voltages of the capacitors C1 and C2, respectively.
C1 220 μF/160 V
M2 IRF740
Photographs of the implemented prototypes and important
Di2 MUR860 waveforms of the proposed converter are shown in Figs. 9 and 10,
L2 1.3 mH 1 mH respectively. Fig. 11 also shows current waveforms of the
C2 22 μF/400 V inductors L1 and L2 in the implemented prototypes. According to
Fig. 11, average current of the inductor L1 in the proposed

Fig. 8 Schematic of the implemented proposed converter and its control circuit

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 Fig. 11 Current waveforms of the inductors L1 and L2
a Conventional cascade boost converter
b Proposed converter

converter is lower in comparison with the conventional cascade

boost converter which results in lower conduction losses.
Comparison of the experimental and simulation results justifies the
theoretical analysis. Output voltage waveform of the proposed
converter at start-up condition is illustrated in Fig. 12 which shows
that rise time of the output voltage is approximately equal to 4.25 ms.
This value is smaller than the output voltage rise time of the
conventional cascade boost converter which is equal to 5.8 ms.
Efficiencies of the implemented prototypes have been measured
under different load conditions and the results are plotted in
Fig. 13. As it can be observed, the proposed converter topology
has higher efficiency in all load conditions. In addition, efficiency

Fig. 10 Some important waveforms of the implemented proposed converter

a Current and voltage waveforms of the switch M1
b Current and voltage waveforms of the diode Di1
c Current and voltage waveforms of the switch M2 Fig. 12 Output voltage waveform of the proposed converter at start-up
d Current and voltage waveforms of the diode Di2 condition

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Fig. 13 Efficiencies of the implemented prototypes
drop in the conventional cascade boost converter in heavy loads is
higher compared with the proposed converter.
8 Conclusion
One of the best high step-up converters is the cascade boost
converter. Low voltage stress of the high current switch in input
stage is the best advantage of this converter. In addition,
conduction losses of the semiconductor devices are low. The main
disadvantage of this converter is high losses of the input inductor.
In this paper, a new cascade boost converter topology is
introduced in which current rating of the input inductor is lower
than the conventional converter. Therefore, conduction losses of
the inductor are reduced. The proposed converter is analysed and
theoretical analysis is justified using simulation and experimental
results.
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