EE 382M

VLSI–II: Advanced Circuit Design

I/O & ESD Design

Byron Krauter, IBM

EE382M VLSI-II Class Notes Foil # 1 The University of Texas at Austin

 Outline
• Logic Requirements
• Other Complications
• Transmission Line Behavior
• Basic CMOS I/O and Receiver Design
• Actual CMOS I/O and Receiver Design
– Impedance Matching & Slew Rate Control
– Mixed Voltages
– ESD and other extreme conditions
• Increasing Bandwidth
– Source Synchronous I/O or Co-transmitted Clock
– Pipelined Bus or Bus Pumping
– Dual Data Rate
– Simultaneous Bi-Directional
– Pattern Based Driver Compensation

EE382M VLSI-II Class Notes Foil # 2 The University of Texas at Austin2

 Logic Requirements

EE382M VLSI-II Class Notes Foil # 3 The University of Texas at Austin

 Logic Requirements
• Send 1’s and 0’s chip to chip
– Can be accomplished with simple inverters??

Chip A Chip B

EE382M VLSI-II Class Notes Foil # 4 The University of Texas at Austin4

 Complications
• Pin Count Limitations
– Bi-directional signaling
– Simultaneous switching noise
• Transmission Line Behavior
– Limited net topologies work
– Terminations required
– Skin effect
– Dielectric loss
• Other Noises
– Reflections
– Discontinuity noise
– Crosstalk and connector noise
• Mixed Voltages
• ESD and Other Handling Complications

EE382M VLSI-II Class Notes Foil # 5 The University of Texas at Austin5

 Transmission Line Behavior

EE382M VLSI-II Class Notes Foil # 6 The University of Texas at Austin

 But First A Few Words on
Common Ground Interconnect
Models

EE382M VLSI-II Class Notes Foil # 7 The University of Texas at Austin

 Example - Two Wires & One Source
• Twin lead transmission line modeled as a single section
and driven by a Thevenin source

Rsource L11 Rwire

0.5*Cwire M12 0.5*Cwire

L22 Rwire

EE382M VLSI-II Class Notes Foil # 8 The University of Texas at Austin

 Example - Two Wires & One Source
• Being concerned with local potentials only (i.e. capacitor
potentials) inductances and resistances can be combined

Rsource L11 Rwire L22 Rwire

0.5*Cwire M12 0.5*Cwire

Rsource L11+ L22 - 2*M12

0.5*Cwire 2*Rwire 0.5*Cwire

EE382M VLSI-II Class Notes Foil # 9 The University of Texas at Austin

 Example - Three Wires & Two Sources
• When multiple wires form a cutset, treat one wire as a
reference lead and fold it into the other wires*.

Rs1 L11 R1
Cutset

0.5*C1g M1g 0.5*C1g

Rg 0.5*C12

0.5*C12 M12 Lgg

0.5*C2g M2g 0.5*C2g

Rs2 L22 R2
* Brian Young, “Digital Signal Integrity: Modeling and Simulation
with Interconnects and Packages”
EE382M VLSI-II Class Notes Foil # 10 The University of Texas at Austin
 Example - Three Wires & Two Sources
• Resulting loop impedance model for three parallel wires
driven by two Thevenin sources

mutual resistances

Rs1 L11+Lgg-2M1g R1+Rg v1

i2Rg

0.5*C1g 0.5*C1g
M12-M1g-M2g+Lgg
0.5*C12 v2
0.5*C12
i1Rg

Rs2 L22+Lgg-2M1g R2+Rg

0.5*C2g
0.5*C1g

EE382M VLSI-II Class Notes Foil # 11 The University of Texas at Austin

 Transmission Line Behavior
• On and off chip signals can always be modeled with lumped
RLC circuits

• Wire segments are modeled with π or t segments

• L, R, C, and G can be frequency dependent

• But inductance is not always important

EE382M VLSI-II Class Notes Foil # 12 The University of Texas at Austin

 Transmission Line Behavior
• Inductance is important when
– Driver source impedance Rs is low
Rs < Zo
where Zo = characteristic impedance of line
– Driver rise time τr is fast
τr < 2.5 τf
where τf = time of flight
– Line loss is low
R << jωL or (R / 2Zo) << 1
Wave front
decays exponentially
• Can be restated for point to point nets as with this constant
RsCtot < 1/2 RlineCline < τf

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EE382M VLSI-II Class Notes Foil # 13
 When Inductance is Important
• Nets ring and net delays become unpredictable unless:
– Net topologies are constrained
• Point to point nets
• Periodically loaded nets
• Near and far end clusters
– Nets are driven appropriately
• Not to strong and not to weak
• Not to fast and not to slow
– Nets are terminated appropriately
• Source termination
• Far end termination
– Resistance to Vdd or Gnd or any Thevenin Voltage
• AC termination = RC circuit
• Active hold clamps
• Diode or Schottky diode clamps

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EE382M VLSI-II Class Notes Foil # 14
 Transmission Line Behavior
• Perfectly source terminated point to point, loss-less net

τf
Rs = Zo Zo = L
C
τf = LC

far end

V(t) near end

τf
time
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EE382M VLSI-II Class Notes Foil # 15
 Transmission Line Behavior
• Under driven point to point, loss-less net

τf
Rs = 3Zo Zo = L
C
τf = LC

Approximates
far end RC step response

V(t)
near end
time
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EE382M VLSI-II Class Notes Foil # 16
 Transmission Line Behavior
• Over driven point to point, loss-less net

τf
Rs = 1/3 Zo Zo = L
C
τf = LC

far end

V(t)
near end
time
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EE382M VLSI-II Class Notes Foil # 17
 Reflection and Transmission

With incident wave Vinc traveling down the line

Voltage reflection coefficient

ZL - Zo
1, ZL= ∞
Γv = Γv = 0, ZL= Zo
ZL+ Zo
-1, ZL= 0

Voltage transmission coefficient

2ZL
Τv = 1 + Γ v =
ZL+ Zo

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EE382M VLSI-II Class Notes Foil # 18
 Equivalent Circuits Along Line

Rs near end
+
Vs Zo Vinc
-
Zo along line

2Vinc Zo Zdiscontinuity

Zo far end

2Vinc ZL

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EE382M VLSI-II Class Notes Foil # 19
 Discontinuities Along Line

Rs = Zo Vs=1
1
C 1/2
Vs
1/2 (1- e-2t/ZoC)

Vs=1
Rs = Zo 1

1/2
Vs L 1- 1/2(1- e-2Zot/L)

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EE382M VLSI-II Class Notes Foil # 20
 Well Behaved Net Topologies
• Point to Point Nets

Source terminated
Rs = Zo τf

Far end terminated

Rs << Zo τf
Vterm
Rterm ≅ Zo

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EE382M VLSI-II Class Notes Foil # 21
 Well Behaved Net Topologies
• Periodically Loaded Nets

Source terminated: Near end switches last

Rs = Zeff

CL CL CL CL

L
Zeff =
With periodic loading C + nCL
τf = L(C+nCL)
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EE382M VLSI-II Class Notes Foil # 22
 Well Behaved Net Topologies
• Periodically Loaded Nets

Far end terminated: Near end switches first

Rs << Zeff Rterm ≅ Zeff

Vterm
CL CL CL CL

L
Zeff =
With periodic loading C + nCL
τf = L(C+nCL)
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EE382M VLSI-II Class Notes Foil # 23
 Well Behaved Net Topologies
• Near end (or Star) cluster

Rs = Zo/N

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EE382M VLSI-II Class Notes Foil # 24
 Well Behaved Net Topologies
• Far-end cluster

Rs = Zo/N Zo/N

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EE382M VLSI-II Class Notes Foil # 25
 Well Behaved Net Topologies
• Double far-end terminated bus

Rs << Zo

Vterm Vterm

CL CL CL CL CL

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EE382M VLSI-II Class Notes Foil # 26
 Ideal Transmission Lines

Ideal
I(z) Telegrapher’s Equation
∂i ∂V
= −C
∂z ∂t ∂ 2V ∂ 2V
= LC 2
V(z) ∂V ∂i ∂z 2
∂t
= −L
∂z ∂t

− j ( γz −ωt ) j ( γz +ωt )
V = Re [V +
e +V −
e ]
Steady State Solution:
1 + − j ( γz −ωt ) j ( γz +ωt )
I = Re ( [V e +V e
−
])
Z

L
where Z= γ = ω LC
C
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EE382M VLSI-II Class Notes Foil # 27
 Transmission Lines with Loss

Z(ω) = jωL + R j γ (ω) = (jωL + R) jωC

jωC
≅ L ≅ jω LC (1 - j R/2ω L)
(1 - j R/2ω L)
C
R R
Z (ω ) = Z 0 − j γ (ω ) = ω LC +
2ω C Z0 2 Z0
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EE382M VLSI-II Class Notes Foil # 28
 Waveforms Along a Low Loss Line

Rs << Zo

Vs τf
where τf = length / velocity

With complex impedance & complex propagation constant

high speed wavefront decays exponentially & distorts

1
(1- e-R*length/2Zo)

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EE382M VLSI-II Class Notes Foil # 29
 Distortionless Transmission Line
Oliver Heaviside (1887)

G/C = R/ L

Z(ω) = jωL + R j γ (ω) = (jωL + R)(jωC + G)

jωC + G

L
= LC ( jω + R /L)
=
C

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EE382M VLSI-II Class Notes Foil # 30
 Waveforms Along a Distortionless Line

Rs << Zo

Vs τf
where τf = length / velocity

With real impedance and complex propagation constant

high speed wavefront decays exponentially but without distortion

1
(1- e-R*length/Zo)

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EE382M VLSI-II Class Notes Foil # 31
 Basic CMOS I/O and Receiver
Design

EE382M VLSI-II Class Notes Foil # 32 The University of Texas at Austin

 Bidirection CMOS I/O Buffer

enable Pad
data

enable
0 1
0 0 Hi Z
data
1 1 Hi Z

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EE382M VLSI-II Class Notes Foil # 33
 CMOS I/O Receiver
• Any two input gate that
– Has good noise immunity
– Provides on-chip control when off-chip inputs float
• Example: two input nand

enable
enable 0 1
Pad 0 1 1
data out data
1 1 0
X 1 X

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EE382M VLSI-II Class Notes Foil # 34
 Actual CMOS I/O and Receiver
Design

EE382M VLSI-II Class Notes Foil # 35 The University of Texas at Austin

 Actual CMOS I/O Design
• Output Impedance Control
• Slew Rate Control
• Mixed Voltage Designs
– Input Design for Higher Voltages
– Output Design for Higher Voltages
• Dual Power Supplies
• Floating Well Designs
• Open Source Signaling
• Other Circuits
– Differential I/O Circuits
– Hysteresis Receivers
• ESD Circuits

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EE382M VLSI-II Class Notes Foil # 36
 Output Impedance Control
• Device “resistances” are too variable for source
termination
– Devices are non-linear
– Variations due to Vdd, Temp, and process variations
alone are >2X in linear region!

• Output stages must be designed to reduce this variation

– On-chip resistors designs
– Logically tunable designs

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EE382M VLSI-II Class Notes Foil # 37
 Impedance Control Using On-Chip Resistors
• Given a precise on-chip resistor, this design provides the
best impedance control

enable

Pad

data

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EE382M VLSI-II Class Notes Foil # 38
 Tunable Impedance Control
• Stacked device settings can be preset or dynamically
controlled

p1 p2 p3

enable Pad
data

n1 n2 n3

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EE382M VLSI-II Class Notes Foil # 39
 Slew Rate Control
• Output stage slew rate is controlled to reduce noise
– Cross talk noise
– Simultaneous switching noise
– Reflections at discontinuities

• Slew rate control is accomplished by controlling the pre-

driver delay and/or pre-driver strength

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EE382M VLSI-II Class Notes Foil # 40
 Slew Rate Control
• Output stage is divided and pre-drive signal is designed to
sequentially arrive at the different sections

δ δ

enable Pad
data

δ δ

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EE382M VLSI-II Class Notes Foil # 41
 Slew Rate Control & Impedance Control
• Pre-driver design might even permit crossover currents to
guarantee impedance even during switching

δ δ

enable Pad
data

δ δ
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EE382M VLSI-II Class Notes Foil # 42
 Feedback Slew Rate Control I/O Buffer

enable
Pad

data

(Motorola 68332, McDermott, Carter)

EE382M VLSI-II Class Notes Foil # 43 The University of Texas at Austin

 Mixed Voltage Designs
• Needed when chips have different supply voltages
• Low voltage circuits can be damaged by high voltage
inputs
• High voltage circuits suffer delay & noise problems when
receiving low voltage signals

Vdd1 Bi-directional Vdd2

I/O Buffers

newer older
technology technology

Vdd1 < Vdd2

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EE382M VLSI-II Class Notes Foil # 44
 Input Design for Higher Voltages
• Modifications for gate oxide & ESD protection

Receiving Same Level Receiving Higher Level

ESD Diodes
ESD Diodes

Pad Pad

change beta ratio

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EE382M VLSI-II Class Notes Foil # 45
 Pass Gate Behavior
• nfet and pfet pass gates can be used to limit voltages

V1
Vdd
V1 - Vtn
0

V1
Vdd

0 V1 - Vtp

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EE382M VLSI-II Class Notes Foil # 46
 Dual Supply Designs
• Separately power I/O circuits at a lower voltage
– No additional process steps required
– Extra design to avoid performance penalty
– ESD & simultaneous switching noise compromised

Vdd1 Bi-directional Vdd1 Vdd2

I/O Buffers

newer older
technology technology

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EE382M VLSI-II Class Notes Foil # 47
 Output Stage at a Lower Voltage
• Slow rising delay due to low overdrive on pfet
• Reduced drive = reduced noise immunity on nand receiver

Vdd2 Vdd1 Vdd1 or Vdd2

ESD Diodes
enable

Pad
data

inhibit

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EE382M VLSI-II Class Notes Foil # 48
 Output Stage at a Lower Voltage
• Improve rising delay with nfet pull up
• Change p/n beta ratio on nand to lower switch point

1.8 Volts 1.2 Volts 1.2 or 1.8 Volts

ESD Diodes
enable

Pad
data

inhibit change beta ratio

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EE382M VLSI-II Class Notes Foil # 49
 Dual Supply Designs
• Separately power the I/O circuits at a higher voltage
– More complicated circuits
– ESD & simultaneous switching noise compromised

1.2 Volts 1.8 Volts Bi-directional 1.8 Volts

I/O Buffers

newer older
technology technology

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EE382M VLSI-II Class Notes Foil # 50
 Output Stage at a Higher Voltage
• Slow rising delay due to low overdrive on pfet
• Reduced drive = reduced noise immunity on nand receiver

Vdd2

Level Vdd2
Shifter
Vdd1

enable Vbias
Pad
data

Vdd1

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EE382M VLSI-II Class Notes Foil # 51
 Floating Well Designs
• Enabled output stage sends lower voltage - Vdd1
• Disabled output stage tolerates higher voltage - Vdd2

Vdd1 Vdd1

enable Vdd1
Pad
data

Vdd1

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EE382M VLSI-II Class Notes Foil # 52
 Open Drain Signaling
• Avoids complexity of multiple chip power supplies
– Off-chip termination resistors pull net up
– On-chip nfet devices pull net down
• Increases transmission line design complexity
• Wired OR functionality

Driving Chip

Vtt Vtt

CL CL CL CL CL

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EE382M VLSI-II Class Notes Foil # 53
 Other Circuits
• Differential I/O Circuits
– Reduces simultaneous switching noise
– Improves receiver common mode noise immunity
– Receives smaller signal levels
– “Pseudo” to full differential possible

• Hysteresis Receivers
– High noise immunity
– Excellent for low-speed asynchronous test & control
signals

• Hold Clamps

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EE382M VLSI-II Class Notes Foil # 54
 Differential Output Buffers

Pseudo Differential Outputs

out
Differential Outputs
out Vdd

out out

Vbias

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EE382M VLSI-II Class Notes Foil # 55
 Differential Transmission Lines

Pseudo = two lines

Zo

Zo
Differential = coupled pair

Zeff < Zo
coupled
Zeff < Zo

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EE382M VLSI-II Class Notes Foil # 56
 Differential Far End Termination

Pseudo Differential Termination

Vtt

R = Zo Vtt

R = Zo
Differential Termination

R = 2 Zo

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EE382M VLSI-II Class Notes Foil # 57
 Differential Receivers

Pseudo Differential Receiver

out
Differential Receiver
out Vdd

out out

Vbias

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EE382M VLSI-II Class Notes Foil # 58
 Self Biased Differential Receiver
• Combines best of nfet and pfet differential receivers

Vdd

Pbias
Vdd

out out
out out

Nbias

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EE382M VLSI-II Class Notes Foil # 59
 Self Biased Differential Receiver
• Combines best of nfet and pfet differential receivers
– Rail to rail output swing
– Excellent common mode noise rejection

Vdd

out
or reference

(Bazes, JSSC 91)

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EE382M VLSI-II Class Notes Foil # 60
 Hysteresis Input Receivers
• Separates rising & fall edge dc transfer curves

weak feedback inverter

Pad Vin
Vout

inhibit
Pad Vin Vout

falling rising
Vout

and only

Vin
EE382M VLSI-II Class Notes Foil # 61 The University of Texas at Austin
 Hold Clamps

• Weak clamps hold tri-stated source terminated nets

weak feedback inverter

Pad
Vdd

I/O

• Stronger clamps will actively terminate the net

– Can be slower than passive termination schemes

EE382M VLSI-II Class Notes Foil # 62 The University of Texas at Austin

 ESD Design
• Pins subjected to ESD (electrostatic discharge) events
during test & handling
• Over-voltages can also occur during functional operation
– System power-on
– Hot-plugging
• ESD discharge can occur between any two pins
– I/O to I/O
– I/O to Vdd or Gnd
• Pins are measured against standard ESD tests
– Human body model
– Machine model
– Charged Device Model
• ESD performance depends on many parameters other
circuits don’t care about

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EE382M VLSI-II Class Notes Foil # 63
 ESD Circuits
• Non-breakdown based circuits Primary ESD Circuit in
– Diodes CMOS Designs
– Bipolar Junction Transistor
– MOS FET

• Breakdown based circuits Most Diode Circuits

– Thick Field Oxide Device are really Bipolar Circuits
– SCR (silicon controlled rectifier)

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EE382M VLSI-II Class Notes Foil # 64
 Dual Diode ESD Circuits

Single Supply Design Mixed voltage design

ESD Diodes
ESD Diodes

Pad Pad

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EE382M VLSI-II Class Notes Foil # 65
 FET ESD Circuits: non-breakdown mode

nfet in “diode”
configuration

ESD Diodes

Pad

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EE382M VLSI-II Class Notes Foil # 66
 FET ESD Circuits: breakdown mode

ESD Diodes

Pad

second
breakdown
I
snapback
nfet protects Vgs > Vt
by clamping voltage
after device snapback
V

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EE382M VLSI-II Class Notes Foil # 67
 Diode ESD Circuits
• fet devices are parasitic npn & pnp bipolar circuits
• vertical pnp device to substrate
• horizontal npn device to guard rings (before trench isolation)
• low vdd to gnd impedance to due on-chip capacitance
provide additional discharge paths

ESD Diodes ESD bipolar devices

Pad Pad

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EE382M VLSI-II Class Notes Foil # 68
 Parasitic Bipolar Circuits
• fet devices are parasitic npn & pnp bipolar circuits
• vertical pnp device to substrate

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EE382M VLSI-II Class Notes Foil # 69
 ESD Test Models
• Human Body Model
– Requirements 2 - 4 kVolts
– Positive or negative discharge between any two pins

R = 1.5 KΩ
VHBM DUT

C = 100 pF

ipeak = VHBM/1500

i(t)

t = 2-10 nsec time

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EE382M VLSI-II Class Notes Foil # 70
 ESD Test Models
• Machine Model
– Requirements 200 - 400 Volts
– Positive or negative discharge between any two pins

L = 0.5 - 0.75 μH

VMM DUT
R < 8.5 Ω

C = 200 pF

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EE382M VLSI-II Class Notes Foil # 71
 ESD Performance Factors
• Diode symmetry is important
– Bipolar conduction increases with temperature
– Hot spots conduct more, heat up more, conduct more,
… and finally burn out
• Layout corners are rounded to reduce electric fields
• Decoupling capacitance needed between all supplies
• Functional performance requirements impose ESD size &
load capacitance constraints
• Parasitic bipolar effects abound
• Breakdown clamps don’t scale

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EE382M VLSI-II Class Notes Foil # 72
 Increasing Bandwidth

EE382M VLSI-II Class Notes Foil # 73 The University of Texas at Austin

 Common Clock Transfers
• Chip to chip transfers controlled by common bus clock
• Equal length card routes to each chip & on-chip PLL’s
minimize clock skew

Chip A

PLL PLL Chip B

clock
source
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EE382M VLSI-II Class Notes Foil # 74
 Common Clock Transfers
Cycle time to meet setup time

max(Tclk - A+TAclk +Tdrive+ Ttof+ Treceive + Tsetup ) - min(TBclk - Tclk - B) < Tcycle

Chip A Tdrive Ttof Treceive Tsetup

TBclk
TAclk PLL
PLL
Chip B
Tclk - A Tclk - B

clock
source
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EE382M VLSI-II Class Notes Foil # 75
 Source Synchronous I/O
• Send source clock with source data
• Resolve clock phase differences with τ1, τ2, & τ3

Chip B
Chip A
τ3

τ1 τ2 PLL
PLL

clock
source
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EE382M VLSI-II Class Notes Foil # 76
 Bus Pumping

• With Ttof > Tcycle, multiple bits are present on the wire

Chip A Chip B
τ3

τ1 τ2 PLL
PLL

clock
source
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EE382M VLSI-II Class Notes Foil # 77
 Dual Data Rate
• Conventional source synchronous design
– Data launched & captured on single clock edge
– Clock switches at f
– Maximium data rate = 1/2 * f
• Dual data rate - if clock can switch at f, why not data?
– Data is launched & captured on both clock edges
– Clock switches f
– Maximum data rate = f

Conventional Dual Data Rate

Clock

Data

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EE382M VLSI-II Class Notes Foil # 78
 Simultaneous Bidirectional Signaling
• Two chips send & receive data simultaneously on a
point to point net
• Waveforms superimpose on the transmission line
• Each chip selects it’s receiver reference voltage based
on the data it sent
• Sending data is subtracted from total waveform

Chip A Chip B

3/4 Vdd 3/4 Vdd

1/4 Vdd 1/4 Vdd

EE382M VLSI-II Class Notes Foil # 79 The University of Texas at Austin

 Pattern Based Driver Compensation
• Incident waveforms along a long-lossy lines attenuate
• Slow “RC” like response to final level

Rs = Zo

Vs τf
where τf = length / velocity

With complex impedance and propagation constant

high speed wavefront decays exponentially

1/2
(1- e-R*length/2Zo)

EE382M VLSI-II Class Notes Foil # 80 The University of Texas at Austin

 Pattern Based Driver Compensation

• Adjust driver strength based on bits sent in earlier

cycles
• Example: When driving low to high
– Drive harder if previous bits sent = 00
– Drive weaker if previous bits sent = 10

Without Compensation With Compensation

1 0 0 1 0 0 1 0 0 1 0 0
Receiver
Switch Point

Drive harder
EE382M VLSI-II Class Notes Foil # 81 The University of Texas at Austin
 Increasing Bandwidth
• Preceding techniques cannot be achieved through
clever circuit design alone
• Requires good packaging technology & net design
– Good termination
– Minimal capacitive & inductive discontinuities
– Low cross-talk
– Low simultaneous switching noise

EE382M VLSI-II Class Notes Foil # 82 The University of Texas at Austin

 SerDes Architecture

EE382M VLSI-II Class Notes Foil # 83 The University of Texas at Austin

 PCI-Express Interface

EE382M VLSI-II Class Notes Foil # 84 The University of Texas at Austin