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TPS54327
SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015
Iout (2 A/div)
100 ms/div
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54327
SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes.......................................... 9
2 Applications ........................................................... 1 8 Application and Implementation ........................ 10
3 Description ............................................................. 1 8.1 Application Information............................................ 10
4 Revision History..................................................... 2 8.2 Typical Application ................................................. 10
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 14
6 Specifications......................................................... 4 10 Layout................................................................... 14
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 14
6.2 ESD Ratings.............................................................. 4 10.2 Layout Examples................................................... 15
6.3 Recommended Operating Conditions....................... 4 10.3 Thermal Considerations ........................................ 17
6.4 Thermal Information .................................................. 5 11 Device and Documentation Support ................. 18
6.5 Electrical Characteristics........................................... 5 11.1 Documentation Support ........................................ 18
6.6 Typical Characteristics .............................................. 6 11.2 Community Resources.......................................... 18
7 Detailed Description .............................................. 7 11.3 Trademarks ........................................................... 18
7.1 Overview ................................................................... 7 11.4 Electrostatic Discharge Caution ............................ 18
7.2 Functional Block Diagram ......................................... 7 11.5 Glossary ................................................................ 18
7.3 Feature Description................................................... 7 12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Removed Ordering Information table .................................................................................................................................... 1
DDA Package
8-Pin HSOP DRC Package
Top View 10-Pin VSON
Top View
1 EN VIN 8 EN 1 10 VIN
4 SS GND 5
Pin Functions
PIN
TYPE DESCRIPTION
NAME HSOP VSON
EN 1 1 I Enable input control. Active high.
VFB 2 2 I Converter feedback input. Connect to output voltage with feedback resistor divider.
5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND.
VREG5 3 3 O
VREG5 is not active when EN is low.
SS 4 4 O Soft-start control. An external capacitor should be connected to GND.
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB
GND 5 5 G
returns to GND at a single point.
SW 6 6, 7 O Switch node connection between high-side NFET and low-side NFET.
Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor
VBST 7 8 I between VBST and SW pins. An internal diode is connected between VREG5 and
VBST.
VIN 8 9, 10 P Input voltage supply pin.
PowerPAD of the package. Must be soldered to achieve appropriate dissipation. Must
PowerPAD Back side — G
be connected to GND.
Exposed
Thermal pad of the package. PGND power ground return of internal low-side FET.
thermal — Back side G
Must be soldered to achieve appropriate dissipation.
pad
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN, EN –0.3 20 V
VBST –0.3 26 V
VBST (10 ns transient) –0.3 28 V
Input voltage VBST (vs SW) –0.3 6.5 V
VFB, SS –0.3 6.5 V
SW –2 20 V
SW (10 ns transient) –3 22 V
VREG5 –0.3 6.5 V
Output voltage
GND –0.3 0.3 V
Voltage from GND to thermal pad, Vdiff –0.2 0.2 V
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
1200 10.0
1000
8.0
800
6.0
600
4.0
400
2.0
200
0 0
-50 0 50 100 150 -50 0 50 100 150
Tj - Junction Temperature - °C Tj - Junction Temperature - °C
Figure 1. VIN Current vs Junction Temperature Figure 2. VIN Shutdown Current vs Junction Temperature
100 100
90 VIN = 18 V
90
80
VOUT = 3.3 V
EN - Input Current - mA
70
80
Efficiency - %
60 VOUT = 2.5 V
70 VOUT = 1.8 V
50
40
60
30
20 50
10
40
0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
0 2 4 6 8 10 12 14 16 18 20 IOUT - Output Current - A
EN - Input Voltage - V
900 900
IO = 1 A
850 850
800
fs - Switching Frequency - kHz
800
fs - Switching Frequency - kHz
VO = 3.3 V VO = 1.8 V
750 750
700 700
500 500
450 450
400 400
0 5 10 15 20 0 0.5 1 1.5 2 2.5 3
VIN - Input Voltage - V IO - Output Current - A
Figure 5. Switching Frequency vs Input Voltage Figure 6. Switching Frequency vs Output Current
7 Detailed Description
7.1 Overview
The TPS54327 device is a 3-A synchronous step-down (buck) converter with two integrated N-channel
MOSFETs. It operates using D-CAP2 mode control. The fast transient response of D-CAP2 control reduces the
output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use
of low ESR output capacitors including ceramic and special polymer types.
EN EN VIN
1
Logic
VIN
8
VREG5
VBST
Control Logic 7
Ref +
SS + PWM
1 shot
VFB SW VO
2 - 6
XCON
ON
VREG5
VREG5 Ceramic
3 Capacitor
SGND
SS SS 5
4 Softstart
GND
PGND
SGND
+ SW
OCP
- PGND
VIN
REF Ref
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
Because the DC gain is dependent on the output voltage, the required inductor value will increase as the output
voltage increases. For higher output voltages above 1.8 V, additional phase boost can be achieved by adding a
feed forward capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for
fSW.
Use 700 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 6.
V V - VOUT
I = OUT x IN(max)
IPP V L x f
IN(max) O SW (4)
I
lpp
I =I +
Ipeak O 2 (5)
2 1 2
I = I + I
Lo(RMS) O 12 IPP (6)
For this design example, the calculated peak current is 3.47 A and the calculated RMS current is 3.01 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of
11 A.
Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: TPS54327
TPS54327
SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 www.ti.com
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54327 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22uF to 68uF. Use Equation 7 to
determine the required RMS current rating for the output capacitor.
VOUT x (VIN - VOUT )
I =
Co(RMS) 12 x VIN x LO x fSW
(7)
For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.271 A and each output capacitor is rated for 4 A.
1.08 1.08
1.07 1.07
VO - Output Voltage - V
VO - Output Voltage - V
VIN = 18 V VIN = 12 V IO = 0 A
VIN = 5 V
1.06 1.06
IO = 1 A
1.05 1.05
1.04 1.04
0 0.5 1 1.5 2 2.5 3 0 5 10 15 20
IO - Output Current - A VI - Input Voltage - V
Figure 8. 1.05-V Output Voltage vs Output Current Figure 9. 1.05-V Output Voltage vs Input Voltage
VREG5 (5 V/div)
Iout (2 A/div)
Figure 10. 1.05-V, 0-A to 3-A Load Transient Response Figure 11. Start-Up Wave Form
SW (5 V/div)
SW (5 V/div)
Figure 12. Voltage Ripple at Output (IO = 3 A) Figure 13. Voltage Ripple at Input (IO = 3 A)
100.0 100.0
90.0 90.0
80.0 80.0
Efficiency (%)
60.0 60.0
40.0 40.0
30.0 30.0
20.0 20.0
10.0 10.0
0.0 0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.001 0.01 0.1 1 10
Output Current (A) Output Current (A)
Figure 14. TPS54327EVM-686 Efficiency Figure 15. TPS54327EVM-686 Light Load Efficiency
10 Layout
VIN VIN
INPUT
BYPASS
CAPACITOR
VIN
HIGH FREQENCY
BYPASS
FEEDBACK CAPACITOR
RESISTORS
TO ENABLE
CONTROL EN VIN
BOOST
VFB VBST CAPACITOR
VREG5 SW
BIAS SS GND
OUTPUT
INDUCTOR
VOUT
CAP
SLOW
START
CAP
EXPOSED
THERMAL PAD
Connection to
AREA OUTPUT
POWER GROUND FILTER
on internal or CAPACITOR
bottom layer
ANALOG
GROUND
TRACE
POWER GROUND
VIN VIN
INPUT
BYPASS
CAPACITOR
VIN
FEEDBACK
HIGH FREQENCY
RESISTORS BYPASS
TO ENABLE
CONTROL EN VIN CAPACITOR
VFB VIN
VREG5 VBST
BOOST
CAPACITOR
BIAS
CAP SS SW VOUT
SLOW
START GND SW OUTPUT
CAP
INDUCTOR
EXPOSED OUTPUT
THERMAL PAD FILTER
AREA
ANALOG
Connection to
CAPACITOR
GROUND
TRACE POWER GROUND
on internal or
bottom layer
POWER GROUND
11.3 Trademarks
D-CAP2, E2E are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 1-Mar-2017
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TPS54327DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS CU NIPDAU | CU SN Level-2-260C-1 YEAR -40 to 85 54327
& no Sb/Br)
TPS54327DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS CU NIPDAU | CU SN Level-2-260C-1 YEAR -40 to 85 54327
& no Sb/Br)
TPS54327DRCR ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 54327
& no Sb/Br)
TPS54327DRCT ACTIVE VSON DRC 10 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 54327
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 1-Mar-2017
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jan-2016
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jan-2016
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
GENERIC PACKAGE VIEW
DRC 10 VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204102-3/M
PACKAGE OUTLINE
DRC0010J SCALE 4.000
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
3.1 B
A
2.9
1.0 C
0.8
SEATING PLANE
0.05
0.00 0.08 C
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED 4X (0.25)
THERMAL PAD
5 6
2X 11 SYMM
2
2.4 0.1
10
1
8X 0.5 0.30
10X
0.18
PIN 1 ID SYMM
0.1 C A B
(OPTIONAL)
0.5 0.05 C
10X
0.3
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
SYMM (2.4)
(3.4)
(0.95)
8X (0.5)
5 6
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND
EXPOSED METAL
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
11 TYP
10X (0.6)
1
10
(1.53)
10X (0.24) 2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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