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Circuit Characterization
and Performance
Estimation

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Resistance Estimation
• The resistance of uniform slab of
conducting material may be defined as
   l 
R    
 t  w 
where   resistivity
t  thicknes
l  conductor length
w  conductor width
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Resistance Estimation
• It also can be given as

l 
R  RS  
 w
where Rs is the sheet resistance having
units of Ω/square

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Resistance Estimation
• Thus to obtain the resistance of a
conductor on a layer, multiply the sheet
resistance Rs by the ratio of the length to
width of the conductor

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Resistance Estimation
• The
resistances
are equivalent
since the ratio
of length to
width is equal

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Resistance Estimation
• Typical
sheet
resistances

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Resistance Estimation
• The channel resistance may be given by

L
Rc  k  
W 
1
Where k 
cox Vgs  Vt 
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Resistance Estimation
• Resistance
of non-
rectangular
regions

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Resistance Estimation
• Resistance
of non-
rectangular
regions

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Resistance Estimation
• Table 4.2

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Resistance Estimation
Contacts and via resistance
• The resistance associated with them is
dependent on the contacted materials and
proportional to the area of the contact
• Reducing the contact size will increase the
resistance
• Typical range: 0.25 to few tens of Ωs
• For low resistance interlayer connections
multiple contacts are used
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Capacitance Estimation
• Dynamic response depends upon parasitic
capacitances
• Interconnection capacitances are formed
by metal, poly, and diffusion wires
• Total capacitance consists of
– Gate capacitance
– Diffusion capacitance
– Routing capacitance

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MOS Capacitor Characteristics


• The capacitance - voltage characteristics
of MOS capacitor depend on the state of
the semiconductor surface
• The surface may be in
– Accumulation
– Depletion
– inversion

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MOS Capacitor Characteristics


• MOS capacitance
accumulation depletion

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MOS Capacitor Characteristics


• The accumulation layer is formed when
Vg< 0
• The negative charge on the gate attracts
holes toward silicon surface
• The MOS structure behaves like a parallel-
plate capacitor
  SiO2  0 
• The gate capacitance is CO    A
 tox 
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MOS Capacitor Characteristics


• When a small positive voltage is applied to
the gate with respect to the substrate, a
depletion layer is formed in the p-substrate
directly under the gate
• The positive gate voltage repels holes,
leaving a negatively charged region
depleted of carriers

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MOS Capacitor Characteristics


• The charge density is proportional to
– Doping concentration, N
– Charge, q
– Depth of depletion region, d
– Gate to source voltage, increases

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MOS Capacitor Characteristics


• The depletion capacitance is given by

  o Si 
Cdep   A
 d 
where d  depletion layer depth
 Si  dielectric cons tan t of silicon, 12

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MOS Capacitor Characteristics


• As the depth of depletion region increases,
the capacitance from gate to substrate will
decrease
• The total capacitance is given by

CoCdep
C gb 
Co  Cdep

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MOS Capacitor Characteristics


Inversion As function of Vgs

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MOS Capacitor Characteristics


• Increasing gate voltage, creates n channel
thereby increasing conductivity
• Surface inversion restores low frequency
capacitance Co
• The dynamic capacitance remains the
same as for the maximum depletion
situation

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MOS Capacitor Characteristics


• The capacitance may be given by

Cgb = CO Low frequency

CoCdep
C gb   Cmin High frequency
Co  Cdep

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MOS device Capacitance


• Parasitic capacitance for an MOS trasistor

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MOS device Capacitance


• Cgs, Cgd = gate to channel, lumped at the
source and the drain regions of the
channel respectively
• Csb, Cdb = source and drain capacitances
to bulk / substrate
• Cgb = gate to bulk capacitance
• The total gate capacitance is
Cg = Cgb + Cgs + Cgd
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MOS device Capacitance


Off region
• for Vgs< Vt when MOS device is off, no
channel
• Cgs = Cgd = 0
• Cgb can be modeled as the series
combination of the two capacitors (Co and
Cdep)

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MOS device Capacitance


Non-saturation region
• for Vgs - Vt > Vds channel formation takes
place
• Cgs and Cgd are now significance
• These capacitances are dependent on
gate voltage
• Their value may be estimated

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MOS device Capacitance

1   SiO2  0 
C gd  C gs    A
2  tox 

• Cgb effectively fall to zero

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MOS device Capacitance


• Circuit symbols for parasitic capacitances

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MOS device Capacitance


Saturation region
• for Vgs - Vt < Vds channel is heavily inverted
• Drain region of the channel is pinched off
• Cgd = 0
• Cgs increases to approximately to

2   SiO2  0 
  A
3  tox 
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MOS device Capacitance


• Approximation of intrinsic MOS gate
capacitance

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