BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI

(PILANI, K.K.BIRLA GOA CAMPUSES)

II SEMESTER 2017-18
MEL G642 VLSI ARCHITECTURE 06-03-2018
Mid Sem Exam (CLOSED BOOK) MM:20 Duration 90 min
Q1. (a) What is a Carry select adder?
(b) Supposing you have fast 8 bit adder available to you as a building block, using this building
block and the carry select adder architecture, design the fastest possible 32 bit adder. [1M+3M]
Q2. With the help of schematic diagram explain the two different strategies used for register control
logic design in a CISC microprocessor.[4M]

Q3. With reference to the execution unit block diagram and associated rules of operation (given at
the end of the paper) write level 2 flowcharts for
(a) Address mode sequence for Register Indirect with displacement addressing mode
[Ry+d]@].Clearly state the assumptions you are making.
(b) A common sequence that can implement register to register instructions ADD, SUB and AND.
[3M+3M]
Q4. A CISC instruction set contains a powerful instruction that can test all the elements of a one
dimensional array and return the total count of non-zero elements of the array. RX field in the
instruction word specifies the register that contains the array size (number of elements in the array);
RY field specifies the register into which the count of non-zero elements of the array is returned by
the instruction. Elements of the array are stored in the memory at successive addresses starting
from the absolute address specified in the extension word of the instruction. At the end of the
execution of instruction value of Rx will be Zero

Write level 2 flowcharts for the instruction using the execution unit schematic diagram and rules of
operation given at the end of the QP. [6M]

Rules of Operation for the Execution Unit:

1. A transfer from source to bus to destination takes one state time
2. A source can drive up to three destination loads
3. Inputs to the ALU are from the A internal bus and either K (values 0, +1, -1) or the B internal
bus
4. When the ALU is a destination, T1 is automatically loaded from the ALU output
5. A transfer to AO activates the on-chip external bus controller
6. ALU supports addition and subtraction (B input – A input) operations on 2’s complement
binary integers, and can set condition codes reflecting condition of the ALU
result:V(arithmetic overflow), N(ALU result negative), Z(ALU result zero) when desired, or
leave the condition codes unaltered if so desired.
7. All memory addresses are represented as positive integers in 2’s complement binary
representation