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MEL G642
Memory addressing
MEL G642
Memory addressing
MEL G642
Memory addressing modes
MEL G642
Inputs
Memory addressing circuit in
Register File/Control
path (Instruction
Decoder) Address
calculation
Addressing feedback
logic circuit
Initial
general
Keeper
MEL G642
address
Control path/Instruction
Decoder
Combinational
output
Address pointer
Registered
output
MEL G642
Memory addressing circuit in
general
MEL G642
MEL G642
General addressing circuits
MEL G642
General addressing circuits
MEL G642
General addressing circuits
MEL G642
Modulo addressing of FIFO buffer
MEL G642
Hardware Accelerated Memory Addressing
MEL G642
Modulo++ addressing circuit
MEL G642
Modulo-- addressing circuit
MEL G642
Bit-Reversed Addressing
Given a buffer size of 8, an index register set to 4, and an initial
pointer set to 0x100, the sequence of accesses to the buffer is shown in
Table
MEL G642
Bit-Reversed Addressing
Few restrictions are required to use this method
MEL G642
RF fundamentals
MEL G642
Datapath in a DSP processor
RF ALU MAC
Control path (CP)
DM1 DM2
PM
AGU1 AGU2
MEL G642
General register file
MEL G642
General register file
MEL G642
Register file
MEL G642
Write circuit Read circuit
reg_select
RF: register file
MEL G642
Store circuit
MEL G642
Physical design: Gate count problem
MEL G642
Physical design: fan-in fan-out problem
Selected operand
MEL G642
How to manage critical path
MEL G642
Special registers in general register file
Specific
function
A general register in a register file
MEL G642
Special registers in general register
Address
calculation
logic for a
special register
MEL G642
file
MEL G642
Special function registers are in RF?
MEL G642
Special function registers are in RF?
MEL G642
RF multiple data write
MEL G642
The End :: Thank you for your attention
Questions?
MEL G642
Flip flop made up of 10 gates using Transmission gate
logic
MEL G642
Operand selection is implemented using complimentary
pass transistor logic.
PMOS used to eliminate the
need for inverter to generate S’
MEL G642
Similarly 32:1 and 16:1 can be built.
Each 2:1 mux require 2 transistor.
For 32:1 mux using 2:1 no of levels required is 5.
Therefore gate count is for 32:1 mux is (32+16+8+4+2)
The final stage will have a level restorer transistor which accounts for an extra gate.
Output buffer so
not counted
Driving buffers tends to depend on the load capacitance to be driven and number of stages used for it.
MEL G642