ME 515 Mechatronics 10/5/2006

ME 515 Mechatronics

Digital Electronics
Asanga Ratnaweera
Department of Mechanical Engineering
Faculty of Engineering
University of Peradeniya
Tel: 081239 (3627)
Email: asangar@pdn.ac.lk

Introduction to Digital
Electronics
„ Digital circuits are evolved from
transistor circuits being able to output at
one of the two voltage levels depending on
the levels at its inputs.
„ The two levels, usually 0 or 5 V are the
low and high signals and represented by
0 and 1.
„ Therefore, binary number system is
widely used with digital circuitry.

5 October 2006 Asanga Ratnaweera, Department of 2

Mechanical Engineering

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ME 515 Mechatronics 10/5/2006

Boolean Expressions, Logic

Gates & Truth Tables
A B Z
0 0 0
Z = A.B AND 0 1 0
1 0 0
1 1 1
A B Z
0 0 0
Z = A+B OR 0 1 1
1 0 1
1 1 1

Z = A⊕B
A
Z
B XOR

A Z

Z=A NOT 0 1
1 0

5 October 2006 Asanga Ratnaweera, Department of 3

Mechanical Engineering

Boolean Expressions, Logic

Gates & Truth Tables
A B Z
Z = A+B NOR 0 0 1
0 1 0
1 0 0
1 1 0

F = AB NAND

F=A F
BUF

5 October 2006 Asanga Ratnaweera, Department of 4

Mechanical Engineering

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Commercial Logic ICs

+Vcc
+Vcc
14 13 12 11 10 9 8
14 13 12 11 10 9 8

7408 7432

1 2 3 4 5 6 7
1 2 3 4 5 6 7
Gnd
G nd
(0 V )
(0 V )

5 October 2006 Asanga Ratnaweera, Department of 5

Mechanical Engineering

Logic Families
Description TTL CMOS
Code 74XX, 74LSXX 40XX or 74HCXX
Supply voltage 4.75-5.25 V 5-15 V
Max. supply current -100 mA -0.02 mA
Input Output Input Output
0 state Voltage / V 0.8 0.5 1.5 0.05
Current / mA -0.4 8 -0.0001 0.5
1 state Voltage / V 2.0 2.7 3.5 V 4.95
Current / mA 0.02 -0.4 0.0001 -0.2
Max. Op. frequency 33 MHz 10 MHz
Active power Cons. 8 mW 0.1 mW
5 October 2006 Asanga Ratnaweera, Department of 6
Mechanical Engineering

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Classification of Digital
circuits
„ Digital electronics is classified as:
{ Combinational logic circuits
„ Combination logic output depends only
on the inputs levels.
{ Sequential logic circuits.
„ The output of sequential logic depends
on both stored levels and the input levels.
Therefore, sequential logic is capable of
“remembering” a particular state.

5 October 2006 Asanga Ratnaweera, Department of 7

Mechanical Engineering

Combinational logic circuits

A B C Z Z = A.B.C
0 0 0 0
0 0 1 0
Z = A.B.C
0 1 0 0
0 1 1 0
1 0 0 0 Therefore;
1 0 1 1

1 1 0 0
Z = A.B.C or A.B.C
1 1 1 1
Z = A.B.C + A.B.C
Truth Table

5 October 2006 Asanga Ratnaweera, Department of 8

Mechanical Engineering

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Combinational logic circuits

„ Producing Boolean expressions from truth
table:
{ Find the 1s in the Z column
{ Write the Boolean expression for each 1( logic high
output)
{ Write the expressions out in words, e.g. Z = ( A AND
NOT B AND C) OR (A AND B AND C)
{ Write out the inputs, e.g. A , B C
{ Draw in any NOT gates
{ Draw in the AND gates
{ Finally draw in the OR gates if required

5 October 2006 Asanga Ratnaweera, Department of 9

Mechanical Engineering

Combinational logic circuits

A B C Z
0 0 0 0
0 0 1 0 Z = A.B.C + A.B.C
0 1 0 0
0 1 1 0
1 0 0 0 A
1 0 1 1

1 1 0 0
B
Z
1 1 1 1 C

5 October 2006 Asanga Ratnaweera, Department of 10

Mechanical Engineering

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ME 515 Mechatronics 10/5/2006

Combinational logic circuits

„ Pin-out Diagrams & Drawing Circuits
{ You must be able to select suitable logic ICs
(chips) and draw in the connections for a
given logic system. An example is given
below. Don’t forget to draw in the
connections for +Vcc ( the positive supply
voltage) and 0v.
{ Remember you don’t need to use all the
logic gates in a chip – if you only need
one, you only use one!

5 October 2006 Asanga Ratnaweera, Department of 11

Mechanical Engineering

Combinational logic circuits

+Vcc

+Vcc +Vcc
14 13 12 11 10 9 8 14 13 12 11 10 9 8

7408 7432

1 2 3 4 5 6 7 1 2 3 4 5 6 7
Gnd Gnd
(0V) (0V)
Input A OUTPUT

Input B

0v

5 October 2006 Asanga Ratnaweera, Department of 12

Mechanical Engineering

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Combinational logic circuits

„ Boolean simplification
{ De Morgan’s theorem

x• y = x+ y
x+ y = x• y
{ Karnaugh Map
„ A grid of 2N squares where N is the number of input
variables in the Boolean expressions.
„ K-maps are usually used for minimization expressions
with six or fewer variables
5 October 2006 Asanga Ratnaweera, Department of 13
Mechanical Engineering

Combinational logic circuits

„ Ex: For three variables

{ Each square represents one minterm

{ Only one variable changes between adjacent squares
{ The maps are constructed to “wrap” around so that
top and bottom corresponding squares are adjacent

5 October 2006 Asanga Ratnaweera, Department of 14

Mechanical Engineering

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Combinational logic circuits

For two variables

For four variables
24 = 16

5 October 2006 Asanga Ratnaweera, Department of 15

Mechanical Engineering

Combinational logic circuits

„ Filling out K-Map

0 0 1 0

0 1 1 1

The adjacent squares that have “1”s are combined in groups of 2, 4

or 8.
When squares can be chosen as several groups, the largest group
has to be selected and each square should be used only once
5 October 2006 Asanga Ratnaweera, Department of 16
Mechanical Engineering

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Combinational logic circuits

BC
„ Identify the variables
which do not change
0 0 1 0 within the cluster and
0 1 1 1 write them down as a
Boolean expression
AC AB

X = BC +AC + AB

5 October 2006 Asanga Ratnaweera, Department of 17

Mechanical Engineering

Combinational logic circuits

„ More examples
CD
AB 00 01 11 10
00 1 0 1 1
01 0 0 1 0
11 0 0 1 0
10 1 1 1 1

5 October 2006 Asanga Ratnaweera, Department of 18

Mechanical Engineering

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Design of Combination
Logic circuits
„ Ex:
{ Three push buttons are provided to turn on
a machine in an automobile assembly plant.
For safety purposes, the machine is to be
turned on, only if at least two of the
buttons are pushed. Obtain a suitable Logic
Circuit.

5 October 2006 Asanga Ratnaweera, Department of 19

Mechanical Engineering

Applications of
Combinational circuits
„ Adders / substructures

Half adder

Full adder
5 October 2006 Asanga Ratnaweera, Department of 20
Mechanical Engineering

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Applications of
Combinational circuits
„ Encoders
{ A binary encoder generates a binary code
corresponding to the input value presented
at its inputs

Ex: 8 bit encoder

If 5 is pressed, binary
number 0000 0101 should
be generated at the
output of the encoder

5 October 2006 Asanga Ratnaweera, Department of 21

Mechanical Engineering

Applications of
Combinational circuits
„ Encoders

5 October 2006 Asanga Ratnaweera, Department of 22

Mechanical Engineering

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Applications of
Combinational circuits
„ Decoders
{ A binary decoder converts binary information
to discrete outputs.

5 October 2006 Asanga Ratnaweera, Department of 23

Mechanical Engineering

Applications of
Combinational circuits
„ Decoders

5 October 2006 Asanga Ratnaweera, Department of 24

Mechanical Engineering

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Applications of
Combinational circuits
„ Multiplexers
{ A multiplexer selects binary information
from one of many input lines and directs it
to a single output line.

5 October 2006 Asanga Ratnaweera, Department of 25

Mechanical Engineering

Applications of
Combinational circuits
„ Multiplexers

5 October 2006 Asanga Ratnaweera, Department of 26

Mechanical Engineering

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Applications of
Combinational circuits
„ De-multiplexers
{ A de-multiplexer receives binary information on
a single input line and passes this information
to one of its many output lines.

5 October 2006 Asanga Ratnaweera, Department of 27

Mechanical Engineering

Sequential logic circuits

„ The output of a sequential logic device
depends on its present internal state and
the present inputs.
{ Sequential logic device has some kind of
memory of at least part of its ``history'' (i.e., its
previous inputs).
„ The memory elements in a sequential
circuit are called flip-flops.

5 October 2006 Asanga Ratnaweera, Department of 28

Mechanical Engineering

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Flop-Flops
„ A flip-flop circuit can be constructed
from two NAND gates or two NOR gates.

5 October 2006 Asanga Ratnaweera, Department of 29

Mechanical Engineering

Flop-Flops
„ Clocked SR Flip-Flop
{ Information from the S and R inputs passes through to
the basic flip-flop only when the clock pulse goes to 1.
With both S=1 and R=1, the occurrence of a clock pulse
causes both outputs to momentarily go to 0.

5 October 2006 Asanga Ratnaweera, Department of 30

Mechanical Engineering

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Flop-Flops
„ D Flip-Flop

{ The D input goes directly into the S input and the

complement of the D input goes to the R input. The D
input is sampled during the occurrence of a clock pulse.
If it is 1, the flip-flop is switched to the set state (unless
it was already set). If it is 0, the flip-flop switches to the
clear state.

5 October 2006 Asanga Ratnaweera, Department of 31

Mechanical Engineering

Flop-Flops
„ JK Flip-Flop
{ A JK flip-flop is a refinement of the SR flip-
flop in that the indeterminate state of the
SR type is defined in the JK type.

5 October 2006 Asanga Ratnaweera, Department of 32

Mechanical Engineering

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Flop-Flops
„ T Flip-Flop
„ The T flip-flop is a single input version
of the JK flip-flop. The output of the T
flip-flop "toggles" with each clock pulse.

5 October 2006 Asanga Ratnaweera, Department of 33

Mechanical Engineering

Flop-Flops
„ Triggering of Flip-flops
{ The clock pulse goes through two signal
transitions: from 0 to 1 and the return from
1 to 0. The positive transition is defined as
the positive edge and the negative
transition as the negative edge. These flip-
flops are termed edge-triggered flip-flops

5 October 2006 Asanga Ratnaweera, Department of 34

Mechanical Engineering

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Triggering of Flip-flops
„ Edge-triggered flip-flops

Ex: Positive edge triggered SR flip-flop

Truth table Timing diagram

5 October 2006 Asanga Ratnaweera, Department of 35
Mechanical Engineering

Triggering of Flip-flops
„ Level-triggered flip-flops
{ Level-triggered flip-flops respond to their inputs
while the clock signal is at a high level and retain
their output values after the level change

Truth table
Timing diagram

5 October 2006 Asanga Ratnaweera, Department of 36

Mechanical Engineering

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Clock pulse generation

„ 555 timer

5 October 2006 Asanga Ratnaweera, Department of 37

Mechanical Engineering

Clock pulse generation

5 October 2006 Asanga Ratnaweera, Department of 38

Mechanical Engineering

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Clock pulse generation

„ 555 timer
{ T = 0.7 × (R1 + 2R2) × C1
{ f = 1.4
(R1 + 2R2) × C1
T = time period in seconds (s)
f = frequency in hertz (Hz)
R1 = resistance in ohms ( )
R2 = resistance in ohms ( )
C1 = capacitance in farads (F)
{ The time period can be split into two parts:
„ T = Tm + Ts
Mark time (output high): Tm = 0.7 × (R1 + R2) × C1
Space time (output low): Ts = 0.7 × R2 × C1

5 October 2006 Asanga Ratnaweera, Department of 39

Mechanical Engineering

Clock pulse generation

„ 555 timer

5 October 2006 Asanga Ratnaweera, Department of 40

Mechanical Engineering

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Flop-Flop ICs
„ Flip-flops are commercially available as
IC packages

5 October 2006 Asanga Ratnaweera, Department of 41

Mechanical Engineering

State Machine
„ A state machine is a device that stores
the status of something at a given time
and can operate on input to change the
status and/or cause an action or
output to take place for any given
change.
{ Ex: computer.

5 October 2006 Asanga Ratnaweera, Department of 42

Mechanical Engineering

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State Machine
„ Ex: Design of a modulo-4 up-down
counter
{ State transition diagram

1
00 01
0

0 0 1
1

11 0 10

5 October 2006 Asanga Ratnaweera, Department of 43

Mechanical Engineering

Design of an up-down
counter
„ Ex: Design of a modulo-4 up-down counter
{ State Table
Input Current Current Next state Next state
x state / q1 state / q2 / Q1 / Q2

0 0 0 1 1
0 0 1 0 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 1
1 1 1 0 0
5 October 2006 Asanga Ratnaweera, Department of 44
Mechanical Engineering

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Design of an up-down
counter
„ Ex: Design of a modulo-4 up-down counter
{ State Transition Table with SR flip flops

x q1 q2 Q1 Q2 S1 R1 S2 R2

0 0 0 1 1 1 0 1 0
0 0 1 0 0 0 d 0 1
0 1 0 0 1 0 1 1 0
0 1 1 1 0 d 0 0 1
1 0 0 0 1 0 d 1 0
1 0 1 1 0 1 0 0 1
1 1 0 1 1 d 0 1 0
1 1 1 0 0 0 1 0 1
5 October 2006 Asanga Ratnaweera, Department of 45
Mechanical Engineering

Design of an up-down
counter
„ Use K-maps for simplification

5 October 2006 Asanga Ratnaweera, Department of 46

Mechanical Engineering

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Design of an up-down
counter
„ Logic circuit

5 October 2006 Asanga Ratnaweera, Department of 47

Mechanical Engineering

Applications of Digital
Electronics
„ Binary counters

5 October 2006 Asanga Ratnaweera, Department of 48

Mechanical Engineering

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Applications of Digital
Electronics
„ Decade counters
{ Use to perform binary
counting
{ A negative edge-triggered
counter and the output is
binary coded decimal
(BCD) consists of four
bits.
{ Ex: LS 7490 IC

Output sequence
5 October 2006 Asanga Ratnaweera, Department of 49
Mechanical Engineering

Applications of Digital
Electronics
„ Decade counters
{ Timing diagram

Remember: this is a negative edge-triggered counter

5 October 2006 Asanga Ratnaweera, Department of 50

Mechanical Engineering

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Applications of Digital
Electronics
„ Decade counters
{ BCD counters can be cascaded in order to count in powers
of 10.
{ Output D can be used as the clock input for the second
decade counter (7490)
{ Cascading two together in order to raise the range for
counting from 0 to 99.

5 October 2006 Asanga Ratnaweera, Department of 51

Mechanical Engineering

Applications of Digital
Electronics
„ Decade counters

Note:IC 7447 negative logic seven segment LED code

(LED Switches ON when output is low)
5 October 2006 Asanga Ratnaweera, Department of 52
Mechanical Engineering

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Applications of Digital
Electronics
„ Data registers

5 October 2006 Asanga Ratnaweera, Department of 53

Mechanical Engineering

Applications of Digital
Electronics
„ Serial & Parallel Interfaces

5 October 2006 Asanga Ratnaweera, Department of 54

Mechanical Engineering

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Applications of Digital
Electronics
„ Serial & Parallel Interfaces

5 October 2006 Asanga Ratnaweera, Department of 55

Mechanical Engineering

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