DESIGN OF TRAFFIC LIGHT CONTROLLER USING FPGA

module Traffic
(
input [4:0] nsCounter,
input [3:0] ewCounter,
input [1:0] yellowCounter,
input NS_VEHICLE_DETECT,
input EW_VEHICLE_DETECT,
output reg NS_RED,
output reg NS_YELLOW,
output reg NS_GREEN,
output reg EW_RED,
output reg EW_YELLOW,
output reg EW_GREEN
);

// Sets the start state at: 001100

initial begin
NS_RED <= 0;
NS_YELLOW <= 0;
NS_GREEN <= 1;
EW_RED <= 1;
EW_YELLOW <= 0;
EW_GREEN <= 0;
end

always @ (nsCounter) begin

// Sets the start state at: 010100
if (nsCounter == 31 & EW_VEHICLE_DETECT & NS_GREEN) begin
NS_RED <= 0;
NS_YELLOW <= 1;
NS_GREEN <= 0;
EW_RED <= 1;
EW_YELLOW <= 0;
EW_GREEN <= 0;
end
end

// Sets the start state at: 100010

always @ (ewCounter) begin
if (ewCounter == 15 & EW_GREEN) begin
NS_RED <= 1;
NS_YELLOW <= 0;
NS_GREEN <= 0;
EW_RED <= 0;
EW_YELLOW <= 1;
EW_GREEN <= 0;
 end
end

// Sets the start state at: 001100

always @ (yellowCounter) begin
if (yellowCounter == 3 & NS_YELLOW) begin
NS_RED <= 1;
NS_YELLOW <= 0;
NS_GREEN <= 0;
EW_RED <= 0;
EW_YELLOW <= 0;
EW_GREEN <= 1;
end

// Sets the start state at: 100001

if (yellowCounter == 3 & EW_YELLOW) begin
NS_RED <= 0;
NS_YELLOW <= 0;
NS_GREEN <= 1;
EW_RED <= 1;
EW_YELLOW <= 0;
EW_GREEN <= 0;
end
end
endmodule

/*
A Counter for the North-South Traffic Light
Counts from 0-31
*/
module nsCounter
(
input clk,
output [4:0] count
);

wire clk;
reg[4:0] count;

initial
count = 0;

always @ ( negedge clk )

count[0] <= ~count[0];

always @ ( negedge count[0] )

count[1] <= ~count[1];
 always @ ( negedge count[1] )
count[2] <= ~count[2];

always @ ( negedge count[2] )

count[3] <= ~count[3];

always @ ( negedge count[3] )

count[4] <= ~count[4];

endmodule

/*
A Counter for the East-West Traffic Light
Counts from 0-15
*/
module ewCounter
(
input clk,
output [3:0] count
);

wire clk;
reg[3:0] count;

initial
count = 0;

always @ ( negedge clk )

count[0] <= ~count[0];

always @ ( negedge count[0] )

count[1] <= ~count[1];

always @ ( negedge count[1] )

count[2] <= ~count[2];

always @ ( negedge count[2] )

count[3] <= ~count[3];

endmodule

/*
A Counter for the common yellow Traffic Light
Counts from 0-3
*/
module yellowCounter
(
input clk,
output [1:0] count
);

wire clk;
reg[1:0] count;

initial
count = 0;

always @ ( negedge clk )

count[0] <= ~count[0];

always @ ( negedge count[0] )

count[1] <= ~count[1];

endmodule
 SCHEMATIC ENTRY AND SPICE SIMULATION OF CMOS NOT GATE
Procedure:

1. Open S-Edit window.

2. Go to File  New  New design
3. Go to Cell New View
4. Add libraries file to the New Cell.
5. Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.
8. Observe DC inputs and outputs by giving appropriate inputs.
Schematic Diagram:

Fig (a): CMOS Inverter

Tanner Spice Code:

* SPICE export by: SEDIT 13.12

* Export time: Fri Mar 16 11:43:07 2019

* Design: adm705-1

* Cell: Cell3

* View: view0

* Export as: top-level cell

* Export mode: hierarchical

* Exclude .model: no

* Exclude .end: no

* Expand paths: yes

* Wrap lines: no

* Root path: C:\Documents and Settings\Administrator\Desktop\adm705-1

* Exclude global pins: no

* Control property name: SPICE

********* Simulation Settings - General section *********

.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools

v13.1\Libraries\Models\Generic_025.lib" TT

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER > 0 --------

MNMOS_1 Out N_2 Gnd N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MPMOS_1 Out N_2 Vdd N_3 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

VVoltageSource_1 Vdd Gnd DC 5

VVoltageSource_2 N_2 Gnd PULSE(0 5 0 5n 5n 95n 200n)

.PRINT TRAN V(Out)

.PRINT TRAN V(N_2)

********* Simulation Settings - Analysis section *********

.tran 350ns 500ns

.dc lin source VVoltageSource_1 0 5 0.5

.print dc v(MNMOS_1,Gnd)

********* Simulation Settings - Additional SPICE commands *********

.end
Output responses:
Schematic Diagram:

Fig(a): Differential Amplifier Schematic

Tanner Spice Code:

********* Simulation Settings - General section *********

.lib "C:\Documents and Settings\user11\My Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib " TT

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER > 0 --------

RResistor_1 Vdd N_5 R=50
RResistor_2 Vdd N_7 R=50
MNMOS_1 N_5 N_2 N_3 N_4 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 N_7 N_1 N_3 N_6 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_2 Vdd Gnd DC 5
VVoltageSource_3 N_2 Gnd PULSE(0 5 0 5n 5n 95n 200n)
VVoltageSource_5 Gnd pos_PortNotFound_0 PULSE(0 5 0 5n 5n 95n 200n)
ICurrentSource_1 N_3 Gnd DC 5u
.PRINT TRAN V(N_2)
.PRINT TRAN V(N_7)
.PRINT TRAN V(N_1)
.PRINT TRAN V(N_5)

********* Simulation Settings - Analysis section *********

*.tran 5ns 500ns
.dc lin source vvoltagesource_3 -3 3 1
.print dc i(mnmos_2,n_7) i(mnmos_1,n_5)

********* Simulation Settings - Additional SPICE commands *********

.end
Output responses:

Fig (b): Differential Amplifier Waveforms

Result:

The differential amplifier is constructed in Tanner EDA v13.1, the spice code is
generated and wave forms are verified.
 FPGA SYNTHESIS, PLACEMENT & ROUTING AND POST-PLACEMENT & ROUTING SIMULATION

OUTPUT WAVEFORM