A P P L I C A T I O N N O T E

SystemVerilog
Versus
OpenVera

Stephen Bailey
Mentor Graphics
Version 0.3, 28 June 04

w w w. m e n t o r. c o m
Introduction
The inspiration for many of the new language capabilities in SystemVerilog has come from
proprietary hardware verification languages (HVL) such as Vera and e, especially the former.
Therefore, it is understandable that people may be prone to assume that the assertion and verifi-
cation capabilities in SystemVerilog are identical to those of OpenVera. Although there are many
similarities, the two languages are different. If they were identical, it would be possible to suc-
cessfully compile and simulate Vera source code in any simulator that supports SystemVerilog.
Of course, this is not true, and anyone who believes otherwise will be unpleasantly surprised.
How SystemVerilog differs from OpenVera™ is the topic of this paper.

SystemVerilog Assertions versus OpenVera Assertions

Unless otherwise indicated, in this paper, the terms assertion and assertions refer to all directives
(assert, assume, and cover).

Assertions
Inline Specification
SystemVerilog assertions (SVA) can be placed inline (concurrently or procedurally), or they may
be organized with or within interfaces, modules and, to a limited extent, packages. OpenVera
Assertions™ (OVA) do not support inline specification of assertions.1 OVA must be packaged in
units (as discussed below).
In effect, SystemVerilog supports specification of assertions both inline and in separate files.
OVA only supports the specification of assertions in a separate source file.

Packaging
In SystemVerilog, assertions are defined within module or generate regions as a concurrent
statement. That is, they are located within modules.
In OVA, the cover directives are located in OVA units. An OVA unit looks like a Verilog module
except the module/endmodule keywords are replaced by the unit/endunit keywords and the port
declarations use the Verilog ANSI style.

SystemVerilog Versus OpenVera 1

 Binding
OVA requires a binding of a unit to a module in the de-sign. Therefore, each OVA unit used in
verification will have one or more bind specifications. SystemVerilog does not require a binding
but provides a bind construct to facilitate separation of design from verification. Furthermore,
there are differences in the semantics of the binding.

Syntactic differences:
SVA:
bind 2module_or instance block_with_props inst_name ( ports ) ;

OVA:
bind module module_name : instance_name ( ports ) ;
bind instances inst1, inst2, …, instN : instance_name ( ports ) ;

Assert
There are syntactic differences between SVA and OVA assert directives. The most obvious difference
is the lexical order of the assertion name and the assert keyword. The OVA message, severity, and
category do not exist in SVA. SVA has an action block that can specify statements on pass or fail
conditions. Finally, OVA supports built-in formulae meant for use with formal verification. SVA
does not support these formulae.

SVA:
<name> : assert ( <expression> ) [ <action_block> ] ;

OVA:
assert <name> : builtin_formula ( <seq_expr> [, message [, severity [, category ]]] ) ;

Cover
The syntax between SVA and OVA cover directives is also different. The 2.3 version of the
OpenVera Language Reference Manual: Assertions (dated April 2003) contains no documentation
for a cover directive. However, there is a third-party tool that supports this undocumented directive.
Since the OVA cover directive is not documented in the OpenVera LRM, the information provided
below is based on the best available information. While accurate, it may not be complete.

SVA:
<name> : cover property ( <sva_sequence> ) [ pass_statement ] ;

OVA:
cover <name> : ( <ova_sequence> ) ;

Assume
The differences in syntax for the assume directive is similar to that documented above for
assert and cover.

2 SystemVerilog Versus OpenVera

 Miscellaneous Directives
OVA defines restrict and model directives that do not exist for SVA.

Clock Specification
Both SVA and OVA provide for the specification of a sampling event (clock specification).
However, the syntax differs between the two languages.

SVA:
The clock expression is specified in the sequence or property specification.
property foo;
@(posedge clk)
ready |=> (ack);
endproperty

sequence bar;
@(posedge sysclk) a ##1 b ##2 c;
endsequence

OVA:
The clock specification defines a block (clocked entity) within which sequences are defined.
unit foo( logic clk, logic ready, logic ack);
clock posedge clk {
s_foo : (if ready then ack);
}
endunit

SystemVerilog Versus OpenVera 3

 Sequence Syntax
The difference in sequence operator syntax between the two languages is best presented via
a comparison table. The differences are not trivial.

Operator Description SystemVerilog OpenVera Assertion

Time/cycle advancement ##n #n
Consecutive repetition
with range
seq[*n] seq * [n]
seq[*n:m] seq * [n .. m]
Non-consecutive repetition seq[=n], seq[=n:m] N/A
Goto repetition seq[->n] N/A
Infinite (unbounded) range [n:$] [n..]
Implication (same cycle)
Next cycle
<LHS> |-> <RHS> if (cond) then <T> [else <F>]

Antecedent
Sequence conjunction (and)
Intersection (length-matching and)
Sequence disjunction (or)
Convert sequence to Boolean
first_match
Condition over sequence
Sequence within another sequence
Local variable assignment
SVA assignment w/in seq.
<LHS> |=> <RHS> (else is optional)
cond must be boolean condition
<LHS> and <RHS> <LHS> && <RHS>
<LHS> intersect <RHS> <LHS> intersect <RHS>
<LHS> or <RHS> <LHS> || <RHS>
<seq>.matched matched <seq> )
first_match( <seq> ) first_match( <seq> )
(cond) throughout <seq> istrue (boolexpr) in <seq>
length [int/range] in <seq>
seq within seq
a ##1 (b[->1], var = e) init var_name = const_value;

OVA assignment is stmt

var_name <= expr;

Unconditional match `true any

Templates (reusable props) template name ( params ) : { …}
temp_name inst_name ( params ) ;
Loop generation Verilog for generate for (lcv=expr; end_expr;
lcv=incr_expr) { … }
Formula operators always (assertion block) always
N/A eventually
N/A next, wnext
N/A globally
disable iff (approximate) iff
N/A until, wuntil
N/A followed_by
N/A triggers
N/A accept … in …
N/A reject … in …
Multiple-clocked sequences Must use matched to convert sequence in
one clock domain to a Boolean value for
Multiple @<clk_expr>

use in another clock domain.

clauses in sequence

4 SystemVerilog Versus OpenVera

 Predefined/Built-in Functions and Tasks
The following table shows the differences in support for various built-in functions and tasks
for SystemVerilog and OVA.

Description SystemVerilog OpenVera Assertions

Previous value of a signal $past( expr, clk_ev ) past ( sig, cycles )

Future value of a signal N/A future ( bit_vec_expr )

Procedural sampling $sampled( expr, clk_ev ) N/A

Rising edge $rose( expr, clk_ev ) N/A

Falling edge $fell ( expr, clk_ev ) N/A

No event for time $stable ( expr, clk_ev ) N/A

Number of bits 1 in vector $countones ( expr ) count ( bit_vector_expr )

One hot $onehot ( expr ) N/A

One hot with all 0 allowed $onehot0 ( expr ) N/A

Check for unknowns $isunknown ( expr ) N/A

OpenVera versus SystemVerilog for Testbench and Verification

Vera’s syntax is more heavily influenced by C than is SystemVerilog’s. This is easily seen in
the use of curly braces {} to denote the beginning and ending of a block in Vera whereas
SystemVerilog uses a semicolon ; to denote the end of a declaration, and it uses begin and
endxyz keywords to bracket blocks.
Other differences exist in the syntax and semantics between the two languages.

Program Block
SystemVerilog program blocks can have ports and parameters. OpenVera program blocks do not
have an interface defined in this manner. Instead, an “interface” block is specified to provide the
connection between the OpenVera program block and the design.
An OpenVera interface is not the same as a SystemVerilog interface (see section on interfaces
below).

SystemVerilog Versus OpenVera 5

 Syntactic Differences in Block Syntax
OpenVera:
program <name> {
..
}

SystemVerilog:
program <name> [ ( port-list ) ] ;
…
endprogram

OpenVera Interfaces and SystemVerilog Clocking Blocks

OpenVera’s interface defines how the Vera testbench connects up with the design. This connection
also specifies input and output skews relative to a signal (such as a clock). SystemVerilog inter-
faces serve a completely different purpose. The SystemVerilog program block can be connected
directly to the design (and may use SystemVerilog interfaces to do so). The SystemVerilog clocking
block provides the mechanism by which signal sampling is defined within the testbench.
OpenVera requires a bind port specification to bind the Vera program to the design’s ports.

Classes
OpenVera classes can be declared as “extern” in a header file. Whereas, classes cannot be
declared as “extern” in SystemVerilog. OpenVera class members can be local or public.
SystemVerilog class members can be local, public (default), or protected. There is no public
keyword in SystemVerilog.

Globally Applicable Syntactic Differences

Syntactic construct SystemVerilog OpenVera

Block declaration task foo ; task foo {
(program, task, class, etc.) endtask }

Block begin-end delimiters begin {

end }

6 SystemVerilog Versus OpenVera

Subprograms
Feature SystemVerilog OpenVera
Automatic Tasks and functions, by default, are static. Tasks and functions are always automatic.
The automatic keyword is required to
declare task as automatic.
Argument passing Value: default mechanism. Value: default mechanism
Reference: parameters declared as ref Reference: parameters declared as var
are passed by reference. are passed by reference.
Default parameter values Yes Yes
Optional parameters No (Not in the Vera sense) Yes
Declaration scope Module or generate scope. Global by default.
Generally, Verilog name space is global. Use local keyword to limit scope.
Return statement Yes Yes
Discarding function result void’(func(a, b, c)); void = func(a, b, c);

Data Types
Type SystemVerilog OpenVera
Integer 2-state int integer (always signed)
Integer 4-state integer N/A
64-bit integer longint N/A
Signed integer int signed N/A
Unsigned integer int unsigned N/A

Bit 2-state bit N/A

Bit 4-state logic bit
Associative arrays
Where:* denotes an unspecified index type (that is, only unspecified index types)
<elem_type> <arr>[<index-type>]; <elem_type> <arr>[];

System (built-in) tasks

(when the same task is defined
$<taskname>(…) <taskname>(…)

in both languages)

Enumerated types enum [<base-type>] { lit1 enum <name> = lit1, lit2, …;

[=encoding], lit2, … }

Note: Must combine with typedef to name

[<obj>];

the enum type.

Packed data Arrays: Location of index range
Structs: use of packed keyword
Class members via use of the packed
keyword. Can be modified with big_endian
and little_endian, bit_normal, and
bit_reverse. pack() and unpack() prede-
fined methods.

SystemVerilog Versus OpenVera 7

Preprocessor Macros
Macro SystemVerilog OpenVera
Textual file include `include “filename” #include “filename”
`include <filename> #include <filename>

General ` indicates a preprocessor macro # indicates a preprocessor macro

Miscellaneous
Capability SystemVerilog OpenVera
Regions (mutually exclusive access N/A Yes, regions
to values)

printf formatted text output $display printf

Fork-join statements
Format specifiers: d, o, h, b, e, f, g, s
Ending keyword is underscored:
join_any
join_none
join
NOTE: no join_all (keyword)
Sequential statement blocks in a fork-join
are bracketed with begin-end
Additional forma specifiers: D, I, I, H, x, X,
O, B, u, U c, C, S, p, P, m, M, v, V, _, %
Does not support: e, f, g
Join is ending keyword combined
with modifying keyword:
join any
join none
join all (or simply join)
Sequential statement blocks in a fork-join
are bracketed with {}

Waiting for a child thread N/A wait_child

Constraints and Weightings

Capability SystemVerilog OpenVera
Random data rand randc

rand Dynamic arrays rand logic [7:0] len;

randc rand integer data[];
constraint db {data.size == len; }
rand bit [7:0] len; len; Set membership
rand integer data[] assoc_size
exp inside { <set> } exp in { <set> } Implication in constraints
!(exp inside { <set> }) exp !in { <set> }

(cond) -> { <set> } (cond) => { <set> } Rand sequence production weightings
if (cond) { <set> } if (cond) { <set> }
else { <set> } else { <set> }
Lhs : rhs1 := 2 Lhs : &(2) rhs1 Aborting rand sequence productions
| rhs2 := 5 | &(5) rhs2
break terminates sequence block break terminates sequence block Passing values between productions
return aborts the current production continue aborts the current production

8 SystemVerilog Versus OpenVera

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