AD781–SPECIFICATIONS

DC SPECIFICATIONS (TMIN to TMAX, VCC = +12 V 6 10%, VEE = –12 V 6 10%, CL = 20 pF, unless otherwise noted)
AD781J AD781A AD781S
Parameter Min Typ Max Min Typ Max Min Typ Max Units
SAMPLING CHARACTERISTICS
Acquisition Time
10 V Step to 0.01% 600 700 600 700 600 700 ns
10 V Step to 0.1% 500 600 500 600 500 600 ns
Small Signal Bandwidth 4 4 4 MHz
Full Power Bandwidth 1 1 1 MHz
HOLD CHARACTERISTICS
Effective Aperture Delay (25°C) –35 –25 –15 –35 –25 –15 –35 –25 –15 ns
Aperture Jitter (25°C) 50 75 50 75 50 75 ps
Hold Settling (to 1 mV, 25°C) 250 500 250 500 250 500 ns
Droop Rate 0.01 1 0.01 1 0.01 1 µV/µs
Feedthrough (25°C)
(VIN = ± 5 V, 100 kHz) –86 –86 –86 dB
1
ACCURACY CHARACTERISTICS
Hold Mode Offset –4 –1 +3 –4 –1 +3 –4 –1 +3 mV
Hold Mode Offset Drift 10 10 10 µV/°C
Sample Mode Offset 50 200 50 200 50 200 mV
Nonlinearity ± 0.002 ± 0.003 ± 0.002 ± 0.003 ± 0.003 ± 0.005 % FS
Gain Error ± 0.01 ± 0.025 ± 0.01 ± 0.025 ± 0.01 ± 0.025 % FS
OUTPUT CHARACTERISTICS
Output Drive Current –5 +5 –5 +5 –5 +5 mA
Output Resistance, DC 0.3 0.5 0.3 0.5 0.3 0.5 Ω
Total Output Noise (DC to 5 MHz) 150 150 150 µV rms
Sampled DC Uncertainty 85 85 85 µV rms
Hold Mode Noise (DC to 5 MHz) 125 125 125 µV rms
Short Circuit Current
Source 20 20 20 mA
Sink 10 10 10 mA
INPUT CHARACTERISTICS
Input Voltage Range –5 +5 –5 +5 –5 +5 V
Bias Current 50 250 50 250 50 250 nA
Input Impedance 50 50 50 MΩ
Input Capacitance 2 2 2 pF
DIGITAL CHARACTERISTICS
Input Voltage Low 0.8 0.8 0.8 V
Input Voltage High 2.0 2.0 2.0 V
Input Current High (VIN = 5 V) 2 10 2 10 2 10 µA
POWER SUPPLY CHARACTERISTICS
Operating Voltage Range ± 10.8 ± 12 ± 13.2 ± 10.8 ± 12 ± 13.2 ± 10.8 ± 12 ± 13.2 V
Supply Current 4 6.5 4 6.5 4 7 mA
+PSRR (+12 V ± 10%) 70 80 70 80 70 80 dB
–PSRR (–12 V ± 10%) 65 75 65 75 65 75 dB
Power Consumption 95 175 95 175 95 185 mW
TEMPERATURE RANGE
Specified Performance 0 +70 –40 +85 –55 +125 °C
NOTE
1
Specified and tested over an input range of ± 5 V.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed although only those shown in boldface are tested.

–2– REV. A
 AD781
(TMIN to TMAX, VCC = +12 V 6 10%, VEE = –12 V 6 10%, CL = 20 pF,
HOLD MODE AC SPECIFICATIONS unless otherwise noted)1
AD781J AD781A AD781S
Parameter Min Typ Max Min Typ Max Min Typ Max Units
TOTAL HARMONIC DISTORTION
FIN = 10 kHz –90 –80 –90 –80 –90 –80 dB
FIN = 50 kHz –73 –73 –73 dB
FIN = 100 kHz –68 –68 –68 dB
SIGNAL-TO-NOISE AND DISTORTION
FIN = 10 kHz 72 78 72 78 72 78 dB
FIN = 50 kHz 73 73 73 dB
FIN = 100 kHz 67 67 67 dB
INTERMODULATION DISTORTION
FIN1 = 49 kHz, FIN2 = 50 kHz
2nd Order Products –77 –77 –77 dB
3rd Order Products –78 –78 –78 dB
NOTE
1
FIN amplitude = 0 dB and F SAMPLE = 500 kHz unless otherwise indicated.
Specifications shown in boldface are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed although only those shown in boldface are tested.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION

With
Spec Respect to Min Max Unit VCC 1 8 OUT

VCC Common –0.3 +15 V IN 2 AD781 7 S/H

VEE Common –15 +0.3 V TOP VIEW
Control Input Common –0.5 +7 V COMMON 3 (Not to Scale) 6 NC
Analog Input Common –12 +12 V
Output Short Circuit to NC 4 5 VEE
Ground, VCC, or VEE Indefinite
Maximum Junction
Temperature +175 °C ORDERING GUIDE
Storage –65 +150 °C
Lead Temperature Temperature Package
(10 sec max) +300 °C Model1 Range Description Options2
Power Dissipation 195 mW AD781JN 0°C to +70°C 8-Pin Plastic DIP N-8
*Stresses above those listed under “Absolute Maximum Ratings” may cause per- AD781AN –40°C to +85°C 8-Pin Plastic DIP N-8
manent damage to the device. This is a stress rating only and functional opera- AD781SQ –55°C to +125°C 8-Pin Cerdip Q-8
tion of the device at these or any other conditions above those indicated in the
NOTES
operational section of this specification is not implied. 1
For details on grade and package offerings screened in accordance with
MIL-STD-883, refer to the Analog Devices Military Products Databook or
current AD781/883B data sheet.
2
N = Plastic DIP; Q = Cerdip.

CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
WARNING!
static fields. Unused devices must be stored in conductive foam or shunts.
ESD SENSITIVE DEVICE

REV. A –3–
AD781
80 10.0 –10

EFFECTIVE APERTURE DELAY – ns

70
V+
60 1.0 –15

DROOP RATE – µV/µs

50
PSRR – dB

V–
40 0.1 –20

30

20 0.01 –25

10

0 0.001 –30
1 10 100 1k 10k 100k 1M 0 25 50 75 100 125 150 100 1k 10k 100k 1M
FREQUENCY – Hz TEMPERATURE – °C FREQUENCY – Hz

Power Supply Rejection Ratio vs. Droop Rate vs. Temperature, Effective Aperture Delay vs.
Frequency VIN = 0 V Frequency

200 5 5

150

SUPPLY CURRENT – mA
SUPPLY CURRENT – mA

100 4 4
BIAS CURRENT – nA

50

0 3 3

–50

–100 2 2

–150

–200 1 1
–10 –5 0 5 10 –75 –50 –25 0 25 50 75 100 125 150 ±10 ±11 ±12 ±13 ±14 ±15
INPUT VOLTAGE – V TEMPERATURE – °C SUPPLY VOLTAGE – V

Bias Current vs. Input Voltage Supply Current vs. Temperature Supply Current vs. Supply Voltage

1000

750
ACQUISITION TIME – ns

500

250

0
0 2 4 6 8 10
INPUT STEP – V

Acquisition Time (to 0.01%) vs.

Input Step Size

–4– REV. A

DEFINITIONS OF SPECIFICATIONS
Acquisition Time—The length of time that the SHA must
remain in the sample mode in order to acquire a full-scale input
step to a given level of accuracy.
Small Signal Bandwidth—The frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 100 mV p-p sine wave.
Full Power Bandwidth—The frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 10 V p-p sine wave.
Effective Aperture Delay—The difference between the switch
delay and the analog delay of the SHA channel. A negative
number indicates that the analog portion of the overall delay is
greater than the switch portion. This effective delay represents
the point in time, relative to the hold command, that the input
signal will be sampled.
Aperture Jitter—The variations in aperture delay for
successive samples. Aperture jitter puts an upper limit on the
maximum frequency that can be accurately sampled.
Hold Settling Time—The time required for the output to
settle to within a specified level of accuracy of its final held value
after the hold command has been given.
Droop Rate—The drift in output voltage while in the hold
mode.
Feedthrough—The attenuated version of a changing input
signal that appears at the output when the SHA is in the hold
mode.
Hold Mode Offset—The difference between the input signal
and the held output. This offset term applies only in the hold
mode and includes the error caused by charge injection and all
other internal offsets. It is specified for an input of 0 V.
Tracking Mode Offset—The difference between the input and
output signals when the SHA is in the track mode.
Nonlinearity--The deviation from a straight line on a plot of
input vs. (held) output as referenced to a straight line drawn
between endpoints, over an input range of –5 V and +5 V.
Gain Error—Deviation from a gain of +1 on the transfer
function of input vs. held output.
Power Supply Rejection Ratio—A measure of change in the
held output voltage for a specified change in the positive or
negative supply.
Sampled DC Uncertainty—The internal rms SHA noise that
is sampled onto the hold capacitor.
Hold Mode Noise—The rms noise at the output of the SHA
while in the hold mode, specified over a given bandwidth.
Total Output Noise—The total rms noise that is seen at the
output of the SHA while in the hold mode. It is the rms
summation of the sampled dc uncertainty and the hold mode
noise.
Output Drive Current—The maximum current the SHA can
source (or sink) while maintaining a change in hold mode offset
of less than 2.5 mV.
REV. A
AD781
Signal-To-Noise and Distortion (S/N+D) Ratio—S/N+D is
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
S/N+D is expressed in decibels.
Total Harmonic Distortion (THD)—THD is the ratio of the
rms sum of the first six harmonic components to the rms value
of the measured input signal and is expressed as a percentage or
in decibels.
Intermodulation Distortion (IMD)—With inputs consisting
of sine waves at two frequencies, fa and fb, any device with
nonlinearities will create distortion products, of order (m+n), at
sum and difference frequency of mfa± nfb, where m, n = 0, 1, 2,
3.... Intermodulation terms are those for which m or n is not
equal to zero. For example, the second order terms are (fa+fb)
and (fa–fb), and the third order terms are (2fa+fb), (2fa–fb),
(fa+2fb) and (fa–2fb). The IMD products are expressed as the
decibel ratio of the rms sum of the measured input signals to the
rms sum of the distortion terms. The two signals are of equal
amplitude, and peak value of their sums is –0.5 dB from full
scale. The IMD products are normalized to a 0 dB input signal.
FUNCTIONAL DESCRIPTION
The AD781 is a complete sample-and hold amplifier that
provides high speed sampling to 12-bit accuracy in less than
700 ns.
The AD781 is completely self-contained, including an on-chip
hold capacitor, and requires no external components or
adjustments to perform the sampling function. Both input and
output are treated as a single-ended signal, referred to common.
The AD781 utilizes a proprietary circuit design which includes a
self-correcting architecture. This sample-and-hold circuit
corrects for internal errors after the hold command has been
given, by compensating for amplifier gain and offset errors, and
charge injection errors. Due to the nature of the design, the
SHA output in the sample mode is not intended to provide an
accurate representation of the input. However, in hold mode,
the internal circuitry is reconfigured to produce an accurately
held version of the input signal. Below is a block diagram of the
AD781.
VCC 1 8 OUT
IN 2 7 S/H
X1
COMMON 3 6 NC
4 5 VEE
NC AD781
Functional Block Diagram
–5–
AD781
DYNAMIC PERFORMANCE (VOUT HOLD – VIN ), mV
The AD781 is compatible with 12-bit A-to-D converters in
terms of both accuracy and speed. The fast acquisition time, fast +1
hold settling time and good output drive capability allow the
AD781 to be used with high speed, high resolution A-to-D
converters like the AD674 and AD7672. The AD781’s fast
acquisition time provides high throughput rates for multichannel V IN , VOLTS
data acquisition systems. Typically, the sample and hold can
acquire a 10 V step in less than 600 ns. Figure 1 shows the –5 –4 –3 –2 –1 1 2 3 4 +5
settling accuracy as a function of acquisition time.

0.08 HOLD MODE OFFSET

VOUT ACQUISITION ACCURACY – %

GAIN ERROR –1
0.06 NONLINEARITY

0.04
0.02
0 plished through the A-to-D itself or by an external amplifier
0 250 500
ACQUISITION TIME – ns
Figure 1. VOUT Settling vs. Acquisition Time
The hold settling determines the required time, after the hold
command is given, for the output to settle to its final specified
accuracy. The typical settling behavior of the AD781 is shown
in Figure 2. The settling time of the AD781 is sufficiently fast to
allow the SHA, in most cases, to directly drive an A-to-D
converter without the need for an added “start convert” delay.
Figure 3. Hold Mode Offset, Gain Error and Nonlinearity
For applications where it is important to obtain zero offset, the
hold mode offset may be nulled externally at the input to the
A-to-D converter. Adjustment of the offset may be accom-
750 1000
with offset nulling capability (e.g., AD711). The offset will
change less than 0.5 mV over the specified temperature range.
SUPPLY DECOUPLING AND GROUNDING
CONSIDERATIONS
As with any high speed, high resolution data acquisition system,
the power supplies should be well regulated and free from exces-
sive high frequency noise (ripple). The supply connection to the
AD781 should also be capable of delivering transient currents to
the device. To achieve the specified accuracy and dynamic per-
formance, decoupling capacitors must be placed directly at both
the positive and negative supply pins to common. Ceramic type
0.1 µF capacitors should be connected from VCC and VEE to
common.

ANALOG DIGITAL
P.S. P.S.

+12V C –12V C +5V

0.1µF 0.1µF 1µF 1µF 1µF

+
INPUTS
7 9 11 15 1 DIGITAL
Figure 2. Typical AD781 Hold Mode AD781 AD674 DATA
OUTPUT

HOLD MODE OFFSET SIGNAL GROUND

The dc accuracy of the AD781 is determined primarily by the
hold mode offset. The hold mode offset refers to the difference
between the final held output voltage and the input signal at the
time the hold command is given. The hold mode offset arises
from a voltage error introduced onto the hold capacitor by
charge injection of the internal switches. The nominal hold
mode offset is specified for a 0 V input condition. Over the
input range of –5 V to +5 V, the AD781 is also characterized for
an effective gain error and nonlinearity of the held value, as
shown in Figure 3. As indicated by the AD781 specifications,
the hold mode offset is very stable over temperature.
Figure 4. Basic Grounding and Decoupling Diagram
The AD781 does not provide separate analog and digital ground
leads as is the case with most A-to-D converters. The common
pin is the single ground terminal for the device. It is the refer-
ence point for the sampled input voltage and the held output
voltage and also the digital ground return path. The common
pin should be connected to the reference (analog) ground of the
A-to-D converter with a separate ground lead. Since the analog
and digital grounds in the AD781 are connected internally, the

–6– REV. A
 AD781
common pin should also be connected to the digital ground, Measurements of Figures 7 and 8 were made using a 14-bit A/D
which is usually tied to analog common at the A-to-D converter. converter with VIN = 10 V p-p and a sample frequency of
Figure 4 illustrates the recommended decoupling and grounding 100 kSPS.
practice.
1%
NOISE CHARACTERISTICS
Designers of data conversion circuits must also consider the 1/2 BIT @
8 BITS
effect of noise sources on the accuracy of the data acquisition
system. A sample-and-hold amplifier that precedes the A-to-D 0.1%
1/2 BIT @
converter introduces some noise and represents another source 10 BITS
of uncertainty in the conversion process. The noise from the
AD781 is specified as the total output noise, which includes 1/2 BIT @
12 BITS
both the sampled wideband noise of the SHA in addition to the
0.01%
band limited output noise. The total output noise is the rms
sum of the sampled dc uncertainty and the hold mode noise. A 1/2 BIT @
14 BITS
plot of the total output noise vs. the equivalent input bandwidth APERTURE JITTER TYPICAL AT 50ps
of the converter being used is given in Figure 5.

300 1k 10k 100k 1M

FREQUENCY – Hz

Figure 6. Error Magnitude vs. Frequency

OUTPUT NOISE – µV rms

200 –65

–70

100 –75
THD – dB

–80

0 –85
1k 10k 100k 1M 10M
FREQUENCY – Hz –90
Figure 5. RMS Noise vs. Input Bandwidth of ADC
–95
DRIVING THE ANALOG INPUTS 100 1k 10k 100k 1M

For best performance, it is important to drive the AD781 analog FREQUENCY – Hz

input from a low impedance signal source. This enhances the Figure 7. Total Harmonic Distortion vs. Frequency
sampling accuracy by minimizing the analog and digital
crosstalk. Signals which come from higher impedance sources 90
(e.g., over 5 kΩ) will have a relatively higher level of crosstalk.
80
For applications where signals have high source impedance, an
operational amplifier buffer in front of the AD781 is required. 70
The AD711 (precision BiFET op amp) is recommended for 60
S/(N + D) – dB

these applications.
50
HIGH FREQUENCY SAMPLING 40
Aperture jitter and distortion are the primary factors which limit
frequency domain performance of a sample-and-hold amplifier. 30

Aperture jitter modulates the phase of the hold command and 20

produces an effective noise on the sampled analog input. The
10
magnitude of the jitter induced noise is directly related to the
frequency of the input signal. 0
100 1k 10k 100k
A graph showing the magnitude of the jitter induced error vs.
FREQUENCY – Hz
frequency of the input signal is given in Figure 6.
Figure 8. Signal/(Noise and Distortion) vs. Frequency
The accuracy in sampling high frequency signals is also con-
strained by the distortion and noise created by the sample-and
hold. The level of distortion increases with frequency and re-
duces the “effective number of bits” of the conversion.

REV. A –7–
AD781
AD781 TO AD674 INTERFACE 20

Figure 9 shows a typical data acquisition circuit using the

0
AD781, a high linearity, low aperture jitter SHA and the AD674
a 12-bit high speed ADC. The time between the AD674 status –20
line going high and the actual start of conversion allows the

AMPLITUDE – dB
AD781 to settle to 0.01%. As a result, the AD674 status line –40

can be used to control the AD781; only an inverter is needed to

C1509–10–2/91
–60
interface the two devices.
–80
STATUS
–100
+5V
0.1µF –120
+12V 7404 6 2 1
OR EQUIV.
CE 12/8 VL –140
0.1µF 28 STS 0 3 7 10 13 16 20 23 26 30 33
FREQUENCY BINS – kHz
15 DGND
1 7
VCC 4 NC
3 CS Figure 10. FFT Plot of AD781 to AD674 Interface,
S/H
NC
4 A0 AD674 FIN = 1 kHz
6
IN
VIN 2 OUT
8 13 10 V
3 IN 16
AD781 12-BIT
GND NC 14 20 VIN D0–11 THREE-STATE
VEE
5 DATA
27
GAIN
10 REF IN
0.1µF 100Ω
–12V
8 REF OUT
100Ω
12 BIP OFFSET
OFFSET

CONVERT 5 R/C

9 AGND

7 11

+12V –12V
4.7µF 0.1µF 0.1µF 4.7µF

Figure 9. AD781 to AD674 Interface

OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

Cerdip (Q) Package Mini-DIP (N) Package

PRINTED IN U.S.A.

–8– REV. A