Acer Aspire 5750 5750G Gateway NV57H - Compal - LA-6901P

A B C D E
Compal Confidential
Model Name : P5WE0
File Name : LA-6901P
1 1
BOM P/N:43
Compal Confidential
/
/x
su
2 2
P5WE0 M/B Schematics Document
p.
om
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
Nvidia N12P GS/GV
yc
m
//
3 2010-08-11 3
p:
REV:0.1
tt
h
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/11 Deciphered Date 2011/08/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P5WE0 M/B LA-6901P Schematic
Date: Friday, August 27, 2010 Sheet 1 of 59
A B C D E
A B C D E
Fan Control
page 38
1 1
100MHz PCI-E 2.0x16 5GT/s PER LANE

PEG(DIS) Intel Memory BUS(DDRIII)
Nvidia 133MHz Dual Channel 204pin DDRIII-SO-DIMM X2
N12P GS/GV Sandy Bridge BANK 0, 1, 2, 3 page 12,13
1.5V DDRIII 1066/1333
Processor
page23~31
rPGA989
page 5~11
/
HDMI(DIS) CRT(DIS) LVDS(DIS) FDI x8 DMI x4 USB 2.0 conn x2 Bluetooth CMOS Camera 3G connector
Conn
/x
USB port 9,12 on 3G/B
HDMI Conn. CRT Conn. LVDS Conn. 100MHz 100MHz
USB port 0,1 on USB port 13 USB port 10
USB/B page 39 page 39 page 32 page 32
page 34 page 33 page 32 2.7GT/s 1GB/s x4
su
2 USBx14 3.3V 48MHz 2
LVDS(UMA/OPTIMUS)
Intel
CRT(UMA/OPTIMUS) HD Audio 3.3V 24MHz
p.
TMDS(UMA/OPTIMUS) Cougar Point-M
PCH
om
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz HDA Codec
989pin BGA ALC271X/277X
port 5 port 2,3 port 1 SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz SPI page 43
page 14~22
LAN(GbE) &
yc
USB 3.0 conn x1 MINI Card x2
WLAN, WWAN Card Reader
USB port 12,13 BCM57785
page 45 page 38 page 36 SPI ROM x1 Int. Speaker Phone Jack x 2
m
port 0,1 port 2 page 14
page 44 page 44
SATA HDD SATA CDROM
//
3
Card Reader RJ45 Conn. page Conn. page 35 LPC BUS 3
35
Conn. page 37
page 37
33MHz
p:
Sub-board ENE KB930

tt
page 40
LS-6901P LF-6901P
USB 2.0/B 2Port
RTC CKT. FPC for USB3.0
h
USB Port0,1 page 39 CPU XDP

page 14
Touch Pad Int.KBD
page 41 page 6
page 41
LS-6902P
Power On/Off CKT. PWR/B
page 42 PCH XDP
page 39
BIOS ROM page 14
page 40
DC/DC Interface CKT. LS-6903P
4 page 46 3G/B 4
page 41
Power Circuit DC/DC

LS-6904P
page 48~56 USB 3.0 /B Security Classification Compal Secret Data Compal Electronics, Inc.
2010/08/11 2011/08/11 Title
1 port as USB3.0 Issued Date Deciphered Date
Block Diagrams
1 port as USB2.0 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 41 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
A B C D E
A B C D E
Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON
BATT+ Battery power supply (12.6V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
B+ AC or battery power rail for power circuit. N/A N/A N/A
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF
+1.05VS_VTT +1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH ON OFF OFF Board ID / SKU ID Table for AD channel
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF Vcc 3.3V +/- 5%
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF 0 0 0 V 0 V 0 V EVT
/
+1.8VSDGPU +1.8VS to +1.8VSDGPU switched power rail for GPU ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V DVT
/x
+3VALW +3VALW always on power rail ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V PVT
+3VALW_EC +3VALW always to KBC ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V Pre-MP
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
su
2 2
+3VS +3VALW to +3VS power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5VALW +5VALWP to +5VALW power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON*
p.
+5VS +5VALW to +5VS switched power rail ON OFF OFF
BOARD ID Table BTO Option Table
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON*
BTO Item BOM Structure
om
+RTCVCC RTC power ON ON ON Board ID PCB Revision
UMA Only UMAO@
0 0.1
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
UMA with OPTIMUS UMA@
1 0.2
Dis with OPTIMUS DIS@
EC SM Bus1 address EC SM Bus2 address 2 0.3
DIS Only DISO@
yc
3 1.0
Device Address Device Address
OPTIMUS OPT@
4
Smart Battery 0001 011X b
Non-OPTIMUS NOPT@
5
3G 3G@
m
6
Blue Tooth BT@
7
USB2.0 USB20@
PCH SM Bus address
// USB3.0 USB30@
3 VRAM X76@ 3
Device Address
USB Port Table Connector CONN@
Clock Generator (9LVS3199AKLFT, 1101 0010b Unpop @
p:
RTM890N-631-VB-GRT) 3 External
DDR DIMM0 1001 000Xb
USB 2.0 USB 1.1 Port USB Port LAN Chip A0 version A0@
DDR DIMM2 1001 010Xb
LAN Chip B0 version B0@
0 USB/B (Right Side)
tt
UHCI0
1 USB/B (Right Side)
3G & BT & USB30 & USB20 Config
2 USB 2.0 & USB3.0 Conn.
h
3G SKU: 3G@ USB30 SKU: USB30@ OPTMIUS SKU: OPT@ UHCI1

3
BT SKU: BT@ USB20 SKU: USB20@ Non-OPTMIUS SKU: NOPT@ EHCI1
4
LAN Chip A0 version: A0@ UHCI2
5
LAN chip B0 Version: B0@
6
UHCI3
7
BOM Config 8 Mini Card 1(WLAN)
UHCI4
UMA Only: BT@/3G@/USB30@/UMA@/UMAO@/NOPT@/A0@ 9 3G/B(WWAN)
OPTIMUS: BT@/3G@/USB30@/UMA@/DIS@/X76@/OPT@/A0@ 10 Camera
EHCI2 UHCI5
DIS Only: BT@/3G@/USB30@/DISO@/DIS@/X76@/NOPT@/A0@ 11 Mini Card 2(Reserved)
4 4
VRAM BOM Config 12 SIM Card (3G/B)
UHCI6
X76***BOL01: Samsung 13 Blue Tooth
X76***BOL02: Hynix
VRAM P/N : Security Classification Compal Secret Data Compal Electronics, Inc.
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P) Issued Date 2010/08/11 Deciphered Date 2011/08/11 Title
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
Notes List
Custom 0.1
A B C D E
5 4 3 2 1
+1.05VS_VTT
PEG_ICOMPI and PEG_RCOMPO signals should be
shorted and routed,
1
max length = 500 mils,trace width=4mils
R517
24.9_0402_1% PEG_ICOMPO signals should be routed with - max
JCPU1A
length = 500 mils,trace width=12mils
2
D
PEG_ICOMPI J22 PEG_COMP spacing =15mils D
PEG_ICOMPO J21
15 DMI_CRX_PTX_N0 B27 DMI_RX#[0] H22
PEG_RCOMPO
15 DMI_CRX_PTX_N1 B25 DMI_RX#[1]
15 DMI_CRX_PTX_N2 A25 DMI_RX#[2]
15 DMI_CRX_PTX_N3 B24 DMI_RX#[3] PEG_RX#[0] K33PEG_GTX_C_HRX_N15 C46 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N15
PEG_RX#[1] M35PEG_GTX_C_HRX_N14 C49 1 2 DIS@ 0.22U_0402_10V6K
PEG_GTX_HRX_N14
15 DMI_CRX_PTX_P0 B28 DMI_RX[0] PEG_RX#[2] L34PEG_GTX_C_HRX_N13 C51 1 2 DIS@ 0.22U_0402_10V6K
PEG_GTX_HRX_N13
15 DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35PEG_GTX_C_HRX_N12 C53 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N12
DMI
PEG_GTX_C_HRX_N11 C60 1 PEG_GTX_HRX_N11
15 DMI_CRX_PTX_P2 A24 DMI_RX[2] PEG_RX#[4] J32
PEG_GTX_C_HRX_N10 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N10 PEG_GTX_HRX_N[0..15] 22
15 DMI_CRX_PTX_P3 B23 H34 C71 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N9 PEG_GTX_HRX_P[0..15] 22
DMI_RX[3] PEG_RX#[5] PEG_GTX_C_HRX_N9
PEG_RX#[6] H31 C75 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_N8
PEG_GTX_C_HRX_N8
15 DMI_CTX_PRX_N0 G21 DMI_TX#[0] G33 C82 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_N7 PEG_HTX_C_GRX_N[0..15] 22
PEG_RX#[7] PEG_GTX_C_HRX_N7
15 DMI_CTX_PRX_N1 E22 DMI_TX#[1] G30 C92 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P[0..15] 22
PEG_RX#[8] PEG_GTX_C_HRX_N6 C93 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N6
15 DMI_CTX_PRX_N2 F21 DMI_TX#[2] F35
PEG_RX#[9] PEG_GTX_C_HRX_N5 PEG_GTX_HRX_N5
15 DMI_CTX_PRX_N3 D21 DMI_TX#[3] E34PEG_GTX_C_HRX_N4 C102 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_N4
PEG_RX#[10]
PEG_RX#[11] E32PEG_GTX_C_HRX_N3 C111 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_N3
15 DMI_CTX_PRX_P0 G22 DMI_TX[0] D33PEG_GTX_C_HRX_N2 C113 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N2
PEG_RX#[12]
15 DMI_CTX_PRX_P1 D22 DMI_TX[1] D31PEG_GTX_C_HRX_N1 C125 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N1
/
PEG_RX#[13]
PCI EXPRESS* - GRAPHICS

15 DMI_CTX_PRX_P2 F20 DMI_TX[2] B33PEG_GTX_C_HRX_N0 C129 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_N0
PEG_RX#[14]
15 DMI_CTX_PRX_P3 C21 DMI_TX[3] C32 C144 1 2 DIS@ 0.22U_0402_10V6K
PEG_RX#[15]
/x
PEG_GTX_C_HRX_P15 PEG_GTX_HRX_P15
PEG_RX[0] J33 PEG_GTX_C_HRX_P14 C47 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P14
PEG_RX[1] L35PEG_GTX_C_HRX_P13 C50 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P13
PEG_RX[2] K34PEG_GTX_C_HRX_P12 C52 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P12
15 FDI_CTX_PRX_N0 A21 FDI0_TX#[0] H35PEG_GTX_C_HRX_P11 C56 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P11
PEG_RX[3]
15 FDI_CTX_PRX_N1 H19 FDI0_TX#[1] H32PEG_GTX_C_HRX_P10 C66 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P10
PEG_RX[4]
E19
su
15 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5] G34PEG_GTX_C_HRX_P9 C68 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P9
Intel(R) FDI
C 15 FDI_CTX_PRX_N3 F18 FDI0_TX#[3] G31PEG_GTX_C_HRX_P8 C81 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P8 C
PEG_RX[6]
15 FDI_CTX_PRX_N4 B21 F33PEG_GTX_C_HRX_P7 C86 1
C20
FDI1_TX#[0] PEG_RX[7] 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P7
15 FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8] F30PEG_GTX_C_HRX_P6 C89 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P6
15 FDI_CTX_PRX_N6 D18 FDI1_TX#[2] E35PEG_GTX_C_HRX_P5 C100 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P5
PEG_RX[9]
15 FDI_CTX_PRX_N7 E17 E33PEG_GTX_C_HRX_P4 C105 1
FDI1_TX#[3] PEG_RX[10] 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P4
p.
F32PEG_GTX_C_HRX_P3 C106 1 PEG_GTX_HRX_P3
PEG_RX[11] 2 DIS@ 0.22U_0402_10V6K
D34PEG_GTX_C_HRX_P2 C117 1 PEG_GTX_HRX_P2
A22
PEG_RX[12] 2 DIS@ 0.22U_0402_10V6K
15 FDI_CTX_PRX_P0 FDI0_TX[0] E31PEG_GTX_C_HRX_P1 C119 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P1
PEG_RX[13]
15 FDI_CTX_PRX_P1 G19 C33PEG_GTX_C_HRX_P0 C135 1
FDI0_TX[1] PEG_RX[14] 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P0
om
15 FDI_CTX_PRX_P2 E20 FDI0_TX[2] B32 C138 1 2 DIS@ 0.22U_0402_10V6K
PEG_RX[15]
15 FDI_CTX_PRX_P3 G18 FDI0_TX[3] PEG_HTX_GRX_N15 PEG_HTX_C_GRX_N15
15 FDI_CTX_PRX_P4 B20 M29PEG_HTX_GRX_N14 C516 2 DIS@ 0.22U_0402_10V6K
15 FDI_CTX_PRX_P5 C19
FDI1_TX[0] PEG_TX#[0]
M32PEG_HTX_GRX_N13 C520 1 1 2 DIS@ 0.22U_0402_10V6K
PEG_HTX_C_GRX_N14
15 FDI_CTX_PRX_P6 D19
FDI1_TX[1] PEG_TX#[1]
M31PEG_HTX_GRX_N12
C529 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N13
FDI1_TX[2] PEG_TX#[2] PEG_HTX_C_GRX_N12
15 FDI_CTX_PRX_P7 F17 FDI1_TX[3] L32 PEG_HTX_GRX_N11 C534 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N11
PEG_TX#[3]
+1.05VS_VTT PEG_TX#[4] L29 PEG_HTX_GRX_N10 C538 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N10
15 FDI_FSYNC0 J18 K31PEG_HTX_GRX_N9
yc
FDI0_FSYNC PEG_TX#[5] C540 1 2 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N9
15 FDI_FSYNC1 J17 K28PEG_HTX_GRX_N8 C542 1 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N8
FDI1_FSYNC PEG_TX#[6]
J30 PEG_HTX_GRX_N7
C544 1 2 2DIS@ 0.22U_0402_10V6K
PEG_TX#[7] PEG_HTX_C_GRX_N7
eDP_COMPIO and ICOMPO signals should 15 FDI_INT H20 FDI_INT J28 PEG_HTX_GRX_N6 C546 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N6
PEG_TX#[8] C548 1 2 DIS@ 0.22U_0402_10V6K
be shorted near balls, H29PEG_HTX_GRX_N5 PEG_HTX_C_GRX_N5
1
15 FDI_LSYNC0 J19 PEG_TX#[9] C550 1 2 DIS@ 0.22U_0402_10V6K

FDI0_LSYNC G27PEG_HTX_GRX_N4 PEG_HTX_C_GRX_N4
Trace Width for EDP_COMPIO=4mils,
m
R145 15 FDI_LSYNC1 H17 PEG_TX#[10] C552 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N3
FDI1_LSYNC PEG_TX#[11] E29PEG_HTX_GRX_N3
EDP_ICOMPO=12mils, 24.9_0402_1% F27PEG_HTX_GRX_N2 PEG_HTX_C_GRX_N2
PEG_TX#[12] C554 1 2 DIS@ 0.22U_0402_10V6K
and both length less than 500 mils... PEG_TX#[13] D28PEG_HTX_GRX_N1 C556 DIS@ PEG_HTX_C_GRX_N1
0.22U_0402_10V6K
F26PEG_HTX_GRX_N0
C558 1 1 2 2 DIS@ 0.22U_0402_10V6K
PEG_HTX_C_GRX_N0
2
should not be left floating PEG_TX#[14] C560 1 2 DIS@ 0.22U_0402_10V6K

,even if disable eDP function...
EDP_COMP
//
A18
PEG_TX#[15] E25
PEG_HTX_GRX_P15 PEG_HTX_C_GRX_P15
eDP_COMPIO
A17 M28PEG_HTX_GRX_P14 C515 1 2 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P14
B eDP_ICOMPO PEG_TX[0] B
B16 M33PEG_HTX_GRX_P13 C528
C533 2 DIS@ PEG_HTX_C_GRX_P13
0.22U_0402_10V6K
eDP_HPD PEG_TX[1] 1 1 2 DIS@ 0.22U_0402_10V6K
PEG_TX[2] M30PEG_HTX_GRX_P12 PEG_HTX_C_GRX_P12
L31 PEG_HTX_GRX_P11 C536 2 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P11
PEG_TX[3] C539 1 1 2 DIS@ 0.22U_0402_10V6K
p:
C15 PEG_TX[4] L28 PEG_HTX_GRX_P10 PEG_HTX_C_GRX_P10

eDP_AUX
D15 K30PEG_HTX_GRX_P9 PEG_HTX_C_GRX_P9
eDP
eDP_AUX# PEG_TX[5] C541 1 2 DIS@ 0.22U_0402_10V6K
PEG_TX[6] K27PEG_HTX_GRX_P8 PEG_HTX_C_GRX_P8
C543 1 2 DIS@ 0.22U_0402_10V6K
J29 PEG_HTX_GRX_P7 C545 1 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P7
C17
PEG_TX[7]
J27 PEG_HTX_GRX_P6
C547 1 2 2DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P6
tt
eDP_TX[0] PEG_TX[8]
F16 H28PEG_HTX_GRX_P5 C549 1 PEG_HTX_C_GRX_P5
eDP_TX[1] PEG_TX[9]
G28PEG_HTX_GRX_P4 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P4
C16 C553
eDP_TX[2] PEG_TX[10]
E28PEG_HTX_GRX_P3 1 1 2 DIS@
C551 2 DIS@0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_HTX_C_GRX_P3
G15 eDP_TX[3] PEG_TX[11]
F28PEG_HTX_GRX_P2 PEG_HTX_C_GRX_P2
h
PEG_TX[12] C555 1 2 DIS@ 0.22U_0402_10V6K

C18 PEG_TX[13] D27PEG_HTX_GRX_P1 C557 1 2 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P1
eDP_TX#[0]
E16 PEG_TX[14] E26PEG_HTX_GRX_P0 C559 1 2 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P0
eDP_TX#[1]
D16 PEG_TX[15] D25 C561 1 2 DIS@ 0.22U_0402_10V6K
eDP_TX#[2]
F15 eDP_TX#[3]
Sandy Bridge_rPGA_Rev0p61
CONN@
Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
A A
Security Classification Compal Secret Data

PROCESSOR(1/7) DMI,FDI,PEG
Custom 0.1
5 4 3 2 1
5 4 3 2 1
+1.05VS_VTT +1.05VS_VTT
+1.05VS_VTT @ JXDP1
1 GND0 2
XDP_PREQ# GND1
3 OBSFN_A0 4
XDP_PRDY# OBSFN_C0
5 OBSFN_A1 6
OBSFN_C1
0.1U_0402_16V4Z
C128
0.1U_0402_16V4Z
C59
1 1 7 GND2 8
XDP_BPM#0 GND3
Place near JXDP1 XDP_BPM#1
9 OBSDATA_A0 OBSDATA_C0
10
11 OBSDATA_A1 12
@ @ OBSDATA_C1
13 14
2 2 XDP_BPM#2 GND4 GND5
15 16
XDP_BPM#3 OBSDATA_A2 OBSDATA_C2
17 18
+3VS R58 OBSDATA_A3 OBSDATA_C3
19 GND6 20
4.7K_0402_5% GND7
21 OBSFN_B0 22
D
1 2 OBSFN_D0 D
+3VS 23 24
2
OBSFN_B1 OBSFN_D1
25 26
XDP_BPM#4 GND8 GND9
27 OBSDATA_B0 28
6 1 SMB_DATA_S3 XDP_BPM#5 OBSDATA_D0
14,37 PCH_SMBDATA 29 30
OBSDATA_B1 OBSDATA_D1 +3VS
31 GND10 32
Q6A XDP_BPM#6 GND11
33 34
DMN66D0LDW-7_SOT363-6 XDP_BPM#7 OBSDATA_B2 OBSDATA_D2 XDP_DBRESET# R40 2 1 1K_0402_5%
35 36
@ R59 OBSDATA_B3 OBSDATA_D3
+3VS 37 GND12 38 CLK_CPU_ITP
H_CPUPWRGD R54 @ H_CPUPWRGD_XDP GND13
4.7K_0402_5% 1 2 1K_0402_5% 39 40 CLK_CPU_ITP 14
R55 @ CFD_PWRBTN#_XDP PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_CPU_ITP#
1 2 +3VS 15,39 PBTN_OUT# 1 2 0_0402_5% 41 42 CLK_CPU_ITP# 14
HOOK1 ITPCLK#/HOOK5
5
CFG0 XDP_HOOK2 43 VCC_OBS_AB 44 XDP_RST#_R

R56 1 @ 2 1K_0402_5% VCC_OBS_CD R39 2 @ 1 1K_0402_5% PLT_RST# 17,35,38,39,45
7 CFG0 SYS_PWROK SYS_PWROK_XDP 45 46 XDP_DBRESET#
SMB_CLK_S3 R57 @ HOOK2 RESET#/HOOK6
14,37 PCH_SMBCLK 3 4 1 2 0_0402_5% 47 48
HOOK3 DBR#/HOOK7
SMB_DATA_S3 49 GND14 50 XDP_TDO
Q6B GND15
SMB_CLK_S3 51 52 XDP_TRST#
SDA TD0
DMN66D0LDW-7_SOT363-6 53 54 XDP_TDI
SCL TRST#
@ XDP_TCK 55 56 XDP_TMS
TCK1 TDI
57 58
TCK0 TMS
59 60
GND16 GND17
SAMTE_BSH-030-01-L-D-A
/
/x
SNB_IVB# had changed the name to JCPU1B
su
PROC_SELCT#,function for future platform,
C C
connect to the DF_TVS strap on the PCH
CLK_CPU_DMI
A28 CLK_CPU_DMI 14
MISC
BCLK CLK_CPU_DMI#
CLOCKS
17 H_SNB_IVB# C26 A27 CLK_CPU_DMI# 14
SNB_IVB# BCLK#
p.
AN34 If use External Graphic or
SKTOCC#
A16 R516 2 1 1K_0402_5% use integrated without eDP
DPLL_REF_SSCLK R518 2
A15 1 1K_0402_5% +1.05VS_VTT
DPLL_REF_SSCLK# DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT
om
T6 PAD H_CATERR#
AL33 CATERR#
@
R93
THERMAL
0_0402_5%
H_PECI_ISO SM_DRAMRST#
Processor Pullups 18,39 H_PECI 1 2 AN33 PECI SM_DRAMRST# R8 SM_DRAMRST# 6
H_CPUPWRGD_R
DDR3
MISC
R84 +1.05VS_VTT
2 1 10K_0402_5% 2 R91 1 62_0402_5% R92
yc
H_PROCHOT# 56_0402_5% H_PROCHOT#_R SM_RCOMP0 R231 2 1 140_0402_1%
39,49 H_PROCHOT# AL32 AK1 SM_RCOMP1
1 2 PROCHOT# SM_RCOMP[0]
A5 SM_RCOMP2 R566 2 1 25.5_0402_1%
SM_RCOMP[1]
R97 SM_RCOMP[2] A4 R571 2 1 200_0402_1%
0_0402_5% H_THEMTRIP#_R
18 H_THRMTRIP# 1 2 AN32 THERMTRIP#
DDR3 Compensation Signals
PU/PD for JTAG signals
m
+1.05VS_VTT
Buffered reset to CPU
+3VS XDP_TMS
0_0402_5% R106 2 1 51_0402_5%
XDP_PRDY#_R @ XDP_PRDY#
AP29XDP_PREQ#_R 2 1R80 XDP_TDI_R
PRDY# XDP_PREQ# R99
@ 1R83 2 1 51_0402_5%
+1.05VS_VTT
// PREQ#
AP27
XDP_TCK
2
0_0402_5% XDP_TDO
1 R96 AR26 XDP_TMS ESD request...2010/07/27 R105 2 1 51_0402_5%
C162 TCK
PWR MANAGEMENT
JTAG & BPM

B AR27 XDP_TRST# XDP_TCK B
0.1U_0402_16V4Z 0_0402_5% H_PM_SYNC_R TMS
15 H_PM_SYNC 1 2 AM34 AP30 R111 2 1 51_0402_5%
PM_SYNC TRST#
XDP_TDI_R XDP_TDI XDP_TRST#
1
2
R81 AR28 XDP_TDO_R 1 R100 2 0_0402_5%XDP_TDO
p:
R90 TDI R95 2 1 51_0402_5%

0_0402_5% H_CPUPWRGD_R TDO
AP26 1 R110 2 0_0402_5%
75_0402_5% 18 H_CPUPWRGD AP33
朆 ⢾䘬暣OK
1 2 UNCOREPWRGOOD
@
5
U7 R87 UNCOREPWRGOOD: CORE

R782 2 BUFO_CPU_RST# 43_0402_1% BUF_CPU_RST# DBRESET#_R XDP_DBRESET#
2
1
0_0402_5% 1 XDP_DBRESET# 15
P
PLT_RST# NC 1 2 PM_DRAM_PWRGD_R AL35 1 R101 2 0_0402_5%

DBR#
tt
4 V8
R64 2 2 Y SM_DRAMPWROK
1
1
A XDP_BPM#0
G
0_0402_5% SN74LVC1G07DCKR_SC70-5 SM_DRAMPWROK:DRAM power ok XDP_BPM#0_R

@ AT28 XDP_BPM#1_R 0_0402_5% 2 @ 1 R79 XDP_BPM#1
BPM#[0]
R88 AR29
3
BPM#[1] XDP_BPM#2_R 0_0402_5% 2 @ XDP_BPM#2

1 R75
h
0_0402_1% BUF_CPU_RST# AR30 XDP_BPM#3_R 0_0402_5% 2 @ @ R73 XDP_BPM#3

AR33
BPM#[2]
AT30
0_0402_5% 2 1 1R66
悥ok⼴婳CPU reset
RESET# BPM#[3] XDP_BPM#4_R XDP_BPM#4
2
BPM#[4] AP32 XDP_BPM#5_R XDP_BPM#5

RESET#: AR31 0_0402_5%2 2 @ @ 1 1R51R62
0_0402_5% XDP_BPM#6
BPM#[5] XDP_BPM#6_R
AT31 XDP_BPM#7_R 0_0402_5% 2 @@ R52 XDP_BPM#7
BPM#[6]
AR32 0_0402_5% 2 1 1R53
BPM#[7]
+3VALW
+1.5V_CPU_VDDQ
ESD request...2010/07/27
CONN@
1
C307
1
0.1U_0402_16V4Z
R205
2
200_0402_5%
U11
A
2
74AHC1G09GW_TSSOP5 A
5
15 SYS_PWROK PM_SYS_PWRGD_BUF PM_DRAM_PWRGD_R

1 1
P
15 PM_DRAM_PWRGD B 2
O 4 R204 0_0402_1%
2
A
G
R203
3
39_0402_1%
@
2010/08/11 2011/08/11 Title
2
Issued Date Deciphered Date

PROCESSOR(2/7) PM,XDP,CLK
Custom 0.1
5 4 3 2 Date: Friday, August 27, 2010 1 Sheet 5 of 59
5 4 3 2 1
JCPU1C JCPU1D
11 DDR_A_D[0..63] AB6 SA_CLK_DDR0 11 12 DDR_B_D[0..63] AE2 SB_CLK_DDR0 12

SA_CLK[0] SB_CLK[0]
AA6 SA_CLK_DDR#0 11 AD2 SB_CLK_DDR#0 12
DDR_A_D0 SA_CLK#[0] DDR_B_D0 SB_CLK#[0]
C5 V9 DDRA_CKE0_DIMMA 11 C9 R9 DDRB_CKE0_DIMMB 12
DDR_A_D1 SA_DQ[0] SA_CKE[0] DDR_B_D1 SB_DQ[0] SB_CKE[0]
D5 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 D10
D2 C8
D6 AA5 SA_CLK_DDR1 11 A9 AE1 SB_CLK_DDR1 12
D DDR_A_D5 SA_DQ[4] SA_CLK[1] DDR_B_D5 SB_DQ[4] SB_CLK[1] D
C6 AB5 SA_CLK_DDR#1 11 A8 AD1 SB_CLK_DDR#1 12
DDR_A_D6 SA_DQ[5] SA_CLK#[1] DDR_B_D6 SB_DQ[5] SB_CLK#[1]
C2 V10 DDRA_CKE1_DIMMA 11 D9 SB_CKE[1] R10 DDRB_CKE1_DIMMB 12
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_B_D7 SB_DQ[6]
C3 D8
F10 G4
F8 F4 SB_DQ[9]
DDR_A_D10 SA_DQ[9] DDR_B_D10 F1
G10 AB4 SB_DQ[10] SB_CLK[2] AB2
DDR_A_D11 SA_DQ[10] SA_CLK[2] DDR_B_D11 G1
G9 AA4 SB_DQ[11] AA2
DDR_A_D12 SA_DQ[11] SA_CLK#[2] DDR_B_D12 SB_CLK#[2]
F9 W9 G5 T9
DDR_A_D13 SA_DQ[12] SA_CKE[2] DDR_B_D13 SB_DQ[12] SB_CKE[2]
F7 F5 SB_DQ[13]
DDR_A_D14 SA_DQ[13] DDR_B_D14
G8 F2 SB_DQ[14]
G7 G2
K4 AB3 J7 SB_DQ[16] AA1
DDR_A_D17 SA_DQ[16] SA_CLK[3] DDR_B_D17 SB_CLK[3]
K5 AA3 J8 SB_DQ[17] AB1
DDR_A_D18 SA_DQ[17] SA_CLK#[3] DDR_B_D18 SB_CLK#[3]
K1 W10 K10 SB_DQ[18] T10
DDR_A_D19 SA_DQ[18] SA_CKE[3] DDR_B_D19 SB_CKE[3]
J1 K9 SB_DQ[19]
DDR_A_D21 J5 J9
SA_DQ[20] DDR_B_D21 SB_DQ[20]
J4 J10
K8 AD3
DDR_A_D23 J2
SA_DQ[22] SA_CS#[0] AK3 DDRA_CS0_DIMMA# 11 DDR_B_D23
K7
SB_DQ[22] SB_CS#[0] DDRB_CS0_DIMMB# 12
AE3
DDR_A_D24 K2 SA_DQ[23] SA_CS#[1] AL3 DDRA_CS1_DIMMA# 11 DDR_B_D24
M5
SB_DQ[23] SB_CS#[1] DDRB_CS1_DIMMB# 12
M8 AD6
DDR_A_D25 SA_DQ[24] SA_CS#[2] AG1 DDR_B_D25
N4
SB_DQ[24] SB_CS#[2]
AE6
/
N10
DDR_A_D26 SA_DQ[25] SA_CS#[3] AH1 DDR_B_D26
N2
SB_DQ[25] SB_CS#[3]
DDR_A_D27 N8 SA_DQ[26] DDR_B_D27 SB_DQ[26]
DDR_A_D28 N7 N1
M10 M4
/x
DDR_A_D30 M9 SA_ODT[0] AH3 SA_ODT0 11 DDR_B_D30
N5
SB_DQ[29] SB_ODT[0] AE4 SB_ODT0 12
DDR SYSTEM MEMORY B

SA_DQ[29]
DDR_A_D31 N9 SA_ODT[1] AG3
SA_ODT1 11 M2 SB_ODT[1] AD4 SB_ODT1 12
DDR SYSTEM MEMORY A

M1
DDR_A_D32 M7
SA_DQ[31] SA_ODT[2] AG2 DDR_B_D32 SB_DQ[31] SB_ODT[2] AD5
AM5
DDR_A_D33 AG6 SA_DQ[32] SA_ODT[3] AH2 DDR_B_D33 SB_DQ[32] SB_ODT[3] AE5
DDR_A_D34 AG5 DDR_B_D34 AM6 SB_DQ[33]
SA_DQ[33] AR3
DDR_A_D35 AK6 DDR_B_D35 SB_DQ[34]
su
DDR_A_D36 SA_DQ[34] AP3
AK5 SA_DQ[35] DDR_B_D36 SB_DQ[35]
C DDR_A_D37 AH5 DDR_A_DQS#0 DDR_A_DQS#[0..7] 11 DDR_B_D37 AN3 DDR_B_DQS#[0..7] 12 C
SA_DQ[36] SB_DQ[36] D7 DDR_B_DQS#0
DDR_A_D38 AH6 C4 DDR_A_DQS#1 DDR_B_D38 AN2 SB_DQS#[0]
SA_DQ[37] SA_DQS#[0] SB_DQ[37] F3 DDR_B_DQS#1
DDR_A_D39 AJ5 G6 DDR_A_DQS#2 DDR_B_D39 AN1 SB_DQS#[1]
SA_DQ[38] SA_DQS#[1] SB_DQ[38] K6 DDR_B_DQS#2
DDR_A_D40 AJ6 J3 DDR_A_DQS#3 DDR_B_D40 AP2 SB_DQS#[2] DDR_B_DQS#3
SA_DQ[39] SA_DQS#[2] SB_DQ[39] N3
DDR_A_D41 AJ8 M6 DDR_A_DQS#4 DDR_B_D41 AP5 SB_DQS#[3] DDR_B_DQS#4
SA_DQS#[3] SB_DQ[40]
p.
DDR_A_D42 SA_DQ[40] AL6 DDR_A_DQS#5 AN9 AN5
AK8 SA_DQS#[4] DDR_B_D42 SB_DQ[41] SB_DQS#[4] DDR_B_DQS#5
DDR_A_D43 SA_DQ[41] AM8 DDR_A_DQS#6 AT5 AP9
AJ9 SA_DQS#[5] DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
DDR_A_D44 SA_DQ[42] AR12 DDR_A_DQS#7 AT6 AK12
AK9 SA_DQS#[6] DDR_B_D44 SB_DQ[43] SB_DQS#[6] DDR_B_DQS#7
DDR_A_D45 SA_DQ[43] AM15 AP6 AP15
AH8 SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 SA_DQ[44] DDR_B_D46 AN8
AH9 SB_DQ[45]
om
DDR_A_D47 SA_DQ[45] AR6
AL9 DDR_B_D47 SB_DQ[46]
DDR_A_D48 SA_DQ[46] AR5
AL8 DDR_B_D48 SB_DQ[47]
DDR_A_D49 SA_DQ[47] DDR_A_DQS0 DDR_A_DQS[0..7] 11 DDR_B_D49 AR9 DDR_B_DQS[0..7] 12
AP11 SB_DQ[48] DDR_B_DQS0
DDR_A_D50 SA_DQ[48] D4 DDR_A_DQS1 AJ11 SB_DQS[0] C7
AN11 SA_DQS[0] DDR_B_D50 SB_DQ[49] DDR_B_DQS1
DDR_A_D51 SA_DQ[49] F6 DDR_A_DQS2 DDR_B_D51 AT8 SB_DQS[1] G3
AL12 SA_DQS[1] SB_DQ[50] DDR_B_DQS2
DDR_A_D52 SA_DQ[50] K3 DDR_A_DQS3 DDR_B_D52 AT9 SB_DQS[2] J6
AM12 SA_DQS[2] SB_DQ[51] DDR_B_DQS3
DDR_A_D53 SA_DQ[51] N6 DDR_A_DQS4 DDR_B_D53 AH11 SB_DQS[3] M3
AM11 SA_DQS[3] SB_DQ[52] AN6 DDR_B_DQS4
DDR_A_D54 SA_DQ[52] AL5 DDR_A_DQS5 DDR_B_D54 AR8 SB_DQS[4]
AL11 SA_DQS[4] SB_DQ[53] DDR_B_DQS5
yc
DDR_A_D55 SA_DQ[53] AM9 DDR_A_DQS6 DDR_B_D55 AJ12 AP8
AP12 SA_DQS[5] SB_DQ[54] SB_DQS[5] DDR_B_DQS6
DDR_A_D56 SA_DQ[54] AK11
AN12 AR11 DDR_A_DQS7 DDR_B_D56 AH12 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
DDR_A_D57 SA_DQ[55] SA_DQS[6] DDR_B_D57 AT11 AP14
AJ14 AM14 SB_DQ[56] SB_DQS[7]
DDR_A_D58 SA_DQ[56] SA_DQS[7] AN14
AH14 DDR_B_D58 SB_DQ[57]
DDR_A_D59 SA_DQ[57] DDR_B_D59 AR14
DDR_A_D60 AL15 SB_DQ[58]
SA_DQ[58] DDR_B_D60 AT14
AK15 SB_DQ[59]
m
DDR_A_D61 SA_DQ[59] DDR_A_MA0 DDR_A_MA[0..15] 11 DDR_B_D61 AT12 DDR_B_MA[0..15] 12
AL14 SB_DQ[60] DDR_B_MA0
DDR_A_D62 SA_DQ[60] AA8
AK14 AD10 DDR_A_MA1 DDR_B_D62 AN15
SB_DQ[61] SB_MA[0] DDR_B_MA1
DDR_A_D63 SA_DQ[61] SA_MA[0] T7
AJ15 W1 DDR_A_MA2 DDR_B_D63 AR15
SA_DQ[62] SA_MA[1] R7
AH15 W2 DDR_A_MA3 AT15
SA_DQ[63] SA_MA[2] T6
W7 DDR_A_MA4 SB_MA[3] DDR_B_MA4
SA_MA[3]
SA_MA[4]
V3
//
DDR_A_MA5
DDR_A_MA6
SB_MA[4]
SB_MA[5]
T2
T4
DDR_B_MA5
V2 DDR_B_MA6
SA_MA[5] T3
B SA_MA[6] W3 DDR_A_MA7 AA9 SB_MA[6] DDR_B_MA7 B
11 DDR_A_BS0 12 DDR_B_BS0 R2
AE10 SA_BS[0] SA_MA[7] W6 DDR_A_MA8 AA7
SB_BS[0] SB_MA[7] DDR_B_MA8
11 DDR_A_BS1 AF10 DDR_A_MA9 12 DDR_B_BS1 SB_BS[1] T5 DDR_B_MA9
SA_BS[1] V1 R6 SB_MA[8]
11 DDR_A_BS2 SA_MA[8] 12 DDR_B_BS2 R3
V6 SA_BS[2] W5 DDR_A_MA10 SB_BS[2] SB_MA[9] DDR_B_MA10
SA_MA[9] AB7
p:
AD8 DDR_A_MA11 SB_MA[10] DDR_B_MA11

SA_MA[10] DDR_A_MA12 R1
V4 SB_MA[11] DDR_B_MA12
SA_MA[11] DDR_A_MA13 T1 DDR_B_MA13
W4 AA10 SB_MA[12]
11 DDR_A_CAS# AE8 SA_MA[12] DDR_A_MA14 12 DDR_B_CAS# SB_CAS# AB10 DDR_B_MA14
SA_CAS# AF8 DDR_A_MA15 AB8 SB_MA[13]
11 DDR_A_RAS# AD9 SA_MA[13] 12 DDR_B_RAS# SB_RAS# R5 DDR_B_MA15
SA_RAS# V5 AB9 SB_MA[14]
11 DDR_A_WE# SA_MA[14] 12 DDR_B_WE# R4
tt
AF9 V7 SB_WE# SB_MA[15]

SA_WE# SA_MA[15]
h
Sandy Bridge_rPGA_Rev0p61 CONN@ CONN@
Follow CRB1.0 +1.5V
忂䞍DIMM reset
1
@ R184
0_0402_5% R217
CPU
1 2 1K_0402_5%
R155
2
SM_DRAMRST# DIMM_DRAMRST#_R 1K_0402_5%

5 SM_DRAMRST# DIMM_DRAMRST# 11,12
S
3 1 1 2
Q12
2
BSS138_NL_SOT23-3
S0
R186
G
2
A 4.99K_0402_1% RST_GATE hgih ,MOS ON

<BOM Structure> A
SM_DRAMRST# HIGH,DIMM_DRAMRST# HIGH
Dimm not reset
1
S3
11,12,14 RST_GATE RST_GATE Low ,MOS OFF
SM_DRAMRST# lo,DIMM_DRAMRST# HIGH
Dimm not reset
1 S4,5 Security Classification Compal Secret Data Compal Electronics, Inc.
RST_GATE Low ,MOS OFF Issued Date 2010/08/11 Deciphered Date 2011/08/11 Title
C293
2
0.047U_0402_16V7K SM_DRAMRST# lo,DIMM_DRAMRST# low
PROCESSOR(3/7) DDRIII
Dimm reset Size Document Number Rev
Custom 0.1
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
CFG2
1
R112
1K_0402_1%
2
D D
JCPU1E PEG Static Lane Reversal - CFG2 is for the 16x
RSVD28 L7 1: Normal Operation; Lane # definition matches

RSVD29
AG7 CFG2 socket pin map definition
CFG0 AK28 AE7
5 CFG0 CFG[0] RSVD30
AK29 AK2
CFG2 CFG[1] RSVD31
AL26 W8 0:Lane Reversed
CFG4
CFG5
AL27
AK26
CFG[2]
CFG[3]
CFG[4]
RSVD32
* CFG4
AL29 AT26
CFG6 CFG[5] RSVD33
AL30 AM33
1
CFG7 CFG[6] RSVD34 @
AM31 CFG[7] AJ27
RSVD35
AM32 CFG[8]
AM30 R109
/
CFG[9] 1K_0402_1%
AM28 CFG[10]
AM26
2
CFG[11]
AN28
CFG[12]
/x
AN31 T8
CFG[13] RSVD37
AN26 J16
CFG[14] RSVD38
AM27 H16
CFG[15] RSVD39
AK31 CFG[16] G16
RSVD40
AN29 CFG[17]
Display Port Presence Strap
su
C C
AJ31 change to VAXG_VAL_SENSE AR35 1 : Disabled; No Physical Display Port
AH31
AJ33
change
change
to VSSAXG_VAL_SENSE
to VCC_VAL_SENSE
T4
T2
PAD @
PAD @
AJ31
AH31
RSVD1
RSVD2
RSVD41
RSVD42
RSVD43
AT34
AT33
CFG4 * attached to Embedded Display Port
T3 PAD @ AJ33 AP35
AH33 change to VSS_VAL_SENSE T5 PAD @ RSVD3 RSVD44 AR34 0 : Enabled; An external Display Port device is
AH33
p.
RSVD4 RSVD45
connected to the Embedded Display Port
AJ26
RSVD5
RESERVED
RSVD6 and RSVD7 had changed to
SA_DIMM_VREFDQ and SB_DIMMVREFDQ
om
CFG6
RSVD46 B34
SA_DIMM_VREFDQ
11 SA_DIMM_VREFDQ B4 A33
SB_DIMM_VREFDQ RSVD6 RSVD47 CFG5
12 SB_DIMM_VREFDQ D1 A34
RSVD7 RSVD48
B35
1
RSVD49
SA_DIMM_VREFDQ C35
1
1
RSVD50 R107 R108

SB_DIMM_VREFDQ F25 1K_0402_1% @ @ 1K_0402_1%
R154 R164 RSVD8
For Future CPU M3 support, F24
yc
1K_0402_1% 1K_0402_1% RSVD9
F23
2
Sandey bridge not supportM3, D24
RSVD10 AJ32
2
2
RSVD11 RSVD51
Check list1.0&CRB say can NC G25
RSVD12 RSVD52
AK32
G24
RSVD13 AH27 change to VCC_DIE_SENSE
E23
RSVD14
D23
m
RSVD15
C30 AH27 PAD T7
RSVD16 RSVD53
A31 @
RSVD17
B30 RSVD18
B29 PCIE Port Bifurcation Straps
RSVD19
D30 AN35
VCCIO_SEL
B31
RSVD20
RSVD21
// RSVD54
RSVD55 AM35
RSVD54 and RSVD55 had changed to 11: (Default) x16 - Device 1 functions 1 and 2 disabled
A30
*10: x8, x8 - Device 1 function 1 enabled ; function 2
1
RSVD22
B C29 RSVD23 BCLK_ITP and BCLK_ITP# B
R513 CFG[6:5]
@ 10K_0402_5% disabled
J20 RSVD24 01: Reserved - (Device 1 function 1 disabled ; function
p:
B18 AT2
2
VCCIO_SEL RSVD25 RSVD56

A19 RSVD26 RSVD57 AT1 2 enabled)
RSVD58 AR1
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
VCCIO_SEL For 2012 CPU support J15
RSVD27
tt
1/NC : (Default) +1.05VS_VTT

A19 * 0: +1.0VS_VTT
KEY B1 CFG7
h
1
R102
RSVD26 had changed the name to VCCIO_SEL @ 1K_0402_1%
Need PH +3VALW 10K at +1.05VS_VTT source
2
for 2012 processor +1.05V and +1.0V select
CONN@
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion
A
0: PEG Wait for BIOS for training A
Security Classification
2010/08/11
Compal Secret Data
2011/08/11 Title
Compal Electronics, Inc.
PROCESSOR(4/7) RSVD,CFG
Custom 0.1
5 4 3 2 1
5 4 3 2 1
SV type CPU JCPU1F POWER

+CPU_CORE
QC 94A
+1.05VS_VTT
DC 53A 8.5A
AG35
VCC1 +1.05VS_VTT
1 1 1 1 1 AG34 AH13
VCC2 VCCIO1
22U_0805_6.3V6M
10U_0805_6.3V6M
C204
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
C206
22U_0805_6.3V6M
10U_0805_6.3V6M
C202
22U_0805_6.3V6M
10U_0805_6.3V6M
C205
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
C203
AG33 AH10 1 1 1 1 1 1 1 1 1 1
VCC3 VCCIO2
AG32 AG10
VCC4 VCCIO3
C292
C652
C229
C288
C647
C641
C232
C291
C290
C289
2 AG31 VCC5 AC10
2 2 2 2 VCCIO4
AG30 VCC6 Y10 2
D VCCIO5 2 2 2 2 2 2 2 2 2 D
AG29 U10
VCC7 VCCIO6
AG28 P10
VCC8 VCCIO7
AG27 L10
VCC9 VCCIO8
AG26 VCC10 J14
VCCIO9
AF35 VCC11 J13
1 1 VCCIO10
1 1 ' 1 AF34 J12
VCC12
10U_0805_6.3V6M
C222
10U_0805_6.3V6M
C207
22U_0805_6.3V6M
VCCIO11
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
C223
10U_0805_6.3V6M
C227
10U_0805_6.3V6M
C218
AF33 J11 1 1 1 1 1 1
VCC13
330U_D2_2V_Y
VCCIO12
330U_D2_2V_Y
AF32 H14
VCC14
C638
C648
+
C651
VCCIO13
C649
C650
C616
AF31 +
2 2 2 2 VCC15 VCCIO14 H12
2 AF30 H11 @ @
VCC16 VCCIO15 2 2 2 2
AF29 VCC17 G14 2
VCCIO16 2
AF28 VCC18 G13
VCCIO17
PEG AND DDR

AF27 VCC19 G12
AF26
VCCIO18
VCC20 F14
AD35 VCCIO19
VCC21 F13
AD34 VCCIO20
+CPU_CORE VCC22 F12
AD33 VCCIO21
VCC23 VCCIO22 F11
AD32
AD31
VCC24 VCCIO23 E14
E12
INTEL Recommend
VCC25 VCCIO24
1 1 1 1 1 1
AD30
AD29
VCC26
E11
2*330uF,12*22uF
/
1 1
22U_0805_6.3V6M
C622
22U_0805_6.3V6M
C171
VCC27
22U_0805_6.3V6M
C574
22U_0805_6.3V6M
C160
22U_0805_6.3V6M
C627
22U_0805_6.3V6M
C575
VCCIO25
22U_0805_6.3V6M
C635
22U_0805_6.3V6M
C172
AD28
AD27
VCC28
VCC29
VCCIO26
VCCIO27
D14
D13 from PDDG 1.0
2 2 2 2 2 2 AD26 D12
/x
2 2 VCC30 VCCIO28
AC35 VCC31 D11
AC34 VCCIO29
VCC32 VCCIO30 C14
AC33 VCC33 C13
AC32 VCCIO31
VCC34 VCCIO32 C12
AC31 C11
VCC35 VCCIO33
AC30 B14
VCC36
22U_0805_6.3V6M
1 1 VCCIO34
su
1 1 1 AC29 B12
22U_0805_6.3V6M
C609
22U_0805_6.3V6M
C608
1 1 1 VCC37
22U_0805_6.3V6M
C610
C606
22U_0805_6.3V6M
C224
VCCIO35
22U_0805_6.3V6M
C607
22U_0805_6.3V6M
C225
AC28
22U_0805_6.3V6M
C226
C
VCC38 A14 C
AC27 VCCIO36
VCC39 A13
AC26 VCCIO37
2 2 2 2 2 VCC40 A12
2 2 2 AA35 VCCIO38
VCC41 A11
INTEL Recommend AA34 VCC42
VCCIO39
p.
AA33 J23
VCC43 VCCIO40
4*470uF,16*22uF and 10*10uF AA32
AA31
VCC44
VCC45
from PDDG 1.0 AA30
AA29
VCC46
VCC47
om
AA28
VCC48
AA27
VCC49
+CPU_CORE AA26 +1.05VS_VTT +1.05VS_VTT
VCC50
CORE SUPPLY
Follow Power Suggestion , Y35
VCC51
Y34
place 3-pin Cap for CPU_CORE VCC52
Y33
1
VCC53
1
Y32 R447
VCC54
Y31 R450 75_0402_5%
1 1 1 VCC55
yc
1 Y30
470U_D2_2VM_R4M
130_0402_5%
470U_D2_2VM_R4M
470U_D2_2VM_R4M
1 VCC56
470U_D2_2VM_R4M
470U_D2_2VM_R4M
Y29
C626
+
C233
C562
+ + VCC57
C151
2
C152
+ Y28 VCC58
2
Y27 VCC59
2 3 2 3 2 3 Y26 R448
2 3 VCC60
2 3 V35 H_CPU_SVIDALRT#
SVID
VCC61 43_0402_1% VR_SVID_ALRT# 54
m
V34 VIDALERT# AJ29 H_CPU_SVIDCLK
VCC62 AJ30 H_CPU_SVIDDAT 1 2 VR_SVID_CLK 54
V33 VIDSCLK R446 2 0_0402_5%
PAW00 V32
VCC63
VCC64 VIDSOUT
AJ28
R449 1 1 2 0_0402_5% VR_SVID_DAT 54
V31
use 470uF*2 V30
VCC65
VCC66
330uF*3
// V29
V28
VCC67
VCC68 Place the PU
V27
B VCC69 resistors close to VR B
V26
VCC70
U35
VCC71
U34
VCC72
U33
p:
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
tt
VCC78
U27
VCC79 +CPU_CORE
Place the PU
U26
R35
VCC80 resistors close to CPU
VCC81
R34
VCC82
h
1
R33 VCC83
R32 VCC84 R445
R31 VCC85 100_0402_1%
R30 VCC86
R29
SENSE LINES
VCC87
2
R28 VCCSENSE_R
VCC88 VSSSENSE_R R444 1 2 0_0402_5% VCCSENSE 54
R27 VCC_SENSE AJ35 R443 1 0_0402_5%
VCC89 2 VSSSENSE 54
R26 VSS_SENSE AJ34
VCC90
P35 VCC91
P34 VCC92
1
P33 VCCIO_SENSE 52
VCC93 VSSIO_SENSE
P32 B10 R442
VCC94 VCCIO_SENSE A10
VSSIO_SENSE
P31 VSSIO_SENSE
1
VCC95 100_0402_1%
P30 change to
VCC96
P29
VCC97 VSS_SENSE_VCCIO R163
2
P28
VCC98 10_0402_5%
P27
VCC99
P26
2
VCC100 Should change to connect form
A A
power cirucit & layout differential
with VCCIO_SENSE.
IssuedCONN@
Date 2010/08/11 Deciphered Date 2011/08/11 Title
PROCESSOR(5/7) PWR,BYPASS
Custom 0.1
5 4 3 2 1
5 4 3 2 1
D D
INTEL Recommend
2*470uF,12*22uF
+VGFX_CORE
from PDDG 1.0 QC 33A POWER
/
JCPU1G
DC 26A
SENSE
LINES
/x
AT24 AK35 VCC_AXG_SENSE 54
1
UMA@ UMA@ UMA@ UMA@ VAXG1 VAXG_SENSE

UMA@ UMA@ AT23 AK34 VSS_AXG_SENSE 54
22U_0805_6.3V6M
VSSAXG_SENSE
22U_0805_6.3V6M
VAXG2
22U_0805_6.3V6M
22U_0805_6.3V6M
R151
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 AT21
C625
C211
VAXG3
C231
C272
C611
C212
0_0402_5% AT20 +1.5V_CPU_VDDQ
VAXG4
DISO@ AT18
VAXG5
AT17
2
2 2 2 2 2 VAXG6
2
su
AR24 VAXG7 +V_SM_VREF should
1
C AR23 VAXG8 C
AR21 VAXG9 have 20 mil trace width R582
AR20 100_0402_1%
VREF
VAXG10
AR18 VAXG11
AR17 +V_SM_VREF
VAXG12
2
AP24 AL1
p.
VAXG13 SM_VREF
AP23
UMA@ UMA@ VAXG14
1
UMA@ UMA@ UMA@ UMA@ AP21 1
22U_0805_6.3V6M
VAXG15
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 C688
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 AP20 R575
C209
1 1 VAXG16
C275
C271
C274
0.1U_0402_16V4Z
C210
C242
AP18 100_0402_1%
VAXG17
AP17
om
VAXG18 2
2 2 2 2 AN24
VAXG19
2
2 2 AN23
VAXG20 <BOM Structure>
AN21 +1.5V_CPU_VDDQ
VAXG21
AN20 VAXG22 +1.5V
DDR3 -1.5V RAILS

AN18 VAXG23 J1
AN17 VAXG24 10A
GRAPHICS
AM24 AF7 1 2
VAXG25 VDDQ1
AM23 AF4
yc
VAXG26 VDDQ2 PAD-OPEN 4x4m
AM21 AF1 1
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
VAXG27 @
330U_D2_2V_Y
VDDQ3 1 1 1 1 1
10U_0805_6.3V6M
AM20 AC7
22U_0805_6.3V6M
VAXG28 1
C355
22U_0805_6.3V6M
1 1 VDDQ4 +
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 AM18 AC4 +1.5VS
C362
C599
C365
330U_D2_2V_Y
C363
C361
1
C341
1 VAXG29
330U_D2_2V_Y
C208
VDDQ5
C273
C364
C600
AM17 AC1
C646
UMA@ + VAXG30
C645
+ UMA@ VDDQ6 J2
AL24 VAXG31 Y7 2 2 2 2 2 2
@ VDDQ7 2 1 2
m
2 @ UMA@ 2 AL23 VAXG32 Y4
2 VDDQ8
2 2 UMA@ 2 AL21 VAXG33 VDDQ9
Y1
AL20 U7 PAD-OPEN 4x4m
VAXG34 VDDQ10 @
AL18 VAXG35 U4
VDDQ11
AL17 U1
VAXG36 VDDQ12
// AK24
AK23
VAXG37
VAXG38
VDDQ13 P7
P4 Short for +1.5VS to +1.5V_1
Vaxg AK21
VDDQ14
P1
VAXG39 VDDQ15
INTEL Recommend
Ʉ Can connect to GND if motherboard only
B AK20 B
VAXG40
AK18
AK17
VAXG41
VAXG42 INTEL Recommend 1*330uF,6*10uF
supports external graphics and if GFX VR is not AJ24
p:
VAXG43
AJ23 1*330uF,3*10uF from PDDG 1.0
Ʉ VAXG can be left floating in a common
stuffed in a common motherboard design, AJ21
VAXG44
VAXG45
AJ20
AJ18
VAXG46 from PDDG 1.0
motherboard design (Gfx VR keeps VAXG from AJ17
VAXG47 +VCCSA
VAXG48 6A
tt
floating) if the VR is stuffed
SA RAIL
AH24 VAXG49
AH23 +VCCSA
VAXG50
AH21 VAXG51 M27
VCCSA1
AH20 VAXG52 M26
VCCSA2
h
10U_0805_6.3V6M
AH18 VCCSA_SENSE
10U_0805_6.3V6M
L26
10U_0603_6.3V6M
10U_0805_6.3V6M
VAXG53 VCCSA3 1 1 1 R1371 2 0_0402_5%
AH17 J26 1
VAXG54 VCCSA4
C219
C605
J25
C213
If possible,use os-con cap
C214
VCCSA5 1
330U_D2_2V_Y
J24 @
VCCSA6 2 2 if not,use the D2 size
C221
H26 2 2 +
VCCSA7
VCCSA8 H25
R1411 2 0_0402_5%
1.8V RAIL
VSSSA_SENSE 51
2
+1.8VS
R528
1.2A
0_0805_5%
+1.8VS_VCCPLL
1 2 VCCSA_SENSE 51
B6 H23
MISC
VCCPLL1 VCCSA_SENSE
A6
1U_0402_6.3V6K
C653
1 VCCPLL2
1U_0402_6.3V6K
C654
1 1 A2 VCCSA
VCCPLL3 VCCSA_VID0
330U_D2_2V_Y
10U_0805_6.3V6M
C655
1 VCCSA_VID1
C664
+ C22 VCCSA_VID1 51 VID0 VID1 Vout 2011CPU 2012CPU

FC_C22
2 C24
2 VCCSA_VID1 0 0 0.9V V V
FC_C22
2
2
1
2
A change to R143
0 1 0.8V V V A
Sandy Bridge_rPGA_Rev0p61 10K_0402_5% R138
VCCSA_VID0 @ 0_0402_5%
1 0 0.725V X V
INTEL Recommend
1
CONN@
2
1 1 0.675V X V
1*330uF,1*10uF and 2*1uF(0402)
from PDDG 1.0 Security Classification Compal Secret Data Compal Electronics, Inc.
PROCESSOR(6/7) PWR
Custom 0.1
5 4 3 2 1
5 4 3 2 1
JCPU1H JCPU1I
D D
AT35 AJ22
VSS1 VSS81
AT32 AJ19
VSS2 VSS82
AT29 AJ16 T35 F22
VSS3 VSS83 VSS161 VSS234
AT27 VSS4 AJ13 T34 F19
VSS84 VSS162 VSS235
AT25 VSS5 AJ10 T33 E30
VSS85 VSS163 VSS236
AT22 AJ7 T32 E27
AT19 AJ4 T31 E24
AT16 AJ3 T30 E21
AT13 AJ2 T29 E18
AT10 AJ1 T28 E15
AT7 VSS11 AH35 T27 E13
AT4 VSS91 VSS169 VSS242
VSS12 AH34 T26 E10
VSS92 VSS170 VSS243
AT3 VSS13 AH32 P9 E9
VSS93 VSS171 VSS244
AR25 VSS14 AH30 P8 E8
VSS94 VSS172 VSS245
AR22 VSS15 AH29 P6 E7
AR19 VSS95 VSS173 VSS246
VSS16 AH28 P5 E6
VSS17 VSS97 AH26 P3 E5
AR13 AH25 VSS175 VSS248
VSS18 VSS98 P2 E4
VSS19 VSS99 N35 E3
VSS20 VSS100 N34 E2
VSS21 N33 E1
/
VSS22 AH7 N32 D35
AP34 VSS102 VSS180 VSS253
VSS23 AH4 N31 D32
VSS24 VSS104 AG9 N30 D29
VSS182
/x
AP28 AG8 N29 VSS255
VSS25 VSS105 VSS183 VSS256 D26
AP25 AG4 N28 D20
AP22 AF6 N27 D17
AP19 VSS28 AF5 N26 C34
VSS29 AF3 M34 C31
VSS30 AF2 L33 C28
AE35
su
VSS31 VSS111 L30 C27
AP7 AE34 VSS189 VSS262
C VSS32 VSS112 L27 C25 C
VSS33 VSS113 L9 C23
VSS34 VSS114 L8 C10
AN30 AE31 VSS192 VSS265
VSS35 VSS115 L6 C1
AN27 AE30 VSS193 VSS266
VSS36 VSS116 L5 B22
AN25 VSS194 VSS267
VSS AE29 L4
p.
VSS37 B19
AN22
AN19
VSS38
VSS39
VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269 B17
B15
AN16 AE26 L1 VSS270
VSS40 VSS120 VSS198 B13
AN13
VSS41 AE9 K35 VSS271
AN10 VSS121 VSS199 B11
AD7 VSS272
om
VSS42 VSS122 K32 B9
AN7 AC9 VSS200 VSS273
VSS43 VSS123 K29 B8
AN4 AC8 VSS201 VSS274
VSS44 VSS124 K26 B7
AM29 AC6 VSS202 VSS275
VSS45 VSS125 J34 B5
VSS46 VSS126 J31 B3
VSS47 VSS127 H33 B2
VSS48 VSS128 H30 A35
AM16 AB35 VSS206 VSS279
VSS49 VSS129 H27 A32
AM13 AB34 VSS207 VSS280
VSS50 H24
yc
AM10 VSS130 VSS208 A29
VSS51 AB33 H21 VSS281
AM1 VSS135 VSS213
AB28
m
VSS56 VSS136 H9
AL34 AB27 VSS214
VSS57 VSS137 H8
AL31 AB26 VSS215
VSS58 VSS138 H7
AL28 Y9 VSS216
VSS59 VSS139 H6
AL25 Y8 VSS217
VSS60 VSS140 H5
AL22 Y6 VSS218
AL19
AL16
VSS61
VSS62
// VSS141
VSS142 Y5
H4
H3
VSS219
VSS220
VSS63 VSS143 Y3 H2
AL13 Y2 VSS221
B VSS64 VSS144 H1 B
AL10 W35 VSS222
VSS65 VSS145 G35
AL7 W34 VSS223
VSS66 VSS146 G32
AL4 W33 VSS224
VSS67 VSS147 G29
p:
AL2 VSS68 W32 VSS225

AK33 VSS148 G26
VSS69 W31 VSS226
AK30 VSS149 G23
VSS70 W30 VSS227
AK27 VSS150 G20
VSS71 W29 VSS228
AK25 VSS151 G17
VSS72 W28 VSS229
AK22 VSS152 G11
tt
VSS73 W27 VSS230

AK19 VSS153 F34
VSS74 W26 VSS231
AK16 VSS154 F31
VSS75 U9 VSS232
AK13 VSS155 F29
VSS76 U8 VSS233
AK10 VSS156
h
VSS77 U6
AK7 VSS157
VSS78 U5
AK4 VSS158
VSS79 U3
AJ25 VSS159
VSS80 U2
VSS160
CONN@
CONN@
A A

PROCESSOR(7/7) VSS
Custom 0.1
5 4 3 2 1
5 4 3 2 1
+1.5V
1
R320
1K_0402_1%
+1.5V +1.5V
M3 support @ R133
0_0402_5% JDIMM1
2
+V_DDR_REFA 1 VREF_DQ 2
7 SA_DIMM_VREFDQ 1 2 VSS1
3 VSS2 4 DDR_A_D4
DQ4
2.2U_0603_6.3V6K
1
0.1U_0402_16V4Z
DDR_A_D0 5 DQ0 6 DDR_A_D5
DQ5
C408
C411
DDR_A_D1 7 DQ1 8
VSS3
D
3 1 R319 1 1 9 VSS4 10 DDR_A_DQS#0
Q46 DDR_A0_DM0 DQS#0 DDR_A_DQS0
1K_0402_1% 11 DM0 12
BSS138_NL_SOT23-3 @ DQS0
13 VSS5 14
VSS6
2
DDR_A_D2 DDR_A_D6
G
D 15 DQ2 16 D
2
2 2 DDR_A_D3 DQ6 DDR_A_D7
6,12,14 RST_GATE 17 DQ3 18
DQ7
19 VSS7 20
DDR_A_D8 VSS8 DDR_A_D12
DDR_A_DQS#[0..7] 6 21 DQ8 22
DDR_A_D9 DQ12 DDR_A_D13
23 DQ9 24
DQ13
DDR_A_DQS[0..7] 6 25 VSS9 26
DDR_A_DQS#1 VSS10 DDR_A0_DM1
27 DQS#1 28
DDR_A_DQS1 DM1 DDR3_DRAMRST#
DDR_A_D[0..63] 6 29 DQS1 30 DIMM_DRAMRST# 6,12
RESET#
All VREF traces should DDR_A_D10 31 VSS11
VSS12
32
DDR_A_D14
DDR_A_MA[0..15] 6 33 34
have 10 mil trace width DDR_A_D11 DQ10
35 DQ11
DQ14
36
DDR_A_D15
DQ15
DDR_A_D16 37 VSS13 38
VSS14 DDR_A_D20
DDR_A_D17 39 DQ16 40
DQ20 DDR_A_D21
41 DQ17 42
Layout Note: DQ21
DDR_A_DQS#2 43 VSS15 44
VSS16 DDR_A0_DM2
Place near JDIMM1 DDR_A_DQS2 45 DQS#2 46
DM2
+1.5V 47 DQS2 48
VSS17 DDR_A_D22
DDR_A_D18 49 VSS18 50 DDR_A_D23
DQ22
DDR_A_D19 51 DQ18 52
DQ23
53 DQ19 54 DDR_A_D28
VSS19
DDR_A_D24 55 VSS20 56
1U_0402_6.3V6K
C409
DQ28 DDR_A_D29
1U_0402_6.3V6K
C385
1U_0402_6.3V6K
C410
1U_0402_6.3V6K
C371
DDR_A_D25 57 DQ24 58
1 DQ29
1 59 DQ25 60 DDR_A_DQS#3
1 1 VSS21
DDR_A0_DM3 61 VSS22 62 DDR_A_DQS3
DQS#3
63 DM3 64
DQS3
2 2 DDR_A_D26 65 VSS23 66 DDR_A_D30
2 2 VSS24
DDR_A_D27 67 DQ26 68 DDR_A_D31
DQ30
/
69 DQ27 70
DQ31
71 VSS25 72
VSS26
/x
DDRA_CKE0_DIMMA DDRA_CKE1_DIMMA
6 DDRA_CKE0_DIMMA 73 74 DDRA_CKE1_DIMMA 6
+1.5V CKE0 CKE1
75 VDD1 76 DDR_A_MA15
VDD2
DDR_A_BS2 77 78 DDR_A_MA14
6 DDR_A_BS2 NC1 A15
79 BA2 80
A14
DDR_A_MA12 81 82 DDR_A_MA11
10U_0603_6.3V6M
C378
C C
10U_0603_6.3V6M
C415
10U_0603_6.3V6M
C384
10U_0603_6.3V6M
C414
VDD3 VDD4
1 1 1 1 A12/BC# A11
85 86
A9 A7
su
VDD5 VDD6
A8 A6
2 2 2 2 91 A5 92
DDR_A_MA3 A4
93 94 DDR_A_MA2
DDR_A_MA1 VDD7 VDD8
95 96 DDR_A_MA0
A3 A2
97 A1 98
SA_CLK_DDR0 A0 SA_CLK_DDR1
99 100
6 SA_CLK_DDR0 SA_CLK_DDR#0 VDD9 VDD10 SA_CLK_DDR1 6
SA_CLK_DDR#1
p.
101 CK0 102
6 SA_CLK_DDR#0 CK1 SA_CLK_DDR#1 6 +1.5V
103 104
DDR_A_MA10 CK0# CK1# DDR_A_BS1
105 106
DDR_A_BS0 VDD11 VDD12 DDR_A_RAS# DDR_A_BS1 6
+1.5V 107 108
6 DDR_A_BS0 A10/AP BA1 DDR_A_RAS# 6
109 110
DDR_A_WE# BA0 RAS# DDRA_CS0_DIMMA#
111 112
1
6 DDR_A_WE# DDR_A_CAS# VDD13 VDD14 SA_ODT0 DDRA_CS0_DIMMA# 6
113
om
6 DDR_A_CAS# WE# S0# 114 SA_ODT0 6 R267
10U_0603_6.3V6M
C413
115 116
10U_0603_6.3V6M
C412
10U_0603_6.3V6M
1 DDR_A_MA13 CAS# ODT0 SA_ODT1 1K_0402_1%

117 118
330U_D2_2V_Y
1 1 1 DDRA_CS1_DIMMA# VDD15 VDD16 SA_ODT1 6

119 120
C407
C383
+ 6 DDRA_CS1_DIMMA# A13 ODT1
2
121 122
S1# NC2 +VREF_CA
123 VDD17 124
2 VDD18
2 2 2 125 126
DDR_A_D32 NCTEST VREF_CA DDR_A_D36
127 128
2.2U_0603_6.3V6K
DDR_A_D33 VSS27 VSS28 DDR_A_D37
0.1U_0402_16V4Z
C373
129 130
1
C372
DQ32 DQ36
131 132 1 R266
DDR_A_DQS#4 DQ33 DQ37 DDR_A0_DM4 1
yc
@ DDR_A_DQS4 133 VSS29 134 1K_0402_1%
VSS30
135 136
DQS#4 DM4 DDR_A_D38
DDR_A_D34 137 138
DQS4 VSS31 DDR_A_D39 2
2
DDR_A_D35 139 140 2
VSS32 DQ38
141 DQ34 142
DQ39 DDR_A_D44
DDR_A_D40 143 DQ35 144 DDR_A_D45
+0.75VS VSS33
DDR_A_D41 145 VSS34 146
DQ44
147
m
DQ40 DQ45 148 DDR_A_DQS#5
DDR_A0_DM5 149 DQ41 150 DDR_A_DQS5
VSS35
151 VSS36 152
DQS#5
1U_0402_6.3V6K
C395
1U_0402_6.3V6K
C394
1U_0402_6.3V6K
C393
153 154
1U_0402_6.3V6K
C388
B DDR_A_D42 DM5 DQS5 DDR_A_D46 B

1 1 1 DDR_A_D43 155 156 DDR_A_D47
1 VSS37 VSS38
157 DQ42 158
DQ46
159 160
2 2 2 2
// DDR_A_D48
DDR_A_D49 161
163
DQ43
VSS39
DQ47
VSS40
162
164
DDR_A_D52
DDR_A_D53
DQ48 DQ52
DDR_A_DQS#6 165 166 DDR_A0_DM6
DQ49 DQ53
DDR_A_DQS6 167 VSS41 168
VSS42
169 DQS#6 170 DDR_A_D54
DDR_A_D50 DM6
171 DQS6 172 DDR_A_D55
DDR_A_D51 VSS43
173 174
VSS44 DQ54
p:
175 176 DDR_A_D60
Layout Note: DDR_A_D56 DQ50 DQ55
177 178 DDR_A_D61
DDR_A_D57 DQ51 VSS45
Place near JDIMM1.203,204 179 VSS46 180
DQ60
181 182 DDR_A_DQS#7
DDR_A0_DM7 DQ56 DQ61
183 184 DDR_A_DQS7
DQ57 VSS47
185 186
DDR_A_D58 VSS48 DQS#7 DDR_A_D62
187 188
tt
DDR_A0_DM0 DM7 DQS7

0_0402_5% 2 1 R315 DDR_A0_DM1
DDR_A_D59 189 190 DDR_A_D63
0_0402_5% 2 1 R284 VSS49 VSS50
DDR_A0_DM2 191 192
0_0402_5% 2 1 R286 DQ58 DQ62
DDR_A0_DM3 193 DQ59 194
0_0402_5% 2 1 R316 DQ63 D_CK_SDATA
DDR_A0_DM4 195 VSS51 196
0_0402_5% 2 +3VS VSS52 D_CK_SCLK D_CK_SDATA 12,14
1 R285 DDR_A0_DM5 197 198
h
0_0402_5% 2 SA0 EVENT# D_CK_SCLK 12,14

1 R318 DDR_A0_DM6 199 VDDSPD 200
0_0402_5% 2 R283 DDR_A0_DM7 +0.75VS SDA +0.75VS
0_0402_5% 2 11 R312 201 202
SA1 SCL
203 204
0.1U_0402_16V4Z
C404
2.2U_0603_6.3V6K
C416
10K_0402_5%
R301
VTT1 VTT2
1
10K_0402_5%
R302
1 1 205 G1 206
FOX_AS0A626-U8SN-7F G2
CONN@
2 2
2
<Address(SA1,SA0): 00>
A
DIMM_1 Reserve H:8mm A

DDRIII DIMMA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
5 4 3 2 Date: Friday, August 27,12010 Sheet 11 of 59
5 4 3 2 1
+1.5V
1
+1.5V +1.5V
R341 JDIMM2
1K_0402_1% +V_DDR_REFC 1 2
VREF_DQ VSS1 DDR_B_D4
M3 support @ R346
DDR_B_D0
3
VSS2 DQ4 4
2.2U_0603_6.3V6K
DDR_B_D5
0.1U_0402_16V4Z
0_0402_5% 5 6
DQ0 DQ5
C438
DDR_B_D1
C437
7 SB_DIMM_VREFDQ 1 2 7 8
DQ1 VSS3 DDR_B_DQS#0
1 1 9 10
VSS4 DQS#0
1
DDR_B0_DM0 11 12 DDR_B_DQS0
DM0 DQS0
13 VSS5 14
DDR_B_D2 VSS6 DDR_B_D6
D
3 1 R340 15 16
2 2 DDR_B_D3 DQ2 DQ6 DDR_B_D7
Q47 1K_0402_1% 17 18
DQ3 DQ7
BSS138_NL_SOT23-3 @ 19 20
VSS7 VSS8
2
DDR_B_D8 21 22 DDR_B_D12
G
DQ8 DQ12
2
DDR_B_D9 23 24 DDR_B_D13
6,11,14 RST_GATE DQ9 DQ13
D 25 26 D
DDR_B_DQS#1 VSS9 VSS10 DDR_B0_DM1
27 DQS#1 28
DDR_B_DQS1 DM1 DDR3_DRAMRST#
29 30 DIMM_DRAMRST# 6,11
DQS1 RESET#
DDR_B_DQS#[0..7] 6 All VREF traces should DDR_B_D10
31 VSS11 VSS12 32
DDR_B_D14
33 34
DDR_B_DQS[0..7] 6
have 10 mil trace width DDR_B_D11 35
DQ10 DQ14
36 DDR_B_D15
DQ11 DQ15
37 38
DDR_B_D16 VSS13 VSS14 DDR_B_D20
DDR_B_D[0..63] 6 39 DQ16 40
DDR_B_D17 DQ20 DDR_B_D21
41 42
DQ17 DQ21
DDR_B_MA[0..15] 6 43 44
DDR_B_DQS#2 VSS15 VSS16 DDR_B0_DM2
45 46
DDR_B_DQS2 DQS#2 DM2
47 DQS2 48
VSS17 DDR_B_D22
49 50
DDR_B_D18 VSS18 DQ22 DDR_B_D23
51 DQ18 52
DDR_B_D19 DQ23
Layout Note: 53
DQ19 VSS19
54
DDR_B_D28
55 56
Place near JDIMM2 DDR_B_D24
57
VSS20 DQ28
58
DDR_B_D29
+1.5V DDR_B_D25 DQ24 DQ29
59 DQ25 60
VSS21 DDR_B_DQS#3
61 VSS22 62
DDR_B0_DM3 DQS#3 DDR_B_DQS3
63 64
DM3 DQS3
65 VSS23 66
1U_0402_6.3V6K
C444
67 68
1U_0402_6.3V6K
C430
1U_0402_6.3V6K
C429
1U_0402_6.3V6K
C445
DDR_B_D27 DQ26 DQ30 DDR_B_D31

1 69 DQ27 70
1 1 1 DQ31
71 VSS25 72
VSS26
2 2 2 2
DDRB_CKE0_DIMMB DDRB_CKE1_DIMMB
/
6 DDRB_CKE0_DIMMB 73 74 DDRB_CKE1_DIMMB 6
CKE0 CKE1
75 76
VDD1 VDD2 DDR_B_MA15
DDR_B_BS2 77 78 DDR_B_MA14
NC1 A15
6 DDR_B_BS2 79 80
BA2 A14
/x
DDR_B_MA12 81 VDD3 82
VDD4 DDR_B_MA11
+1.5V DDR_B_MA9 83 84 DDR_B_MA7
A12/BC# A11
85 A9 86
A7
DDR_B_MA8 87 88 DDR_B_MA6
VDD5 VDD6
DDR_B_MA5 89 A8 90 DDR_B_MA4
A6
91 92
C A5 A4 C
10U_0603_6.3V6M
C424
10U_0603_6.3V6M
C450
93 94
10U_0603_6.3V6M
C449
10U_0603_6.3V6M
C425
DDR_B_MA3 VDD7 VDD8 DDR_B_MA2

1 DDR_B_MA1 95 A3 96 DDR_B_MA0
1 1 1 A2
su
97 A1 98
A0
SB_CLK_DDR0 99 VDD9 100 SB_CLK_DDR1
6 SB_CLK_DDR0 VDD10 SB_CLK_DDR1 6
SB_CLK_DDR#0 101 102 SB_CLK_DDR#1
2 2 6 SB_CLK_DDR#0 CK0 CK1 SB_CLK_DDR#1 6
2 2 103 104 +1.5V
CK0# CK1#
DDR_B_MA10 105 106 DDR_B_BS1
VDD11 VDD12 DDR_B_BS1 6
DDR_B_BS0 107 108 DDR_B_RAS#
6 DDR_B_BS0 A10/AP BA1 DDR_B_RAS# 6
109 110
BA0 RAS#
DDR_B_WE# 111 112
p.
VDD13 VDD14 DDRB_CS0_DIMMB#
6 DDR_B_WE# 113 114 DDRB_CS0_DIMMB# 6
1
DDR_B_CAS# WE# S0# SB_ODT0
6 DDR_B_CAS# 115 116 SB_ODT0 6
CAS# ODT0 R351
+1.5V DDR_B_MA13 117 VDD15 118 SB_ODT1 1K_0402_1%
VDD16 SB_ODT1 6
DDRB_CS1_DIMMB# 119 120
6 DDRB_CS1_DIMMB# A13 ODT1
121 122
S1# NC2
2
123 124 +VREF_CC
om
VDD17 VDD18
125 NCTEST 126
VREF_CA
10U_0603_6.3V6M
C447
DDR_B_D32 127 128 DDR_B_D36

10U_0603_6.3V6M
10U_0603_6.3V6M
C448
2.2U_0603_6.3V6K
1 VSS27 VSS28
DDR_B_D33 129 130 DDR_B_D37
C451
330U_D2_2V_Y
1 1 1 DQ32 DQ36
1
131 132
0.1U_0402_16V4Z
C446
C426
C359
+ DQ33 DQ37 1
DDR_B_DQS#4 133 134 DDR_B0_DM4 R350
VSS29 VSS30 1
DDR_B_DQS4 135 DQS#4 136 1K_0402_1%
2 DM4
2 2 2 137 138 DDR_B_D38
DQS4 VSS31
DDR_B_D34 139 140 DDR_B_D39 2
VSS32 DQ38
2
DDR_B_D35 141 142 2
DQ34 DQ39
143 144 DDR_B_D44
yc
DDR_B_D40 DQ35 VSS33
@ 145 146 DDR_B_D45
DDR_B_D41 VSS34 DQ44
147 148
DQ40 DQ45
149 150 DDR_B_DQS#5
DDR_B0_DM5 DQ41 VSS35
151 VSS36 152 DDR_B_DQS5
DQS#5
153 DM5 154
DDR_B_D42 DQS5
+0.75VS 155 156 DDR_B_D46
DDR_B_D43 VSS37 VSS38
157 158 DDR_B_D47
m
DQ42 DQ46
159 DQ43 160
DDR_B_D48 DQ47 DDR_B_D52
161 VSS39 162
163 164
1U_0402_6.3V6K
C440
1U_0402_6.3V6K
C427
B DQ48 DQ52 B
1U_0402_6.3V6K
C428
165 166
1U_0402_6.3V6K
C439
1 1 DDR_B_DQS#6 DQ49 DQ53 DDR_B0_DM6

1 167 168
1 DDR_B_DQS6 VSS41 VSS42
169 DQS#6 170
DM6
2 2
2
// DDR_B_D50
DDR_B_D51
171
173
DQS6
VSS44
VSS43
DQ54
172
174
DDR_B_D54
DDR_B_D55
2 175 176
DQ50 DQ55 DDR_B_D60
177 DQ51 178
179 VSS46 180
+3VS DDR_B_D57 DQ60
181 182
DQ56 DQ61 DDR_B_DQS#7
183 184
DDR_B0_DM7 DQ57 VSS47 DDR_B_DQS7
185 186
p:
VSS48 DQS#7
Layout Note: 187 DM7 188
DDR_B_D58 DQS7 DDR_B_D62
189 190
10K_0402_5%
R344
Place near JDIMM2.203,204 DDR_B_D59 VSS49 VSS50 DDR_B_D63

191 192
2
DQ58 DQ62
193 194
DQ59 DQ63
195 VSS51 196 D_CK_SDATA
VSS52
DDR_B0_DM0 +3VS 197 SA0 198 D_CK_SCLK D_CK_SDATA 11,14
EVENT#
tt
DDR_B0_DM1 199 VDDSPD 200 D_CK_SCLK 11,14

SDA
DDR_B0_DM2 201 202
1
0_0402_5% 2 1 R349 +0.75VS SA1 SCL +0.75VS

DDR_B0_DM3 203 204
0_0402_5% 2 1 R322 DDR_B0_DM4
VTT1 VTT2
0_0402_5% 2 1 R321
1
10K_0402_5%
R345
0.1U_0402_16V4Z
C435
DDR_B0_DM5 205 206

2.2U_0603_6.3V6K
C436
0_0402_5% 2 1 R338 G1 G2
h
0_0402_5% 2 1 R323 DDR_B0_DM6 FOX_AS0A626-U4RN-7F

1 1
DDR_B0_DM7 CONN@
0_0402_5% 2 1 R347
0_0402_5% 2 1 R317
0_0402_5% 2 1 R348
2
2 2 <Address(SA1,SA0): 10>
DIMM_2 Reserve H:4mm
A A

DDRIII DIMMB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
5 4 3 2 Date: Friday, August 27,12010 Sheet 12 of 59
5 4 3 2 1
PCH_RTCX1
1 2 PCH_RTCX2
R568 10M_0402_5%
32.768KHZ_12.5PF_Q13MC14610002
1
4
Y3
OSC
OSC
18P_0402_50V8J
1 1
C686
NC
NC
C682 18P_0402_50V8J
2
D 2 2 D
+RTCVCC
R567 1 2 1M_0402_5% SM_INTRUDER#
R585 1 2 330K_0402_5% PCH_INTVRMEN
INTVRMEN
* HL烉烉Integrated
Integrated VRM enable
VRM disable
(INTVRMEN should always be pull high.)
RTCRST close RAM door
+3VS
/
R294 1 @ 2 1K_0402_5% PCH_SPKR U33A
1
HIGH= Enable ( No Reboot ) +RTCVCC J7 PCH_RTCX1 LPC_AD0
1 A20 C38 LPC_AD1 LPC_AD0 39
/x
LOW= Disable (Default) RTCX1 FWH0 / LAD0
* 0_0603_5% A38 LPC_AD2 LPC_AD1 39
LPC
C360 PCH_RTCX2 FWH1 / LAD1
@ C20 B37 LPC_AD3 LPC_AD2 39
1U_0603_10V6K RTCX2 FWH2 / LAD2
C37 LPC_AD3 39
2
+3VALW_PCH 2 PCH_RTCRST# FWH3 / LAD3
R556 1 2 D20
1K_0402_5% R248 20K_0402_5% RTCRST# LPC_FRAME# +3VS
HDA_SDOUT_PCH PCH_SRTCRST# D36 LPC_FRAME# 39
2 @ 1 1 2 FWH4 / LFRAME#
G22 SERIRQ
SRTCRST#
su
R557 R243 20K_0402_5% E36 R275 2 1 10K_0402_5%
1
SM_INTRUDER#
RTC
C 0_0402_5% 1 LDRQ0# C
K22 K36 PCH_SATALED#
39 HDA_SDO 2 1 J8 INTRUDER# LDRQ1# / GPIO23 R640 2 1 10K_0402_5%
C356 PCH_INTVRMEN SERIRQ
1U_0603_10V6K 0_0603_5% C17 V5 SERIRQ 39
INTVRMEN SERIRQ
HDA_SDO as Capella ME override (GPIO33) 2 @ PCH_GPIO19
R624 1 10K_0402_5%
2
2
ME debug mode,this signal has a weak internal PD
p.
AM3 SATA_PRX_DTX_N0 34
Low = Disabled (Default) HDA_BITCLK_PCH SATA0RXN
* N34
HDA_BCLK SATA0RXP
AM1 SATA_PRX_DTX_P0 34
HDD
SATA 6G
High = Enabled [Flash Descriptor Security Overide] HDA_SYNC_PCH AP7 SATA_PTX_DRX_N0 34
SRTCRST close RAM door SATA0TXN SATA_PTX_DRX_P0 34
L34 AP5
HDA_SYNC SATA0TXP
+3VALW_PCH PCH_SPKR
om
41 PCH_SPKR T10 AM10
SPKR SATA1RXN
HDA_SYNC_PCH HDA_RST_PCH# AM8
R539 2 1 1K_0402_5% SATA1RXP
K34 AP11
HDA_RST# SATA1TXN
AP10
This signal has a weak internal pull-down SATA1TXP
HDA_SDIN0
41 HDA_SDIN0 E34 AD7 SATA_PRX_DTX_N2 34
HDA_SDIN0 SATA2RXN SATA_PRX_DTX_P2 34
On Die PLL VR Select is supplied by AD5
G34
SATA2RXP
AH5 SATA_PTX_DRX_N2 34 ODD
1.5V when smapled high HDA_SDIN1 SATA2TXN
* SATA_PTX_DRX_P2 34
yc
AH4
1.8V when sampled low Prevent back drive issue. C34
SATA2TXP
IHDA
Needs to be pulled High for Huron River platfrom HDA_SDIN2
AB8
SATA3RXN
A34 AB10
HDA_SDIN3 SATA3RXP
+3VS AF3
SATA3TXN
HDA_SDOUT_PCH AF1
R544 SATA3TXP
m
A36
SATA
33_0402_5% HDA_SDO
2
G
HDA_BITCLK_PCH Q36 Y7
41 HDA_BITCLK_AUDIO 1 2 SATA4RXN
BSS138_NL_SOT23-3
HDA_SYNC_PCH Y5
SATA4RXP
R542 3 1 C36 AD3
HDA_DOCK_EN# / GPIO33 SATA4TXN
S
33_0402_5% HDA_SYNC_PCH_R AD1

41 HDA_SYNC_AUDIO SATA4TXP
1
R545
2
R674
// N32
HDA_DOCK_RST# / GPIO13
SATA5RXN
Y3
+3VS
33_0402_5% HDA_RST_PCH# 1 2 SATA5RXP

Y1
41 HDA_RST_AUDIO# 51_0402_5%
1
B @ PCH_JTAG_TCK AB3 B
1 R555 2 SATA5TXN
R540 2 1 J3 AB1 R259
33_0402_5% JTAG_TCK SATA5TXP
HDA_SDOUT_PCH 0_0402_5% PCH_JTAG_TMS +1.05VS_PCH 10K_0402_5%
41 HDA_SDOUT_AUDIO 1 2 R260 SGEN#
JTAG
H7 Y11
p:
PCH_JTAG_TDI JTAG_TMS SATAICOMPO SATA_COMP 37.4_0402_1%
1
2
K5 Y10 1 2
JTAG_TDI SATAICOMPI R258
PCH_JTAG_TDO
+3VALW_PCH +3VALW_PCH +3VALW_PCH +1.05VS_PCH 10K_0402_5%
H1
JTAG_TDO R241 @
AB12
SATA3RCOMPO
tt
49.9_0402_1%
2
SATA3_COMP
AB13 1 2
1
1
SATA3COMPI
1
R666 R637
R646 PCH_SPI_CLK_1
1 2
PCH_SPI_CLK RBIAS_SATA3 GPIO21
200_0402_5% 200_0402_5% 1 2
h
200_0402_5% R681 0_0402_5% T3 AH1 SGEN#

PCH_SPI_CS0#_1 PCH_SPI_CS0# SPI_CLK SATA3RBIAS R625 750_0402_1%
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI 1 2
Y14
2
R651 0_0402_5%
2
SPI_CS0# Switchable GPU 0

2
PCH_SATALED#
SPI
T1
SPI_CS1# PCH_SATALED# 40 *Non-Switchable 1
1
1
1
P3
PCH_SPI_MOSI_1 PCH_SPI_MOSI SATALED# SGEN#
R671 R636 R648
100_0402_1% 100_0402_1% 100_0402_1% 1 2PCH_SPI_MISO V4 V14
PCH_SPI_MISO_1 SPI_MOSI SATA0GP / GPIO21 PCH_GPIO19
R684 0_0402_5% +3VALW_PCH
U3 P1 R655 1 2
1 2 SPI_MISO SATA1GP / GPIO19
2
2
2
R652 0_0402_5% 4.7K_0402_5%

GPIO19 has internal Pull up
COUGARPOINT_FCBGA989~D
+RTCBATT +RTCBATT +3VS Boot BIOS Strap
+CHGRTC PCH_SPI_CS0#_1 U36
Boot BIOS GPIO51 GPIO19
SPI_WP1# PCH_SPI_CLK_1
2
+3VS R654 1 2 3.3K_0402_5% SPI_HOLD1# 1

CS# VCC
8 PCH_SPI_MOSI_1 LPC 0 0
1
R375 3 6 PCH_SPI_MISO_1
WP# SCLK
JBATT1 R667 1 2 3.3K_0402_5% 7 5 Reserved 0 1
+
A 1K_0402_5% HOLD# SI A
4 2
GND SO
+RTCBATT_R - 1 0
3 1
MX25L3205DM2I-12G SOP 8P
2
20mil SPI ROMSA000021A00

FOR ME (4MB) * SPI 1 1
D13
Footprint 200mil
DAN202UT106_SC70-3
+RTCVCC
20mil Security Classification Compal Secret Data Compal Electronics, Inc.
1
Issued Date 2010/08/11 2011/08/11 Title

-
1 Deciphered Date
C471 CONN@ SUYIN_060003HA002G202ZL
PCH (1/8) SATA,HDA,SPI, LPC, XDP
2
0.1U_0402_16V4Z AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2 Custom 0.1
20100416 add
5 4 3 2 1
U33B +3VALW_PCH
PCIE_PRX_DTX_N1 BG34 EC_LID_OUT# R240 1 2 10K_0402_5%

35 PCIE_PRX_DTX_N1 PERN1
35 PCIE_PRX_DTX_P1
PCIE_PRX_DTX_P1 BJ34
PERP1 SMBALERT# / GPIO11 E12 EC_LID_OUT# EC_LID_OUT# 39
PCIE LAN 35 PCIE_PTX_C_DRX_N1
C672 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 AV32 RST_GATE R608 2 1 1K_0402_5%
PETN1
35 PCIE_PTX_C_DRX_P1 C669 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1 AU32 PETP1 SMBCLK H14 PCH_SMBCLK PCH_SMBCLK 5,37
37 PCIE_PRX_DTX_N2
PCIE_PRX_DTX_N2 BE34
PERN2 SMBDATA C9 PCH_SMBDATA PCH_SMBDATA 5,37
PCH_SMBCLK R677 1 2 2.2K_0402_5%
PCIE_PRX_DTX_P2 BF34
37 PCIE_PRX_DTX_P2 PERP2
Mini Card 1 37 PCIE_PTX_C_DRX_N2
C675 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2 BB32 PCH_SMBDATA R662 1 2 2.2K_0402_5%
PCIE_PTX_DRX_P2 PETN2
37 PCIE_PTX_C_DRX_P2 C677 1 2 0.1U_0402_10V7K AY32
SMBUS
PETP2 RST_GATE
SML0ALERT# / GPIO60 A12 RST_GATE 6,11,12
PCIE_PRX_DTX_N3 BG36 PCH_GPIO74 R647 1 2 10K_0402_5%
37 PCIE_PRX_DTX_N3 PERN3
PCIE_PRX_DTX_P3 BJ36 C8
D 37 PCIE_PRX_DTX_P3 PERP3 SML0CLK D
Mini Card 2 C663 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N3 AV34
37 PCIE_PTX_C_DRX_N3 PCIE_PTX_DRX_P3 PETN3 PCH_SML1CLK
37 PCIE_PTX_C_DRX_P3 C665 1 2 0.1U_0402_10V7K AU34 G12 R642 1 2 2.2K_0402_5%
PETP3 SML0DATA
PCIE_PRX_DTX_N4 BF36 PCH_SML1DATA
38 PCIE_PRX_DTX_N4 PERN4 R643 1 2 2.2K_0402_5%
PCIE_PRX_DTX_P4 BE36
38 PCIE_PRX_DTX_P4 PERP4
USB3.0 Right C661 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 PCH_GPIO74
38 PCIE_PTX_C_DRX_N4 AY34 C13
C660 PCIE_PTX_DRX_P4 PETN4 SML1ALERT# / PCHHOT# / GPIO74 PCH_GPIO47
38 PCIE_PTX_C_DRX_P4 1 2 0.1U_0402_10V7K BB34 R280 1 2 10K_0402_5%
PETP4 PCH_SML1CLK
E14
PCI-E*
PCIE_PRX_DTX_N5 SML1CLK / GPIO58
45 PCIE_PRX_DTX_N5 BG37 PERN5
PCIE_PRX_DTX_P5 PCH_SML1DATA
45 PCIE_PRX_DTX_P5 BH37 M16
C813 2 0.1U_0402_10V7K PCIE_PTX_DRX_N5 PERP5 SML1DATA / GPIO75
USB3.0 Left 45 PCIE_PTX_C_DRX_N5 1
PCIE_PTX_DRX_P5
AY36 PETN5
45 PCIE_PTX_C_DRX_P5 C814 1 2 0.1U_0402_10V7K BB36 For DDR
PETP5 +3VS
+3VS BJ38 PERN6

BG38 R669
Controller
PERP6
PCH_GPIO18 AU36 M7 4.7K_0402_5%
PETN6 CL_CLK1
2
R638 2 1 10K_0402_5% AV36 1 2 +3VS
PETP6
Link
PCH_GPIO20 PCH_SMBDATA D_CK_SDATA
R273 2 1 10K_0402_5% BG40 T11 6 1 D_CK_SDATA 11,12
PERN7 CL_DATA1
+3VALW_PCH BJ40 PERP7
AY40
/
PETN7 Q40A
BB40 P10 DMN66D0LDW-7_SOT363-6 R670
R618 PCH_GPIO73 PETP7 CL_RST1#
2 1 10K_0402_5% 4.7K_0402_5%
5
BE38 1 2 +3VS
/x
PCH_GPIO25 PERN8
R630 2 1 10K_0402_5% BC38 PCH_SMBCLK D_CK_SCLK
PERP8 3 4
PCH_GPIO26 AW38 D_CK_SCLK 11,12
PETN8
R653 2 1 10K_0402_5% AY38 PETP8 Q40B
PCH_GPIO44 PCH_GPIO47 DMN66D0LDW-7_SOT363-6
R238 2 1 10K_0402_5% M10
PEG_A_CLKRQ# / GPIO47
PCH_GPIO45 Y40 CLKOUT_PCIE0N
su
R293 2 1 10K_0402_5% Y39
C
CLKOUT_PCIE0P C
PCH_GPIO46 PCH_GPIO73 AB37
CLOCKS
R295 2 1 10K_0402_5% CLKOUT_PEG_A_N
J2 CLKOUT_PEG_A_P AB38
PCIECLKRQ0# / GPIO73 Pull up at EC side.
+3VS
CLK_PCIE_MINI1# CLK_CPU_DMI# For VGA,EC
37 CLK_PCIE_MINI1# CLK_PCIE_MINI1 AB49 AV22CLK_CPU_DMI CLK_CPU_DMI# 5
CLKOUT_PCIE1N CLKOUT_DMI_N
p.
37 CLK_PCIE_MINI1 AB47 AU22 CLK_CPU_DMI 5
Mini Card 1 CLKOUT_PCIE1P CLKOUT_DMI_P
PCH_GPIO18
R650 2 1 0_0402_5%
2
37 MINI1_CLKREQ# M1 PCIECLKRQ1# / GPIO18
AM12 PCH_SML1DATA EC_SMB_DA2
CLKOUT_DP_N / CLKOUT_BCLK1_N EC_SMB_DA2 22,39
CLK_PCIE_USB30# CLKOUT_DP_P / CLKOUT_BCLK1_P AM13 6 1
om
38 CLK_PCIE_USB30# CLK_PCIE_USB30 AA48
USB3.0 38 CLK_PCIE_USB30 CLKOUT_PCIE2N
AA47 CLKOUT_PCIE2P CLK_BUF_CPU_DMI# Q38A
PCH_GPIO20 BF18 CLK_BUF_CPU_DMI R2331 10K_0402_5% DMN66D0LDW-7_SOT363-6
2 210K_0402_5%
5
38 USB30_CLKREQ# CLKIN_DMI_N R234
1
R289 2 1 0_0402_5% V10 BE18
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
PCH_SML1CLK EC_SMB_CK2
CLKIN_GND1# 3 4 EC_SMB_CK2 22,39
CLK_PCIE_LAN#
35 CLK_PCIE_LAN# CLK_PCIE_LAN Y37 BJ30 CLKIN_GND1 R5631 2 10K_0402_5%
PCIE LAN 35 CLK_PCIE_LAN Y36
CLKOUT_PCIE3N CLKIN_DMI2_N
BG30 R5611
Q38B
CLKOUT_PCIE3P CLKIN_DMI2_P 2 10K_0402_5% DMN66D0LDW-7_SOT363-6
yc
PCH_GPIO25
35 LAN_CLKREQ# CLK_BUF_DREF_96M#
R621 1 2 0_0402_5% A8
PCIECLKRQ3# / GPIO25
G24 CLK_BUF_DREF_96M R220 2 10K_0402_5%
CLKIN_DOT_96N
E24 R2211 1 2 10K_0402_5% Pull down 10K ohm
37 CLK_PCIE_MINI2# CLKIN_DOT_96P for using internal Clock
Y43
Mini Card 2 37 CLK_PCIE_MINI2 Y45
CLKOUT_PCIE4N
CLK_BUF_PCIE_SATA#
CLKOUT_PCIE4P
m
PCH_GPIO26 AK7 CLK_BUF_PCIE_SATA R264 10K_0402_5%
37 MINI2_CLKREQ# R664 2 1 0_0402_5% CLKIN_SATA_N / CKSSCD_N 1 1
R265 2 210K_0402_5%
L12 CLKIN_SATA_P / CKSSCD_P AK5
PCIECLKRQ4# / GPIO26
CLK_PCIE_USB30_L# CLK_BUF_ICH_14M
45 CLK_PCIE_USB30_L# CLK_PCIE_USB30_L V45 K45
USB3.0 Left R1751 2 10K_0402_5%
45 CLK_PCIE_USB30_L
PCH_GPIO44
V46
//
CLKOUT_PCIE5N
CLKOUT_PCIE5P
REFCLK14IN
CLK_PCI_LPBACK
45 USB30_CLKREQ#_L CLK_PCI_LPBACK 17
B R772 2 1 0_0402_5% L14 CLKIN_PCILOOPBACK H45
PCIECLKRQ5# / GPIO44 B
CLK_PEG_VGA# XTAL25_IN
22 CLK_PEG_VGA# CLK_PEG_VGA XTAL25_OUT
AB42 XTAL25_IN V47
22 CLK_PEG_VGA CLKOUT_PEG_B_N
p:
AB40 XTAL25_OUT V49

PEG_CLKREQ#_R CLKOUT_PEG_B_P +1.05VS_VTT
E6 XCLK_RCOMP R526
PEG_B_CLKRQ# / GPIO56
90.9_0402_1%
Y47 1 2 XTAL25_IN
XCLK_RCOMP
tt
V40 CLKOUT_PCIE6N
PCH_GPIO45 V42 CLKOUT_PCIE6P XTAL25_OUT
T13 1 2
PCIECLKRQ6# / GPIO45 CLK_FLEX0 R527 1M_0402_5%
h
@ PAD
V38 K43 T9 Y2
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 CLK_FLEX1
FLEX CLOCKS
PCH_GPIO46 V37 CLKOUT_PCIE7P @ 2 1

F47 T8 PAD
CLKOUTFLEX1 / GPIO65 CLK_FLEX2
K12 PCIECLKRQ7# / GPIO46 25MHZ_20PF_7A25000012
CLK_CPU_ITP# H47
5 CLK_CPU_ITP# CLK_CPU_ITP CLKOUTFLEX2 / GPIO66 DGPU_PRSNT# @ PAD 1
AK14 T29 1
5 CLK_CPU_ITP CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK13 K49 +3VS C630
CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67 C631
18P_0402_50V8J 18P_0402_50V8J
2 2
1
<BOM Structure> R159
10K_0402_5%
+3VALW_PCH DGPU_PWR_EN 17,44 UMAO@
DGPU_PRSNT#
2
1
R663
GPIO67
2
A
R632 DGPU_PRSNT# A
DIS@ R160 CLK_PCI_LPBACK R530 C642
10K_0402_5% 10K_0402_5% 10K_0402_5% 33_0402_5% 22P_0402_50V8J
DIS,OPTIMUS 0 DIS@ 2 1 1 2
2
2 2
@
UMA 1 Reserve for EMI please close to@ UH4
1
2N7002E-T1-GE3_SOT23-3
G
PEG_CLKREQ#_R Pull high @ VGA side

1 3 R631 PEG_CLKREQ# 22
D
1 2
1
Q39 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
1
DIS@ R644 DIS@

for safe R668 @ Issued Date 2010/08/11 Deciphered Date 2011/08/11 Title
@
2.2K_0402_5%
2.2K_0402_5%
PCH (2/8) PCIE, SMBUS, CLK
2

2
Custom 0.1
5 4 3 2 1
U33C
+3VALW_PCH DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

4 DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 4
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
R607 2 1 10K_0402_5% SUS_PWR_DN_ACK_R BC12 FDI_CTX_PRX_N4
FDI_RXN4 FDI_CTX_PRX_N4 4
DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5
4 DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 4
R218 2 1 200K_0402_5% PCH_ACIN DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
R247 2 1 10K_0402_5% PCH_GPIO72 DMI_CTX_PRX_P3 BJ20
4 DMI_CTX_PRX_P3 DMI3RXP
BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 4
R610 2 1 10K_0402_5% RI# DMI_CRX_PTX_N0 AW 24 BB14 FDI_CTX_PRX_P1
+3VS 4 DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 4
DMI_CRX_PTX_N1 AW 20 BF14 FDI_CTX_PRX_P2
D 4 DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 4 D
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3
4 DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 4
R597 2 1 200_0402_5% PM_DRAM_PWRGD DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4
FDI_CTX_PRX_P4 4
DMI
FDI
4 DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P5
FDI_RXP5 BG12 FDI_CTX_PRX_P5 4
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6
4 DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 4
R559 2 1 10K_0402_5% PCH_RSMRST# DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7
4 DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 4 +RTCVCC
DMI_CRX_PTX_P2 AY18
4 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI2TXP
4 DMI_CRX_PTX_P3 AU18 DMI3TXP FDI_INT
FDI_INT AW 16 FDI_INT 4 DSWODVREN R577
+1.05VS_PCH
2 1 330K_0402_5%
FDI_FSYNC0
BJ24 DMI_ZCOMP AV12 FDI_FSYNC0 4
FDI_FSYNC0
R581 2 1 330K_0402_5%
DMI_IRCOMP FDI_FSYNC1 @
1 2 BG25 BC10
烉
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 4
R223 49.9_0402_1% DSWODVREN - On Die DSW VR Enable
烉
RBIAS_CPY FDI_LSYNC0 H Enable
R578
1 2
750_0402_1%
BH21 DMI2RBIAS FDI_LSYNC0 AV14
FDI_LSYNC1
FDI_LSYNC0 4 * L Disable
4mil width and place FDI_LSYNC1 BB10 FDI_LSYNC1 4
within 500mil of the PCH
DSWODVREN
DSW VRMEN A18
not support Deep S4,S5 mux
System Power Management
/
with SUS_PWR_DN_ACK not support Deep S4,S5 DPWROK mux with PWROK
SUS_PWR_DN_ACK_R SUSACK#_R PCH_RSMRST#_R check list1.0 P.42
1 2 C12 E22
R599 0_0402_5% SUSACK# DPW ROK R615
/x
0_0402_5%
XDP_DBRESET#_R WAKE#
5 XDP_DBRESET# 1 2 K3 B9 1 2 PCH_PCIE_WAKE# 35,37,38,45
R678 0_0402_5% SYS_RESET# W AKE#
SYS_PWROK PCH_GPIO32 +3VALW_PCH

C P12 SYS_PW ROK N3 C
not support AMT APWROK can mux CLKRUN# / GPIO32
WAKE# R613 1 2 10K_0402_5%
with PWROK (check list1.0 P.40)
su
PCH_PWROK 1 2 PCH_PWROK_R SUS_STAT# T22 PAD
L22 PW ROK SUS_STAT# / GPIO61 G8 PCH_GPIO29
R635 0_0402_5% R235 1 2 10K_0402_5%
@
SUSCLK +3VS
L10 SUSCLK / GPIO62 N14 SUSCLK 39
APW ROK
PCH_GPIO32 R622
T23 PAD 1 2 10K_0402_5%
p.
PM_DRAM_PWRGD PM_SLP_S5#
5 PM_DRAM_PWRGD B13 D10 PM_SLP_S5# 39
DRAMPW ROK SLP_S5# / GPIO63 @
T21 PAD
PCH_RSMRST#_R PM_SLP_S4#
39 PCH_RSMRST# 1 2 C21 H4 PM_SLP_S4# 39
R560 0_0402_5% RSMRST# SLP_S4# @
om
T20 PAD
SUS_PWR_DN_ACK_R PM_SLP_S3# Can be left NC
39 SUS_PWR_DN_ACK 1 2 K16 F4 PM_SLP_S3# 39
R598 0_0402_5% SUSW ARN# / SUS_PW R_DN_ACK / GPIO30 SLP_S3# @ when IAMT is not
PBTN_OUT#_R support on the
5,39 PBTN_OUT# 1 2 E20 G10 platfrom
R673 0_0402_5% PW RBTN# SLP_A#
PCH_ACIN not support
39,43,44,47 ACIN 1 2
yc
H20 SLP_SUS# G16
D9 CH751H-40PT_SOD323-2 ACPRESENT / GPIO31 Deep S4,S5 can NC
T16 PAD PCH EDS1.2 P.74
PCH_GPIO72 H_PM_SYNC
E10 AP14 H_PM_SYNC 5
BATLOW # / GPIO72 PMSYNCH @
RI# PCH_GPIO29
m
A10 RI# K14
SLP_LAN# / GPIO29
Ring Indicator CRB1.0 PH 10K +3VALW
B COUGARPOINT_FCBGA989~D B
//
tell PCH all power ok +3VS
p:
but cpu core

ALL power OK
5
U35
39 PCH_PWROK 2 B
P
SYS_PWROK
4 SYS_PWROK 5
tt
Y
39,54 VGATE 1 A
G
MC74VHC1G08DFT2G_SC70-5
1
R629
R645
h
10K_0402_5%
10K_0402_5%
2
2
A A
Security Classification Compal Secret Data

PCH (3/8) DMI,FDI,PM,
Custom 0.1

5 4 3 2 1
Pull high at LVDS conn side.

U33D
ENBKL R532 2 1 0_0402_5% IGPU_BKLT_EN IGPU_BKLT_EN J47 AP43
22,39 ENBKL L_BKLTEN SDVO_TVCLKINN
31 PCH_ENVDD M45 L_VDD_EN AP45
SDVO_TVCLKINP
UMA@
31 DPST_PWM P45 L_BKLTCTL AM42
SDVO_STALLN
AM40
SDVO_STALLP
31 PCH_LCD_CLK T40 L_DDC_CLK
31 PCH_LCD_DATA K47 L_DDC_DATA AP39
SDVO_INTN
1 1
CTRL_CLK SDVO_INTP
AP40 SDVO_CTRLDATA strap pull high
0.01U_0402_16V7K T45
C193 C191 CTRL_DATA L_CTRL_CLK at level shift page
P39
0.01U_0402_16V7K 2.37K_0402_1% L_CTRL_DATA
D 2 @ 2 @ D
R189 2 1 LVDS_IBG AF37 LVD_IBG P38 SDVO_SCLK SDVO_SCLK 33
SDVO_CTRLCLK
UMA@ AF36
LVD_VBG SDVO_CTRLDATA M39 SDVO_SDATA SDVO_SDATA 33
For RF request 0_0402_5% LVD_VREF AE48
R177 LVD_VREFH
2 1 AE47 AT49
UMA@ LVD_VREFL DDPB_AUXN
AT47
+3VS DDPB_AUXP PCH_DPB_HPD
DDPB_HPD AT40 PCH_DPB_HPD 33
PCH_TXCLK- AK39
31 PCH_TXCLK-
LVDS
CTRL_CLK PCH_TXCLK+ LVDSA_CLK# PCH_DPB_N0
R174 1 UMA@ 2 2.2K_0402_5% 31 PCH_TXCLK+ AK40 AV42 PCH_DPB_N0 33
LVDSA_CLK DDPB_0N PCH_DPB_P0
CTRL_DATA PCH_TXOUT0- DDPB_0P AV40
PCH_DPB_N1
PCH_DPB_P0 33 HDMI D2
R158 1 UMA@ 2 2.2K_0402_5% 31 PCH_TXOUT0- AN48 AV45 PCH_DPB_N1 33
PCH_TXOUT1- LVDSA_DATA#0 DDPB_1N PCH_DPB_P1
AM47 AV46 PCH_DPB_P1 33 HDMI D1
Digital Display Interface

31 PCH_TXOUT1- PCH_TXOUT2- LVDSA_DATA#1 DDPB_1P PCH_DPB_N2
31 PCH_TXOUT2- AK47 AU48 PCH_DPB_N2 33
R156 PCH_LCD_CLK LVDSA_DATA#2 DDPB_2N PCH_DPB_P2
1 UMA@ 2 2.2K_0402_5% AJ48 AU47 PCH_DPB_P2 33 HDMI D0
LVDSA_DATA#3 DDPB_2P PCH_DPB_N3
AV47 PCH_DPB_N3 33
R157 PCH_LCD_DATA PCH_TXOUT0+ DDPB_3N PCH_DPB_P3
1 UMA@ 2 2.2K_0402_5% 31 PCH_TXOUT0+ AN47 AV49 PCH_DPB_P3 33 HDMI CLK
PCH_TXOUT1+ LVDSA_DATA0 DDPB_3P
31 PCH_TXOUT1+ AM49 LVDSA_DATA1
PCH_TXOUT2+ AK49
31 PCH_TXOUT2+ LVDSA_DATA2
AJ47 LVDSA_DATA3 P46
DDPC_CTRLCLK
P42
DDPC_CTRLDATA
/
AF40
LVDSB_CLK#
AF39 AP47
LVDSB_CLK DDPC_AUXN
DDPC_AUXP AP49
/x
AH45 AT38
LVDSB_DATA#0 DDPC_HPD
AH47
+3VS LVDSB_DATA#1
AF49 AY47
LVDSB_DATA#2 DDPC_0N
AF45 LVDSB_DATA#3 AY49
R521 1 UMA@ 2 2.2K_0402_5% PCH_CRT_CLK DDPC_0P
DDPC_1N AY43
AH43 LVDSB_DATA0 AY45
R522 1 UMA@ 2 2.2K_0402_5% PCH_CRT_DATA DDPC_1P
su
AH49 DDPC_2N BA47
LVDSB_DATA1
C AF47 BA48 C
LVDSB_DATA2 DDPC_2P
AF43 DDPC_3N BB47
LVDSB_DATA3
PCH_CRT_B DDPC_3P BB49
R534 1 UMA@ 2 150_0402_1%
PCH_CRT_G PCH_CRT_B
R533 1 UMA@ 2 150_0402_1% N48 M43
p.
32 PCH_CRT_B PCH_CRT_G CRT_BLUE DDPD_CTRLCLK
PCH_CRT_R 32 PCH_CRT_G PCH_CRT_R P49 CRT_GREEN M36
R535 1 UMA@ 2 150_0402_1% DDPD_CTRLDATA
32 PCH_CRT_R T49
CRT_RED
AT45
CRT
PCH_CRT_CLK DDPD_AUXN
T39
om
32 PCH_CRT_CLK PCH_CRT_DATA CRT_DDC_CLK DDPD_AUXP AT43
32 PCH_CRT_DATA M40 BH41
CRT_DDC_DATA DDPD_HPD
BB43
DDPD_0N
32 PCH_CRT_HSYNC M47 BB45
CRT_HSYNC DDPD_0P
32 PCH_CRT_VSYNC M49 BF44
CRT_VSYNC DDPD_1N
BE44
DDPD_1P
CRT_IREF BF42
DDPD_2N
T43 BE42
yc
DAC_IREF DDPD_2P
T42 BJ42
CRT_IRTN DDPD_3N
BG42
1
DDPD_3P
R178
1K_0402_0.5%
m
2
//
B B
p:
tt
h
A A

PCH (4/9) LVDS,CRT,DP,HDMI
Custom 0.1
5 4 3 2
Date: Friday, August 27, 2010 1
Sheet 16 of 59
5 4 3 2 1
U33E
+3VS AY7
NV_CE#0
NV_CE#1 AV7
BG26 NV_CE#2 AU3
R173 10K_0402_5% PCI_PIRQA# TP1
1 2 BJ26 NV_CE#3 BG4
R180 10K_0402_5% PCI_PIRQD# TP2
1 2 BH25
PCI_PIRQC# TP3
R181 1 2 10K_0402_5% BJ16 AT10
PCI_PIRQB# TP4 NV_DQS0
R183 1 2 10K_0402_5% BG16 NV_DQS1 BC8
TP5
AH38
TP6
AH37 NV_DQ0 / NV_IO0 AU2
TP7
AK43 NV_DQ1 / NV_IO1 AT4
D TP8 D
AK45 AT3
WL_OFF# TP9 NV_DQ2 / NV_IO2
R152 1 2 10K_0402_5% C18 NV_DQ3 / NV_IO3 AT1
R153 1 2 10K_0402_5% WWAN_OFF# TP10
N30 NV_DQ4 / NV_IO4 AY3
R161 1 2 10K_0402_5% PCH_GPIO5 TP11
H3 AT5
PCH_GPIO52 TP12 NV_DQ5 / NV_IO5
R162 1 2 10K_0402_5% AH12 AV3
NVRAM
TP13 NV_DQ6 / NV_IO6
AM4 AV1
TP14 NV_DQ7 / NV_IO7
AM5 NV_DQ8 / NV_IO8 BB1
TP15
Y13 NV_DQ9 / NV_IO9 BA3
TP16
K24 BB5
PCH_GPIO2 TP17 NV_DQ10 / NV_IO10
R166 1 2 10K_0402_5% L24 NV_DQ11 / NV_IO11
BB3
DGPU_PWR_EN TP18
R169 1 2 10K_0402_5% AB46 BB7
R170 10K_0402_5% PCH_GPIO4 TP19 NV_DQ12 / NV_IO12
1 2 AB45 BE8
RSVD
ODD_DA# TP20 NV_DQ13 / NV_IO13
R172 1 2 10K_0402_5% BD4
NV_DQ14 / NV_IO14
BF6
NV_DQ15 / NV_IO15
B21 AV5
TP21 NV_ALE DF_TVS
M20 NV_CLE AY1
TP22 DMI Termination Voltage
AY16
PCH_GPIO53 TP23 AV10
R165 1 2 8.2K_0402_5% BG46 NV_RCOMP
TP24 Set to Vcc when HIGH
AT8 DF_TVS
/
NV_RB# Set to Vss when LOW
BE28 AY5
TP25 NV_RE#_WRB0
BC30 BA2
NV_RE#_WRB1
/x
DGPU_HOLD_RST# TP26 DG 1.2 CRB1.0 PH 2.2K series 1K
R188 1 2 8.2K_0402_5% BE32 TP27
BJ32 AT12
TP28 NV_WE#_CK0
BC28 NV_WE#_CK1 BF3
TP29
BE30 +1.8VS
TP30
BF32 USB20_N0
TP31 C24
BG32 USBP0N USB20_P0 USB20_N0 38
TP32 USB/B (Right side)
su
AV26 A24 USB20_P0 38
1
TP33 USBP0P USB20_N1
C BB26 USBP1N C25 USB20_P1 USB20_N1 38 C
TP34 B25 USB/B (Right side) R633
AU28 USBP1P USB20_N2 USB20_P1 38
TP35 C26 2.2K_0402_5%
AY30 USBP2N USB20_P2 USB20_N2 45
TP36 A26 USB Conn. Colay USB3.0
AU26 USBP2P USB20_N3 USB20_P2 45
TP37 K28
AY26 USB20_N3 38
2
TP38 USBP3N USB20_P3 DF_TVS
USB/B (Right side) ,colay USB3.0 H_SNB_IVB# 5
p.
AV28 H28 USB20_P3 38 2 1
TP39 USBP3P
AW30 E28 R626 1K_0402_5%
TP40 USBP4N
D28
USBP4P CLOSE TO THE BRANCHING POINT
C28
USBP5N
A28
USBP5P
om
C29
USBP6N
PCI_PIRQA# B29
USBP6P
PCI_PIRQB# K40
PIRQA# USBP7N
N28 Some PCH config not support USB port 6 & 7.
K38 M28
PCI
PCI_PIRQC# PIRQB# USBP7P USB20_N8
PCI_PIRQD# H38 L30 USB20_P8 USB20_N8 37
PIRQC# USBP8N
G38 PIRQD# USBP8P K30 USB20_N9 USB20_P8 37 Mini Card 1 (WLAN)
DGPU_HOLD_RST# G30 USB20_P9 USB20_N9 37 +3VALW_PCH
GPIO51 Internal pull high USBP9N 3G/B (WWAN)
C46 E30 USB20_P9 37
USB
PCH_GPIO52 REQ1# / GPIO50 USBP9P USB20_N10
C44 C30 USB20_N10 31
yc
DGPU_PWR_EN REQ2# / GPIO52 USBP10N USB20_P10
14,44 DGPU_PWR_EN E40 REQ3# / GPIO54 USBP10P A30 USB20_N11 USB20_P10 31 CMOS Camera (LVDS) USB_OC0#
Boot BIOS Strap bit1 BBS1 L32 USB20_N11 37 USB_OC2# R596 1
WWAN_OFF# USBP11N USB20_P11 R588 1 2 10K_0402_5%
2 10K_0402_5%
37 WWAN_OFF# PCH_GPIO53 D47 GNT1# / GPIO51 USBP11P K32 USB20_N12 USB20_P11 37 Mini2 Card 2 (Reserved) USB_OC7#
Boot BIOS E42 G32 USB20_N12 37 USB_OC5# R595
WL_OFF# GNT2# / GPIO53 USBP12N USB20_P12 1 2 10K_0402_5%
Destination 37 WL_OFF# F46 GNT3# / GPIO55 USBP12P
E32 USB20_N13 USB20_P12 37 SIM Card (3G/B) R590 1 2 10K_0402_5%
Bit11 Bit10
m
C32 USB20_P13 USB20_N13 38
USBP13N USB20_P13 38 Bluetooth
PCH_GPIO2 A32
0 1 Reserved USBP13P
ODD_DA# G42 PIRQE# / GPIO2
GNT1#/ 34 ODD_DA# PCH_GPIO4 G40 USBRBIAS Within 500 mils
1 0 PCI PIRQF# / GPIO3
GPIO51 PCH_GPIO5 C42 PIRQG# / GPIO4 USBRBIAS#
C33
1 2
1 1 SPI
// D44 PIRQH# / GPIO5 R558 22.6_0402_1% USB_OC1#
USB_OC4# R773 1 2 10K_0402_5%
B33 USB_OC3# R612 1 1
B 0 0 LPC PAD T18 @ USBRBIAS R592 2 10K_0402_5%
2 10K_0402_5% B
K10 USB_OC6#
PME# R616 1 2 10K_0402_5%
PLT_RST# USB_OC0#
5,35,38,39,45 PLT_RST# C6 A14 USB_OC1#
PLTRST# OC0# / GPIO59
K20 USB_OC2#
p:
CLK_PCI0
OC1# / GPIO40 USB_OC2# 45
CLK_PCI_LPBACK B17 USB_OC3#
14 CLK_PCI_LPBACK CLK_PCI1 OC2# / GPIO41
CLK_PCI_LPC H49 C16 USB_OC4#
39 CLK_PCI_LPC R531 2 1 22_0402_5%CLK_PCI2 CLKOUT_PCI0 OC3# / GPIO42
H43 L16 USB_OC5#
R529 1PAD 2 22_0402_5%
T30 @
CLK_PCI3 CLKOUT_PCI1 OC4# / GPIO43
J48 A16 USB_OC6#
CLK_PCI4 CLKOUT_PCI2 OC5# / GPIO9 USB_OC7#
PAD T10 @ K42 D14
tt
CLKOUT_PCI3 OC6# / GPIO10

PAD T12 @ H40 OC7# / GPIO14 C14
1 1 CLKOUT_PCI4
C633 C632 COUGARPOINT_FCBGA989~D

0.01U_0402_16V7K 0.01U_0402_16V7K
h
@ 2 2 @ R282
0_0402_5%
For RF request 2 1
@
+3VS +3VS
R296
PLT_RST#
5
U14 100_0402_5%
5
PLT_RST# U15
2 1 2
P
DGPU_HOLD_RST# B PLTRST_VGA# 22
4 DIS@ 1
P
Y IN1 PLT_RST_BUF# 37
R187 2 1 1 A O 4
G
0_0402_5% DIS@ 2 IN2
1
NC7SZ08P5X_NL_SC70-5 R281
3
DIS@ 100K_0402_5% SN74AHC1G08DCKR_SC70-5 R297

3
DIS@ 100K_0402_5%
2
2
A A

PCH (5/9) PCI, USB, NVRAM
Custom 0.1
5 4 3 2 1
HDA_SYNC PH(PLL =+1.5VS)

GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
* H
L
烉
烉On-Die voltage regulator enable
On-Die PLL Voltage Regulator disable
R272 1 2 1K_0402_5% PCH_GPIO28
@ +3VS
ODD_EN# R771 1 2 10K_0402_5%

D D
+3VALW_PCH R768 1 2 4.7K_0402_5%
EC_KBRST# R279 1 2 10K_0402_5%
U33F
PCH_GPIO0 ODD_EN#
T7 C40 ODD_EN# 34
BMBUSY# / GPIO0 TACH4 / GPIO68
PCH_GPIO1 PCH_GPIO69
A42 TACH1 / GPIO1 B41
TACH5 / GPIO69
DGPU_HPD_INT# PCH_GPIO70 +3VS
33 DGPU_HPD_INT# H36 C41
TACH2 / GPIO6 TACH6 / GPIO70
EC_SCI# PCH_GPIO71
39 EC_SCI# E38 A40
TACH3 / GPIO7 TACH7 / GPIO71
2
Deep S4,S5 wake event signal
EC_SMI#
RTC alarm,Power BTN,GPIO27 39 EC_SMI# C10 GPIO8
R278
PCH_GPIO12 10K_0402_5%
PCH_GPIO27 (Have internal Pull-High) C4
LAN_PHY_PWR_CTRL / GPIO12
Deep S4,S5 wake event signal SMIB
1
38,45 SMIB G2 P4 GATEA20 39
No use PD to GND Check list1.0 P.70 GPIO15 A20GATE
/
PCH_PECI_R PECI CPU-EC
AU16 1 2 H_PECI 5,39
CPU/MISC
R661 PCH_GPIO27 PCH_GPIO16 PECI 0_0402_5% @ R239
1 2 10K_0402_5% U2 EC_KBRST#
SATA4GP / GPIO16 CTRL+ALT+DEL
P5 EC_KBRST# 39
/x
RCIN#
GPIO
R193 DGPU_PWROK non CPU power ok
53 VGA_PWROK 1 2 0_0402_5% D40 AY11 H_CPUPWRGD 5
TACH0 / GPIO17 PROCPWRGD
PCH_GPIO22 PCH_THRMTRIP#_R 1 2 H_THRMTRIP# 130 degree
T5 AY10 H_THRMTRIP# 5
SCLOCK / GPIO22 THRMTRIP# R627 390_0402_5% shut sown
PCH_GPIO24
E8 T14
GPIO24 / MEM_LED INIT3_3V#
su
PCH_GPIO27 INIT3_3V Checklist1.0 P.59
C +3VS E16 C
GPIO27
PCH_GPIO28 This signal has weak internal
P8
GPIO28 PU, can't pull low,leave NC
R623 OPTIMUS_EN# BT_ON# AH8
2 1 1K_0402_5% 37,38 BT_ON# K1
NC_1
NOPT@ STP_PCI# / GPIO34
p.
AK11
NC_2
K4
R639 2 1 100K_0402_5% GPIO35
ODD_DETECT# AH10 TS_VSS1~4
OPT@ 34 ODD_DETECT# NC_3
V8
SATA2GP / GPIO36 PD to GND
PCH_GPIO37 AK10
NC_4
om
M5
SATA3GP / GPIO37
OPTIMUS_EN# P37
NC_5
N2
GPIO38 SLOAD / GPIO38
PCH_GPIO39
OPTIMUS_EN# M3 SDATAOUT0 / GPIO39
PCH_GPIO48
V13 SDATAOUT1 / GPIO48 BG2 T58 PAD
* OPTIMUS 0 PCH_GPIO49 VSS_NCTF_15
@
T39 PAD
yc
V3 BG48
Non-OPTIMUS 1 PCH_GPIO57
SATA5GP / GPIO49 VSS_NCTF_16 @
D6 BH3 T59 PAD
GPIO57 VSS_NCTF_17 @ +3VS +3VS +3VS
BH47 T40 PAD
VSS_NCTF_18
@
PAD T61 @ T60 PAD
1
A4
1
VSS_NCTF_1 VSS_NCTF_19 BJ4
1
+3VS @
R554 R550
PAD T46 @ A44 BJ44 T45 PAD R548
VSS_NCTF_2 VSS_NCTF_20 10K_0402_5% 10K_0402_5%
PCH_GPIO37 @ 10K_0402_5%
T43 PAD @ @
R277 PAD T44 @ A45 @
1 2 100K_0402_5% VSS_NCTF_3 VSS_NCTF_21 BJ45 @
//
2
2
2 10K_0402_5% PCH_GPIO0 PCH_GPIO69 PCH_GPIO70 PCH_GPIO71
NCTF
R276 1 PAD T41 @
2
A46 VSS_NCTF_4 BJ46 T42 PAD
VSS_NCTF_22
2
PCH_GPIO1 @ T50 PAD
2
R546 1 2 10K_0402_5% PAD T52 @
2
B B
A5 VSS_NCTF_5 BJ5 @ R549
DGPU_HPD_INT# VSS_NCTF_23 R551
R191 1 2 10K_0402_5% PAD T51 @ R553 10K_0402_5%
A6 T49 PAD 10K_0402_5%
VSS_NCTF_6 BJ6 10K_0402_5%
PCH_GPIO16 VSS_NCTF_24 @
p:
T65 PAD
1
R641 1 2 10K_0402_5% PAD T64 @ B3 C2
1
VSS_NCTF_7 VSS_NCTF_25 @
1
DGPU_PWROK
R194 1 2 10K_0402_5% B47 T38 PAD
PAD T37 @ VSS_NCTF_8 VSS_NCTF_26 C48 @
PCH_GPIO22
R290 1 2 10K_0402_5% T63 PAD
PAD T55 @ BD1 D1
tt
VSS_NCTF_9 VSS_NCTF_27 @ Project ID GPIO69 GPIO70 GPIO71

PAD T34 @ T32 PAD
BD49 D49
R649
PCH_GPIO39 VSS_NCTF_10 VSS_NCTF_28 @ * P5WE0 0 0 0
1 2 10K_0402_5% PAD T56 @ T54 PAD
BE1 E1
VSS_NCTF_11 P7YE0 0 0 0
h
VSS_NCTF_29 @
T33 PAD
PAD T35 @ BE49 E49
ODD_DETECT# VSS_NCTF_12 VSS_NCTF_30 @ x 0 1 0
R291 1 2 100K_0402_5% PAD T57 @
BF1 F1 T53 PAD x 0 1 1
BT_ON# VSS_NCTF_13 VSS_NCTF_31
R619 PAD T36 @ @
1 2 10K_0402_5% T31 PAD
BF49 F49 x 1 0 0
PCH_GPIO48 VSS_NCTF_14 VSS_NCTF_32 @
R292 1 2 10K_0402_5%
PCH_GPIO49 COUGARPOINT_FCBGA989~D x 0 0 1
R274 1 2 10K_0402_5%
<BOM Structure>
GPIO24 Unmultiplexed x 0 1 0
+3VALW_PCH
NOTE: GPIO24 configuration x 0 1 1
register bits are not cleared by
CF9h reset event. x 1 0 0
PCH_GPIO24
R262 1 2 10K_0402_5% CRB1.0 PH10K to +3VALW
x 1 0 1
PCH_GPIO12
R620 1 2 10K_0402_5% x 1 1 0
A A
SMIB
R672 1 2 1K_0402_5% x 1 1 1
PCH_GPIO57
R263 1 2 10K_0402_5%

PCH (6/9) GPIO, CPU, MISC
Custom 0.1
5 4 3 2
Sheet 18 of 59
5 4 3 2 1
+VCCADAC should be powered up during S0

system state.Note that Thermal Sensor +3VS
shares the same power supply rail with DAC L31
MBK1608221YZF_2P
+VCCADAC 2 1
+1.05VS_VTT U33G POWER 1 1 1
0.01U_0402_16V7K
C640
0.1U_0402_10V7K
C644
C629
1300mA 1 1 1
0.1U_0402_10V7K
C777
J3 R523 C276 C615
2 1 +1.05VS_PCH AA23 U48 0_0402_5% 22U_0805_6.3V6M 22U_0805_6.3V6M @ 22U_0805_6.3V6M
VCCCORE[1] VCCADAC 2 2 2
AC23 @
VCCCORE[2] 1mA 2 2 2
10U_0805_6.3V6M
C334
1U_0402_6.3V6K
C320
1U_0402_6.3V6K
C346
CRT
1U_0402_6.3V6K
C319
AD21
PAD-OPEN 4x4m 1 1 1 1
2
VCCCORE[3]
AD23 U47
VCCCORE[4] VSSADAC
VCC CORE
@ AF21
VCCCORE[5]
AF23
D 2 2 2 2 VCCCORE[6] +3VS D
AG21 R149
VCCCORE[7]
AG23 0.022_0805_1%
<BOM Structure>
VCCCORE[8]
AG24 VCCCORE[9] AK36 +VCCA_LVDS<BOM Structure> 1 2
VCCALVDS
UMA@
AG26 1mA
1
VCCCORE[10]
AG27 AK37
VCCCORE[11] VSSALVDS R176
AG29
VCCCORE[12] 0_0402_5%
AJ23
LVDS
VCCCORE[13] DISO@
AJ26 VCCCORE[14] AM37
VCCTX_LVDS[1] +1.8VS
AJ27
2
VCCCORE[15]
AJ29 AM38 L16 UMA@
VCCCORE[16] VCCTX_LVDS[2]
AJ31 0.1UH_MLF1608DR10KT_10%_1608
+1.05VS_PCH VCCCORE[17] +VCCTX_LVDS
60mA VCCTX_LVDS[3]
AP36
1
2 1
0.1uH inductor, 200mA
1 1
1
AP37 C300
VCCTX_LVDS[4] 22U_0805_6.3V6M
AN19 C305 C310 R210
VCCIO[28] UMA@
0.01U_0402_16V7K 0.01U_0402_16V7K
2 UMA@ 2 UMA@ 2
DISO@
+VCCAPLLEXP
PAD T48 @ BJ22 VCCAPLLEXP 266mA 0_0402_5%
2
+3VS
PCH Power Rail Table
烉On-Die PLL voltage regulator enable
On-Die PLL Voltage Regulator V33
HVCMOS
H VCC3_3[6] I/O Buffer Voltage S0 Iccmax
AN16
/
VCCIO[15] Voltage Rail Voltage
1 Current(A)
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 AN17
VCCIO[16]
,VCCAPLLSATA V34 C313
VCC3_3[7]
/x
2925mA 0.1U_0402_10V7K
V_PROC_IO 1.05 0.001 Processor I/F
AN21 2
VCCIO[17]
AN26 V5REF 5 0.001 PCH Core Well Reference Voltage
VCCIO[18] Internal PLL and VRM(+1.5VS)
+VCCAFDI_VRM
AN27 VCCIO[19] AT16
VCCVRM[3] V5REF_Sus 5 0.001 Suspend Well Reference Voltag
su
+1.05VS_PCH +1.05VS_PCH
C AP21 C
VCCIO[20]
AP23 AT20 Vcc3_3 3.3 0.266 I/O Buffer Voltage
VCCIO[21] VCCDMI[1] DMI buffer logic
1
DMI
1U_0402_6.3V6K
C342
10U_0805_6.3V6M
C314
Display DAC Analog Power. This power is

1U_0402_6.3V6K
C325
1U_0402_6.3V6K
C353
1U_0402_6.3V6K
C332
1 1 AP24
VCCIO
1 1 1 VCCIO[22] C344
20mA VccADAC 3.3 0.001 supplied by the core well.
p.
AP26 AB36 1U_0402_6.3V6K
VCCIO[23] VCCIO[1] 2 place near AT20
2 2 1
2 2 2 AT24 VccADPLLA 1.05 0.08 Display PLL A power
VCCIO[24] C308
1U_0402_6.3V6K Core Well I/O Buffer
om
2 place near AB36 VccADPLLB 1.05 0.08 Display PLL B power
AN33
VCCIO[25] 190mA
+3VS AN34 AG16 +1.8VS
VCCIO[26] VCCPNAND[1] VccCore 1.05 1.3 Internal Logic Voltage
NAND / SPI
BH29 VCC3_3[3] AG17
VCCPNAND[2] VccDFTERM should PH +1.8VS or +3VS VccDMI 1.05 0.042 DMI Buffer Voltage
1 1
C322 C349
yc
0.1U_0402_10V7K AJ16 0.1U_0402_10V7K
VCCPNAND[3] VccIO 1.05 2.925 Core Well I/O buffers
2 +VCCAFDI_VRM 2
AP16
VCCVRM[2] 1.05 V Supply for Intel R Management
VCCPNAND[4] AJ17
VccASW 1.05 1.01 Engine and Integrated LAN
+1.05VS_VCCAPLL_FDI
PAD T19 @ BG6
m
VCCFDIPLL
+1.05VS_PCH VccSPI 3.3 0.02 3.3 V Supply for SPI Controller Logic
+3VS
AP17 VCCIO[27]
FDI
V1
Trace 20mil 20mA VCCSPI VccDSW 3.3 0.003 3.3v supply for Deep S4/S5 well
1 AU20
VCCDMI[2]
// 1 For SPI control logi
B C347
C703 VccpNAND 1.8 0.19 1.8V power supply for DF_TVS B
COUGARPOINT_FCBGA989~D 1U_0402_6.3V6K
2
2 1U_0402_6.3V6K
VccRTC 3.3 6 uA Battery Voltage
p:
GPIO28 VccSus3_3 3.3 0.266 Suspend Well I/O Buffer Voltage

On-Die PLL Voltage Regulator
H
VccSusHDA 3.3 / 1.5 0.01
High Definition Audio Controller Suspend
Voltage
tt
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 +VCCAFDI_VRM
+1.5VS 1.8 V Internal PLL and VRMs (1.8 V for
VccVRM 1.8 / 1.5 0.16 Desktop)
h
+VCCAFDI_VRM
R257 2 1 0_0603_5%
VccCLKDMI 1.05 0.02 DMI Clock Buffer Voltage
VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP VccSSC 1.05 0.095 Spread Modulators Power Supply
惵HDA_SYNC PH(PLL =+1.5VS)

VCCVRM = 160mA detal waiting for newest spec
VccDIFFCLKN 1.05 0.055 Differential Clock Buffers Power Supply
Analog power supply for LVDS (Mobile
VccALVDS 3.3 0.001 Only)
Analog power supply for LVDS (Mobile
VccTX_LVDS 1.8 0.06 Only)
A A

PCH (7/9) PWR
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Have internal VRM

+3VS R150
0_0805_5% +1.05VS_PCH R167
1 2 +1.05V analog 0_0603_5%
@ internal clock PLL 2 1 +VCCACLK
L14 Can NC VCC3_3 = 266mA detal waiting for newest spec
10UH_LB2012T100MR_20% @
1 2 +3VS_VCC_CLKF33 VCCDMI = 42mA detal waiting for newest spec
1 1
+3VALW_PCH U33J POWER +1.05VS_PCH
1U_0402_6.3V6K
C304
10U_0805_10V4Z
C277
1 AD49 N26
Not support Deep S4,S5 VCCACLK VCCIO[29]
2 1
2 connect to +3VALW C340 P26
0.1U_0402_10V7K VCCIO[30] C321
T16
D 2 VCCDSW3_3 1U_0402_6.3V6K D
P28
VCCIO[31] 2
PAD T17 @ +PCH_VCCDSW V12
3mA T27
DCPSUSBYP VCCIO[32]
T29
suppied by internal +3VS_VCC_CLKF33 VCCIO[33] +3VALW_PCH
T38
VCC3_3[5]
1.05V VR must NC
VCCSUS3_3[7] T23
PAD T11 @ +VCCAPLL_CPY_PCH BH23 VCCAPLLDMI2 119mA T24
VCCSUS3_3[8] 1 1 +5VALW_PCH +3VALW_PCH
GPIO28
+1.05VS_PCH AL29 C330 C333
On-Die PLL Voltage Regulator VCCIO[14] 0.1U_0402_10V7K
V23 0.1U_0402_10V7K
USB
H VCCSUS3_3[9] Place near Place near
2
1
PAD T13 @ +VCCSUS1 AL24 V24 2P24 2P24
DCPSUS[3] VCCSUS3_3[10] D8
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 R202
P24 100_0402_5% CH751H-40PT_SOD323-2
,VCCAPLLSATA VCCSUS3_3[6]
+1.05VS_PCH
AA19
1
VCCASW[1]
2
+PCH_V5REF_SUS
+1.05VS_PCH
AA21
1010mA VCCIO[34] T26
1
VCCASW[2]
/
+1.05VS_PCH +PCH_V5REF_SUS C318
L12
10UH_LB2012T100MR_20%
AA24
VCCASW[3] 1mA V5REF_SUS
M26
0.1U_0603_25V7K
+1.05VS_VCCA_A_DPL 1 1 2
Clock and Miscellaneous

22U_0805_6.3V6M
C335
22U_0805_6.3V6M
C336
1 2 AA26
VCCASW[4] +VCCA_USBSUS
/x
AN23 +3VALW_PCH @ T14 PAD
DCPSUS[4] suppied by internal
1U_0402_6.3V6K
C296
AA27
220U_B2_2.5VM_R35
C279
1 2 VCCASW[5]
1
2 AN24 1.05V VR Must NC
AA29 VCCSUS3_3[1]
+ VCCASW[6]
+5VS +3VS
AA31
2 VCCASW[7]
2
su
+PCH_V5REF_RUN +3VALW_PCH
C AC26 1mA P34
2
VCCASW[8] V5REF C
1
1 1
1
1U_0402_6.3V6K
C327
AC27 D7
1U_0402_6.3V6K
C326
1U_0402_6.3V6K
C316
+1.05VS_VCCA_B_DPL VCCASW[9] +3V_VCCPSUS R148
1 2 N20 1 100_0402_5% CH751H-40PT_SOD323-2
PCI/GPIO/LPC
VCCSUS3_3[2] C352
L11 AC29
2 VCCASW[10] 1U_0402_6.3V6K
220U_B2_2.5VM_R35
C278
10UH_LB2012T100MR_20% 2 2 N22
1U_0402_6.3V6K
C295
p.
1
1
VCCSUS3_3[3] +PCH_V5REF_RUN
2
AC31
+ 1 VCCASW[11] 2
P20 1
SGA00001700 VCCSUS3_3[4]
AD29 +3VS
VCCASW[12] C244
220U 2.5V M B2 VCCSUS3_3[5]
P22
2 2 AD31 1U_0603_10V6K
om
ESR 35mohm@100Khz VCCASW[13] 2
W21 AA16
VCCASW[14] VCC3_3[1]
1 1 1
W23 VCC3_3[8] W16 C704 C343 C309
VCCASW[15]
0.1U_0402_10V7K
Place near 0.1U_0402_10V7K
Place near 0.1U_0402_10V7K
Place near
W24 T34
VCCASW[16] VCC3_3[4] AJ2 AA16,W16 T34
2 2 2
W26
yc
VCCASW[17]
W29
VCCASW[18]
+1.05VS_PCH
W31 AJ2
VCCASW[19] VCC3_3[2]
W33
m
VCCASW[20]
AF13
VCCIO[5]
+VCCRTCEXT 1
N16 DCPRTC
AH13 C350
1 VCCIO[12]
C348
0.1U_0402_10V7K
+VCCAFDI_VRM
// Y49 VCCVRM[4] VCCIO[13]
AH14 2
1U_0402_6.3V6K
B 2 <BOM Structure> GPIO28

B

+1.05VS_VCCA_A_DPL AF14
VCCIO[6] On-Die PLL Voltage Regulator
BD47 80mA
SATA
VCCADPLLA +VCCSATAPLL @ T62 PAD H
+1.05VS_VCCA_B_DPL AK1 +VCCAFDI_VRM
p:
VCCAPLLSATA
+1.05VS_PCH BF47 VCCADPLLB 80mA VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
+VCCAFDI_VRM
VCCVRM[1]
AF11 ,VCCAPLLSATA
AF17
VCCIO[7]
AF33 VCCIO[8] +1.05VS_PCH
55mA
tt
AF34 AC16
VCCIO[9] VCCIO[2]
1 C317 AG34
1 C311 1 C312 1U_0402_6.3V6K
VCCIO[11]
AC17
1U_0402_6.3V6K 1U_0402_6.3V6K VCCIO[3] 1
Place Place Place C351
AG33 AD17
h
near AF17 near AF33, VCCIO[10] VCCIO[4] 1U_0402_6.3V6K

2 2 near AG33 2 95mA
AF34,AG34 +VCCSST 2 +1.05VS_PCH
1 2 C354 V16
DCPSST
0.1U_0402_10V7K
+1.05VM_VCCSUS +VCCME_22
PAD T15 @ T17 DCPSUS[1] T21 R237 2 1 0_0603_5%
suppied by internal VCCASW[22]
V19
MISC
1.05V VR Must NC +1.05VS_PCH

DCPSUS[2]
+VCCME_23
V21 R224 2 1 0_0603_5%
VCCASW[23]
1mA
CPU
BJ8 V_PROC_IO +VCCME_21

R236 2 1 0_0603_5%
T19
1 VCCASW[21]
+RTCVCC +3VALW_PCH
4.7U_0603_6.3V6K
C700
1 1
0.1U_0402_10V7K
C693
0.1U_0402_10V7K
C694
+VCCSUSHDA
Need +3VALW and 0.1U close PCH
RTC
A22 10mAVCCSUSHDA P32 R206 1 0_0603_5%

HDA
2 VCCRTC 2
2 2
0.1U_0402_10V7K
C685
1U_0402_6.3V6K
C331
0.1U_0402_10V7K
C687
A 1 1 1 COUGARPOINT_FCBGA989~D 1 A
C315
Close P32
0.1U_0402_16V4Z
Place
near BJ8 2 2 2 2

2010/08/11 2011/08/11 Title
Issued Date Deciphered Date PCH (8/9) PWR
Custom 0.1
5 4 3 2 1
5 4 3 2 1
U33I
AY4 H46
VSS[159] VSS[259]
AY42 K18
VSS[160] VSS[260]
AY46 VSS[161] K26
AY8
VSS[261]
VSS[162] VSS[262] K39
B11 K46
D U33H VSS[163] VSS[263] D
B15 K7
VSS[164] VSS[264]
H5 B19 L18
VSS[0] VSS[165] VSS[265]
B23 VSS[166] L2
AA17 AK38 VSS[266]
VSS[1] VSS[80] B27 VSS[167] L20
AA2 AK4 VSS[267]
VSS[2] VSS[81] B31 L26
AA3 VSS[168] VSS[268]
VSS[3] AK42 B35 L28
VSS[82] VSS[169] VSS[269]
AA33 AK46 B39 L36
VSS[4] VSS[83] VSS[170] VSS[270]
AA34 VSS[5] AK8 B7 L48
VSS[84] VSS[171] VSS[271]
AB11 VSS[6] AL16 F45 M12
VSS[85] VSS[172] VSS[272]
AB14 AL17 BB12 P16
VSS[7] VSS[86] VSS[173] VSS[273]
AB39 AL19 BB16 M18
VSS[8] VSS[87] VSS[174] VSS[274]
AB4 AL2 BB20 M22
VSS[9] VSS[88] VSS[175] VSS[275]
AB43 AL21 BB22 M24
VSS[10] VSS[89] VSS[176] VSS[276]
AB5 AL23 BB24 M30
VSS[11] VSS[90] VSS[177] VSS[277]
AB7 AL26 BB28 M32
VSS[12] VSS[91] VSS[178] VSS[278]
AC19 AL27 BB30 M34
VSS[13] VSS[92] VSS[179] VSS[279]
AC2 VSS[14] AL31 BB38 M38
VSS[93] VSS[180] VSS[280]
AC21 VSS[15] AL33 BB4 M4
AC24 VSS[94] VSS[181] VSS[281]
VSS[16] VSS[95] AL34 BB46 M42
AC33 AL48 VSS[182] VSS[282]
VSS[17] VSS[96] BC14 VSS[183] M46
AC34 AM11 BC18 VSS[283]
VSS[18] M8
/
AC48 VSS[97] VSS[184] VSS[284]
VSS[19] VSS[98] AM14 BC2 N18
AD10 AM36 VSS[185] VSS[285]
VSS[20] VSS[99] BC22 P30
AD11 AM39 VSS[186] VSS[286]
VSS[21] VSS[100] BC26 N47
VSS[187]
/x
AD12 AM43 BC32 VSS[287]
VSS[22] VSS[101] VSS[188] P11
AD13 AM45 BC34 VSS[288]
VSS[23] VSS[102] VSS[189] P18
AD19 AM46 BC36 VSS[289]
VSS[24] VSS[103] VSS[190] T33
AD24 AM7 BC40 VSS[290]
VSS[25] VSS[104] VSS[191] P40
AD26 AN2 BC42 VSS[291]
VSS[26] VSS[105] VSS[192] P43
AD27 AN29 BC48 VSS[292]
VSS[27] VSS[106] VSS[193] P47
AD33 AN3 VSS[293]
su
VSS[28] VSS[107] BD46 P7
AD34 AN31 VSS[194] VSS[294]
C VSS[29] VSS[108] BD5 VSS[195] R2 C
AD36 AP12 BE22 VSS[295]
VSS[30] VSS[109] VSS[196] R48
AD37 AP19 BE26 VSS[296]
VSS[31] VSS[110] VSS[197] T12
AD38 AP28 BE40 VSS[297]
VSS[32] VSS[111] VSS[198] VSS[298] T31
AD39 VSS[33] AP30 BF10
AD4 VSS[112] VSS[199] T37
AP32 VSS[299]
p.
VSS[34] VSS[113] BF12 T4
AD40 AP38 VSS[200] VSS[300]
VSS[35] VSS[114] BF16 W34
AD42 AP4 VSS[201] VSS[301]
VSS[36] VSS[115] BF20 T46
AD43 AP42 VSS[202] VSS[302]
VSS[37] VSS[116] BF22 T47
AD45 AP46 VSS[203] VSS[303]
VSS[38] VSS[117] BF24 T8
AD46 AP8 VSS[204] VSS[304]
om
VSS[39] VSS[118] BF26 V11
AD8 AR2 VSS[205] VSS[305]
VSS[40] VSS[119] BF28 V17
AE2 AR48 VSS[206] VSS[306]
VSS[41] VSS[120] BD3 V26
AE3 AT11 VSS[207] VSS[307]
VSS[42] VSS[121] BF30 V27
AF10 AT13 VSS[208] VSS[308]
VSS[43] VSS[122] BF38 V29
AF12 AT18 VSS[209] VSS[309]
VSS[44] VSS[123] BF40 V31
AD14 AT22 VSS[210] VSS[310]
VSS[45] VSS[124] BF8 VSS[211] V36
AD16 AT26 VSS[311]
VSS[46] VSS[125] BG17 V39
AF16 AT28 VSS[212] VSS[312]
VSS[47] BG21
yc
AF19 VSS[126] VSS[213] V43
VSS[48] AT30 BG33 VSS[313]
AF24 VSS[127] VSS[214] V7
VSS[49] AT32 BG44 VSS[314]
AF26 VSS[128] VSS[215] W17
VSS[50] AT34 BG8 VSS[315]
AF27 VSS[129] VSS[216] VSS[316] W19
VSS[51] AT39 BH11 W2
AF29 VSS[130] AT42 VSS[217] VSS[317]
VSS[52] VSS[131] BH15 W27
AF31 AT46 VSS[218] VSS[318]
m
VSS[53] VSS[132] BH17 W48
AF38 VSS[54] AT7 VSS[219] VSS[319]
VSS[133] BH19 VSS[220] Y12
AF4 VSS[55] AU24 VSS[320]
AF42 VSS[134] H10 Y38
VSS[56] VSS[135] AU30 BH27 VSS[221] VSS[321]
AF46 AV16 VSS[222] VSS[322] Y4
VSS[57] VSS[136] BH31 Y42
AF5 AV20 VSS[223] VSS[323]
AF7
AF8
VSS[58]
VSS[59]
VSS[137]
VSS[138] AV24
//
BH33
BH35
VSS[224]
VSS[225]
VSS[324] Y46
Y8
VSS[60] VSS[139] AV30 BH39 VSS[325]
AG19 AV38 VSS[226] VSS[328] BG29
B VSS[61] VSS[140] BH43 N24
B
AG2 VSS[62] AV4 VSS[227] VSS[329]
AG31 VSS[141] BH7 AJ3
VSS[63] AV43 VSS[228] VSS[330]
AG48 VSS[142] D3 AD47
VSS[64] AV8 VSS[229] VSS[331]
VSS[143] D12
p:
AH11 AW14 VSS[230] B43

VSS[65] VSS[144] D16 VSS[333]
AH3 AW18 VSS[231] BE10
VSS[66] VSS[145] D18 VSS[334]
AH36 AW2 VSS[232] VSS[335] BG41
VSS[67] VSS[146] D22
AH39 AW22 VSS[233] VSS[337] G14
VSS[68] VSS[147] D24
AH40 AW26 VSS[234] H16
VSS[69] VSS[148] D26 VSS[338]
AH42 T36
tt
VSS[70] AW28 VSS[235] VSS[340]

AH46 VSS[149] D30 BG22
VSS[71] AW32 VSS[236] VSS[342]
AH7 VSS[150] D32 VSS[237] BG24
VSS[72] AW34 VSS[343]
AJ19 VSS[151] D34 C22
VSS[73] AW36 VSS[238] VSS[344]
VSS[152] D38 AP13
AJ21 AW40
h
VSS[74] VSS[153] VSS[239] VSS[345]

AW48 D42 VSS[240] M14
AJ24 VSS[154] VSS[346]
AJ33 VSS[75] D8 AP3
VSS[76] AV11 VSS[241] VSS[347]
AJ34 VSS[155] E18 AP1
VSS[77] AY12 VSS[242] VSS[348]
AK12 VSS[156] E26 BE16
VSS[78] VSS[157] AY22 VSS[243] VSS[349]
AK3 AY28 G18 BC16
VSS[79] VSS[158] VSS[244] VSS[350]
G20 BG28
COUGARPOINT_FCBGA989~D VSS[245] VSS[351]
G26 BJ28
<BOM Structure> VSS[246] VSS[352]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34
VSS[257]
A F3 VSS[258]
A
<BOM Structure>

PCH (9/9) VSS
Custom 0.1
5 4 3 2 1
A B C D E
U27A
4 PEG_HTX_C_GRX_P0 AP17 Part 1 of 7 K1 GPIO I/O USAGE

PEX_RX0 GPIO0 VGA_HDMI_DET
4 PEG_HTX_C_GRX_N0 AN17 K2 VGA_HDMI_DET 33
PEX_RX0_N GPIO1 VGA_PNL_PWM
4 PEG_HTX_C_GRX_P1 AN19 K3 VGA_PNL_PWM 31
PEX_RX1 GPIO2 ENVDD
4 PEG_HTX_C_GRX_N1 AP19 PEX_RX1_N GPIO3 H3
VGA_BKL_EN ENVDD 31 GPIO0 IN N/A
4 PEG_HTX_C_GRX_P2 AR19 H2
PEX_RX2 GPIO4 GPU_VID0
4 PEG_HTX_C_GRX_N2 AR20 H1 GPU_VID0 53
PEX_RX2_N GPIO5 GPU_VID1
4 PEG_HTX_C_GRX_P3 AP20
PEX_RX3 GPIO6 H4 GPU_VID1 53 GPIO1 IN HPD_IFPC
4 PEG_HTX_C_GRX_N3 AN20 H5
PEX_RX3_N GPIO7
4 PEG_HTX_C_GRX_P4 AN22 H6 R78 2 DIS@ 1 10K_0402_5% +3VSDGPU
PEX_RX4 GPIO8
4 PEG_HTX_C_GRX_N4 AP22 PEX_RX4_N GPIO9 J7 R70 2 DIS@ 1 10K_0402_5% GPIO2 OUT N/A
4 PEG_HTX_C_GRX_P5 AR22 PEX_RX5 K4
GPIO10
4 PEG_HTX_C_GRX_N5 AR23 PEX_RX5_N K5
GPIO11
AP23 GPIO3 OUT N/A
GPIO
4 PEG_HTX_C_GRX_P6 PEX_RX6 H7 R74 2 DIS@ 1 10K_0402_5% +3VSDGPU
1 GPIO12 1
4 PEG_HTX_C_GRX_N6 AN23 J4
PEX_RX6_N GPIO13
4 PEG_HTX_C_GRX_P7 AN25 J6
PEX_RX7 GPIO14
4 PEG_HTX_C_GRX_N7 AP25
PEX_RX7_N GPIO15
L1 GPIO4 OUT N/A
4 PEG_HTX_C_GRX_P8 AR25 PEX_RX8 L2
GPIO16
4 PEG_HTX_C_GRX_N8 AR26 PEX_RX8_N L4
GPIO17
4 PEG_HTX_C_GRX_P9 AP26 PEX_RX9 GPIO18 M4 GPIO5 OUT GPU Core VID0
4 PEG_HTX_C_GRX_N9 AN26 L7 DIS@
PEX_RX9_N GPIO19 VGA_HDMI_DET
4 PEG_HTX_C_GRX_P10 AN28 L5 2 R118 1 10K_0402_5%
PEX_RX10 GPIO20 DIS@
4 PEG_HTX_C_GRX_N10 AP28 PEX_RX10_N GPIO21
K6 VGA_PNL_PWM
GPIO6 OUT GPU Core VID1
4 PEG_HTX_C_GRX_P11 AR28 L6 2 R117 1 10K_0402_5%
PEX_RX11 GPIO22
4 PEG_HTX_C_GRX_N11 AR29 M6 DIS@
PEX_RX11_N GPIO23 ENVDD
4 PEG_HTX_C_GRX_P12 AP29
PEX_RX12 GPIO24
M7 2 R72 1 10K_0402_5% GPIO7 OUT N/A
4 PEG_HTX_C_GRX_N12 AN29 DIS@
PEX_RX12_N VGA_BKL_EN
4 PEG_HTX_C_GRX_P13 AN31 N1 2 R115 1 10K_0402_5%
PEX_RX13 MIOA_D0_NC
4 PEG_HTX_C_GRX_N13 AP31
PEX_RX13_N MIOA_D1_NC
P4 GPIO8 IN OVERT
4 PEG_HTX_C_GRX_P14 AR31 P1
4 PEG_HTX_C_GRX_N14 PEX_RX14 MIOA_D2_NC
AR32 PEX_RX14_N P2
4 PEG_HTX_C_GRX_P15 MIOA_D3_NC GPIO9 OUT ALERT
AR34 PEX_RX15 P3
4 PEG_HTX_C_GRX_N15 MIOA_D4_NC
AP34 T3
PEX_RX15_N MIOA_D5_NC
T2
MIOA_D6_NC GPIO10 OUT N/A
/
T1
4 PEG_GTX_HRX_P0 AL17 MIOA_D7_NC
PEX_TX0 MIOA_D8_NC U4
4 PEG_GTX_HRX_N0 AM17
PCI EXPRESS
PEX_TX0_N MIOA_D9_NC U1 VGA_BKL_EN ENBKL
4 PEG_GTX_HRX_P1 AM18 U2 2 DISO@ 1 R116 GPIO11 OUT N/A
/x
PEX_TX1 MIOA_D10_NC 0_0402_5% ENBKL 16,39
4 PEG_GTX_HRX_N1 AM19 U3
PEX_TX1_N MIOA_D11_NC
4 PEG_GTX_HRX_P2 AL19 R6
4 PEG_GTX_HRX_N2
PEX_TX2 MIOA_D12_NC GPIO12 IN PWR_LEVEL
AK19
DVO
PEX_TX2_N MIOA_D13_NC T6
4 PEG_GTX_HRX_P3 AL20 N6
4 PEG_GTX_HRX_N3 PEX_TX3 MIOA_D14_NC
AM20 +3VSDGPU
4 PEG_GTX_HRX_P4 PEX_TX3_N GPIO13 OUT N/A
AM21 Y1
PEX_TX4
su
4 PEG_GTX_HRX_N4 AM22 MIOB_D0_NC I2CS_SCL
PEX_TX4_N MIOB_D1_NC Y2 R495 1 DIS@ 2 2.2K_0402_5%
2 4 PEG_GTX_HRX_P5 AL22 Y3 I2CS_SDA 2
4 PEG_GTX_HRX_N5 PEX_TX5 MIOB_D2_NC GPIO14 OUT N/A
AK22 AB3 I2CH_SCL R494
4 PEG_GTX_HRX_P6 PEX_TX5_N MIOB_D3_NC 1 DIS@ 2 2.2K_0402_5%
AL23 PEX_TX6 AB2 I2CH_SDA R122 DIS@
1DIS@ 2.2K_0402_5%
22.2K_0402_5%
4 PEG_GTX_HRX_N6 AM23 MIOB_D4_NC I2CB_SCL R121 1 2
PEX_TX6_N AB1
4 PEG_GTX_HRX_P7 AM24 MIOB_D5_NC I2CB_SDA R120 1 DIS@ 2 2.2K_0402_5%
PEX_TX7 AC4 R119 1 DIS@ 2 2.2K_0402_5%
p.
4 PEG_GTX_HRX_N7 AM25 MIOB_D6_NC VGA_LCD_CLK
PEX_TX7_N AC1
4 PEG_GTX_HRX_P8 AL25 MIOB_D7_NC VGA_LCD_DATA
PEX_TX8 AC2 R502 1 DIS@ 2 2.2K_0402_5%
4 PEG_GTX_HRX_N8 AK25 MIOB_D8_NC
PEX_TX8_N AC3 R497 1 DIS@ 2 2.2K_0402_5%
4 PEG_GTX_HRX_P9 AL26 MIOB_D9_NC VGA_DDC_CLK XTALOUT XTALIN
PEX_TX9 AE3
4 PEG_GTX_HRX_N9 AM26 MIOBD_10_NC VGA_DDC_DATA
PEX_TX9_N AE2 R123 1 DIS@
DIS@ 22.2K_0402_5%
2.2K_0402_5% @
om
4 PEG_GTX_HRX_P10 AM27 MIOB_D11_NC R124 1 2
4 PEG_GTX_HRX_N10 PEX_TX10 U6 R474 1M_0402_5%
AM28 MIOB_D12_NC
4 PEG_GTX_HRX_P11 PEX_TX10_N W6
AL28 MIOB_D13_NC VGA_CRT_R
4 PEG_GTX_HRX_N11 PEX_TX11 Y6 R45 1 DIS@ 2 150_0402_1% 2 1
AK28 MIOB_D14_NC VGA_CRT_G
4 PEG_GTX_HRX_P12 PEX_TX11_N VGA_CRT_B R48 1 DIS@ 2 150_0402_1%
AK29 PEX_TX12 N3
4 PEG_GTX_HRX_N12 MIOA_HSYNC_NC R49 1 DIS@ 2 150_0402_1% Y1 DIS@ 1
AL29 L3
4 PEG_GTX_HRX_P13 PEX_TX12_N MIOA_VSYNC_NC 27MHZ_16PF_X5H027000FG1H
1
AM29 DIS@ C577
4 PEG_GTX_HRX_N13 PEX_TX13
AM30 W1 DIS@ C576 18P_0402_50V8J
4 PEG_GTX_HRX_P14 PEX_TX13_N MIOB_HSYNC_NC
yc
AM31 W2 18P_0402_50V8J 2
4 PEG_GTX_HRX_N14 PEX_TX14 MIOB_VSYNC_NC
AM32 2
4 PEG_GTX_HRX_P15 PEX_TX14_N
AN32 N2
4 PEG_GTX_HRX_N15 PEX_TX15 MIOA_DE_NC
AP32 P5
PEX_TX15_N MIOA_CTL3_NC
MIOA_VREF_NC N5
m
+3VSDGPU 1 DIS@ 14 CLK_PEG_VGA MIOB_DE_NC Y5
2 AR16
R418 10K_0402_5% 14 CLK_PEG_VGA# PEX_REFCLK MIOB_CTL3_NC W3
AR17 AF1
14 PEG_CLKREQ#
AR13
PEX_REFCLK_N MIOB_VREF_NC External Spread Spectrum OSC_OUT XTAL_OUTBUFF
PEX_CLKREQ_N R479 1 DIS@ 2 10K_0402_5% R477 1 @ 2 22_0402_5%
N4
// MIOA_CLKIN_NC
1
2 1 AJ17 MIOA_CLKOUT_NC R4 U29
PEX_TSTCLK_OUT
R44 @ AJ18
200_0402_1% R465 1 DIS@ 2 10K_0402_5% 1 6 R455
PEX_TSTCLK_OUT_N REFOUT VSS
3 MIOB_CLKIN_NC AE1 10K_0402_5% 3
OSC_SPREAD
17 PLTRST_VGA# MIOB_CLKOUT_NC V4 2 5 DIS@
2 1 AM16 XOUT MODOUT
PEX_RST_N OSC_OUT
2
R67 DIS@ 2.49K_0402_1% AG21
MIOA_CLKOUT_NC_N T4 3 4 +3VSDGPU
PEX_TERMP
p:
W4 XIN/CLKIN VDD
+1.05VSDGPU MIOB_CLKOUT_NC_N OSC_SPREAD XTAL_SSIN
150mA +GPU_PLLVDD R458 1 DIS@ 2 10K_0402_5% R476 1 @ 2 22_0402_5%
FBMA-L10-160808-300LMT 0603 1
DIS@ U5 @ ASM3P2872AF-06OR_TSOT-23-6 @
MIOACAL_PD_VDDQ_NC
0.1U_0402_16V4Z
10U_0603_6.3V6M
AE9 T5 C581
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 1 PLLVDD MIOACAL_PU_GND_NC
DIS@ C146
DIS@ C190
4700P_0402_25V7K
1
22U_0805_6.3V6M
DIS@ C186
1 0.1U_0402_16V4Z
DIS@ C180
0.1U_0402_16V4Z
L9 1 1 1
tt
2
@ C187
DIS@ C189
AF9 AA7 R462 1 DIS@ 2 10K_0402_5%

DIS@ C184
1 1 1 SP_PLLVDD MIOBCAL_PD_VDDQ_NC
MIOBCAL_PU_GND_NC AA6 R454
XTALIN AD9 10K_0402_5%
CLK
2 2 2 VID_PLLVDD
2 XTALOUT DIS@
B1
2
2
h
2 2
XTAL_OUTBUFF B2
XTAL_IN
AM15
VGA_CRT_R 32
VGA_CRT_G 32
If External Spread Spectrum not stuff then stuff resistor
XTAL_OUT DACA_RED
under GPU XTAL_SSIN AM14 VGA_CRT_B 32
D1 DACA_GREEN
XTAL_OUTBUFF AL14
D2 DACA_BLUE
XTAL_SSIN VGA_CRT_HSYNC 32
AM13 VGA_CRT_VSYNC 32
DACA_HSYNC
I2CS_SCL AL13 +DACA_VDD
I2CS_SDA
DACA_VSYNC 120 mA
1 2 +3VSDGPU
E2 I2CS_SCL AJ12 L5
DACA_VDD
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VGA_LCD_CLK E1 AK12 FBMA-L10-160808-301LMT_2P
I2CS_SDA DACA_VREF
VGA_LCD_DATA AK13
0.1U_0402_16V4Z
4.7U_0603_6.3V6M
1U_0402_6.3V6K
31 VGA_LCD_CLK DACA_RSET DISO@
DIS@ C124
DISO@ C140
124_0402_1%
E3 1 1
10K_0402_5%
+3VSDGPU 31 VGA_LCD_DATA I2CC_SCL
DACs
I2CB_SCL 1
R65
E4 AK4
DISO@ C136
1
DISO@ C176
1
DISO@ C132
1
OPT@ R113
For RF request @ I2CB_SDA I2CC_SDA DACB_RED 1 1 1
@ AL4
C195 G3 DACB_GREEN
C197 AJ4
I2C
0.01U_0402_16V7K VGA_DDC_CLK I2CB_SCL DACB_BLUE

DIS@
2 2
0.01U_0402_16V7K G2
2 2 VGA_DDC_DATA I2CB_SDA
I2CS_SCL 2 2 2
2
32 VGA_DDC_CLK AM1
2
EC_SMB_CK2 14,39 CRT G1 DACB_HSYNC
2
32 VGA_DDC_DATA I2CA_SCL DACB_VSYNC AM2 DIS@
I2CH_SCL G4 R466 2 1 10K_0402_5%
4 1 6 I2CA_SDA 4
I2CH_SDA
DACB_VDD AG7 Under GPU
2N7002DWH_SOT363-6 F6
I2CH_SCL AK6 @ R467 1
@ C154 1
2 124_0402_1%
2 0.1U_0402_16V4Z
DACB_VREF
+3VSDGPUDIS@ G6 AH7
Q31A I2CH_SDA DACB_RSET
5
N12P-GV1-A1_BGA973 DIS@
I2CS_SDA
4 3 EC_SMB_DA2 14,39
2N7002DWH_SOT363-6
Q31B DIS@
N12P PEG 1/9
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom P5WE0 M/B LA-6901P Schematic 0.1
A B C D Date: Friday, August 27, 2010 E Sheet 22 of 59
A
VRAM Interface 27
27
MDA[15..0]
MDA[31..16]
MDA[15..0]
MDA[31..16] 29 MDC[15..0]
MDC[15..0]
MDC[31..16]
MDA[47..32] 29 MDC[31..16]
28 MDA[47..32] MDC[47..32]
MDA[63..48] 30 MDC[47..32]
28 MDA[63..48] MDC[63..48]
30 MDC[63..48]
U27B U27C
CMDA[30..0] 27,28 CMDC[30..0] 29,30
Part 2 of 7 U30 CMDA0 Part 3 of 7 CMDC0
MDA0 FBA_CMD0 CMDA1 MDC0 FBC_CMD0 F18
L32 V30 B13 CMDC1
MDA1 FBA_D0 FBA_CMD1 CMDA2 MDC1 FBC_D0 E19
N33 U31 FBC_CMD1 CMDC2
MDA2 FBA_D1 FBA_CMD2 CMDA3 D13 D18
L33 V32 MDC2 FBC_D1 FBC_CMD2 CMDC3
MDA3 FBA_D2 FBA_CMD3 CMDA4 A13 C17
N34 T35 MDC3 FBC_D2 FBC_CMD3 CMDC4
MDA4 FBA_D3 FBA_CMD4 CMDA5 A14 FBC_D3 F19
N35 U33 MDC4 FBC_CMD4 CMDC5
MDA5 FBA_D4 FBA_CMD5 CMDA6 C16 FBC_D4 C19
P35 W32 MDC5 FBC_CMD5 CMDC6
MDA6 FBA_D5 FBA_CMD6 CMDA7 B16 B17
P33 W33 MDC6 FBC_D5 FBC_CMD6 CMDC7
MDA7 FBA_D6 FBA_CMD7 CMDA8 MDC7 A17 E20
P34 W31 FBC_D6 FBC_CMD7 CMDC8
MDA8 FBA_D7 FBA_CMD8 CMDA9 MDC8 D16 FBC_D7 B19
K35 W34 FBC_CMD8 CMDC9
MDA9 FBA_D8 FBA_CMD9 CMDA10 MDC9 C13 FBC_D8 D20
K33 U34 FBC_CMD9 CMDC10
MDA10 FBA_D9 FBA_CMD10 CMDA11 MDC10 B11 FBC_D9 A19
K34 U35 FBC_CMD10 CMDC11
MDA11 FBA_D10 FBA_CMD11 CMDA12 MDC11 C11 FBC_D10 D19
H33 U32 FBC_CMD11 CMDC12
MDA12 FBA_D11 FBA_CMD12 CMDA13 MDC12 A11 FBC_D11 C20 CMDC13
G34 T34 C10 FBC_CMD12
MDA13 FBA_D12 FBA_CMD13 CMDA14 MDC13 FBC_D12 F20 CMDC14
G33 T33 FBC_CMD13
MDA14 FBA_D13 FBA_CMD14 CMDA15 MDC14 C8 B20 CMDC15
E34 W30 FBC_D13 FBC_CMD14
MDA15 FBA_D14 FBA_CMD15 CMDA16 MDC15 B8 G21 CMDC16
E33 AB30 FBC_D14 FBC_CMD15
MDA16 FBA_D15 FBA_CMD16 CMDA17 MDC16 A8 F22 CMDC17
G31 AA30 FBC_D15 FBC_CMD16
MDA17 FBA_D16 FBA_CMD17 CMDA18 MDC17 E8 F24 CMDC18
/
F30 AB31 FBC_D16 FBC_CMD17
MDA18 FBA_D17 FBA_CMD18 CMDA19 MDC18 F8 FBC_D17 F23 CMDC19
G30 AA32 FBC_CMD18
MDA19 FBA_D18 FBA_CMD19 CMDA20 MDC19 F10 FBC_D18 C25 CMDC20
G32 AB33 CMDA21 FBC_CMD19
MDA20 FBA_D19 FBA_CMD20 MDC20 F9 FBC_D19 C23 CMDC21
FBC_CMD20
/x
MDA21 K30 Y32 CMDA22 F12 F21
FBA_D20 FBA_CMD21 MDC21 FBC_D20 FBC_CMD21 CMDC22
MDA22 K32 Y33 CMDA23 D8 E22
MDA23 H30 AB34 CMDA24 D11 D21
MDA24 K31 AB35 CMDA25 E11 A23
MDA25 L31 Y35 CMDA26 D12
FBA_D24 FBA_CMD25 MDC25 FBC_D24 D22 CMDC26
MDA26 L30 W35 CMDA27 E13 FBC_CMD25
FBA_D25 FBA_CMD26 MDC26 FBC_D25 FBC_CMD26 B23 CMDC27
MEMORY INTERFACE
MDA27 M32 Y34
su
MEMORY INTERFACE C
FBA_D26 FBA_CMD27 CMDA28 MDC27 F13 C22 CMDC28
MDA28 N30 Y31 FBC_D26 FBC_CMD27
FBA_D27 FBA_CMD28 CMDA29 MDC28 F14 B22 CMDC29
MDA29 M30 Y30 FBC_D27 FBC_CMD28
FBA_D28 FBA_CMD29 CMDA30 MDC29 F15 A22 CMDC30
MDA30 P31 W29 FBC_D28 FBC_CMD29
FBA_D29 FBA_CMD30 MDC30 E16 A20
MDA31 R32 Y29 FBC_D29 FBC_CMD30
FBA_D30 FBA_CMD31 MDC31 F16 G20
MDA32 R30 DQMA0 DQMA[3..0] 27 FBC_D30 FBC_CMD31 DQMC[3..0] 29
FBA_D31 MDC32 F17 DQMC0
MDA33 AG30 P32 DQMA1 FBC_D31
p.
FBA_D32 FBA_DQM0 MDC33 D29 A16 DQMC1
MDA34 AG32 H34 DQMA2 FBC_D32 FBC_DQM0
FBA_D33 FBA_DQM1 MDC34 F27 D10 DQMC2
MDA35 AH31 J30 DQMA3 FBC_D33 FBC_DQM1
FBA_D34 FBA_DQM2 MDC35 F28 F11 DQMC3
MDA36 AF31 P30 DQMA4 DQMA[7..4] 28 FBC_D34 FBC_DQM2 DQMC[7..4] 30
FBA_D35 FBA_DQM3 MDC36 E28 D15 DQMC4
MDA37 AF30 AF32 DQMA5 MDC37 FBC_D35 FBC_DQM3
FBA_D36 FBA_DQM4 D26 FBC_D36 D27 DQMC5
MDA38 AE30 AL32 DQMA6 FBC_DQM4
om
FBA_D37 FBA_DQM5 MDC38 F25 D34 DQMC6
MDA39 AC32 AL34 DQMA7 MDC39 FBC_D37 FBC_DQM5
FBA_D38 FBA_DQM6 D24 FBC_D38 A34 DQMC7
MDA40 AD30 AF35 MDC40 FBC_DQM6
FBA_D39 FBA_DQM7 E25 FBC_D39 D28
MDA41 AN33 DQSA#0 DQSA#[3..0] 27 MDC41 FBC_DQM7 DQSC#[3..0] 29
FBA_D40 E32 DQSC#0
MDA42 AL31 L35 DQSA#1 MDC42 FBC_D40
FBA_D41 F32 DQSC#1
A
MDA43 AM33 FBA_DQS_RN0 DQSA#2 FBC_D41 B14

FBA_D42 G35 MDC43 D33 FBC_DQS_RN0 DQSC#2
MDA44 AL33 FBA_DQS_RN1 DQSA#3 FBC_D42 B10
1
FBA_D43 H31 MDC44 E31 FBC_DQS_RN1 DQSC#3

1
MDA45 AK30 FBA_DQS_RN2 DQSA#4 FBC_D43 D9

FBA_D44 N32 DQSA#[7..4] 28 MDC45 C33 FBC_DQS_RN2 DQSC#4 DQSC#[7..4] 30
MDA46 AK32 FBA_DQS_RN3 DQSA#5 FBC_D44 E14
AD32 MDC46 FBC_DQS_RN3
yc
FBA_D45 FBA_DQS_RN4 DQSA#6 F29 F26 DQSC#5
MDA47 AJ30 AJ31 MDC47 FBC_D45 FBC_DQS_RN4
FBA_D46 FBA_DQS_RN5 DQSA#7 D30 D31 DQSC#6
MDA48 AH30 AJ35 MDC48 FBC_D46 FBC_DQS_RN5 DQSC#7
FBA_D47 FBA_DQS_RN6 E29 A31
MDA49 AH33 AC34 MDC49 FBC_D47 FBC_DQS_RN6
FBA_D48 FBA_DQS_RN7 B29 A26
MDA50 AH35 DQSA0 DQSA[3..0] 27 MDC50 FBC_D48 FBC_DQS_RN7 DQSC0 DQSC[3..0] 29
FBA_D49 C31
MDA51 AH34 L34 DQSA1 MDC51 FBC_D49 DQSC1
FBA_D50 FBA_DQS_WP0 C29 C14
MDA52 AH32 DQSA2 FBC_D50
m
FBA_D51 H35 MDC52 B31 FBC_DQS_WP0 DQSC2
MDA53 AJ33 FBA_DQS_WP1 DQSA3 FBC_D51 A10
FBA_D52 J32 MDC53 C32 FBC_DQS_WP1 DQSC3
MDA54 AL35 FBA_DQS_WP2 DQSA4 DQSA[7..4] 28 FBC_D52 E10
FBA_D53 N31 MDC54 B32 FBC_DQS_WP2 DQSC4 DQSC[7..4] 30
MDA55 AM34 FBA_DQS_WP3 DQSA5 FBC_D53 D14
FBA_D54 AE31 MDC55 B35 FBC_DQS_WP3 DQSC5
MDA56 AM35 FBA_DQS_WP4 DQSA6 MDC56 FBC_D54 E26
FBA_D55 FBA_DQS_WP5
AJ32 B34 FBC_DQS_WP4 DQSC6
MDA57 AF33 DQSA7 MDC57 FBC_D55 D32
MDA58
MDA59
AE32
FBA_D56
FBA_D57
FBA_DQS_WP6
FBA_DQS_WP7
AJ34
AC33
// MDC58 A29
B28
FBC_D56
FBC_DQS_WP5
FBC_DQS_WP6 A32
B26
DQSC7
AF34 FBA_D58 MDC59 FBC_D57 FBC_DQS_WP7
MDA60 AE35 MDC60 A28
FBA_D59 P29 FBC_D58
MDA61 AE34 FBA_WCK0 MDC61 C28 G14
FBA_D60 R29 FBC_D59 FBC_WCK0
MDA62 AE33 FBA_WCK0_N MDC62 C26 G15
FBA_D61 L29 FBC_D60 FBC_WCK0_N
MDA63 AB32 FBA_WCK1 MDC63 D25 G11
FBA_D62 M29 FBC_D61 FBC_WCK1
p:
AC35 FBA_WCK1_N B25 FBC_D62 G12

FBA_D63 AG29 A25 FBC_WCK1_N
FBA_WCK2 FBC_D63 G27
+FB_PLLAVDD_0 AH29 +1.5VSDGPU FBC_WCK2
FBA_WCK2_N G28
AG27 FB_DLLAVDD_0 AD29 FBC_WCK2_N
FBA_WCK3 G24
AF27 FB_PLLAVDD_0 AE29 FBC_WCK3
+FB_PLLAVDD_1 FBA_WCK3_N 2 DIS@ 1 K27 G25
FBCAL_PD_VDDQ FBC_WCK3_N
tt
J19 40.2_0402_1% DIS@ R36

FB_DLLAVDD_1 2 1
J18 T32 CLKA0 27 40.2_0402_1% R42 L27 CLKC0 29
FB_PLLAVDD_1 FBA_CLK0 FBCAL_PU_GND
T31 CLKA0# 27 DIS@ 1 FBC_CLK0 E17 CLKC0# 29
FBA_CLK0_N 2
FBA_DEBUG0 J27 FBB_DEBUG0
60.4_0402_1% R41 M27 FBC_CLK0_N D17
FB_VREF_NC FBCAL_TERM_GND
h
FBA_DEBUG1 T30 AC31 CLKA1 28 FBB_DEBUG1 CLKC1 30

FBA_DEBUG0 FBA_CLK1 CLKA1# 28 G19 D23 CLKC1# 30
T29 AC30 FBC_DEBUG0 FBC_CLK1
FBA_DEBUG1 FBA_CLK1_N G16 E23
FBB_DEBUG1 FBC_CLK1_N
N12P-GV1-A1_BGA973 DIS@ N12P-GV1-A1_BGA973

DIS@
+FB_PLLAVDD_0 +FB_PLLAVDD_1
+1.5VSDGPU DIS@ DIS@
FBA_DEBUG0 +1.05VSDGPU +1.05VSDGPU
2 1 2 1
0.1U_0402_16V4Z
100mA 100mA
10U_0805_6.3V6M
0.1U_0402_16V4Z
L25 L26
0.1U_0402_16V4Z
DIS@ 1
C55
2 1
10U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
FBB_DEBUG0
DIS@ C501
C54
DIS@ C101
60.4_0402_1% R38 1 1 BLM18PG330SN1_2P 1 BLM18PG330SN1_2P
DIS@ C583
DIS@ C582
DIS@ C584
DIS@ C578
1U_0603_10V4Z
DIS@ C505
DIS@ C504
1U_0603_10V4Z
1 1 1 1 1 1
2 DIS@ 1
DIS@
60.4_0402_1% R43
DIS@
2
FBA_DEBUG1 2 2 2
2 DIS@ 1 2 2 2 2 2 2
10K_0402_5% R34
FBB_DEBUG1
2 DIS@ 1
10K_0402_5% R478

2010/08/11 2011/08/11 Title
Issued Date Deciphered Date N12P VRAM 2/9
A

5 4 3 2 1
For GB2-128 & GB2b-128 colayout....

U27D +3VSDGPU
Part 4 of 7
2
31 VGA_TXCLK+ AM11 IFPA_TXC A2
NC_0
31 VGA_TXCLK- AM12 A7 R774
IFPA_TXC_N NC_1
31 VGA_TXOUT0+ AM8 B7 10K_0402_5%
IFPA_TXD0 NC_2
31 VGA_TXOUT0- AL8 NC_3 C5 @
IFPA_TXD0_N STRAP4
31 VGA_TXOUT1+ AM10 C7
1
D IFPA_TXD1 NC_4 STRAP4 D
31 VGA_TXOUT1- AM9 D5
IFPA_TXD1_N NC_5
31 VGA_TXOUT2+ AK10 D6
2
IFPA_TXD2 NC_6 STRAP3
31 VGA_TXOUT2- AL10 NC_7 D7
IFPA_TXD2_N R775
AK11 NC_8 E5
IFPA_TXD3 PGOOD
AL11 E7 2 R778 1 10K_0402_5%
IFPA_TXD3_N NC_9 @
F4 @
NC_10 10K_0402_5%
G5
1
NC_11
AP13 NC_12 H32
IFPB_TXC
AN13 IFPB_TXC_N J25
NC_13
AN8 IFPB_TXD4 J26
NC_14 STRAP_REF2
AP8 P6 2 R779 1
IFPB_TXD4_N NC_15 @
AP10 U7
IFPB_TXD5 NC_16 40.2K_0402_1% +3VSDGPU
AN10 V6
IFPB_TXD5_N NC_17
AR11 Y4
IFPB_TXD6 NC_18
AR10 AA4
2
IFPB_TXD6_N NC_19
AN11 IFPB_TXD7 AB4
NC_20 R776
AP11 IFPB_TXD7_N AB7
NC_21 10K_0402_5%
AC5
NC_22
NC
AD6 @
NC_23
33 VGA_HDMI_TXD2+ AM7 AF6
1
IFPC_L0 NC_24 STRAP3
33 VGA_HDMI_TXD2- AM6 AG6
/
IFPC_L0_N NC_25
33 VGA_HDMI_TXD1+ AL5 AG20
2
IFPC_L1 NC_26
33 VGA_HDMI_TXD1- AM5 AJ5
IFPC_L1_N NC_27 R777
33 VGA_HDMI_TXD0+ AM3 AK15
IFPC_L2
/x
33 VGA_HDMI_TXD0- NC_28 10K_0402_5%
AM4 AL7
IFPC_L2_N NC_29
33 VGA_HDMI_TXC+ AP1 @
IFPC_L3
33 VGA_HDMI_TXC- AR2
1
IFPC_L3_N
AR8 IFPD_L0
su
AR7 IFPD_L0_N
C AP7 IFPD_L1 C
AN7 IFPD_L1_N
AN5 IFPD_L2
AP5 IFPD_L2_N LVDS/TMDS
AR5 IFPD_L3
p.
AR4 IFPD_L3_N
AH6
IFPE_L0
AH5
IFPE_L0_N
om
AH4
IFPE_L1
AG4
IFPE_L1_N
AF4
AF5
IFPE_L2 Straps MULTI LEVEL STRAPS
IFPE_L2_N
AE6 +3VSDGPU +3VSDGPU
IFPE_L3
AE5
IFPE_L3_N
R484 1 DIS@ 2 0_0402_5%
1
D35 R485
15K_0402_1%
34.8K_0402_1%
1
1
@ R480
10K_0402_1%
1
@ R482
15K_0402_1%
15K_0402_1%
45.3K_0402_1%
R128
DIS@ R481
R125
1 DIS@ 2 0_0402_5%
R475
AL2 VDD_SENSE_0
yc
+3VSDGPU IFPF_L0 P7 R483 1 DIS@
AL3 VDD_SENSE_1 2 0_0402_5% GCORE_SEN 53
IFPF_L0_N AD20
AJ3 VDD_SENSE_2
IFPF_L1
AJ2
DIS@
@
IFPF_L1_N
@
2
1
2
AJ1
2
IFPF_L2
1
AH1 R488 1DIS@

AD19 R487 DIS@ 2 0_0402_5%
0_0402_5% FB_GND 53 STRAP0 ROM_SI
R94 IFPF_L2_N GND_SENSE_0 1 2
m
4.7K_0402_5% R89 AH2 IFPF_L3 E35 STRAP1 ROM_SO
GND_SENSE_1
DIS@ 4.7K_0402_5% AH3 IFPF_L3_N R7 R486 1 DIS@ 2 0_0402_5% STRAP2 ROM_SCLK
GND_SENSE_2
DIS@
2
20K_0402_5%
1
X76@ R453
15K_0402_1%
1
1
@ R126
10K_0402_1%
34.8K_0402_1%
DIS@ R461
33 VGA_HDMI_SCLK
24.9K_0402_1%
DIS@ R127
45.3K_0402_1%
//
R460
GS@ R459
33 VGA_HDMI_SDATA AP2
IFPC_AUX_I2CW_SCL
AN3
IFPC_AUX_I2CW_SDA_N TEST
B DIS@ B
R403 1 2 10K_0402_5%
2
@
2
JTAG_TCK
2
AP4
2
AP35 @
2
IFPD_AUX_I2CX_SCL
2
TESTMODE JTAG_TDI PAD T27
AN4 AP14 @
IFPD_AUX_I2CX_SDA_N JTAG_TCK JTAG_TDO PAD T1
AN14
p:
JTAG_TDI PAD T24 @

AN16 JTAG_TMS @
JTAG_TDO JTAG_TRST PAD T26
AE4 IFPE_AUX_I2CY_SCL AR14 @
JTAG_TMS PAD T25
AD4 IFPE_AUX_I2CY_SDA_N AP16
JTAG_TRST_N
R417 2 DIS@ 110K_0402_5%
tt
AF3 IFPF_AUX_I2CZ_SCL GV@ R459

AF2 IFPF_AUX_I2CZ_SDA_N SERIAL ROM_CS#
45K_0402_1%
R129 1 @ 2 10K_0402_5% +3VSDGPU
ROM_CS_N C3 ROM_SI
h
ROM_SI D3 ROM_SO N12P-GS strap0 strap1 strap2 ROM_SI ROM_SO ROM_SCLK

C4 ROM_SCLK
ROM_SO
D4 64MX16 H L L L L H
ROM_SCLK
Samsung 45K 35K 25K 20K 10K 15K Strap 2 for GV1,
SA000035700 Pull low 45K Ohm
+3VSDGPU GENERAL R130 2 DIS@ 1 36K_0402_1%
if unuse this pin , pull down 36k
A5 64MX16 H L L L L H
NC/SPDIF_NC
A4 R457 2 DIS@ Hynix 45K 35K 25K 15K 10K 15K
BUFRST_N 1 40.2K_0402_1%
1 @ 2 N9 SA000032400
MULTI_STRAP_REF0_GND
R463 10K_0402_5% AB5 R456 2 DIS@
STRAP0 CEC 1 40.2K_0402_1%
M9 128MX16 H L L L L H
STRAP1 W5 MULTI_STRAP_REF1_GND
STRAP0 Samsung 45K 35K 25K 45K 10K 15K
STRAP2 W7 B5
STRAP1 THERMDP
V7 B4
STRAP2 THERMDN
128MX16 H L L L L H
Hynix 45K 35K 25K 35K 10K 15K
SA00003VS10
N12P-GV1-A1_BGA973
A A
DIS@

N12P LVDS 3/9
Custom 0.1
5 4 3 2 1
5 4 3 2 1
D D
U27E
/
+1.5VSDGPU
7200mA +1.05VSDGPU
Part 5 of 7
AG11
2500mA
J23 PEX_IOVDDQ_0
/x
FBVDDQ_0
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V4Z
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6M
AG12
4.7U_0603_6.3V6M
J24
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEX_IOVDDQ_1
C70
FBVDDQ_1
C91
C58
DIS@ C103
C90
DIS@ C183
C85
1
DIS@ C108
C69
1 AG13 1 1 1
C67
C80
DIS@ C126
DIS@ C109
1 1 1 1 J29 PEX_IOVDDQ_2 1 1 1 1
FBVDDQ_2
AA27 PEX_IOVDDQ_3 AG15
FBVDDQ_3
AA29 PEX_IOVDDQ_4 AG16
FBVDDQ_4
DIS@
DIS@
DIS@
DIS@
DIS@
AG17
DIS@
AA31
DIS@
DIS@
2 2 FBVDDQ_5 PEX_IOVDDQ_5 2 2 2 2
2 2 2 2 AB27 AG18 2 2 2
FBVDDQ_6 PEX_IOVDDQ_6
Under GPU
su
AB29 PEX_IOVDDQ_7 AG22
FBVDDQ_7
C AC27 PEX_IOVDDQ_8 AG23 C
FBVDDQ_8
AD27 AG24 +1.05VSDGPU
under GPU FBVDDQ_9 PEX_IOVDDQ_9
AE27 AG25
AJ28 AG26
22U_0805_6.3V6M
1U_0402_6.3V6K
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V4Z
AJ14
0.1U_0402_16V4Z
B18
4.7U_0603_6.3V6M
0.1U_0402_16V4Z
DIS@ C62
0.1U_0402_16V4Z
C79
0.1U_0402_16V4Z
C84
C63
1
C98
p.
1U_0402_6.3V6K
C73
E21 AJ15 1 1 1
0.1U_0402_16V4Z
4.7U_0603_6.3V6M
DIS@ C116
DIS@ C104
C76
PEX_IOVDDQ_13 1 1
C64
1 1 1 FBVDDQ_13 1
C65
AJ19
C87
G17
C61
1 1 1 FBVDDQ_14 PEX_IOVDDQ_14
G18 AJ21
DIS@
DIS@
DIS@
DIS@
AJ22
DIS@
G22 2
DIS@
PEX_IOVDDQ_16 2 2 2
DIS@
FBVDDQ_16 2 2 Under GPU

DIS@
AJ24 2
DIS@
2 G8
DIS@
2 2 FBVDDQ_17 PEX_IOVDDQ_17
2
om
2 2 G9 AJ25
H29 AJ27
POWER
+1.05VSDGPU J14 AK18 DIS@ +1.05VSDGPU
220mA
under GPU J15
FBVDDQ_20
FBVDDQ_21
PEX_IOVDDQ_20
PEX_IOVDDQ_21 AK20
2 1
BLM18PG181SN1D_0603 +IFPAB_PLLVDD J16 AK23
4.7U_0603_6.3V6M
FBVDDQ_22 PEX_IOVDDQ_22 L6
0.1U_0402_16V4Z
2 1 J17 AK26
1U_0402_6.3V6K
DIS@ C179
FBVDDQ_23 PEX_IOVDDQ_23 FBMA-L10-160808-121LMT_2P
DIS@ C120
DISO@L4
DISO@L4 J20 AL16 1 1
DIS@ C115
C173 C174 FBVDDQ_24 PEX_IOVDDQ_24 1
C149 J21
0.1U_0402_16V4Z
4.7U_0603_6.3V6M
FBVDDQ_25
4.7U_0603_6.3V6M
1 1
yc
1U_0402_6.3V6K
1 J22
1
1 FBVDDQ_26
R103
N27
FBVDDQ_27
2500 mA 2 2
C175 P27 AK16 2
DISO@
DISO@
DISO@ 10K_0402_5% FBVDDQ_28 PEX_IOVDD_0

DISO@
2 2 2 R27 AK17
2 OPT@ FBVDDQ_29 PEX_IOVDD_1
T27 AK21 NV recommand 0720
FBVDDQ_30 PEX_IOVDD_2
U27 AK24
2
FBVDDQ_31 PEX_IOVDD_3 Under GPU
m
U29 AK27 +3VSDGPU
FBVDDQ_32 PEX_IOVDD_4
V27 FBVDDQ_33
V29 FBVDDQ_34
V34 +PEX_PLLVDD 120mA
1U_0402_6.3V6K
2 @
4.7U_0603_6.3V6M
1
0.1U_0402_16V4Z
FBVDDQ_35
W27 AG14
C99
R82
DIS@ C148
DIS@ C147
FBVDDQ_36 PEX_PLLVDD 1
+1.8VSDGPU
300 mA
// Y27 FBVDDQ_37
1 1
0_0603_5% +1.05VSDGPU
DISO@ +IFPAB_IOVDD +IFPAB_PLLVDD +PEX_SVDD_3V3 120mA 2 DIS@ 1
DIS@
B 2 1 AK9 AG19 2 2 R98
B
L7 IFPAB_PLLVDD PEX_SVDD_3V3 2
1K_0402_1% 2 DIS@ 1 R71 F7
0.1U_0402_16V4Z
0_0603_5%
0.1U_0402_16V4Z
1 C177 1 C178 AJ11

1U_0402_6.3V6K
BLM18PG181SN1D_0603 1 C150 IFPAB_RSET PEX_SVDD_3V3_NC

4.7U_0603_6.3V6M
1
1
+IFPAB_IOVDD
p:
AG9 +VDD33 120mA

DISO@
DISO@
C182 R114
DISO@
IFPA_IOVDD
DISO@ 2 2 2 10K_0402_5% AG10 J10 Under GPU
IFPB_IOVDD VDD33_0 +3VSDGPU
2 OPT@ J11
+IFPC_PLLVDD VDD33_1
J12
VDD33_2 2 DIS@ 1
2
AJ9 J13
1U_0402_6.3V6K
1K_0402_1% 2 DIS@ 1 R76
0.1U_0402_16V4Z
tt
0.1U_0402_16V4Z
IFPC_PLLVDD VDD33_3
0.1U_0402_16V4Z
DIS@ C141
R63
DIS@ C122
AK7 J9
DIS@ C118
4.7U_0603_6.3V6M
+IFPC_IOVDD IFPC_RSET VDD33_4 1 1 1
DIS@ C134
0_0603_5%
DIS@ C137
1 1
AJ8 IFPC_IOVDD
+3VSDGPU
h
+IFPC_PLLVDD P9 2 2 2
AC6 MIOA_VDDQ_NC_0 2
440 mA Under GPU R9 2
C143
0.1U_0402_16V4Z
+3VSDGPU IFPD_PLLVDD MIOA_VDDQ_NC_1
1K_0402_1% 2 DIS@ 1+IFPC_IOVDD
R464 AB6 T9
IFPD_RSET MIOA_VDDQ_NC_2 1
MIOA_VDDQ_NC_3 U9+3VSDGPU
+IFPC_PLLVDD AK8
DISO@ IFPD_IOVDD Under GPU
DIS@
2 1
C158
0.1U_0402_16V4Z
C153
1U_0402_6.3V6K
L8 AA9 2
C185
10K_0402_5%2 DIS@ 1 R468

0.1U_0402_16V4Z
AJ6 MIOB_VDDQ_NC_0
C188
4.7U_0603_6.3V6M
BLM18PG181SN1D_0603 1 1K_0402_1% 2 DIS@ 1 R469 AB9

C181
1
0.1U_0402_16V4Z
IFPEF_PLLVDD MIOB_VDDQ_NC_1
1 AL1 W9
C142
1
0.1U_0402_16V4Z
1 IFPEF_RSET MIOB_VDDQ_NC_2
MIOB_VDDQ_NC_3 Y9
1
DISO@
AE7 1
DISO@
10K_0402_5%1 DIS@ 2 R68 IFPE_IOVDD

DISO@
2 2 AD7
DISO@
2 R131 IFPF_IOVDD
DISO@
2 2 10K_0402_5%
DIS@
OPT@ 2
2
N12P-GV1-A1_BGA973
Under GPU
A DIS@ A
+1.05VSDGPU
DISO@ 570 mA
2 1 +IFPC_IOVDD
L3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DISO@ C155
BLM18PG181SN1D_0603 1
1U_0402_6.3V6K
DISO@ C156
4.7U_0603_6.3V6M
1
DISO@ C157
1 1 Security Classification Compal Secret Data Compal Electronics, Inc.

DISO@ C159
2 2010/08/11 2011/08/11 Title

2 R77 Issued Date Deciphered Date
2 2 10K_0402_5%
OPT@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12P POWER & GND 4/9
Custom P5WE0 M/B LA-6901P Schematic 0.1
2
Under GPU DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5 4 3 2 1
5 4 3 2 1
D U27F D
B3 Part 6 of 7
GND_0
B6 V18
GND_1 GND_97
B9 V20
GND_2 GND_98
B12 V22
GND_3 GND_99
B15 GND_4 V24
B21 GND_100 +VGA_CORE
GND_5 GND_101 V31 +VGA_CORE
B24
B27
GND_6 GND_102 Y11 Under GPU
GND_7 Y13 U27G
GND_103
B30
GND_8 GND_104 Y15 41020mA
B33 GND_9 Y17 AB11 VDD_0 P21
GND_105
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
VDD_56
0.01U_0402_16V7K
0.01U_0402_16V7K
C2
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
GND_10 GND_106 Y19 AB13 VDD_1 Part 7 of 7 P23
DIS@ C121
C72
DIS@ C107
VDD_57
C94
C83
C88
DIS@ C114
DIS@ C110
C34 Y21 1 1 1 1 1 1 AB15 VDD_2 P25
GND_11 GND_107 1 1 VDD_58
E6 GND_12 Y23 AB17 VDD_3 R11
E9 GND_108 VDD_59
GND_13 Y25 AB19 VDD_4 R12
GND_109
DIS@
E12 VDD_60
DIS@
DIS@
DIS@
GND_14 AA2 2 2 2 AB21 VDD_5 R13
E15 GND_110 2 2 2 2 2 VDD_61
GND_15 AA5 AB23 VDD_6 R14
E18 GND_111 VDD_62
GND_16 AA11 AB25 R15
E24 GND_112 VDD_7 VDD_63
GND_17 GND_113 AA12 AC11 VDD_8 R16
E27 AA13 AC12 VDD_9 VDD_64
GND_18
/
GND_114 VDD_65 R17
E30 GND_19 AA14 AC13 VDD_10
GND_115 VDD_66 R18
F2 AA15 AC14 VDD_11
GND_20 GND_116 R19
0.047U_0402_16V7K
0.022U_0402_16V7K
0.022U_0402_16V7K
0.1U_0402_16V4Z
F31 VDD_67
0.022U_0402_16V7K
0.047U_0402_16V7K
0.047U_0402_16V7K
AA16
0.1U_0402_16V4Z
GND_21 GND_117 AC15 VDD_12 R20
C96
DIS@C112
C78
DIS@ C95
/x
F34 VDD_68
C97
C74
C77
1 1
DIS@ C130
GND_22 AA17 1 1 1 1 1 AC16 VDD_13
GND_118 1 R21
F5 GND_23 AA18 AC17 VDD_14 VDD_69
J2 GND_119 VDD_70 R22
GND_24 GND_120 AA19 AC18 VDD_15 R23
DIS@
DIS@
J5 VDD_71
DIS@
DIS@
DIS@
GND_25 GND_121 AA20 2 2 2 2 AC19 VDD_16 R24
J31 AA21 2 2 2 2 VDD_72
GND_26 GND_122 AC20 VDD_17 R25
J34 GND_27 AA22 VDD_73
GND_123 AC21 VDD_18 T12
K9 VDD_74
su
GND_28 AA23 AC22 VDD_19
L9 GND_124 T14
C GND_29 AA24 AC23 VDD_20 VDD_75 C
M2 GND_125 T16
AA25 VDD_76
POWER
GND_30 GND_126 AC24 VDD_21 T18
M5 AA34 VDD_77
GND_31 GND_127 AC25 VDD_22 T20
M11 GND_32 AB12 VDD_78
GND_128 AD12 VDD_23 T22
GND_129 AD14 VDD_24
0.22U_0603_16V7K
0.22U_0603_16V7K
M15 T24
0.22U_0603_16V7K
AB16 VDD_80
p.
GND_34
1U_0603_10V4Z
AD16 VDD_25 V11
DIS@ C131
GND_130
DIS@ C133
M17 1 1 VDD_81
DIS@ C123
GND_35 AB18
DIS@ C139
GND_131 1 1 AD18 VDD_26 V13
M21 GND_132 AD22 VDD_27 V15
GND_37 AB22 VDD_83
M23 GND_133 AD24 VDD_28 V17
GND_38 AB24 2 2 VDD_84
M25 GND_134 2 L11 VDD_29 V19
AC9 VDD_85
om
GND_39 GND_135 2 L12 VDD_30 V21
M31 GND_40 AD2 VDD_86
M34 GND_136 L13 VDD_31 V23
GND_41 AD5 VDD_87
GND_137 L14 VDD_32 V25
GND
N11 GND_42 AD11 VDD_88

N12 GND_138
AD13 Put Under GPU L15 VDD_33
VDD_89
W11
GND_43 GND_139 L16 VDD_34 W12
N14 GND_140 L17 VDD_35 W13
GND_45 AD17 VDD_91
N15 GND_141 L18 VDD_36 W14
GND_46 AD21 VDD_92
N16 GND_142 L19 VDD_37 W15
AD23 +VGA_CORE VDD_93
yc
GND_47 GND_143 L20 VDD_38 W16
N17 AD25 VDD_94
GND_48 GND_144 L21 VDD_39 W17
N19 GND_145 L22 VDD_40 W18
AD34 VDD_96
330U_D2E_2.5VM_R6M
GND_50 GND_146 L23 VDD_41 W19
N20
330U_D2E_2.5VM_R6M
AE11 VDD_97
10U_0603_6.3V6M
GND_51
10U_0603_6.3V6M
N21 GND_147 1 L24 VDD_42 W20
4.7U_0805_10V4Z
AE12 VDD_98
DIS@ C594
DIS@ C604
GND_52
DIS@ C595
22U_0805_6.3V6M
N22 GND_148 1 1 1 L25 VDD_43 W21
C1
DIS@ C592
47U_0805_4V6
m
DIS@ C593
GND_53 AE13 + 1 VDD_99
DIS@ C591
N23 GND_149 + 1 1 M12 VDD_44 W22
GND_54 GND_150 AE14 VDD_100
N24 M14 VDD_45 W23
GND_55 GND_151 AE15 VDD_101
N25 M16 VDD_46 W24
DIS@
GND_56 AE16 2 2 2 VDD_102
P12 GND_152 2 2 2 M18 VDD_47 W25
GND_57 GND_153 AE17 2 VDD_103
P14 M20 VDD_48 Y12
P16
GND_58
GND_59
GND_154
GND_155
AE18
AE19
// M22 VDD_49
M24 VDD_50
VDD_104
VDD_105 Y14
Y16
P18 AE20 VDD_106
GND_60 GND_156 P11 VDD_51
B P20 AE21 VDD_107 Y18 B
P22 AE22 VDD_108 Y20
P24 AE23 VDD_109 Y22
R2 AE24 VDD_110 Y24
GND_64
p:
R5 GND_160 P19 VDD_55

GND_65 AE25
R31 GND_161
GND_66 AG2
R34 GND_162
GND_67 AG5
T11 GND_163
GND_68 AG31
T13 GND_164
GND_69 AG34
GND_165
tt
T15 GND_70 AK2

GND_166 N12P-GV1-A1_BGA973
T17 GND_71 AK5
T19 GND_167
GND_72 GND_168 AK14
T21 AK31 DIS@
GND_73 GND_169
T23
h
GND_74 GND_170 AK34

T25 AL6
GND_75 GND_171
U11 AL9
GND_76 GND_172
U12 AL12
GND_77 GND_173
U13 AL15
GND_78 GND_174
U14 AL18
GND_79 GND_175
U15 AL21
GND_80 GND_176
U16 AL24
GND_81 GND_177
U17 AL27
GND_82 GND_178
U18 AL30
GND_83 GND_179
U19 AN2
GND_84 GND_180
U20 AN34
GND_85 GND_181
U21 AP3
GND_86 GND_182
U22 GND_87 AP6
U23 GND_183
GND_88 AP9
U24 GND_184
GND_89 AP12
U25 GND_185
GND_90 AP15
GND_186
V2 GND_91 AP18
GND_187
V5 AP21
A GND_92 GND_188 A
V9 AP24
GND_93 GND_189
V12 GND_94 AP27
GND_190
V14 GND_95 AP30
GND_191
V16 AP33
GND_96 GND_192
N12P-GV1-A1_BGA973 Security Classification Compal Secret Data Compal Electronics, Inc.

DIS@
N12P POWER & GND 5/9
5 4 3 2 1
5 4 3 2 1
VRAM DDR3 chips (1GB) Mode D

Address 0..31 32..63
CMD0 CS0_L#
D
64Mx16 DDR3 *8==>1GB CMD1 D
CMD2 ODT_L
CMD3 CKE
CMD4 A14 A14
DQSA[7..0] CMD5 RST RST
23,28 DQSA[7..0]
U23 X76@ U4 X76@
DQSA#[7..0]
23,28 DQSA#[7..0] +MEM_VREF1
CMD6 A9 A9
+MEM_VREF0 MDA18 E3 MDA3
DQMA[7..0] M8 E3 M8 DQL0
VREFCA DQL0 MDA19 VREFCA MDA4 CMD7 A7 A7
23,28 DQMA[7..0] H1 F7 H1 F7
VREFDQ DQL1 MDA23 VREFDQ DQL1 MDA2
MDA[63..0] F2 F2
CMDA9 DQL2 MDA17 CMDA9 DQL2 MDA7 CMD8 A2 A2
23,28 MDA[63..0] N3 F8 N3 A0 DQL3 F8
CMDA11 A0 DQL3 MDA21 Group2 CMDA11 MDA0 Group0
CMDA[30..0] P7 H3 P7 A1 DQL4 H3
CMDA8 A1 DQL4 MDA16 CMDA8 MDA5 CMD9 A0 A0
23,28 CMDA[30..0] P3 H8 P3 A2 H8
CMDA25 A2 DQL5 MDA20 CMDA25 DQL5 MDA1
N2 G2 N2 A3 G2
CMDA10 A3 DQL6 MDA22 CMDA10 DQL6 MDA6 CMD10 A4 A4
P8 H7 P8 A4 H7
CMDA24 A4 DQL7 CMDA24 DQL7
P2 P2 A5
CMDA22 A5 CMDA22 CMD11 A1 A1
R8 A6
/
+1.5VSDGPU CMDA7 R8 MDA12 CMDA7 MDA29
A6 R2 A7 D7
CMDA21 R2 D7 MDA11 CMDA21 DQU0 MDA26
CMDA6 T8
A7 DQU0
C3 T8 A8 C3 CMD12 BA0 BA0
A8 DQU1 MDA14 CMDA6 DQU1 MDA31
R3 C8 R3 A9 C8
/x
CMDA29 A9 DQU2 MDA8 CMDA29 DQU2 MDA28 CMD13 WE* WE*
CMDA23 L7 C2 L7 A10/AP C2
DIS@ A10/AP DQU3 MDA13 Group1 CMDA23 DQU3 MDA27 Group3
CMDA28 R7 A7 CMDA28 R7 A11 A7
R391 A11 DQU4 MDA10 DQU4 MDA25 CMD14 A15 A15
CMDA20 N7 A2 MDA15 CMDA20 N7 A12 A2 MDA30
240_0402_1% A12 DQU5 DQU5
CMDA4 T3 B8 MDA9 CMDA4 T3 A13 DQU6 B8 MDA24
CMDA14 T7
A13 DQU6
A3 CMDA14 T7 A14 A3 CMD15 CAS* CAS*
A14 DQU7 DQU7
+MEM_VREF0 M7 +1.5VSDGPU M7 A15/BA3 +1.5VSDGPU CMD16 CS0_H#
su
A15/BA3
C CMDA12 C
CMDA12 CMD17
0.1U_0402_10V6K
DIS@
1 CMDA27 M2 B2 CMDA27 M2 BA0 B2

BA0 VDD VDD
DIS@ CMDA26 N8 D9 CMDA26 N8 BA1 D9
BA1 VDD VDD CMD18 ODT_H
R392 M3 G7 M3 BA2 G7
BA2 VDD VDD
240_0402_1% 2 K2 K2
VDD
C495
CMD19 CKE_H
p.
VDD K8
K8 VDD
CLKA0 VDD CLKA0 N1
N1 VDD CMD20 A13 A13
CLKA0# J7 VDD CLKA0# J7 N9
CK N9 CK VDD
CMDA3 K7 VDD CMDA3 K7 R1
CK R1 CK VDD CMD21 A8 A8
K9 VDD +1.5VSDGPU K9
CKE/CKE0 R9 +1.5VSDGPU
CKE/CKE0 R9 VDD
om
VDD
CMDA2 CMDA2
CMD22 A6 A6
+1.5VSDGPU
CMDA0 K1 VDDQ
A1 CMDA0 K1 ODT/ODT0 VDDQ A1 CMD23 A11 A11
ODT/ODT0 L2 CS/CS0
CMDA30 L2
CS/CS0 VDDQ
A8 CMDA30 VDDQ A8
J3 RAS
CMDA15 J3 RAS VDDQ
C1 CMDA15
K3 CAS VDDQ C1 CMD24 A5 A5
DIS@ CMDA13 K3 CAS VDDQ
C9 CMDA13
L3 WE VDDQ C9
R23 L3 WE 310mA VDDQ D2 VDDQ D2 CMD25 A3 A3
240_0402_1% VDDQ
E9 310mA VDDQ E9
yc
DQSA2
VDDQ F1 DQSA0 VDDQ F1 CMD26 BA2 BA2
DQSA1 DQSA3 F3
F3
DQSL VDDQ H2 DQSL VDDQ H2
C7
+MEM_VREF1 C7 DQSU VDDQ
H9 DQSU VDDQ H9 CMD27 BA1 BA1
DQMA2 DQMA0
CMD28 A12 A12
0.1U_0402_10V6K
DIS@
1
DIS@
DQMA1 E7 A9 DQMA3 E7
DML VSS A9
m
DML VSS
R25 D3 VSS B3 D3
DMU VSS B3 CMD29 A10 A10
DMU
240_0402_1% E1 VSS E1
DQSA#2 VSS DQSA#0
2 VSS G8 CMD30 RAS* RAS*
C25
G8
DQSA#1 VSS DQSA#3 G3
G3 DQSL J2 B7 DQSL VSS J2
VSS
B7 J8 DQSU VSS J8
DQSU VSS
VSS
//
M1 VSS M1
Not Available
CMDA5 M9 CMDA5 VSS M9 LOW HIGH

VSS
B P1 T2 VSS P1 B
VSS
ZQ0
T2 RESET P9 ZQ1
RESET VSS P9
VSS
T1 L8 VSS T1
VSS
CLKA0
L8
ZQ/ZQ0 T9 ZQ/ZQ0 VSS T9
p:
1
1
VSS
23 CLKA0 1 2 CMDA2
R12 DIS@ DIS@ CMDA3 R397 1 DIS@ 2 10K_0402_5% Command Bit Default Pull-down
J1 B1
1
@ R395 J1 B1 R390 NC/ODT1 VSSQ CMDA5 R398 1 DIS@ 2 10K_0402_5%

NC/ODT1 VSSQ L1 B9 DIS@
DIS@ 80.6_0402_1% 243_0402_1% L1 B9 243_0402_1% NC/CS1 VSSQ CMDA18 ODTx 10k
NC/CS1 VSSQ J9 VSSQ D1 R401R399 10K_0402_5%
R15 J9 D1 NC/CE1 CMDA19 1 1 2 2 10K_0402_5%
NC/CE1 VSSQ
2
2
L9 D8 CKEx 10k
tt
160_0402_1% L9 D8 NCZQ1 VSSQ R400 1 DIS@DIS@2 10K_0402_5% DDR3

NCZQ1 VSSQ E2
E2 VSSQ RST 10k
CLKA0# VSSQ E8
2
23 CLKA0# E8 VSSQ
VSSQ F9 CS* No Termination
1 2 F9 VSSQ
VSSQ G1
h
R11 1 G1 VSSQ
@ VSSQ VSSQ G9
@ G9
C4 VSSQ
80.6_0402_1% 96-BALL
0.01U_0402_16V7K 96-BALL SDRAM DDR3
2 SDRAM DDR3 K4B1G1646E-HC12_FBGA96
NV recommand 0720 K4B1G1646E-HC12_FBGA96
+1.5VSDGPU +1.5VSDGPU
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
1U_0603_10V6K
1U_0603_10V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0603_10V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0603_10V6K
1U_0603_10V6K
1U_0603_10V6K
0.1U_0402_16V4Z
1U_0603_10V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0603_10V6K
DIS@ C493
0.1U_0402_16V4Z
DIS@ C508
DIS@ C502
C31
DIS@ C488
AMD :SA00003PF10
DIS@ C506
C18
DIS@ C512
DIS@ C511
1 1 1
0.1U_0402_16V4Z
1 1 1 1 1 1
C33
C27
C35
C19
C22
DIS@ C487
DIS@ C486
C34
C21
1 1 1 1 1 1 1 1 1
DIS@ C497
1 (S IC D3 64M16/800 23EY2387MB-12 PG-TFBGA 96P 1.5V)

DIS@
DIS@
DIS@
2
DIS@
DIS@
2
DIS@
DIS@
DIS@
2
DIS@
2 2 2
2 2 2 2 2 2 2 2 2
2
A A

N12P DDR3 6/9
Custom 0.1
5 4 3 2 1
VRAM DDR3 chips (1GB) Mode D

Address 0..31 32..63
64Mx16 DDR3 *8==>1GB CMD0 CS0_L#
CMD1
D D
CMD2 ODT_L
U3 X76@ U24 X76@
CMD3 CKE
+MEM_VREF2 MDA39 +MEM_VREF3 M8 E3 MDA58
M8 E3 VREFCA DQL0
VREFCA DQL0 MDA35 F7 MDA59 CMD4 A14 A14
H1 F7 H1 DQL1
DQMA[7..0] VREFDQ DQL1 MDA37 VREFDQ MDA56
23,27 DQMA[7..0] F2 F2
CMDA9 DQL2 MDA33 CMDA9 DQL2 MDA63
CMDA[30..0] CMDA11 N3 DQL3
F8 N3 A0 DQL3 F8 CMD5 RST RST
A0 MDA38 Group4 CMDA11 P7 H3 MDA57 Group7
23,27 CMDA[30..0] P7 H3 A1 DQL4
CMDA8 A1 DQL4 MDA32 CMDA8 P3 H8 MDA61 CMD6 A9 A9
DQSA#[7..0] P3 H8 A2 DQL5
CMDA25 A2 DQL5 MDA36 CMDA25 N2 G2 MDA60
23,27 DQSA#[7..0] CMDA10 N2 G2 A3 DQL6
A3 DQL6 MDA34 CMDA10 P8 H7 MDA62 CMD7 A7 A7
DQSA[7..0] CMDA24 P8 H7 CMDA24 A4 DQL7
A4 DQL7 P2
23,27 DQSA[7..0] CMDA22 P2 A5
A5 CMDA22 R8 CMD8 A2 A2
MDA[63..0] CMDA7 R8 A6 CMDA7 A6
MDA42 R2 D7 MDA49
23,27 MDA[63..0] CMDA21 R2 A7 D7 CMDA21 A7 DQU0
DQU0 MDA45 T8 C3 MDA53 CMD9 A0 A0
CMDA6 T8 A8 C3 CMDA6 A8 DQU1
DQU1 MDA40 R3 C8 MDA51
CMDA29 R3 A9 C8 MDA44 CMDA29 A9 DQU2 MDA55
DQU2 L7 C2 CMD10 A4 A4
CMDA23 L7 A10/AP C2 CMDA23 A10/AP DQU3
DQU3 MDA41 Group5 R7 MDA48 Group6
CMDA28 R7 A7 A11 A7
A11 DQU4 MDA47 CMDA28 DQU4 MDA54 CMD11 A1 A1
CMDA20 N7 A2 N7 A2
+1.5VSDGPU A12 DQU5 MDA43 CMDA20 A12 DQU5 MDA50
CMDA4 T3 B8 CMDA4 T3 B8
A13 DQU6 MDA46 A13 DQU6 MDA52 CMD12 BA0 BA0
T7 A3
/
CMDA14 T7 A3 CMDA14 A14 DQU7
A14 DQU7 M7
M7 +1.5VSDGPU A15/BA3 +1.5VSDGPU
DIS@
A15/BA3 CMD13 WE* WE*
R21 CMDA12
/x
CMDA12 CMD14 A15 A15
240_0402_1% M2 B2 M2 BA0 B2
CMDA27 BA0 VDD CMDA27 VDD
CMDA26 N8 D9 N8 BA1 D9
BA1 VDD CMDA26 VDD CMD15 CAS* CAS*
M3 G7 M3 BA2 VDD G7
BA2 VDD K2
+MEM_VREF2 K2 VDD
VDD
K8 K8 CMD16 CS0_H#
VDD VDD
CLKA1 N1 CLKA1 N1
VDD CMD17
su
VDD J7 N9
0.1U_0402_10V6K
DIS@
DIS@ 1 CLKA1# J7 CK N9 CLKA1# CK VDD

C K7 VDD K7 R1 C
R22 CMDA19 CK R1 CMDA19 CK VDD
240_0402_1% K9 VDD
R9 +1.5VSDGPU
K9
CKE/CKE0 R9 +1.5VSDGPU
CMD18 ODT_H
CKE/CKE0 VDD VDD
2 CMD19 CKE_H
C23
CMDA18 CMDA18
CMDA16 K1 A1 CMDA16 K1 ODT/ODT0 A1
ODT/ODT0 VDDQ VDDQ CMD20 A13 A13
p.
CMDA30 L2 A8 L2 CS/CS0 A8
CS/CS0 VDDQ CMDA30 VDDQ
CMDA15 J3 C1 J3 RAS C1
RAS VDDQ CMDA15 VDDQ CMD21 A8 A8
CMDA13 K3 C9 K3 CAS C9
CAS VDDQ CMDA13 VDDQ
L3 L3 WE D2
WE D2 VDDQ CMD22 A6 A6
+1.5VSDGPU
310mA VDDQ E9 310mA VDDQ E9
VDDQ
om
DQSA4 F1 DQSA7 VDDQ F1
DQSA5 F3
VDDQ
H2 DQSA6 F3 H2 CMD23 A11 A11
DQSL VDDQ DQSL VDDQ
C7 H9 C7 H9
DIS@ DQSU VDDQ DQSU VDDQ CMD24 A5 A5
R393
240_0402_1% DQMA4 DQMA7 CMD25 A3 A3
DQMA5 E7
DML VSS A9 DQMA6 E7
DML VSS A9
D3
DMU VSS B3 D3
DMU VSS B3 CMD26 BA2 BA2
VSS E1 VSS E1
yc
+MEM_VREF3 DQSA#4
VSS
G8 DQSA#7 VSS G8 CMD27 BA1 BA1
G3
DQSA#5 G3 DQSL VSS
J2 DQSA#6
B7 DQSL VSS J2
B7 J8 DQSU VSS J8 CMD28 A12 A12
0.1U_0402_10V6K
DIS@
1 DQSU VSS
DIS@
VSS
M1 VSS M1
R396
VSS
M9 VSS M9 CMD29 A10 A10
CMDA5
VSS P1
240_0402_1% CMDA5 P1
m
VSS T2
2 T2 RESET VSS P9
C503
ZQ2 RESET VSS

P9
ZQ3 CMD30 RAS* RAS*
VSS
T1
L8 VSS T1
L8
ZQ/ZQ0 VSS
T9 ZQ/ZQ0 VSS T9 Not Available
1
1
DIS@
DIS@ LOW HIGH
R24 J1
L1
NC/ODT1 VSSQ
// B1
B9
R389
243_0402_1%
J1
L1
NC/ODT1
NC/CS1
VSSQ
VSSQ
B1
B9
243_0402_1% NC/CS1 VSSQ J9 D1
CLKA1 J9 D1 NC/CE1 VSSQ
B 23 CLKA1 1 2 NC/CE1 VSSQ D8 B
L9
2
R10 L9 D8 VSSQ
2
NCZQ1 VSSQ NCZQ1 E2
1
@ E2 VSSQ
VSSQ E8
DIS@ 80.6_0402_1% VSSQ E8 VSSQ
F9
p:
R14 VSSQ F9 VSSQ

G1 VSSQ G1
160_0402_1% VSSQ
G9 VSSQ G9
VSSQ
2
CLKA1#
23 CLKA1# 96-BALL
96-BALL
1 2 SDRAM DDR3
SDRAM DDR3
tt
R9 K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
@ 1
80.6_0402_1% @
C3
0.01U_0402_16V7K
h
NV recommand 0720 2
+1.5VSDGPU +1.5VSDGPU
0.1U_0402_16V4Z
1U_0603_10V6K
C30
C26
0.1U_0402_16V4Z
1U_0603_10V6K
1U_0603_10V6K
0.1U_0402_16V4Z
C28
C17
C14
0.1U_0402_16V4Z
1U_0603_10V6K
0.1U_0402_16V4Z
C16
0.1U_0402_16V4Z
1U_0603_10V6K
1U_0603_10V6K
C15
C24
0.1U_0402_16V4Z
DIS@ C492
DIS@ C494
DIS@ C509
DIS@ C510
1U_0603_10V6K
C20
1U_0603_10V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C32
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 2
DIS@ C490
1 1 1
DIS@ C507
DIS@ C491
DIS@ C489
DIS@ C496
1 1 1 1 1 1
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2 2 2 2 2 2 2 2 2 1
DIS@
DIS@
2 2 2
2 2 2 2 2 2
A A

N12P DDR3 7/9
Custom 0.1
5 4 3 2 1
Mode D
Address 0..31 32..63
VRAM DDR3 chips (1GB) CMD0 CS0_L#
CMD1
64Mx16 DDR3 *8==>1GB CMD2 ODT_L
D D
CMD3 CKE
CMD4 A14 A14
DQSC[7..0]
CMD5 RST RST
23,30 DQSC[7..0]
DQSC#[7..0]
CMD6 A9 A9
23,30 DQSC#[7..0] U28 X76@ U6 X76@
DQMC[7..0] +MEM_VREF5
CMD7 A7 A7
+MEM_VREF4 E3 MDC22 MDC3
23,30 DQMC[7..0] M8 DQL0 M8 E3
VREFCA MDC16 VREFCA DQL0 MDC7 CMD8 A2 A2
H1 F7 H1 F7
MDC[63..0] VREFDQ DQL1 MDC18 VREFDQ DQL1 MDC1
23,30 MDC[63..0] F2 F2
CMDC9 DQL2 MDC19 CMDC9 DQL2 MDC4
CMDC[30..0] N3 A0 DQL3
F8 N3 F8 CMD9 A0 A0
CMDC11 H3 MDC23 Group2 CMDC11 A0 DQL3 MDC2 Group0
23,30 CMDC[30..0] P7 A1 DQL4 P7 H3
CMDC8 P3 H8 MDC17 CMDC8 A1 DQL4 MDC6 CMD10 A4 A4
CMDC25 A2 DQL5 MDC20 P3 H8
N2 G2 CMDC25 A2 DQL5 MDC0
CMDC10 A3 DQL6 MDC21 N2 G2
P8 H7 CMDC10 A3 DQL6 MDC5 CMD11 A1 A1
CMDC24 A4 DQL7 P8 H7
P2 CMDC24 A4 DQL7
CMDC22 A5 CMDC22 P2
R8 A5 CMD12 BA0 BA0
CMDC7 A6 MDC13 CMDC7 R8 A6
+1.5VSDGPU R2 D7 MDC28
CMDC21 A7 DQU0 MDC10 CMDC21 R2 A7 D7
T8 C3 DQU0 MDC24 CMD13 WE* WE*
T8
/
CMDC6 A8 DQU1 MDC14 CMDC6 A8 DQU1 C3 MDC31
R3 A9 C8 R3 C8
CMDC29 DQU2 MDC9 CMDC29 A9 DQU2 MDC25 CMD14 A15 A15
L7 A10/AP C2 L7 C2
CMDC23 DQU3 MDC12 Group1 CMDC23 A10/AP DQU3 MDC29 Group3
DIS@ R7 A11 A7 R7 A7
/x
CMDC28 DQU4 MDC8 CMDC28 A11 DQU4 MDC27 CMD15 CAS* CAS*
R435 CMDC20 N7 A12 A2 MDC15 N7 A2
DQU5 CMDC20 A12 DQU5 MDC30
240_0402_1% CMDC4 T3 B8 MDC11 CMDC4 T3 B8
A13 DQU6 A13 DQU6 MDC26 CMD16 CS0_H#
CMDC14 T7 DQU7 A3 T7 A3
A14 CMDC14 A14 DQU7
+MEM_VREF4 M7 +1.5VSDGPU M7 +1.5VSDGPU
A15/BA3 A15/BA3 CMD17
CMDC12 CMDC12
0.1U_0402_10V6K
DIS@
CMD18 ODT_H
su
1 M2 BA0 B2 M2 BA0 B2
CMDC27 VDD CMDC27 VDD
C DIS@ N8 BA1 D9 N8 BA1 D9 C
CMDC26 VDD CMDC26 VDD CMD19 CKE_H
R436 M3 G7 M3 BA2 G7
BA2 VDD VDD
240_0402_1% 2 VDD K2 K2
C570
K8 VDD
K8
CMD20 A13 A13
VDD VDD
CLKC0 N1 CLKC0 N1
J7 VDD VDD CMD21 A8 A8
p.
CLKC0# CK VDD N9 CLKC0# J7 N9
K7 CK VDD
CMDC3 CK VDD R1 CMDC3 K7 R1
K9 CKE/CKE0 R9 +1.5VSDGPU K9
CK VDD
R9 +1.5VSDGPU
CMD22 A6 A6
VDD CKE/CKE0 VDD
CMDC2 CMDC2
CMD23 A11 A11
om
K1 A1
CMDC0
L2 ODT/ODT0 VDDQ
A8
CMDC0 K1
ODT/ODT0 VDDQ A1 CMD24 A5 A5
L2
CMDC30
J3
CS/CS0 VDDQ
C1
CMDC30 CS/CS0 VDDQ A8
J3
CMDC15
K3
RAS VDDQ
C9
CMDC15 RAS VDDQ C1 CMD25 A3 A3
K3
+1.5VSDGPU CMDC13
L3
CAS VDDQ
D2
CMDC13
L3
CAS VDDQ C9
WE VDDQ
310mAVDDQ E9 WE VDDQ D2 CMD26 BA2 BA2
DQSC2 F1 DQSC0 310mA VDDQ E9
DQSC1 F3
VDDQ
H2 DQSC3 VDDQ F1 CMD27 BA1 BA1
F3
C7
DQSL VDDQ DQSL VDDQ H2
yc
H9 C7
DIS@ DQSU VDDQ DQSU VDDQ H9 CMD28 A12 A12
R86
240_0402_1% DQMC2 DQMC0
DQMC1 E7 A9 DQMC3 E7 A9
CMD29 A10 A10
DML VSS DML VSS
+MEM_VREF5 D3 VSS B3 D3 B3
DMU DMU VSS CMD30 RAS* RAS*
VSS E1 E1
VSS
m
DQSC#2 G8 DQSC#0 G8
VSS VSS Not Available
DQSC#1 G3 J2 DQSC#3 G3
0.1U_0402_10V6K
DIS@
1 B7 DQSL VSS DQSL VSS J2

DQSU J8 B7 J8
DIS@ VSS DQSU VSS LOW HIGH
M1 M1
R85 VSS VSS
M9 M9
240_0402_1% VSS
2 CMDC5 P1
// CMDC5 VSS
C165
T2 VSS VSS P1
RESET P9 T2 P9
VSS RESET VSS
ZQ4 T1 ZQ5 T1
B L8 VSS VSS B
ZQ/ZQ0 VSS T9 L8 T9
ZQ/ZQ0 VSS
1
1
J1 B1 CMDC2 Command Bit Default Pull-down

p:
DIS@ NC/ODT1 VSSQ DIS@ J1 NC/ODT1 B1

L1 B9 VSSQ CMDC3
R437 NC/CS1 VSSQ R50 L1 NC/CS1 B9 R416 1 DIS@
R415 1 DIS@2 10K_0402_5%
2 10K_0402_5% ODTx 10k
J9 D1 VSSQ CMDC5
243_0402_1% NC/CE1 VSSQ 243_0402_1% J9 VSSQ D1 R414 1 2 10K_0402_5%
L9 D8 NC/CE1 CMDC18 CKEx 10k
NCZQ1 VSSQ L9 VSSQ D8 DIS@
DIS@ DDR3
E2 NCZQ1 CMDC19
2
2
VSSQ E2 R413 1 2 10K_0402_5% RST 10k

E8 VSSQ
tt
VSSQ E8 R412 1 DIS@ 2 10K_0402_5%

F9 VSSQ CS* No Termination
VSSQ F9
CLKC0 G1 VSSQ
23 CLKC0 VSSQ G1
G9 VSSQ
VSSQ G9
1 2 VSSQ
96-BALL
h
R61 96-BALL
1
@ SDRAM DDR3
SDRAM DDR3
DIS@ 80.6_0402_1% K4B1G1646E-HC12_FBGA96
R69
160_0402_1%
CLKC0#
23 CLKC0# 1 2 +1.5VSDGPU
2
R60
@ +1.5VSDGPU
1
80.6_0402_1% @
C145
1U_0603_10V6K
0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0603_10V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
DIS@ C127
DIS@ C572
DIS@ C569
1U_0603_10V6K
DIS@ C167
1U_0603_10V6K
1U_0603_10V6K
1U_0603_10V6K
0.1U_0402_16V4Z
1U_0603_10V6K
0.1U_0402_16V4Z
1U_0603_10V6K
0.1U_0402_16V4Z
1 1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
DIS@ C166
DIS@ C567
DIS@ C566
DIS@ C573
NV recommand 0720 1 1 1 1
DIS@ C168
DIS@ C565
DIS@ C571
DIS@ C169
DIS@ C564
DIS@ C170
DIS@ C563
DIS@ C163
DIS@ C161
DIS@ C164
DIS@ C568
1 1 1 1 1 1 1 1 1 1 1
2 2 2 2
2 2 2 2
2 2 2 2 2 2 2 2 2 2 2
A A

N12P DDR3 8/9
Custom 0.1
5 4 3 2 1
VRAM DDR3 chips (1GB)

64Mx16 DDR3 *8==>1GB
D D
DQMC[7..0]
23,29 DQMC[7..0]
CMDC[30..0] Mode D
23,29 CMDC[30..0]
DQSC#[7..0]
Address 0..31 32..63
23,29 DQSC#[7..0] U5 X76@ U26 X76@
DQSC[7..0] +MEM_VREF6 +MEM_VREF7
CMD0 CS0_L#
M8 E3 MDC39 MDC56
23,29 DQSC[7..0] VREFCA DQL0 M8 DQL0 E3
H1 F7 MDC33 VREFCA MDC63 CMD1
MDC[63..0] VREFDQ DQL1 H1 F7
F2 MDC38 VREFDQ DQL1 MDC57
23,29 MDC[63..0] CMDC9 DQL2 DQL2 F2
F8 MDC32 CMDC9 MDC60 CMD2 ODT_L
N3 A0 DQL3 N3 F8
CMDC11 MDC36 Group4 CMDC11 A0 DQL3 MDC59 Group7
P7 H3 P7 H3
CMDC8 A1 DQL4 MDC34 CMDC8 A1 DQL4 MDC61
CMDC25
P3
A2 DQL5 H8 P3 H8 CMD3 CKE
N2 G2 MDC37 CMDC25 A2 DQL5 MDC58
CMDC10 A3 DQL6 MDC35 CMDC10 N2 A3 G2 MDC62
P8 H7 DQL6 CMD4 A14 A14
CMDC24 A4 DQL7 CMDC24 P8 A4 H7
P2 DQL7
CMDC22 A5 CMDC22 P2
R8 A5 CMD5 RST RST
CMDC7 A6 MDC42 CMDC7 R8
+1.5VSDGPU R2 A6 MDC48
CMDC21 A7 DQU0 D7 R2 D7
T8 MDC43 CMDC21 A7 DQU0 MDC55 CMD6 A9 A9
C3 T8
/
CMDC6 A8 DQU1 MDC41 CMDC6 A8 C3 MDC49
R3 C8 R3 DQU1
CMDC29 A9 DQU2 MDC46 CMDC29 A9 C8 MDC52
DIS@
CMDC23
L7 A10/AP C2 CMDC23 L7
DQU2
C2 CMD7 A7 A7
R32 DQU3 MDC40 Group5 A10/AP DQU3 MDC51 Group6
R7 A7 R7 A7
A11
/x
240_0402_1% CMDC28 DQU4 MDC45 CMDC28 A11 DQU4 MDC54 CMD8 A2 A2
CMDC20 N7 A2 CMDC20 N7 A2
A12 DQU5 MDC44 A12 DQU5 MDC50
CMDC4 T3 DQU6 B8 CMDC4 T3 B8
A13 MDC47 A13 DQU6 MDC53 CMD9 A0 A0
CMDC14 T7 DQU7 A3 CMDC14 T7 A3
A14 A14 DQU7
+MEM_VREF6 M7 +1.5VSDGPU M7 +1.5VSDGPU
A15/BA3 A15/BA3 CMD10 A4 A4
CMDC12 CMDC12
0.1U_0402_10V6K
DIS@
DIS@ CMD11 A1 A1
su
1 CMDC27 M2 BA0 B2 M2 BA0 B2
R31 VDD CMDC27 VDD
C CMDC26 N8 BA1 D9 N8 BA1 D9 C
240_0402_1% VDD CMDC26 VDD CMD12 BA0 BA0
M3 VDD G7 M3 BA2 G7
BA2 VDD
2 K2 K2
VDD
C44
K8 VDD
K8
CMD13 WE* WE*
VDD VDD
CLKC1 VDD N1 CLKC1 N1
J7 VDD CMD14 A15 A15
p.
CLKC1# CK N9 CLKC1# J7 N9
K7 VDD CK VDD
CMDC19 CK R1 CMDC19 K7 R1
K9 VDD CK VDD CMD15 CAS* CAS*
CKE/CKE0 R9 +1.5VSDGPU K9 R9 +1.5VSDGPU
VDD CKE/CKE0 VDD
CMDC18 CMDC18
CMD16 CS0_H#
om
CMDC16 K1 A1 CMDC16 K1 ODT/ODT0 A1
+1.5VSDGPU ODT/ODT0 VDDQ VDDQ CMD17
CMDC30 L2 CS/CS0 A8 L2 CS/CS0 A8
VDDQ CMDC30 VDDQ
CMDC15 J3 RAS C1 J3 RAS C1
VDDQ CMDC15 VDDQ CMD18 ODT_H
CMDC13 K3 CAS C9 K3 CAS C9
DIS@ VDDQ CMDC13 VDDQ
L3 WE D2 L3 WE
R407 VDDQ
310mAVDDQ 310mA D2 CMD19 CKE_H
E9 VDDQ E9
240_0402_1% F1 VDDQ
DQSC4 VDDQ DQSC7 F1 CMD20 A13 A13
F3 H2 VDDQ
DQSC5 DQSL VDDQ DQSC6 F3 H2
C7 DQSL VDDQ
yc
DQSU H9 C7 H9
VDDQ DQSU VDDQ CMD21 A8 A8
+MEM_VREF7
DQMC4 DQMC7 CMD22 A6 A6
DQMC5 E7 VSS A9 DQMC6 E7 A9
DML DML VSS
0.1U_0402_10V6K
DIS@
1 D3 VSS B3 D3 B3
DIS@ DMU DMU VSS CMD23 A11 A11
VSS E1 E1
R408 VSS
m
240_0402_1% DQSC#4 G8 DQSC#7 G8
VSS VSS CMD24 A5 A5
DQSC#5 G3 DQSL J2 DQSC#6 G3 J2
2 B7 VSS DQSL VSS
C524
DQSU J8 B7
VSS
M1 DQSU VSS J8 CMD25 A3 A3
VSS VSS M1
M9
VSS M9 CMD26 BA2 BA2
CMDC5
T2 RESET
// VSS
P1
P9
CMDC5
T2
VSS
VSS P1
ZQ6 VSS
T1 ZQ7 RESET VSS
P9 CMD27 BA1 BA1
B L8 VSS T1 B
ZQ/ZQ0 T9 L8 VSS
VSS ZQ/ZQ0 VSS
T9 CMD28 A12 A12
1
J1 B1 DIS@ CMD29 A10 A10
1
p:
NC/ODT1 VSSQ R411 J1 B1

L1 B9 NC/ODT1 VSSQ
DIS@ NC/CS1 VSSQ 243_0402_1% L1 B9 CMD30 RAS* RAS*
CLKC1 J9 D1 NC/CS1 VSSQ
R30 NC/CE1 VSSQ J9 D1
23 CLKC1 D8 NC/CE1 VSSQ
2
243_0402_1% L9 VSSQ D8
1 2 NCZQ1 E2 L9 VSSQ Not Available
VSSQ NCZQ1 E2
R33 E8 VSSQ
2
1
tt
@ VSSQ E8 LOW HIGH

F9 VSSQ
DIS@ 80.6_0402_1% VSSQ F9
G1 VSSQ
R35 VSSQ G1
G9 VSSQ
160_0402_1% VSSQ G9
CLKC1# VSSQ
1 2
h
23 CLKC1# 96-BALL
96-BALL
2
R37 SDRAM DDR3

@ SDRAM DDR3
80.6_0402_1% K4B1G1646E-HC12_FBGA96
1
@
+1.5VSDGPU
C57
NV recommand 0720 0.01U_0402_16V7K +1.5VSDGPU
2
1U_0603_10V6K
0.1U_0402_16V4Z
1U_0603_10V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0603_10V6K
0.1U_0402_16V4Z
1U_0603_10V6K
1U_0603_10V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C37
C39
DIS@ C525
C43
DIS@ C526
DIS@ C517
1U_0603_10V6K
DIS@ C519
0.1U_0402_16V4Z
1U_0603_10V6K
1U_0603_10V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1
0.1U_0402_16V4Z
1 1 1 1 1
C40
DIS@ C518
DIS@ C532
C41
1 1 1 1
C48
DIS@ C522
C45
DIS@ C523
C38
C42
C36
DIS@ C521
1 1 1 1 1 1 1 1
2 2 2 2 2 2
DIS@
2
DIS@
DIS@
2 2 2 2
DIS@
DIS@
2 2 2 2 2 2 2
DIS@
2
DIS@
DIS@
DIS@
DIS@
A A

N12P DDR3 9/9
Custom 0.1
5 4 3 2 1
D D
+LCDVDD
LCD POWER CIRCUIT
+3VALW +3VS
W=60mils
1
+INVPWR_B+ B+
R5 R6 1 +LCDVDD Place closed to JLVDS1 L2
2
300_0603_5% 10K_0402_5% C479
+3VS
W=60mils FBMA-L11-201209-221LMA30T_0805
4.7U_0805_10V4Z 2 1
2
L1
2 FBMA-L11-201209-221LMA30T_0805
R2 1 1 1 2 1
3
1
1
D 1K_0402_5% C484 C485 C11

Q2 2 2 1 2 AP2301GN-HF_SOT23-3 1 1
SSM3K7002F_SC59-3 G 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z C9 C6 SM010014520 3000ma
Q28 2 2 2 680P_0402_50V7K 68P_0402_50V8J
S 220ohm@100mhz
/
1 +LCDVDD
3
C2 2 2 DCR 0.04
0.047U_0402_16V7K W=60mils
1
1
/x
LCDVDD_ON 2
16 PCH_ENVDD 1 UMA@ 2 2 Q1
R1 0_0402_5% G SSM3K7002F_SC59-3 1 1
S C10
3
C483 0.1U_0402_16V4Z
4.7U_0805_10V4Z
2 2 LCD/LED PANEL Conn.
1
22 ENVDD 1 DISO@ 2
su
R3 0_0402_5% R4
C C
100K_0402_5%
W=60mils
2
+INVPWR_B+ JLVDS1
p.
1
2
3
4
DISPOFF# 5
om
INVTPWM 6
7
TXCLK+ 8
TXCLK- 9
DISPOFF# 10
39 BKOFF# R13 1 2 0_0402_5% 11
TXOUT2+
R18 TXOUT2- 12
1 2 10K_0402_5%
13
yc
TXOUT1+ 14
DAC_BRIG TXOUT1- 15
C482 2 1 220P_0402_50V7K 16
INVTPWM TXOUT0+ 17
C5 2 1 220P_0402_50V7K TXOUT0- 18
DISPOFF# 19
C8 1 220P_0402_50V7K
m
2 I2CC_SDA 20
I2CC_SCL 21
22
+3VS 23
+LCDVDD
UMA Only / Optimus 24
// 39 DAC_BRIG
DAC_BRIG
+3VS_CAMERA
25
26
PCH_TXOUT0+ +3VS 1 R388 20_0402_5%
TXOUT0+ R387 1 USB20_CMOS_P10 27
B PCH_TXOUT0- PCH_TXOUT0+ 16 17 USB20_P10 2 0_0402_5% B
TXOUT0- 0_0402_5% 2 UMA@ 1 R471 USB20_CMOS_N10 28
PCH_TXOUT0- 16 17 USB20_N10 R386 1 2 0_0402_5%
0_0402_5% 2 UMA@ 1 R473 29
TXOUT1+ 0_0402_5% UMA@ R441 PCH_TXOUT1+ 1 30
2 1 PCH_TXOUT1+ 16 1
TXOUT1- PCH_TXOUT1-
p:
0_0402_5% 2 UMA@ 1 R452 PCH_TXOUT1- 16 ACES_88341-3000B001

C480 C481 CONN@
TXOUT2+ PCH_TXOUT2+ 22P_0402_50V8J 22P_0402_50V8J
TXOUT2- PCH_TXOUT2- PCH_TXOUT2+ 16 2 2 @
0_0402_5% 2 UMA@ 1 R434 @
0_0402_5% 2 UMA@ 1 R439 PCH_TXOUT2- 16
TXCLK+ PCH_TXCLK+
tt
TXCLK- PCH_TXCLK- PCH_TXCLK+ 16

0_0402_5% UMA@ R432
0_0402_5% 22 UMA@ 11 R430 PCH_TXCLK- 16 +3VS
I2CC_SCL PCH_LCD_CLK VBIOS PWM SETTING

PCH_LCD_CLK 16
h
I2CC_SDA 0_0402_5% 2 UMA@ 1 R504 PCH_LCD_DATA CHANGE TO INVERT

5
PCH_LCD_DATA 16
0_0402_5% 2 UMA@ 1 R499
P
NC
DPST_PWM_1 INVTPWM
16 DPST_PWM 2 4 1 UMA@ 2
A Y
R20 0_0402_5%
G
U1 Reserved for UMA Only and OPTIMA

UMA@
Discrete ONLY
3
74AHC1G14GW_SOT3535
TXOUT0+ VGA_TXOUT0+ D15
TXOUT0- 0_0402_5% 2 DISO@ 1 R470 VGA_TXOUT0- VGA_TXOUT0+ 24
VGA_TXOUT0- 24 INVT_PWM 1 6
I/O1 I/O4
TXOUT1+ 0_0402_5% 2 DISO@ 1 R472 VGA_TXOUT1+ 39 INVT_PWM 1 DISO@ 2 +3VS
TXOUT1- 0_0402_5% DISO@ R440 VGA_TXOUT1- VGA_TXOUT1+ 24 R19 0_0402_5% 2 5
USB20_CMOS_P10 REF1 REF2 USB20_CMOS_N10
0_0402_5% 22 DISO@ 11 R451 VGA_TXOUT1- 24
TXOUT2+ VGA_TXOUT2+ VGA_PNL_PWM 3 4
I/O2 I/O3
TXOUT2- VGA_TXOUT2- VGA_TXOUT2+ 24 22 VGA_PNL_PWM 1 @ 2
0_0402_5% 22 DISO@
0_0402_5% DISO@ 11 R438
R433 VGA_TXOUT2- 24 PJUSB208H_SOT23-6
R17 0_0402_5%
TXCLK+ VGA_TXCLK+
TXCLK- VGA_TXCLK- VGA_TXCLK+ 24
1
A
0_0402_5% 2 DISO@ 1 R431 A
0_0402_5% 2 DISO@ 1 R429 VGA_TXCLK- 24
R16
I2CC_SCL VGA_LCD_CLK 10K_0402_5%
I2CC_SDA VGA_LCD_DATA VGA_LCD_CLK 22
0_0402_5% DISO@ R503
0_0402_5% 22 DISO@ 11 R498 VGA_LCD_DATA 22
2

LVDS Connector
Custom 0.1
A B C D E
1 1
W=40mils
+5VS
2
+R_CRT_VCC +CRT_VCC
2
For DISO only F1
D5 W=40mils
1.1A_6V_SMD1812P110TF
L22,L24,L26 2 1 1 2
use 0 Ohm D17 D18 CH491DPT_SOT23-3 1
PJDLC05C_SOT23-3 PJDLC05C_SOT23-3 C215
0.1U_0402_16V4Z
CRB1.0 use 47ohm@100Mhz Bead
1
1
2
CRT Connector
L32 L33
BLM18BA470SN1D_2P BLM18BA470SN1D_2P
CRT_R CRT_R_1 CRT_R_2 JCRT1
1 2 1 2
L29 L30 6
BLM18BA470SN1D_2P BLM18BA470SN1D_2P 11
/
CRT_G CRT_G_1 CRT_G_2 1
1 2 1 2
L27 L28 7
BLM18BA470SN1D_2P BLM18BA470SN1D_2P 12
CRT_B CRT_B_1 CRT_B_2
/x
1 2 1 2 2
8
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
22P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
13
1
1
1 1 1 1 1 1 1 1 1 3
R524 R520 R510 9
C613
C596
C637
C636
C621
C597
C614
150_0402_1% 150_0402_1% 150_0402_1%
C601
C588
14 G 16
4 17
su
2 2 2 2 G
UMA@ 2 UMA@ 2 UMA@ 2 2 2 10
2
2 2
2
15
1 5
C589
C-H_13-12201513CP
100P_0402_50V8J CONN@
p.
SM010012010 300ma 120ohm@100mhz DCR 0.4 2
CRT_HSYNC_2
+CRT_VCC 1 2 DSUB_12
L13 MBC1608121YZF_0603
om
CRT_VSYNC_2
C243 1 2 0.1U_0402_16V4Z R147 2 1 10K_0402_5% 1 2 1
L10 MBC1608121YZF_0603 1 1
DSUB_15
1
5
U10 C230 C220

10P_0402_50V8J 10P_0402_50V8J C623 2
CRT_HSYNC CRT_HSYNC_1
OE#
P
2 2 68P_0402_50V8J 1
2 4
A Y
G
C586
yc
74AHCT1G125GW_SOT353-5 68P_0402_50V8J
2
3
+CRT_VCC
C228 1 2 0.1U_0402_16V4Z
m
1
5
U9
OE#
P
CRT_VSYNC CRT_VSYNC_1
2 4
A Y
G
// 74AHCT1G125GW_SOT353-5
3
+CRT_VCC
3 3
+3VS
p:
UMA Only / OPTIMUS
1
1
R146 R142
PCH_CRT_R CRT_R 4.7K_0402_5% 4.7K_0402_5%
16 PCH_CRT_R R420 2 UMA@ 1 0_0402_5%
PCH_CRT_G CRT_G
2
tt
2
16 PCH_CRT_G R424 2 UMA@ 1 0_0402_5%
PCH_CRT_B CRT_B CRT_DDC_DATA DSUB_12
16 PCH_CRT_B R422 2 UMA@ 1 0_0402_5% 1 6
PCH_CRT_HSYNC CRT_HSYNC
16 PCH_CRT_HSYNC
h
R428 2 UMA@ 1 33_0402_5% Q11A
5
PCH_CRT_VSYNC CRT_VSYNC DMN66D0LDW-7_SOT363-6
16 PCH_CRT_VSYNC R426 2 UMA@ 1 33_0402_5% CRT_DDC_CLK DSUB_15
PCH_CRT_CLK CRT_DDC_CLK 4 3
16 PCH_CRT_CLK
R506 2 UMA@ 1 0_0402_5%
PCH_CRT_DATA CRT_DDC_DATA Q11B
16 PCH_CRT_DATA R501 2 UMA@ 1 0_0402_5%
DMN66D0LDW-7_SOT363-6
Discrete only
VGA_CRT_R CRT_R
22 VGA_CRT_R R419 2 DISO@ 1 0_0402_5%
VGA_CRT_G CRT_G
4 22 VGA_CRT_G R423 2 DISO@ 1 0_0402_5% 4
VGA_CRT_B R421 2 DISO@ 1 0_0402_5% CRT_B
22 VGA_CRT_B
VGA_CRT_HSYNC CRT_HSYNC
22 VGA_CRT_HSYNC R427 2 DISO@ 1 0_0402_5%
VGA_CRT_VSYNC CRT_VSYNC
22 VGA_CRT_VSYNC R425 2 DISO@ 1 0_0402_5%
VGA_DDC_CLK CRT_DDC_CLK
22 VGA_DDC_CLK R505 2 DISO@ 1 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
VGA_DDC_DATA CRT_DDC_DATA
22 VGA_DDC_DATA Issued Date 2010/08/11 Deciphered Date 2011/08/11 Title
R500 2 DISO@ 1 0_0402_5%
CRT Connector
Custom 0.1
A B C D
Date: Friday, August 27, 2010 E
Sheet 32 of 59
5 4 3 2 1
@ R242 SM070001310 400ma 90ohm@100mhz DCR 0.3

0_0603_5%
D
1 2 W=40mils HDMI_CLK- HDMI_R_CK- D
R574 1 2 0_0402_5%
+HDMI_5V_OUT
D10 F2 1 2
2 1+HDMI_5V L38 1 2
+5VS 1 2
1 WCM-2012-900T_0805
CH491DPT_SOT23-3 1.1A_6V_SMD1812P110TF @ 4
C345 4 3 3
0.1U_0402_16V4Z HDMI_CLK+ R579 1 2 0_0402_5% HDMI_R_CK+
2
+3VS
HDMI_TX0- R565 1 2 0_0402_5% HDMI_R_D0-
1 2
1 2
1
UMAO@ L36
R198 WCM-2012-900T_0805
1M_0402_5% @ 4 3
4 3
HDMI_TX2- HDMI_TX0+ HDMI_R_D0+
2
UMA 16 PCH_DPB_N0 C280 UMAO@ 2 1 .1U_0402_16V7K R569 1 2 0_0402_5%
2
C281 UMAO@ 2 HDMI_TX2+
16 PCH_DPB_P0 1 .1U_0402_16V7K
HDMI_HPD
PCH_DPB_HPD 16
/
HDMI_TX1- 1 3 HDMI_TX1- HDMI_R_D1-
16 PCH_DPB_N1 C283 UMAO@ 2 1 .1U_0402_16V7K Q14 R584 1 2 0_0402_5%
S
HDMI_TX1+
220P_0402_25V8J
C324
16 PCH_DPB_P1 C282 UMAO@ 2 1 .1U_0402_16V7K 1 SSM3K7002F_SC59-3
1
UMAO@ UMAO@ 1 2
1 2
/x
C287 UMAO@ 2 HDMI_TX0- L39
16 PCH_DPB_N2 1 .1U_0402_16V7K R219
HDMI_TX0+ WCM-2012-900T_0805
16 PCH_DPB_P2 C286 UMAO@ 2 1 .1U_0402_16V7K 100K_0402_5%
2 @ 4 3
C285 UMAO@ 2 HDMI_CLK- 4 3
16 PCH_DPB_N3 1 .1U_0402_16V7K
HDMI_CLK+ HDMI_TX1+ HDMI_R_D1+
2
16 PCH_DPB_P3 C284 UMAO@ 2 1 .1U_0402_16V7K R586 1 2 0_0402_5%
su
HDMI_TX2- HDMI_R_D2-
C R591 1 2 0_0402_5% C
NVIDA Recommand 05/10 1 2

L40 1 2
R547 L19 WCM-2012-900T_0805
DIS@
p.
DIS@ @ 4
DIS 24 VGA_HDMI_TXD2- C234 DIS@ 2 1 .1U_0402_16V7K
HDMI_TX2-
10K_0402_5% 4 3 3
HDMI_TX2+ BLM18PG181SN1D_0603 HDMI_HPD HDMI_TX2+ HDMI_R_D2+
24 VGA_HDMI_TXD2+ C235 DIS@ 2 1 .1U_0402_16V7K 22 VGA_HDMI_DET 1 2 R593 1 2 0_0402_5%
2 1
HDMI_TX1-
1
24 VGA_HDMI_TXD1- C237 DIS@ 2 1 .1U_0402_16V7K HDMI_TX1+
om
24 VGA_HDMI_TXD1+ C236 DIS@ 2 1 .1U_0402_16V7K
100K_0402_5%
DIS@ R552
DIS@ HDMI_TX2- HDMI_GND
2
G
HDMI_TX0- D20 HDMI_TX2+ R589 1 UMAO@ 2 619_0402_1%
24 VGA_HDMI_TXD0- C241 DIS@ 2 1 .1U_0402_16V7K HDMI_TX0+ BAV99_SOT23-3 R594 1 UMAO@ 2 619_0402_1%
24 VGA_HDMI_TXD0+ C240 DIS@ 2 1 .1U_0402_16V7K DGPU_HPD_INT# 18
3 1 HDMI_TX1-
R583 1 UMAO@ 2 619_0402_1%
D
C239 DIS@ 2 HDMI_CLK- HDMI_TX1+
1 .1U_0402_16V7K
3
2
24 VGA_HDMI_TXC- HDMI_CLK+ R587 1 UMAO@ 2 619_0402_1%
24 VGA_HDMI_TXC+ C238 DIS@ 2 1 .1U_0402_16V7K +3VSDGPU
Q13 HDMI_TX0-
HDMI_TX0+ R564 1 UMAO@ 2 619_0402_1%
SSM3K7002F_SC59-3 R570 1 UMAO@ 2 619_0402_1%
yc
HDMI_CLK- R573 1 UMAO@ 2 619_0402_1%
HDMI_CLK+
R580 1 UMAO@ 2 619_0402_1%
INTEL use 619 Ohm for terminationn
m
+3VS +HDMI_5V_OUT
1
D
+3VS Q37
2
SDVO_SCLK G
R250 1 UMAO@ 2 2.2K_0402_1% HDMI connector
// SSM3K7002F_SC59-3 S
3
2
2
SDVO_SDATA
B R253 1 UMAO@ 2 2.2K_0402_1% D11 HDMI_HPD JHDMI1 B
D12
RB751V40_SC76-2 RB751V40_SC76-2 19
+HDMI_5V_OUT
18
HP_DET
+5V
NV use 499 Ohm for terminationn
+3VS HDMI_SDATA 17
p:
DDC/CEC_GND
1
1
HDMI_SCLK
2
16
2.2K_0402_5%
2.2K_0402_5%
SDA
15
SCL
14
R256
R255
Pull high at VGA side HDMI_R_CK- 13

Reserved
CEC
12 20
2
G
tt
CK- GND
1
HDMI_R_CK+
1
1109 RF request 11 21
16 SDVO_SCLK HDMI_SCLK_R HDMI_SCLK HDMI_R_D0- CK_shield GND
R249 UMAO@ 0_0402_5% 10 22
24 VGA_HDMI_SCLK R244 11 DIS@ 22 0_0402_5% 3 1
9
CK+ GND
23
S
1 HDMI_R_D0+ D0- GND

8
D0_shield
h
2
HDMI_R_D1-
G
Q16 SSM3K7002F_SC59-3 7
16 SDVO_SDATA R252 1 UMAO@ 2 0_0402_5% HDMI_SDATA_R HDMI_SDATA C357 D0+
47P_0402_50V8J 6
24 VGA_HDMI_SDATA R254 1 DIS@ 2 0_0402_5% HDMI_R_D1+ D1-
3 1 2 5 D1_shield
@ HDMI_R_D2-
S
4 D1+
1
3 D2-
Q17 SSM3K7002F_SC59-3 HDMI_R_D2+ 2
Place closed to JHDMI1 C358
1
D2_shield
47P_0402_50V8J D2+
2 @
ACON_HMR2E-AK120D
CONN@
A A

HDMI Conn
Custom 0.1
5 4 3 2 1
D D
SATA HDD1 Conn.

CL 4.0 mm
JHDD1
1
SATA_PTX_DRX_P0 GND
13 SATA_PTX_DRX_P0 C708 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2
SATA_PTX_DRX_N0 RX+
13 SATA_PTX_DRX_N0 C711 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3
RX-
4
SATA_PRX_DTX_N0 GND
13 SATA_PRX_DTX_N0 C712 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5
SATA_PRX_DTX_P0 TX-
13 SATA_PRX_DTX_P0 C713 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 6 TX+
7 GND +3VS
/
+3VS 8 3.3V 1
9 C453
3.3V
10 3.3V
/x
11 0.1U_0402_16V4Z
+5VS GND 2
R370 12
GND
0_0805_5% 13
+5VS_HDD1 GND
1 2 14
5V
15
5V
16
5V +5VS_HDD1
17
su
GND
C 18 Rsv C
19 GND 100mils
20 12V
21 12V
10U_0805_10V4Z
C744
0.1U_0402_16V4Z
C743
1000P_0402_50V7K
C742
1U_0402_6.3V4Z
C740
22 1 1 1 1
12V
23
p.
GND
24
GND
2 2 2 2
OCTEK_SAT-22DD1G
om
CONN@
SATA ODD Conn.
yc
JODD1
SATA_PTX_C_DRX_P2 1 GND
13 SATA_PTX_DRX_P2 C643 1 2 0.01U_0402_16V7K 2
SATA_PTX_C_DRX_N2 A+
13 SATA_PTX_DRX_N2 C639 1 2 0.01U_0402_16V7K 3
m
A-
SATA_PRX_C_DTX_N2 4 GND
13 SATA_PRX_DTX_N2 C628 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P2 5 B-
13 SATA_PRX_DTX_P2 C624 1 2 0.01U_0402_16V7K 6 +5VS_ODD
B+
7 GND 80mils
// 1 R139 2 0_0402_5%
18 ODD_DETECT# 8
10U_0805_10V4Z
C199
0.1U_0402_16V4Z
C200
+5VS_ODD
1U_0402_6.3V4Z
C201
DP
1000P_0402_50V7K
C192
B +5VS_ODD 9 1 1 1 1 B
+5V
ODD_DA#_R 10 17
17 ODD_DA# +5V GND
R763 1 @ 2 0_0402_5% 11 16
MD GND
12 15 2 2 2
GND GND 2
p:
+5VS +5VS_ODD 13 14
GND GND
R765
0_0805_5% OCTEK_SLS-13SB1G_RV
+VSB
1 2 CONN@
tt
D
6
S
2
1 5 4
1U_0402_6.3V6K
C812
R760 2
h
470K_0402_5% @ 1 Q55
@ SI3456BDV-T1-E3 1N TSOP6
G
2 @
3
1
ODD_EN
2
1
D
1.5M_0402_5%
R764
0.1U_0402_25V6K
C811
Q56 1
18 ODD_EN# 2
G SSM3K7002FU_SC70-3 @
@ S @
3
2
1
A A

HDD & ODD Connector
Custom 0.1
5 4 3 2 1
5 4 3 2 1
+1.2V_LAN
0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z U32
+3V_LAN 37 +LAN_BIASVDDH
1 1 1 1 1 1 1 BIASVDDH
C678 C302 C674 C301 C671 C298 C668 20 +3V_LAN +3VALW
VDDO_CR R543
+1.2V_LAN +LAN_XTALVDDH
60mil
35 17 1 2
4.7U_0603_6.3V6K 2 2 2 2 2 2 2 VDDC XTALVDDH
61 VDDC
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0_1206_5%
48 +LAN_AVDDH
AVDDH 1 1
42 C662 C666
+3V_LAN AVDDH
7 4.7U_0603_6.3V6K
VDDO 2 2
56
D +3V_LAN VDDO D
62 0.1U_0402_16V4Z
VDDO LAN_MIDI3-
TRD3_N 49 LAN_MIDI3- 36
50 LAN_MIDI3+
TRD3_P LAN_MIDI3+ 36
0.1U_0402_16V4Z
LAN_MIDI2-
1 1 1 1 47 LAN_MIDI2- 36
C667 TRD2_N LAN_MIDI2+
C683 C690 C680 46 LAN_MIDI2+ 36
TRD2_P
+LAN_AVDDL LAN_MIDI1-
2
39 AVDDL TRD1_N
43
LAN_MIDI1+ LAN_MIDI1- 36 20mil
4.7U_0603_6.3V6K 2 2 2 45 AVDDL TRD1_P 44 LAN_MIDI1+ 36 L20
0.1U_0402_16V4Z +LAN_XTALVDDH
0.1U_0402_16V4Z 51 1 1 2+3V_LAN
AVDDL LAN_MIDI0-
+LAN_GPHYPLLVDDL TRD0_N 41 LAN_MIDI0- 36 C323 BLM18AG601SN1D_2P
LAN_MIDI0+
36 40 LAN_MIDI0+ 36 0.1U_0402_16V4Z
GPHY_PLLVDDL TRD0_P
+LAN_PCIEPLLVDD 20mil
32 2 L34
PCIE_PLLVDDL +LAN_BIASVDDH
1 1 2
29 C657 BLM18AG601SN1D_2P
PCIE_PLLVDDL 0.1U_0402_16V4Z
SO_LINKLED# 65 LAN_LINK# 36
2
SCLK_SPD1000LED#
66 20mil
+LAN_AVDDH L15
2
/
SPD100LED#_SERIALDO 1 2
1 BLM18AG601SN1D_2P
C299 1
PCIE_PRX_C_DTX_P1 C294
14 PCIE_PRX_DTX_P1 28 67 R200 2 1 0_0402_5% LAN_ACTIVITY# 36
0.1U_0402_16V7K 1 2 C670 PCIE_PRX_C_DTX_N1
/x
14 PCIE_PRX_DTX_N1 PCIE_TXD_P TRAFFICLED#_SERIALDI 0.1U_0402_16V4Z
0.1U_0402_16V7K 1 2 C673 27 2 0.1U_0402_16V4Z
PCIE_TXD_N
14 PCIE_PTX_C_DRX_P1 33 +VDDO_CR_R +VDDO_CR 2
PCIE_RXD_P
14 PCIE_PTX_C_DRX_N1 34 8 R214 2 1 0_0402_5%
PCIE_RXD_N GPIO1_LR_OUT
CR_5IN1_LED#_R R229 2 B0@ 1 0_0402_5% CR_5IN1_LED#
GPIO_0 5 CR_5IN1_LED# 40 +XDPWR_SDPWR_MSPWR
39 EC_PME# R201 1 2 0_0402_5%
R825 (CR_5IN1_LED#) for B0 version
su
SPROM_DOUT
C +3V_LAN
R209 1 64 SPROM_CLK +VDDO_CR
R826 (+VDDO_CR) C
2 4.7K_0402_5% SI_EEDATA
R213 1 @
LAN_PME# CS#_EECLK
63 For B0 version
15,37,38,45 PCH_PCIE_WAKE# 2 0_0402_5% 3 WAKE# R232
5,17,38,39,45 PLT_RST# R225 1 2 0_0402_5% 11 1 2
PREST# B0@
p.
14 CLK_PCIE_LAN 31
PCIE_REFCLK_P 1 1C328 1 0_0805_5%
14 CLK_PCIE_LAN# 30 CR_XD_WE#_SD_DETECT_R CR_XD_WE#_SD_DETECT C676
PCIE_REFCLK_N C337
1 R576 2 1 0_0402_5% CR_XD_WE#_SD_DETECT 36
SD_DETECT/XD_WE#
CR_XD_DETECT#_R CR_XD_DETECT# 2
CR_XD_DETECT# 36 2 0.1U_0402_16V4Z
CR_DATA0 R199 1 2 0_0402_5%
CR_DATA0_R
SR_DISABLE/XD_DETECT# 68 R572 2 1 0_0402_5% 4.7U_0603_6.3V6K 2
om
36 CR_DATA0 CR_DATA1 CR_DATA1_R 25 CR_XD_CE#_MS_INS#_R 0.1U_0402_16V4Z
R207 1 2 0_0402_5% CR_DATA0 R192 2 1 0_0402_5% CR_XD_CE#_MS_INS# CR_XD_CE#_MS_INS# 36
36 CR_DATA1 CR_DATA2 CR_DATA2_R 24 CR_DATA1 59
MS_INS#/XD_CE#
36 CR_DATA2 CR_DATA3 R211 1 2 0_0402_5% CR_DATA3_R 23 CR_XD_RE#_R CR_XD_RE#
CR_DATA2 R227 2 1 0_0402_5% CR_XD_RE# 36
36 CR_DATA3 CR_DATA4 R215 1 2 0_0402_5% CR_DATA4_R 22 9
R168 1 2 0_0402_5% CR_DATA3 GPIO2_MEDIA_SENSE/XD_RE#
36 CR_DATA4 CR_DATA5 CR_DATA5_R 52 CR_WP#_XD_WP#_R CR_WP#_XD_WP#
CR_DATA4 CR_WP#_XD_WP# 36
36 CR_DATA5 CR_DATA6 CR_DATA6_R 53 57 R185 2 1 0_0402_5%
36 CR_DATA6 CR_DATA7
R171 1 2 0_0402_5% CR_DATA7_R
54
CR_DATA5 CR_WP#/XD_WP#
CR_PWR_XD_ALE_R CR_PWR_XD_ALE
R528(CR_PWR_XD_ALE)
R179 1 0_0402_5%
36 CR_DATA7 R182 1 22 0_0402_5% 55
CR_DATA6
60 R196 2 A0@ 1 0_0402_5% CR_PWR_XD_ALE 36 for A0 version
CR_DATA7 CR_LED_CR_BUS_PWR/XD_ALE
yc
CR_CLK_XD_RY_BY#_R CR_CLK_XD_RY_BY# R222 C329
21 CR_CLK_XD_RY_BY# 36
CR_CLK/XD_RY_BY# R216 2 1 0_0402_5% 1 2 1 2
+3VS CR_CMD_XD_CLE_R CR_CMD_XD_CLE
CR_CMD_XD_CLE 36 @
26 R195 @
R190 1 2 1K_0402_5% 58 CR_CMD_XD_CLE 2 1 0_0402_5% 22_0402_5%
VMAIN_PRSNT 0.01U_0402_16V7K
+3V_LAN
m
R228 4.7K_0402_5%
6 For EMI request
1 2 TEST1
40mil L37 40mil
10 +1.2V_LAN_OUT
R824 (CP_PWR_XD_ALE) CR_PWR_XD_ALE 1 2 TEST2
16 1 2 +1.2V_LAN
R226 4.7K_0402_5% SR_LX
for B0 version R208
R212 1 2 B0@ 1 0_0402_5%
2 10K_0402_5%
4
// 13
4.7UH_PG031B-4R7MS_1.1A_20%
1
A0@ LOW_PWR SR_VFB 1 EMI Request...2010/07/27
B
C689 B
LAN_XTALI LAN_XTALO_R C691
LAN_XTALO_R LAN_XTALI 19 0.1U_0402_16V4Z 10U_0805_10V4Z
XTALO 2 2 SM010005500 500ma 600ohm@100mhz DCR 0.38
18
XTALI 20mil
1
p:
R562
40mil +LAN_PCIEPLLVDD L18
15 +3V_LAN +1.2V_LAN
GND PLANE
1 2
200_0402_1% LAN_RDAC 15mil SR_VDDP
14 BLM18AG601SN1D_2P
SR_VDD 1 4.7U_0603_6.3V6K 1
1 2 38 1 0.1U_0402_16V4Z
RDAC C692 C306
2
Y4 LAN_XTALO C684 1
tt
1 2 14 LAN_CLKREQ# R541 1.24K_0402_1% C303

12 0.1U_0402_16V4Z
CLK_REQ#
25MHZ_20PF_7A25000012 2 2 4.7U_0603_6.3V6K
1 BCM57785XA0KMLG_QFN68_8X8 2
1 2
69
PLACE NEXT P14

h
C681
27P_0402_50V8J C679 20mil
2 27P_0402_50V8J +LAN_GPHYPLLVDDL
2
L35 +1.2V_LAN
1 2
1 1 BLM18AG601SN1D_2P
C658 C659
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2
+3V_LAN
SPROM_CLK SPROM_DOUT
(EECLK) (EEDATA)
C634 1 2 0.1U_0402_16V4Z 20mil
+LAN_AVDDL
On chip 1 0
2
L17 +1.2V_LAN
2
@
R536 1 2
R537 4.7K_0402_5% 1 BLM18AG601SN1D_2P
AT24C02 1 1 @ 4.7K_0402_5% C656
1
U31 @ C297
1
A 0.1U_0402_16V4Z A
1
8 A0 1 2
SPROM_CLK VCC
7 A1 2 4.7U_0603_6.3V6K
SPROM_DOUT WP 2
6 A2 3
SCL
5 4
SDA GND
AT24C04BN-SH-T_SO8
2
R538
2
4.7K_0402_5%
R525 Security Classification Compal Secret Data Compal Electronics, Inc.
@ 4.7K_0402_5% 2010/08/11 2011/08/11 Title
1
SM010005500 500ma 600ohm@100mhz DCR 0.38 Broadcom BCM57785

1
Custom 0.1
5 4 3 2 1
LAN Connector
T28
+3V_LAN 2 1
1 24 R384 1K_0402_5% 1
LAN_MIDI3+ TCT1 MCT1 RJ45_MIDI3+
35 LAN_MIDI3+ 2 TD1+ MX1+ 23
35 LAN_MIDI3- LAN_MIDI3- 3 22 RJ45_MIDI3- 220P_0402_50V7K
TD1- MX1- C473
4 21 2 C474 68P_0402_50V8J
TCT2 MCT2 JRJ1
35 LAN_MIDI2+ LAN_MIDI2+ 5 20 RJ45_MIDI2+ @
LAN_MIDI2- TD2+ MX2+ RJ45_MIDI2-
35 LAN_MIDI2- 6 19 2 1 9 Green LED+
D
TD2- MX2- D
7 18 LAN_LINK# 10
LAN_MIDI1+ TCT3 MCT3 RJ45_MIDI1+ 35 LAN_LINK# Green LED-
35 LAN_MIDI1+ 8 TD3+ MX3+ 17
LAN_MIDI1- 9 16 RJ45_MIDI1- RJ45_MIDI0+ 1 14
35 LAN_MIDI1- TD3- MX3- PR1+ SHLD1
SHLD2 13
10 15 RJ45_MIDI0- 2
LAN_MIDI0+ TCT4 MCT4 RJ45_MIDI0+ PR1-
35 LAN_MIDI0+ 11 TD4+ MX4+ 14
LAN_MIDI0- 12 13 RJ45_MIDI0- RJ45_MIDI1+ 3
35 LAN_MIDI0- TD4- MX4- PR2+
RJ45_MIDI2+ 4 PR3+
1
GST5009-E RJ45_MIDI2- 5 PR3-
R493 R492 RJ45_MIDI1- 6
1 1 1 1 PR2-
C617 C618 C619 C620 75_0402_1% 75_0402_1%
RJ45_MIDI3+ 7
2
PR4+
1
2
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 RJ45_MIDI3- 8 PR4-
R491 R490
/
0.1U_0402_16V4Z 0.1U_0402_16V4Z 75_0402_1% 75_0402_1% +3V_LAN 2 1 11 Yellow LED+
R385 1K_0402_5% 1
2
LAN_ACTIVITY# 12
35 LAN_ACTIVITY# Yellow LED-
/x
RJ45_GND 220P_0402_50V7K
68P_0402_50V8J
Place close to TCT pin C476
2 SANTA_130451-K
40mil 2 1
CONN@
@
C475
BOTHHAND: S X'FORM_ GST5009-D LF LAN, SP050006B00 LAN_ACTIVITY#
su
TIMAG:S X'FORM_ IH-160 LAN , SP050006F00 LAN_LINK# C478
C RJ45_GND LANGND C
1 2 40mil
1 1
1000P_1206_2KV7K
C472 C477
2
3
p.
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
D14 2 2
Card Reader Connector @

PJDLC05C_SOT23-3
EMI Request
om
1
R781
1
0_1206_5%
JREAD1 CR_DATA0
2
+XDPW R_SDPW R_MSPW R 13 35 CR_DATA1 CR_DATA0 35
yc
SD_VCC XD_D0
22 MS_VCC XD_D1 36 CR_DATA2 CR_DATA1 35
43 XD_VCC XD_D2 37 CR_DATA3 CR_DATA2 35
XD_D3 38 CR_DATA4 CR_DATA3 35
CR_CLK_XD_RY_BY# XD_D4 39 CR_DATA5 CR_DATA4 35
CR_CMD_XD_CLE 10 XD_D5 40 CR_DATA6 CR_DATA5 35
m
SD_CLK
CR_XD_W E#_SD_DETECT 19 XD_D6 41 CR_DATA7 CR_DATA6 35
SD_CMD
CR_W P#_XD_W P# 1 XD_D7 42 CR_DATA7 35
SD_CD
CR_DATA0 2 SD_WP CR_XD_DETECT#
CR_DATA1 4 XD_CD 26 CR_CLK_XD_RY_BY# CR_XD_DETECT# 35
SD/MMC_DAT0
CR_DATA2 3 SD/MMC_DAT1 XD_R/B 27 CR_XD_RE#
// CR_CLK_XD_RY_BY# 35 +3VS
B
CR_DATA3
CR_DATA4
CR_DATA5
25
23
21
SD/MMC_DAT2
SD/MMC_DAT3
XD_RE
XD_CE
28
29
30
CR_XD_CE#_MS_INS#
CR_CMD_XD_CLE
CR_PW R_XD_ALE
CR_XD_RE# 35
CR_XD_CE#_MS_INS# 35
CR_CMD_XD_CLE 35
For A0 version B
MMC_DATA4 XD_CLE
CR_DATA6 31 CR_PW R_XD_ALE 35
2
17 CR_XD_W E#_SD_DETECT +XDPW R_SDPW R_MSPW R
2
MMC_DATA5 XD_ALE
CR_DATA7 8 32 CR_W P#_XD_W P# CR_XD_W E#_SD_DETECT 35 R271 +3VS
MMC_DATA6 XD_WE R270
p:
5 33 CR_W P#_XD_W P# 35
MMC_DATA7 XD_WP 10K_0402_5% 10K_0402_5% R303 40mil
CR_DATA0 7 1 2 @
SD_GND A0@ A0@ 0_0805_5%
1
CR_DATA1 15
5
1
12
CR_DATA2 11
MS_DATA0 SD_GND
6 CR_PW R_XD_ALE
A0@ 40mil
tt
MS_DATA1 MS_GND 2 U16
P
CR_DATA3 14 24 B CR_PW R_EN#
CR_CLK_XD_RY_BY# MS_DATA2 MS_GND 4 1 8
18 34 Y GND VOUT
MS_DATA3 XD_GND
CR_XD_CE#_MS_INS# 1 A 2 7 1C433 1 1
G
20 XD_GND 44 VIN VOUT C434
CR_CMD_XD_CLE MS_SCLK 3 6 C421
16 45 VIN VOUT
h
300_0603_5%
U13
EPAD
MS_INS GND 5
0.1U_0402_16V4Z
4
1
3
9 GND 46 MC74VHC1G08DFT2G_SC70-5 EN FLG A0@ A0@
MS_BS
0.1U_0402_16V4Z
1 A0@
0.1U_0402_16V4Z
2
4.7U_0603_6.3V6K
C381 R304 2 2
TAITW_R013-P12-HM_NR
9
@ A0@
2
AP2301MPG-13_MSOP8
2
CR_XD_DETECT#
1
D
CR_PW R_EN#
2 Q22
A G SSM3K7002F_SC59-3 A
S
3
LAN Magnetic & RJ45
Custom 0.1
5 4 3 2
Sheet 36 of 59
A B C D E
For Wireless LAN

+3VS_WLAN +1.5VS +3VS_WLAN
1 1 1 1 1 1
C403 C735 C392 C734 C423 C387
+3VS R324 +3VS_WLAN 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0_1206_5% 60mil 2 2 2 2 2 2
2 1
1 Mini Card Power Rating 1
+1.5VS +3VS_WLAN
@ R702
0_0402_5% JMINI1
15,35,38,45 PCH_PCIE_WAKE# 1 2 1 2
1 2
3 3 4
4
5 5 6
6
14 MINI1_CLKREQ# 7 8
7 8
9 9 10
10
14 CLK_PCIE_MINI1# 11 12
11 12
14 CLK_PCIE_MINI1 13 14
13 14 WLAN&BT Combo module circuits
15 16
15 16
17 18 WL_OFF#
17 18 BT BT
19 19 20 PLT_RST_BUF# WL_OFF# 17
20
21 21 22
22 +3VS_MINI1 PLT_RST_BUF# 17 on module on module
14 PCIE_PRX_DTX_N2 23 24 R342 1 2 0_0603_5% +3VS
14 PCIE_PRX_DTX_P2 23 24 Enable Disable
25 26
25 26
27 27 28 MINI1_SMBCLK
28 R337 1 @ 2 0_0402_5% PCH_SMBCLK 5,14
29 30
/
29 30 MINI1_SMBDATA R335 BT_CTRL
14 PCIE_PTX_C_DRX_N2 31
31 32
32 1 @ 2 0_0402_5% PCH_SMBDATA 5,14 H L
14 PCIE_PTX_C_DRX_P2 33 34
33 34 BT_ON#
35 36 USB20_N8 17
/x
35 36 L H
37 38 USB20_P8 17
37 38
39 39 40
+3VS_WLAN 40
41 42 R306 1 2 0_0402_5%
41 42 MINI1_LED# 39
43 44
43 44
45 46
45 46
E51TXD_P80DATA_R 47
47 48
48 (9~16mA)
1
R299 1 2 0_0402_5% E51RXD_P80CLK_R
su
39 E51TXD_P80DATA 49 50 D32
39 E51RXD_P80CLK 49 50
2 R287 1 2 0_0402_5% 51 52 R305 SUSP# BT_CTRL 2
51 52 39,43,51,52 SUSP# 1 2
100K_0402_5%
53 54
1
GNDGND CH751H-40PT_SOD323-2
2
1
1
ACES_51711-0520W-001 D
R300
p.
R288 +3VS_WLAN Q57
100K_0402_5% 1K_0402_1% 18,38 BT_ON# 2
CONN@ G
2
SSM3K7002F_SC59-3 S
3
2
om
BT_CTRL
Reserve
yc
+3VS_FULL +1.5VS +3VS_FULL
60mil
m
+3VS 2 1 +3VS_FULL 1 1 1
1 1 1 C466
R352 0_1206_5% C455 C467 C441
C443 C442 0.1U_0402_16V4Z
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2
2 2 2
//
3 +1.5VS +3VS_FULL +3VS
For 3G / GPS 3
PCH_PCIE_WAKE#
@ R371 JMINI2 To 3G Module Connect
p:
0_0402_5% 1 2
(WLAN_BT_DATA) 1 2 1
1 2
(WLAN_BT_CLK)
3
3 4 4 The same circuit with JMINI1, C531
5 6
5 6 but different PCIE & USB.... 3G@
14 MINI2_CLKREQ# 7 8
7 8 0.1U_0402_16V4Z
9 9 10 2
10
tt
14 CLK_PCIE_MINI2# 11 11 12
12
14 CLK_PCIE_MINI2 13 13 14
14 J3G1 +3VS +3VS
15 15 16
16 22 20
17 17 18 WL_OFF# GND 20
19 18 19
20
h
19 20 PLT_RST_BUF# 19
21 22 18 18
21 22 +3VS_MINI1 +3VS
14 PCIE_PRX_DTX_N3 23 23 24 +3VS Peak: 2.75A 17 17
2
14 PCIE_PRX_DTX_P3 24 R343 1 2 0_0603_5% 16
25 26
27
25 26
28
Normal: 1.1A 16
15 R405
27 28 MINI2_SMBCLK PCH_SMBCLK 15
29 30 MINI2_SMBDATA R334 1 @ 0_0402_5%PCH_SMBDATA 14 14 100K_0402_5%
29 30 2 13
14 PCIE_PTX_C_DRX_N3 31 32 R333 1 @ 0_0402_5% 13 WWAN_OFF# 3G@
31 32 2 12
14 PCIE_PTX_C_DRX_P3 33 34 USB20_N11_R USB20_N11 12 MINI2_LED# WWAN_OFF# 17
1
33 34 11 MINI2_LED# 39
35 36 USB20_P11_R R332 1 2 0_0402_5%USB20_P11 USB20_N11 17 1 11
35 36 1 1 10
37 38 R331 1 0_0402_5% USB20_P11 17 10 USB20_N9_R1
37 38 2 + C535 9 R404 0_0402_5%
39 40 C527 C537 9 USB20_P9_R1 USB20_N9 17
39 40 330U_6.3V_R15M 8 3G@ 2
+3VS_FULL 41 42 MINI2_LED# 3G@ 3G@ 8 1 3G@ USB20_P9 17
41 42 R329 1 2 0_0402_5% 3G@ 7 1 2
43 44 2 2 10U_0603_6.3V6M 7 R402 0_0402_5%
43 44 2 6
45 46 6 USB20_N12 17
45 46
E51TXD_P80DATA_R 47
47 48
48 (9~16mA) 47P_0402_50V8J 5
5
4
USB20_P12 17
E51RXD_P80CLK_R 49 50 4
49 50 3
51 52 3
51 52 2
2
53 54 21 1
GND1 GND2 GND 1
4 Close to 3G CONN 4
ACES_87213-2000G
BELLW_80003-1021 CONN@
CONN@

MINI CARD (WLAN & TV-Tuner)
Custom 0.1
A B C D Date: Friday, August 27, 2010 E Sheet 37 of 59
A B C D E
USB3.0 Conn.
1
USB/B Conn. 1
36
35
34
33
32
31
ACES_50050-03071-001_30P
W=100mils
GND
GND
GND
GND
GND
GND
30 29 +5VALW
30 29 PCIE_PTX_C_DRX_P4 14
28 27 PCIE_PTX_C_DRX_N4 14 JUSB1
28 27
26
24
26 25 25
23
PCIE_PRX_DTX_P4 14 (Port 0,1) 1
24 23 PCIE_PRX_DTX_N4 14 1
22 21 CLK_PCIE_USB30 14 2
22 21 2
20 19 CLK_PCIE_USB30# 14 3 3
20 19
18 17 USB20_N3 17 4 4
18 17 SYSON#
18,45 SMIB 16 15 USB20_P3 17 43,45 SYSON# 5
16 15 5
15,35,37,45 PCH_PCIE_WAKE# 14 13 PLT_RST# 5,17,35,39,45 6
14 13 USB20_N1 6
39,43,45,50 SYSON 12 11 17 USB20_N1 7
12 11 USB20_P1 7
+1.5V 10 10 9 9 USB30_CLKREQ# 14 OD output 17 USB20_P1 8
8
8 7 +3VALW 9
8 7 USB20_N0 9
6 5 17 USB20_N0 10 10
6 5 USB20_P0
+5VALW 4 3 +5VALW 17 USB20_P0 11 11 13
4 3 GND
2 1 12 14
2 1 12 GND
CONN@ JUSB3
ACES_85201-1205N
/
CONN@
/x
su
2 2
p.
om
BT Conn.
yc
+BT_VCC
(Port 11) JBT1

10 8
GND 8
7
m
7
6 USB20_P13 17
6
5 USB20_N13 17
5 (WLAN_BT_DATA)
4
4 (WLAN_BT_CLK)
3
3
2
// 9
2
GND 1
1
BT Wire Cable Note:
3 ACES_87213-0800G 3
CONN@ Pin 3, Pin 4 NC
p:
+3VALW
+3VS
2
C736
tt
BT@ 1
0.1U_0402_16V4Z C731
3
1 BT@
BT_ON# Q41
18,37 BT_ON# 1 BT@ 2 2 1U_0603_10V6K
h
R710 2
10K_0402_5%
2 AP2301GN-HF_SOT23-3
C738
1
BT@
0.1U_0402_16V4Z W=40mils
1 +BT_VCC
1
1
C730 C729 R709
BT@ BT@ 300_0603_5%
4.7U_0805_10V4Z BT@
2
2
0.1U_0402_16V4Z
1
D
2 Q42
4
G 4
SSM3K7002F_SC59-3 S
3
BT@

USB / BT / USBB
Custom 0.1
A B C D E
5 4 3 2 1
+3VALW
EC_MUTE# R362 2 @ 1 10K_0402_5%

65W/90W# R701 2 1 100K_0402_5%
3S/4S# R700 2 1 100K_0402_5%
+5VS
R311 L21
+3VALW 0_0805_5% FBMA-L11-160808-800LMT_0603 TP_CLK R363 1 2 4.7K_0402_5%
1 2 +3VALW_EC 1 2 +EC_VCCA
TP_DATA R364 4.7K_0402_5%
1 1 1 1 2 2 1 1 2
0.1U_0402_16V4Z
C456
0.1U_0402_16V4Z
C728
0.1U_0402_16V4Z
C418
1000P_0402_50V7K
C400
1000P_0402_50V7K
C399
0.1U_0402_16V4Z
C720
C457
D D
0.1U_0402_16V4Z +3VS
ECAGND
@R675
@ R675 2 2 2 2 1 1 2
@ C714
22P_0402_50V8J 33_0402_5% @
2 1 CLK_PCI_LPC BKOFF# R735
2 1 2 1 100K_0402_5%
111
125
22
33
67
96
U20
9 VCC
VCC
VCC
AVCC
VCC
VCC
VCC
+3VALW
EC_RST#
+3VALW R328 2 1 47K_0402_5% GATEA20 R676 2 1 200K_0402_5%
MINI2_LED#
18 GATEA20 1 21 MINI2_LED# 37
C431 2 0.1U_0402_16V4Z EC_KBRST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP#
1 18 EC_KBRST# 2 23 BEEP# 41
SERIRQ KBRST#/GPIO01 BEEP#/PWM2/GPIO10
13 SERIRQ LPC_FRAME# 3 SERIRQ# 26 ACOFF 2 1 ACIN 15,43,44,47
FANPWM1/GPIO12
13 LPC_FRAME# LPC_AD3 4 LFRAME# 27 ACOFF 46,47 D23 CH751H-40PT_SOD323-2
ACOFF/FANPWM2/GPIO13
13 LPC_AD3 LPC_AD2 5 LAD3 ECAGND EC_ACIN C719
13 LPC_AD2 LPC_AD1 7 PWM Output BATT_TEMP C452 2 1 100P_0402_50V8J 2 1 100P_0402_50V8J
+3VALW LAD2
13 LPC_AD1 LPC_AD0 8 63 BATT_TEMP 49
10/1 ENE Recommand LAD1 BATT_TEMP/AD0/GPIO38
LAD0 LPC & MISC
13 LPC_AD0 10 64 ADP_I
BATT_OVP/AD1/GPIO39
KSO1 CLK_PCI_LPC 65 AD_BID0 ADP_I 47,49
ADP_I/AD2/GPIO3A
12 AD Input
/
R336 1 2 47K_0402_5% 17 CLK_PCI_LPC PLT_RST# PCICLK 66
13 AD3/GPIO3B
KSO2 5,17,35,38,45 PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 75 IMON_R
R339 1 2 47K_0402_5% 37 76 R356 2 IMVP_IMON 54
EC_SCI# ECRST# SELIO2#/AD5/GPIO43 1 0_0402_5%
18 EC_SCI# 20 R367
/x
SCI#/GPIO0E
EC_SMI# 38 CLKRUN#/GPIO1D DAC_BRIG VR_HOT# 0_0402_5%
R682 1 2 1K_0402_5% 68 EN_DFAN1 DAC_BRIG 31 54 VR_HOT# H_PROCHOT# 5,49
DAC_BRIG/DA0/GPIO3C 2 1
EC_SMB_DA1 70 IREF EN_DFAN1 42
EN_DFAN1/DA1/GPIO3D
R359 1 2 2.2K_0402_5% KSI0 DA Output 71 CALIBRATE# IREF 47
1
IREF/DA2/GPIO3E D
KSI1 55 72 CALIBRATE# 47 H_PROCHOT#_EC
KSI0/GPIO30 DA3/GPIO3F 2 Q26
EC_SMB_CK1 KSI2 56
KSI1/GPIO31
su
KSI3 57 EC_MUTE# G SSM3K7002F_SC59-3
R358 1 2 2.2K_0402_5% KSI2/GPIO32
C KSI4 58 83 EC_MUTE# 41 S C
3
KSI3/GPIO33 PSCLK1/GPIO4A GFX_CORE_PWRGD
KSI5 59 84 WWAN_LED# GFX_CORE_PWRGD 54
@ R357 KSI4/GPIO34 PSDAT1/GPIO4B
@ C462 KSI6 60 85 H_PROCHOT#_EC WWAN_LED# 40
33_0402_5% KSI5/GPIO35 PSCLK2/GPIO4C
22P_0402_50V8J KSI7 61 KSI6/GPIO36
PS2 Interface PSDAT2/GPIO4D 86 TP_CLK
2 1 1 2 KSI[0..7] KSO0 62 KSI7/GPIO37 87 TP_DATA TP_CLK 40 Latest design guide suggest change QE1 to
TP_CLK/PSCLK3/GPIO4E
p.
40 KSI[0..7] KSO1 39 88 TP_DATA 40
KSO[0..17] KSO2 40
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 74LVC1G06.
Reserve for EMI please close to U44 40 KSO[0..17] KSO1/GPIO21
KSO3 41 KSO2/GPIO22
KSO4 42 97 65W/90W#
KSO3/GPIO23 SDICS#/GPXOA00 65W/90W# 47,49
+3VS KSO5 43 98 HDA_SDO
KSO4/GPIO24
om
44 Int. K/B SDICLK/GPXOA01 HDA_SDO 13
KSO6 KSO5/GPIO25 99 LID_SW# +3VALW
45 SDIDO/GPXOA02 LID_SW# 40
EC_SMB_CK2 KSO7 KSO6/GPIO26 Matrix 109
R360 1 2 2.2K_0402_5%
KSO8 46
KSO7/GPIO27
SPI Device Interface SDIDI/GPXID0
EC_SMB_DA2 KSO9 47 EC_SI_SPI_SO
KSO8/GPIO28 EC_SI_SPI_SO 40
KSO10 48 119 EC_SO_SPI_SI LID_SW#
R361 1 2 2.2K_0402_5% KSO9/GPIO29 SPIDI/RD# R696 2 1 100K_0402_5%
KSO11 49 120 EC_SPICLK EC_SO_SPI_SI 40
KSO10/GPIO2A SPIDO/WR#
EC_SCI# KSO12 50
KSO11/GPIO2B
SPI Flash ROM 126 EC_SPICS#/FSEL# EC_SPICLK 40
KSO13 51 SPICLK/GPIO58 EC_SPICS#/FSEL# 40
R685 1 2 10K_0402_5% KSO12/GPIO2C 128
yc
KSO14 52 SPICS#
KSO15 KSO13/GPIO2D
53
KSO16 KSO14/GPIO2E
54
KSO15/GPIO2F 73 EC_PECI
CIR_RX/GPIO40 H_PECI 5,18
R679 1
PLT_RST# KSO17 81 74 FSTCHG R355 1 2 43_0402_1%
2 100K_0402_5% KSO16/GPIO48 CIR_RLC_TX/GPIO41 FSTCHG 47
82 KSO17/GPIO49 89 BATT_GRN_LED#
FSTCHG/SELIO#/GPIO50 BATT_GRN_LED# 40
90
m
EC_SMB_CK1 BATT_CHGI_LED#/GPIO52
91 BATT_AMB_LED# C815
49 EC_SMB_CK1 EC_SMB_DA1 GPIO CAPS_LED#/GPIO53 BATT_AMB_LED# 40 R780
77
SCL1/GPIO44 92 PWR_LED EC_SPICLK
49 EC_SMB_DA1 EC_SMB_CK2 BATT_LOW_LED#/GPIO54 SYSON PWR_LED 40 1 2
78 93 1 2
14,22 EC_SMB_CK2 EC_SMB_DA2 SDA1/GPIO45 SM Bus SUSP_LED#/GPIO55 VR_ON SYSON 38,43,45,50 @
79 95 @
14,22 EC_SMB_DA2 SCL2/GPIO46 SYSON/GPIO56 VR_ON 54
80 121 EC_ACIN 22_0402_5% 0.01U_0402_16V7K
// SDA2/GPIO47 VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59 127
PM_SLP_S3# PCH_RSMRST# For EMI request
B PCH_RSMRST# 15 B
15 PM_SLP_S3# PM_SLP_S5# 6
EC_SMI# PM_SLP_S3#/GPIO04 100 EC_LID_OUT#
15 PM_SLP_S5# 14 EC_RSMRST#/GPXO03 EC_LID_OUT# 14
EC_XCLK1 18 EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 EC_ON
EC_XCLK0 EC_ON 40,48
EC_PME# 15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 3S/4S#
35 EC_PME# 3S/4S# 47
p:
MINI1_LED# 16 PCH_PWROK
103 BKOFF#
37 MINI1_LED# LID_SW#/GPIO0A EC_SWI#/GPXO06 PCH_PWROK 15
17 SUSP#/GPIO0B 104
@1 1 @ ICH_PWROK/GPXO06 BKOFF# 31
C723 C721
SUS_PWR_DN_ACK 18 PBTN_OUT#/GPIO0C GPO 105
15 SUS_PWR_DN_ACK INVT_PWM 19 GPIO BKOFF#/GPXO08
106
4
1
31 INVT_PWM FAN_SPEED1 EC_PME#/GPIO0D WL_OFF#/GPXO09

15P_0402_50V8J 15P_0402_50V8J 42 FAN_SPEED1
25
EC_THERM#/GPIO11 GPXO10 107 SA_PGOOD SA_PGOOD 51
tt
28
OSC
OSC
2 2 FAN_SPEED1/FANFB1/GPIO14 108
E51TXD_P80DATA 29 GPXO11
37 E51TXD_P80DATA E51RXD_P80CLK FANFB2/GPIO15
30 PM_SLP_S4#
37 E51RXD_P80CLK ON/OFF EC_TX/GPIO16 PM_SLP_S4# 15
31 EC_RX/GPIO17 110 ENBKL
NC
NC
@ 40 ON/OFF PWR_SUSP_LED# 32 PM_SLP_S4#/GPXID1 EAPD ENBKL 16,22

h
40 PWR_SUSP_LED# WLAN_LED# ON_OFF/GPIO18 ENBKL/GPXID2 112 EAPD 41

34 VGATE
40 WLAN_LED# PWR_LED#/GPIO19 114 SUSP# VGATE 15,54
36 GPI GPXID3
3
2
115 PBTN_OUT#
2
NUMLED#/GPIO1A GPXID4 SUSP# 37,43,51,52
X1 116 PBTN_OUT# 5,15 R691
GPXID5
32.768KHZ_12.5PF_Q13MC14610002 EC_XCLK1 117 100K_0402_5%
GPXID6
EC_XCLK0 118 +V18R
GPXID7
15 SUSCLK 122 15mil
XCLK1
1
1 2 123 124 1
XCLK0 V18R
R697 0_0402_5% C398
AGND
11 GND
24 GND
35 GND
94 GND
113 GND
4.7U_0805_10V4Z
R769 2 2
1 100K_0402_5% KB930QF A1 LQFP 128P
20mil
69
ECAGND L23
Board ID 2 1
FBMA-L11-160808-800LMT_0603
+3VALW
Analog Board ID definition,
Please see page 3.
A A
2
Ra R354
100K_0402_5%
AD_BID0
11
8.2K_0402_5%
1
R353
Rb
C454
0.1U_0402_16V4Z
2
EC ENE-KB930
2
Custom 0.1
MAY BE USED3 BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 2 1
1 2 3 4 5 6 7 8
+3VALW 1 2 C722 1 2 0.1U_0402_16V4Z

R688 0_0603_5%
+3VALW
+SPI_VCC
U38 <BOM Structure>

ON/OFF BTN
2
EC_SPICS#/FSEL# 1
39 EC_SPICS#/FSEL# SPI_WP# CE# VDD 8 EC_SPICLK_R R698 1 ON/OFFBTN#
R694 1 2 4.7K_0402_5% 3
WP# SCK 6 2 0_0402_5% EC_SPICLK 39 R144
R690 1 2 4.7K_0402_5%SPI_HOLD# 7 EC_SO_SPI_SI_R R699 1 2 0_0402_5% 100K_0402_5%
+3VALW HOLD# SI 5 EC_SI_SPI_SO_R R692 1
EC_SO_SPI_SI 39
4 VSS SO 2 2 0_0402_5% EC_SI_SPI_SO 39
1
MX25L1005AMC-12G_SOP8
EC_SPICLK_R SW1 2
A ON/OFF 39 A
JKB1 SMT1-05-A_4P
1 3 1
KSO0
2
1 1
KSO1 2 4 3 51ON#
2 51ON# 46
KSO2 2
3 @
KSO3 3
4 0_0402_5% R695 D6
6
5
KSO4 4 CHN202UPT_SC70-3
5 KSI[0..7]
KSO5 5
1
6 KSI[0..7] 39
1
KSO6 6 @ D
KSO7 7 KSO[0..17]
7 C727 EC_ON Q7
8 KSO[0..17] 39 39,48 EC_ON 2
KSO8 8 33P_0402_50V8K G SSM3K7002F_SC59-3
KSO9 9
9
2
10 S
3
KSO10 10
KSO11 11 R104
11
KSO12 12
12
KSO13 13 10K_0402_5%
13
KSO14 14 14
1
15
KSO15
KSO16
KSO17
16
17
15
16
17
KB Conn.
KSI0 18
18
/
KSI1 19
19
KSI2 20
20
KSI3 21
21
22
PWR/B
/x
KSI4 22
KSI5 23 23
KSI6 24 24
KSI7 25 25 27
G1 JPWR1
26 26 28 +3VS
G2 1 +3VALW
1 LID_SW#
2 LID_SW# 39
2
su
ACES_85201-26051 3
3
B CONN@ 4 B
4
5 +3VS
2
+3VS 5 PWR_LED#
KSO16 6
C261 1@ 2 100P_0402_50V8J R496 @ 6 ON/OFFBTN#
7
7
KSO17 8
C262 1@ 100P_0402_50V8J 10K_0402_5% 8
p.
2 9
GND
10
1
KSO15 C260 1@ 100P_0402_50V8J KSO7 C252 1@ 100P_0402_50V8J GND
2 2
5
U8 ACES_85201-0805N
KSO14 C259 1@ KSO6
2 100P_0402_50V8J C251 1@ 2 100P_0402_50V8J 2 CR_5IN1_LED# 35 CONN@
P
MEDIA_LED# B
om
KSO13 KSO5 4
C258 1@ Y
2 100P_0402_50V8J C250 1@ 2 100P_0402_50V8J 1 PCH_SATALED# 13
A
G
KSO12 KSO4
C257 1@ 100P_0402_50V8J C249 1@ 100P_0402_50V8J MC74VHC1G08DFT2G_SC70-5
2 2
3
<BOM Structure>
KSI0 KSO3
C263 1@ 2 100P_0402_50V8J C248 1@ 2 100P_0402_50V8J
KSO11 C256 1@ 100P_0402_50V8J KSI4 LED7
2
yc
C267 1@ 2 100P_0402_50V8J HT-191NB5_BLUE
KSO10
KSI1
C255 1@
C264 1@
2
2
100P_0402_50V8J
100P_0402_50V8J
KSO2
KSO1
C247 1@
C246 1@
2
2
100P_0402_50V8J
100P_0402_50V8J
+3VS 1 2
R380 2.2K_0402_5% 2
B
1
MEDIA_LED#
TP Conn. +5VS
m
KSI2 KSO0 JTP1
LED3
C265 1@ 2 100P_0402_50V8J C245 1@ 2 100P_0402_50V8J HT-191NB5_BLUE 1 1
KSO9 KSI5 2 TP_CLK 39
C268 1@ 2 100P_0402_50V8J 2 TP_DATA 39
C254 1@ 100P_0402_50V8J 3 3 LEFT_BTN#
2 2 1
KSI3 KSI6 4 RIGHT_BTN#
B 4
KSO8
C266 1@
C253 1@
2 100P_0402_50V8J
100P_0402_50V8J KSI7
C269 1@ 2 100P_0402_50V8J
// 5
6
5
6
2 7
C C270 1@ 2 100P_0402_50V8J LED8 GND 1 1 C
HT-191NB5_BLUE 8
GND
WWAN_LED# C217 C216
+3VS WWAN_LED# 39 ACES_85201-0605N @ @
1 2 2 1 CONN@ 2 2
B
p:
R381 2.2K_0402_5%
100P_0402_50V8J 100P_0402_50V8J
TP_CLK LEFT_BTN#
EC Request LED4
WLAN_LED# TP_DATA RIGHT_BTN#
tt
LED5 +3VS WLAN_LED# 39

PWR_LED# 1 2 2 1
+3VALW
1 2 R377 3.9K_0402_5% A
2 1
R374 2.2K_0402_5% +5VS
2
B
3
HT-191UD5_AMBER
D4 D3
h
HT-191NB5_BLUE 1 PJDLC05C_SOT23-3 PJDLC05C_SOT23-3

LED1 C196
PWR_SUSP_LED#
+3VALW 1 2 PWR_SUSP_LED# 39 0.1U_0402_16V4Z
R378 2
3.9K_0402_5% 1 LED6
A 2
BATT_GRN_LED#
+3VALW 1 2 2 1 BATT_GRN_LED# 39
HT-191UD5_AMBER B
R379 2.2K_0402_5%
1
HT-191NB5_BLUE
SW2
SW3
SMT1-05-A_4P
PWR_LED# LED2 LEFT_BTN# RIGHT_BTN# SMT1-05-A_4P
3 1
1 BATT_AMB_LED# 3 1
2 BATT_AMB_LED# 39
R376 2
3.9K_0402_5% 1 4 2
A 4 2
5
6
1
D HT-191UD5_AMBER
5
6
39 PWR_LED
2 Q32
D G D
SSM3K7002F_SC59-3
2
S
3
R512
100K_0402_5%
1

BIOS, I/O Port & K/B Connector
Custom 0.1
1 2 3 4 5 6 Date:
7 Friday, August 27, 2010 Sheet 8 40 of 59
5 4 3 2 1
1 2
R711 0_0805_5% +VDDA
+5VS
60mil 1
U40
40mil Int. Speaker Conn.
IN
1 OUT 5 +VDDA
1
C737 2
GND
4.75V +3VS
R712 20mil JSPK1
0.1U_0402_16V4Z 3 4 1 2 10K_0402_5% SPKR+ R46 1 2 0_0603_5% SPK_R+ 1
2 SHDN BYP SPKR- SPK_R- 1
C741 R47 1 2 0_0603_5% 2
G9191-475T1U_SOT23-5 2
0.01U_0402_16V7K
3
2
@ @ 1 2
1
C739 1U_0402_6.3V4Z D2 3
1
D30 G1
(output = 300 mA) CH751H-40PT_SOD323-2
R725
R728
PJDLC05C_SOT23-3 4
G2
@
D 10K_0402_5% 10K_0402_5% ACES_88266-02001 D
CONN@
2
SM010014520 3000ma 220ohm@100mhz DCR 0.04 C766
2
+PVDD_HDA MONO_IN
1 2
1U_0402_6.3V4Z
1
+PVDD_HDA
1
+VDDA L46 2 1 0.1U_0402_16V4Z C
FBMA-L11-201209-221LMA30T_0805 R723
@
1 1 20mil 39 BEEP# C759 1 2 1 2 2 1
R729
2
C748 B Q44
C745 1U_0402_6.3V4Z 560_0402_5% E 2.4K_0402_1%
SPKL+
20mil SPK_L+
JSPK2
3
10U_0805_10V4Z 2SC2411K_SOT23-3 R8 1 2 0_0603_5% 1
2
2 R724 SPKL- R7 SPK_L- 1
@ 2 13 PCH_SPKR C771 1 21 2 1 2 0_0603_5% 2
R713 2
3
0_0603_5%
1
560_0402_5%
1U_0402_6.3V4Z
Place near Pin46 <BOM Structure> D29 D1 3
G1
PJDLC05C_SOT23-3 4
1
CH751H-40PT_SOD323-2 G2
SM010014520 3000ma 220ohm@100mhz DCR 0.04 @
ACES_88266-02001
2
CONN@
+PVDD1_HDA
+VDDA L50 2 1
FBMA-L11-201209-221LMA30T_0805 1
0.1U_0402_16V4Z
1 20mil HD Audio Codec
C749
1
C750
10U_0805_10V4Z
/
2
2
SM010030010 200ma 120ohm@100mhz DCR 0.2
Singatron 2SJ2326
/x
Place near Pin39 DC021007151
SM010030010 200ma 120ohm@100mhz DCR 0.2
10mil +3VS_DVDD
+3VS
+AVDD_HDA 10U_0603_6.3V6M
L48 2 1
BLM18AG121SN1D_0603
L51 2 1 0.1U_0402_16V4Z
10mil 1 1 1 C751
2
2 Headphone Out
+VDDA C754 C761 C753 C747
BLM18AG121SN1D_0603 1 JHP1
su
1 330P_0402_50V7K COM_MIC
1 0.1U_0402_16V4Z 3
C772 2 1 330P_0402_50V7K
C C752 2 2 1 6 C
C756
0.1U_0402_16V4Z HP_LEFT HPOUT_L_2
10U_0805_10V4Z
2
2 2 Place near Pin1, 9 R716 1 2 75_0603_5% HPOUT_L_1 1
1 2
0.1U_0402_16V4Z HP_RIGHT HPOUT_R_1 L49 FBMA-L11-160808-700LMT_2P
HPOUT_R_2
25
38
46
39
R714 1 2 75_0603_5% 1 2 2
p.
Place near Pin25, 38 U41 L47 FBMA-L11-160808-700LMT_2P 4
DVDD
DVDD_IO
AVDD1
AVDD2
PVDD2
LINE2_C_L PVDD1 SM010004010 300ma 70ohm@100mhz DCR 0.3 HP_PLUG#
INT_MIC_R INT_MIC 14 5
Internal MIC 2 1 C770 1 2 LINE2_L
LINE2_C_R
4.7U_0603_6.3V6K
R726 1K_0402_5%
C769 1 2
15
LINE2_R 35mA SPKL+
68mA 600mA
om
MIC2_C_L
4.7U_0603_6.3V6K 40
SPK_OUT_L+ SINGA_2SJ2326-001111
COM_MIC COM_MIC_R C765 1 2 16 MIC2_L
Combo MIC 4.7U_0603_6.3V6K SPKL- +MIC2_VREFO CONN@
2 1 MIC2_C_R
C764 1 2 17 41
R719 1K_0402_5% MIC2_R SPK_OUT_L-
4.7U_0603_6.3V6K SPKR+
23 45
1
LINE1_L SPK_OUT_R+
MIC2JD R722
24 LINE1_R SPKR- MIC_PLUG#
MIC1_L MIC1_C_L 44 2.2K_0402_5%
SPK_OUT_R-
yc
C763 1 2 21
External MIC MIC1_L HP_LEFT HP_PLUG#
4.7U_0603_6.3V6K
1
MIC1_R MIC1_C_R 32 D
2
HPOUT_L COM_MIC
C762 1 2 22 MIC1_R HP_RIGHT 2
2
3
4.7U_0603_6.3V6K 33 Q43 G 1 2 +MIC1_VREFO
HPOUT_R R720
35 HDA_SDIN0_AUDIO BSS138_NL_SOT23-3 S D28
1 CBN HDA_SDIN0 13 1 22K_0402_5%
3
SDATA_IN 8 C746 PJDLC05C_SOT23-3
1 R721 2
m
C755 33_0402_5%
HDA_SDOUT_AUDIO 13
2.2U_0402_6.3VM 36 SDATA_OUT 5 10U_0805_10V4Z
CBP
2 2
Combo MIC +MIC2_VREFO HDA_SYNC_AUDIO 13
2
2
29 MIC2_VREFO 10
10mil SYNC
D26 D27
11 HDA_RST_AUDIO# 13
Internal MIC RESET#
// CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2
1
30
10mil MIC1_VREFO_R HDA_BITCLK_AUDIO 13
6
External MIC +MIC1_VREFO BCLK
1
1
31 @
10mil MIC1_VREFO_L
B +INTMIC_VREFO B
1
1 2 C757 For EMI
22P_0402_50V8J
C760 1 2
1
R717
@ 2
0_0402_5% R705 R708 MIC JACK
p:
10U_0805_10V4Z 28 LDD_CAP 4.7K_0402_5%

2 4.7K_0402_5%
GPIO0/DMIC_DATA JMIC1
2
1
3 MIC1_L MIC1_L_1 MIC1_L_R
R730 GPIO1/DMIC_CLK L45 1 2 2
19
2 1 JDREF EC_MUTE# 39 MIC1_R 1 MIC1_R_1
2
FBMA-L11-160808-700LMT_2P MIC1_R_R
4
tt
20K_0402_1% PD# R707 1K_0603_5% 3

1 2 L44 1 2
3
MONO_IN R706 1K_0603_5% FBMA-L11-160808-700LMT_2P 4
HP_PLUG#
12
SM010004010 300ma 70ohm@100mhz DCR 0.3 MIC_PLUG#
MIC_PLUG# 2 1 C758 1 SENSE_A 10mil 34
2 2.2U_0402_6.3VM CPVEE PCBEEP 1 5
h
R731 39.2K_0402_1% MIC2JD SENSE_B 1 C733

13 20
2 1 1 2 SENSE A MONO_OUT C732
18 SENSE B 37 220P_0402_50V7K
R727 39 20K_0402_1%
EAPD R718 20K_0402_1% AVSS2 CODEC_VREF
47 220P_0402_50V7K 2 6
1 2 EAPD C767 1
VREF
27
10mil 2 0.1U_0402_16V4Z 2 D25
R715 0_0402_5% 48
SPDIFO PJDLC05C_SOT23-3 SINGA_2SJ-A960-C01
C768 1 2 10U_0805_10V4Z
1
Place next pin27 CONN@
7 26
DVSS AVSS1
43
PVSS2
49 42
GND PVSS1 +INTMIC_VREFO
ALC271X-GR_QFN48_7X7
DGND AGND
SM010004010 300ma 70ohm@100mhz DCR 0.3
INT_MIC_L
For EMI
Int. MIC
1
R394
15mil
10K_0402_5% 15mil
INT_MIC_R L24 INT_MIC_L
3
1 2 JMIC2
2
D16 FBMA-L11-160808-700LMT_2P 1
1
1 2
A C500 2 A
@
220P_0402_50V7K 3
2 G1
PJDLC05C_SOT23-3 4
G2
PJ1 PJ2 ACES_88266-02001
@ JUMP_43X39 @ JUMP_43X39
1
CONN@
1 1
2 2 1 1
2 2
PJ3
@ JUMP_43X39
PJ4
@ JUMP_43X39
1 1 Issued Date 2010/08/11 Deciphered Date 2011/08/11 Title
1 1
2 2 2 2
PJ5 PJ6
@ JUMP_43X39 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC271X
@ JUMP_43X39 Size Document Number Rev
1 1
1 1
2 2 2 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
GND GNDA GND GNDA
5 4 3 2
Sheet 41 of 59
FAN Stand-Off JUSB3 Stand-Off
H1 H2 H3 H4 H5 H6 H7
H_3P4 H_3P4 H_3P4 H_3P4 H_3P4 H_3P4 H_3P4
@ @ @ @ @ @ @
1
1
1
1
1
1
H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
@ @ @ @ @ @ @ @ @ @ @
1
1
1
1
1
1
1
1
1
1
1
/
H19 H20
/x
H_4P0 H_4P0
FAN1 Conn @ @
1
1
+5VS
C580 10U_0805_10V4Z
su
1 2
U30 H21 H22 H23 H24

1 8 H_4P2 H_4P2 H_4P2 H_4P2
VEN GND
2 7
VIN GND
p.
+VCC_FAN1 3 6
VO GND
39 EN_DFAN1 2 1 4 5 @ @ @ @
1
1
VSET GND
1
1
R509 0_0402_5%
1 APL5605KI_SOP8
om
C598 C585
0.1U_0402_16V4Z 10U_0805_10V4Z
2 @ H25 H26
1 2 H27
H_7P0N H_3P0N H_3P5X3P0N
+3VS C587
1000P_0402_50V7K
1 2 @ @ @
1
1
1
1
yc
R489
10K_0402_5%
40mil
JFAN1
2
+VCC_FAN1
1
39 FAN_SPEED1 2
m
3
1
C579 ACES_85205-03001
1000P_0402_50V7K // CONN@
2
FD1 FD3 FD2 FD4
@ @
p:
@ @
1
1
1
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
tt
h

FAN & Screw Hole
Custom 0.1
A B C D E
+5VALW
+1.5V to +1.5VS
+5VALW TO +5VS
2
+1.5V +1.5VS
U12 R246
+5VALW AO4430L_SO8 100K_0402_5%
U22 +5VS 8 1
DMN3030LSS-13_SOP8L-8 7 2 1 1
1
2
10U_0805_10V4Z
C375
1 1
0.1U_0402_16V4Z
C376
0.1U_0402_16V4Z
C377
SUSP
10U_0805_10V4Z
C374
1U_0603_10V4Z
C338
10U_0805_10V4Z
C339
8 1 6 3 52 SUSP
7 2 1 1 1 1 5 R245
2
6 3 1 1 470_0603_5%
6
2 2
1U_0603_10V4Z
C469
10U_0805_10V4Z
C468
1 1 5 R382
4
10U_0805_10V4Z
C465
10U_0805_10V4Z
C464 470_0603_5%
1
2 2 2 2 Q27A
4
2 2 2 DMN66D0LDW-7_SOT363-6
37,39,51,52 SUSP#
6
2 2
1
6
20mil 10mil 1.5VS_GATE
Q15A R251
+VSB 2 1 DMN66D0LDW-7_SOT363-6 2SUSP 10K_0402_5%
20mil 10mil 5VS_GATE SUSP
R269
+VSB 2 1 2 200K_0402_5% 1
2
1
R372 @ C380
510K_0402_5%
R268
20K_0402_5% 1 Q19A 0.1U_0603_25V7K
1
3
C470 DMN66D0LDW-7_SOT363-6
0.1U_0603_25V7K 2
SUSP 5
2
SUSP 2
5
Q15B
4
Q19B DMN66D0LDW-7_SOT363-6
4
/
1
D
ACIN 2 Q21
15,39,44,47 ACIN
/x
G SSM3K7002F_SC59-3
S
3
+5VALW
su
2 2
2
R383
100K_0402_5%
p.
1
+3VALW TO +3VS 38,45 SYSON#
om
+3VALW +3VS
3
U21
DMN3030LSS-13_SOP8L-8 +3VALW TO +3VALW_PCH(PCH AUX Power)
8 1 Q27B
7 2 SYSON 5
38,39,45,50 SYSON
2
10U_0805_10V4Z
C460
10U_0805_10V4Z
C459
1 1 6 3 DMN66D0LDW-7_SOT363-6
1 1
R369
1U_0603_10V4Z
C458
1
10U_0805_10V4Z
C461
4
470_0603_5% +3VALW +3VALW_PCH
R614 R373
yc
40mil
4
2 2 2 100K_0402_5%
2 2 1
6 1
2
10U_0805_10V4Z
C701
0_0805_5%
R368 10mil
20mil
m
47K_0402_5% 3VS_GATE SUSP
+VSB 2 2
2 1
Q25A
1
1 DMN66D0LDW-7_SOT363-6
3
C463
0.1U_0603_25V7K
SUSP 2
//
5
3 3
Q25B
4
p:
+5VALW TO +5VALW_PCH(PCH AUX Power)

tt
h
+5VALW +5VALW_PCH
R197
1 2
0_0603_5%
+0.75VS
+1.05VS_VTT +1.8VS +1.5V
1
R366
2
22_0603_5% R29 @ R365

470_0603_5% R508
470_0603_5% 470_0603_5%
4 4
2
1 1
11
D D
1
D
1
D SUSP SUSP SUSP SYSON#

Q5 2 Q34 2 Q24 2
Q23 2
G G G
G
S SSM3K7002F_SC59-3 S SSM3K7002F_SC59-3 S SSM3K7002F_SC59-3
3
S SSM3K7002F_SC59-3
3
3
3

DC Interface
Custom 0.1
A B C D E
A B C D E
+1.8VS to +1.8VSDGPU for GPU

+1.05VS_VTT to +1.05VSDGPU for GPU +1.8VS
+1.05VS_VTT +1.05VSDGPU
U25
AO4430L_SO8 4A
8 1
1 1
1 7 2 1
2
DIS@ 6 3 DIS@ 1
10U_0805_10V4Z
C498
C513 5 DIS@ R406
6
1
5
1U_0603_10V4Z
C499
10U_0805_10V4Z 470_0603_5%
2 2 DIS@ D Q10
4
2 R136 G
6 1
2 1 +1.8VS_GATE 3
+VSB
510K_0402_5% S S TR DMN3033LDM-7 1N TSOP6
DISO@ DISO@ +1.8VSDGPU
1
4
20mil DIS@ R409 10mil C198 300mA
510K_0402_5% 2 VGA_ON#
1.05VSDGPU_GATE 0.1U_0603_25V7K
+VSB 2 1
6
DIS@ Q29A 2
1
DMN66D0LDW-7_SOT363-6 DISO@
1 1
3
2
1
510K_0402_5%
@ C530 Q9A C194
R410
DIS@ VGA_ON# DISO@ R132
2
0.1U_0603_25V7K DISO@
VGA_ON# 5 2 DISO@ 2
10U_0805_10V4Z
1
470_0603_5%
3 1
2
DIS@ Q29B
4
DMN66D0LDW-7_SOT363-6 2N7002DWH_SOT363-6
/
1
D
ACIN 2 Q30 Q9B
15,39,43,47 ACIN
G VGA_ON# DISO@
5
VGA_ON
/x
S SSM3K7002F_SC59-3 14,17 DGPU_PWR_EN R140 2 1
3
@ 2N7002DWH_SOT363-6 0_0402_5% DIS@
4
su
2 2
+5VALW
2
DIS@
p.
R134
100K_0402_5%
2009/08/17 add VGA_ON#
1
VGA_ON#
53 VGA_ON#
om
+3VS to +3VSDGPU for GPU
+1.5V to +1.5VSDGPUH for GPU
1
+3VS D
+1.5V +1.5VSDGPUH 2 Q8
53 VGA_ON
U2 G SSM3K7002F_SC59-3
+3VSDGPU
1
AO4430L_SO8 @ S
3
8 1 R507 R135
yc
7 2 1 1 1 0_0805_5% DIS@
DIS@ DIS@ DIS@ 1 2
6 3 22K_0402_5%
10U_0805_10V4Z
C13
1 5 C602
DIS@
2
1U_0603_10V4Z
C12
R26 10U_0805_10V4Z
C7 2 2 2
470_0603_5%
4
10U_0805_10V4Z DIS@ 3 1
m
2 +3VALW Q33 100mil(1.5A)
1
1
20mil 10mil AP2301GN-HF_SOT23-3
6
2
2
DIS@ 1 DIS@
+VSB 2
R27
1
1.5VSDGPU_GATE
VGA_ON#
// R515
100K_0402_5% 3VSdelay_gate
DIS@
C590
R511
470_0603_5%
2 10U_0805_10V4Z
2
3 510K_0402_5% 1 Q3A DIS@ 2 3
C29
1
DIS@
1
DIS@
3
510K_0402_5%
DIS@ 1 2
6
1
DIS@ Q35A
R28
DMN66D0LDW-7_SOT363-6 R519
0.1U_0603_25V7K 1K_0402_5% 2N7002DWH_SOT363-6
VGA_ON# @ 2
3
p:
5 DIS@ 3VSdelay_gate
R514 DIS@ 2
2
DIS@ Q3B VGA_ON 1K_0402_5% 2N7002DWH_SOT363-6 1 DIS@

4
5 C612
1
DMN66D0LDW-7_SOT363-6 1 2
1
D Q35B
ACIN 1 0.1U_0603_25V7K
tt
2 Q4
4
G SSM3K7002F_SC59-3 DIS@ 2
S C603
3
0.1U_0603_25V7K 2
h
@ PJ28
2 1
2 1
JUMP_43X118
@ PJ27
+1.5VSDGPUH 2 1 +1.5VSDGPU
2 1
JUMP_43X118
1
+ DIS@
4 4
330U_2.5V_M_R15
C514
2

DC Interface
Custom 0.1
A B C D E
5 4 3 2 1
+3V_USB3.0 +1.05VR R660 1 @ 2 0_0402_5%

+1.5V to +1.05V Transfer Close to U3.D7 Close to U3.P13 USB30@
USB30@ USB30@ USB30@USB30@ USB30@ USB30@ L42 USB30@
For EMI request
+5VALW +1.5V +5VALW +1.05V_USB3.0
C715
C367
C718
C368
C697
C717
C401
C370
C696
C396
C695
C369
C716
U3TXDN2_L U3TXDN2
C389
C366
U18 2 1 1
+3VA_USB3.0 +3VA_USB3.0 2
10U_0603_6.3V6M
1U_0603_10V6K
+1.5V
C402
C420
1 1 6
VCNTL USB30@ USB30@ U3TXDP2_L U3TXDP2 R680 1 @ 2 0_0402_5%
3
5
VIN VOUT
3 1 1 1 1 1
1 1 1 1 1 1 1 1 11 3 4 4
+5VALW 9 4
VIN VOUT
0.01U_0402_16V7K
C379
8P_0402_50V8D
.1U_0402_16V7K
C397
8P_0402_50V8D
0.01U_0402_16V7K
C382
.1U_0402_16V7K
C406
USB30@ 1 1 1 @ USB30@ 1 1 1 @ OCE2012120YZF_0805 L43 USB30@
2 SYSON U2DP2_L U2DP2
C386
2
C405
8 2 22 2 2 1 1
EN 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
2 1 7 2 1 R325 2 2 2 R659 1 @ 2 0_0402_5%
GND
.1U_0402_16V7K
.1U_0402_16V7K
POK FB
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
C419
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
R327 5.1K_0402_1%
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
USB30@ USB30@ 10K_0402_1% 1 2 2
1
USB30@ USB30@ 2 2 2 2 U2DN2_L U2DN2
3 3 4 4
D APL5930KAI-TRG_SO8 R326 R658 1 @ 2 0_0402_5% D
1
USB30@ 32.4K_0402_1% WCM2012F2S-900T04_0805
Vout=0.8(1+10K/32.4K) USB30@ 2 L41 USB30@
U3RXDN2_L U3RXDN2 R683 1 @
1.042 ~ 1.0469 ~ 1.0519V 2 2 0_0402_5%
1 1
2
2
Spec: 0.9975 ~ 1.05 ~ 1.1025 USB30@ USB30@ USB30@ USB30@USB30@ USB30@ USB30@
USB30@
7K for customer request, can use other kind U3RXDP2_L U3RXDP2
3
3 4 4
of capacitor, like Y5V.
R310 OCE2012120YZF_0805
+3VALW to +3V Transfer +3V_USB3.0
+1.05V_USB3.0
0_0805_5%
1 2
+1.05VR +3VA_USB3.0
+3V_USB3.0 +3VA_USB3.0 R657 1 @ 2 0_0402_5%
+3VALW +3V_USB3.0 L22
U19 BLM18AG601SN1D_2P
U34
1 2
3 1
D10
1
H11
USB30@
E11
E12
K11
K12
F13
F14
P13
L10
SYSON
L13
L14
VIN VOUT
G3
G4
N4
N5
N6
C4
C5
C6
C7
D5
C8
C9
D8
D9
H3
H4
P3
E3
E4
D7
F3
L9
L5
L8
38,39,43,50 SYSON 4 5 C422 +USB3_VCCA
VIN/CE VOUT 10U_0805_6.3V6M
USB30@
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
U3AVDO33
U2AVDD10
2 GND 2
RT9701-PB_SOT23-5
USB30@
150U_B2_6.3VM_R35M
C390
14 CLK_PCIE_USB30_L B2 1
/
PECLKP C705.1U_0402_16V7K 2
SPEC Max:+3V---200mA;+1.05V---800mA
470P_0603_50V7K
C391
14 CLK_PCIE_USB30_L# B1 PECLKN U3TX_C_DP2 U3TXDP2_L +
USB30@
USB30@ PCIE_PRX_C_DTX_P5 B6
14 PCIE_PRX_DTX_P5 PCIE_PRX_C_DTX_N5 D2 Idle mode:0.489W: U3TXDP2
U3TX_C_DN2
2
U3TXDN2_L
1
/x
C699 1 2 .1U_0402_16V7K PETXP
14 PCIE_PRX_DTX_N5 C698 1 D1 +3V---43mA;+1.05V---328mA A6 U2DN2_L 1 2 2 1
2 .1U_0402_16V7K PETXN U3TXDN2 D24
USB30@ U2DM2 N8 USB30@
14 PCIE_PTX_C_DRX_P5 F2
PERXP
D3 mode:0.066W: U2DP2_L C706.1U_0402_16V7K 1 6
14 PCIE_PTX_C_DRX_N5 F1 P8U3RXDP2_L I/O1 I/O4
PERXN +3V---5.4mA;+1.05V---45mA U2DP2
B8 +USB3_VCCA
U3RXDP2 2 REF1 REF2 5
U3RXDN2_L +3V_USB3.0 U2DN2 U2DP2
su
U3RXDN2 A8 3 4
C 5,17,35,38,39 PLT_RST# R606 1 USB30@2 0_0402_5% I/O2 I/O3 C
15,35,37,38 PCH_PCIE_WAKE# H2 OCI2B PJUSB208H_SOT23-6
R601 1 USB30@2 0_0402_5% PERSTB
USB30_CLKREQ#_L K1 PEWAKEB G14
OCI1B @
OD output 14 USB30_CLKREQ#_L K2 Can be attach to EC, either. OCI2B
H13
R307 1 USB30@2 10K_0402_5%
R603 1 USB30@2 10K_0402_1% PECREQB OCI1B R308 1 2 10K_0402_5% For ESD request
+3V_USB3.0
USB30@
p.
J2 AUXDET
+3V_USB3.0 @ R604 1 2 100_0402_1% J1 H14
SMI_R
R602 1 USB30@2 10K_0402_5% PSEL PCI Express/ExpressCard select signal PPON2
R605 1 @ SMIB_R H1 J14
18,38 SMIB 2 0_0402_5% SMI
1:others PPON1 D22
P4 U3RXDN2 U3RXDP2 U3TXDP2 D33 U3TXDN2
R600 1 USB30@2 0_0402_5% SMIB
+3V_USB3.0 0:Express Card or Mini card 1
I/O1 I/O4
6
om
P5 1 I/O1 6
R611 1 USB30@2 10K_0402_5% PONRSTB +USB3_VCCA I/O4 +USB3_VCCA
B10 2 5
U3TXDP1 REF1 REF2
1 1 2 2 SPI_CLK_USB 2 REF1 REF2 5
D21 SPI_CS_USB# M2
1U_0603_10V6K
SPISCK U3TXDN1 A10 3 4

1SS355TE-17_SOD323-2 USB_SO_SPI_SI N2 N10 I/O2 I/O3 3 4
C702
1 SPISCB U2DM1 I/O2 I/O3

USB_SI_SPI_SO N1 SPISI PJUSB208H_SOT23-6
USB30@
M1 P10 @ PJUSB208H_SOT23-6
SPISO U2DP1
USB30@ B12 @
U3RXDP1
yc
2 +5VALW +USB3_VCCA
K13 GND A12
U3RXDN1
K14 GND
J13 GND
U17
W=60mils
R298 C432 1 8
As short as possible GND VOUT
m
P12 1.6K_0402_1% .1U_0402_16V7K 2 7
RREF VIN VOUT OCI2B
U2AVSS N12 1 2 1 2 3 6
38,43 SYSON# VIN VOUT
EPAD
C14 USB30@ 4 5
GND EN FLG
+3V_USB3.0 N11 1 2
// U2PVSS 0_0402_5% R313
+3V_USB3.0 USB3_XT1 D6 AP2301MPG-13_MSOP8
9
USB3_XT2 U3AVSS
N14
XT1
M14 U2DN2
B XT2 17 USB20_N2 B
2
1 @ 2 USB20@
1 R704 @R703
@ R703 L52
R687 USB30@0_0402_5% 1 R314 2 USB_OC2# 17
C725 P6 0_0402_5%
p:
.1U_0402_16V7K
10K_0402_5% 47K_0402_5% CSEL 2
2 1 1
USB30@
1
USB30@ 1
2 SPI_CS_USB# GND P14 C417
3
U39 USB_SI_SPI_SO A1 GND GND P11 3 4 4 @
A2
2
SPI_CLK_USB 8 1 USB30@ GND GND P9 U2DP2 0.1U_0402_16V4Z

WCM2012F2S-900T04_0805
tt
2
USB_SO_SPI_SI VCC CS# A3 P7 17 USB20_P2 2

0_0402_5%
R628
7 2 GND GND
SO
0_0402_5%
R634
NC A4 P2
6
SCLK WP#
3
A5
GND GND 1 @ with
Resister overlap 2 L52
5 4 @ GND GND P1 R686 0_0402_5%
SI GND A7 N13
GND GND
h
1
MX25L5121EMC-20G_SO8 A9 GND N9
GND
1
A11 N7
GND GND
USB3_XT1 A13 N3 +USB3_VCCA
GND GND
USB3_XT2 A14 M13
GND GND
+3V_USB3.0 B3 M12
GND GND
B4 M11
GND GND
B5 M10 U3TXDP2
1
GND GND JUSB5

B7 M9
R665 GND GND 9
B9 M8 U3TXDN2 SSTX+
100_0402_5% GND GND 1 For customer request
B11 M7 U2DP2 VBUS
GND GND 8
B13 M6 SSTX- GND_FRAME
GND GND U2DN2 3
2
B14 GND M5 D+
Place as close as C1
GND
M4 U3RXDP2 7 1 2
Y5 GND GND GND
possibile to C2 M3 2 10 R693 0_0603_5%
1 2 GND GND D- GND
C3 L12 U3RXDN2 6 11
U3.N14 and U3.M14 GND GND SSRX+ GND 1 2
C10 L11 4 12 R617 0_0603_5%
24MHZ_12PF_X5H024000DC1H
1 GND GND GND GND
C11 L7 5 13
USB30@ C709 GND GND SSRX- GND
12P_0402_50V8J L6 1 2
1 GND ACON_TARA4-9K1311 C726
A C707 USB30@ CONN@ A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
.1U_0402_16V7K
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
12P_0402_50V8J
USB30@
2
C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
G1
G2
G6
G7
G8
G13
G11
H6
G12
G9
F4
F6
F7
F8
F9
F11
F12
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4
Pin compare table for support USB remote wakeup or not
AUXDET(Pin J2) CSEL(Pin P6) CLK

UPD720200AF1-DAP-A_FBGA176~DSecurity Classification Compal Secret Data
USB30@
Support USB pull high Tied to GND Must use 24MHz crystal: mount Issued Date 2010/08/11 Deciphered Date 2011/08/11 Title
remote wakeup 10k to VDD33 Y1,R19,C40,C41
USB3.0 PD720200
Not support USB Tied to GND pull high Can use either 48MHz or 24MHz When DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
remote wakeup to VDD33 use 48MHz clock: mount R22,R25 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
@ PJP1
ACES_50305-00441-001
PL1
SMB3025500YA_2P
VIN @ PJ7
1 2 +3VALWP 2 1 +3VALW
1 2 1
2 JUMP_43X118
3
4
GND
1
1
1
1
GND PC3
PC1 PC2 PC4
1000P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J 1000P_0402_50V7K
2
2
2
2
@ PJ9 @ PJ10
+5VALWP 2 1 +5VALW +VCCSAP 2 1 +VCCSA
D 2 1 2 1 D
JUMP_43X118 JUMP_43X118
VIN
@ PJ12
+1.8VSP 2 1 +1.8VS
2
2 1
PD1 JUMP_43X118
LL4148_LL34-2
1
PD2 @ PJ14
LL4148_LL34-2 2 1
2 1
BATT+ 2 1
/
1
JUMP_43X118
PR1 PR2
68_1206_5% 68_1206_5% @ PJ15 @ PJ16
VS
/x
PQ1 +1.5VP 2 1 +1.5V +VSBP 1 2
2 1 1 2 +VSB
TP0610K-T1-E3_SOT23-3
2
2
N1 3 1
0.22U_0603_25V7K
1
@ PJ17 @ PJ18
su
1
PR3 1 PC6 2 1 2 1
C 2 1 2 1 C
PC5
100K_0402_5% 0.1U_0603_25V7K
2
2
2
2
@ PJ19 @ PJ20
1 2 +1.05VS_VCCPP 2 1 +1.05VS_VTT +VGFX_COREP +VGFX_CORE
40 51ON#
p.
2 1 2 1 1
2
PR4 JUMP_43X118 JUMP_43X118
22K_0402_5%
@ PJ26
om
2 1 1
2
JUMP_43X118
@ PJ25
+1.5VSDGPUP 2 1 +1.5VSDGPU
2 1
JUMP_43X118
yc
PreCHG PQ2
PR5 VIN PR7 LL4148_LL34-2 TP0610K-T1-E3_SOT23-3 B+
0_0603_5% 1K_1206_5% PD3
+CHGRTC
1 2 +3VLP 1 2 2 1 3 1
m
100K_0402_5%
100K_0402_5%
PR8
1K_1206_5%
1
1
PR9
1 2 PR10
PR11
1K_1206_5%
//
2
1 2
2
B B
PR12
1
1K_1206_5%
1 2 PR13
100K_0402_5%
p:
12
1
PD4
tt
39,47 ACOFF
2
1 2 2
48,49 +5VALWP 3
PQ4
h
BAS40CW_SOT323-3 PQ3 PDTC115EU_SOT323-3

PDTC115EU_SOT323-3
3
3
A A

PWR DCIN / Pre-charge
Custom 0.1
5 4 3 2 1
A B C D
PC181 reserve for EMI Isen solution PQ5

Iada=0~4.74A(90W/19V=4.736A) ADP_I = 19.9*Iadapter*Rsense AO4407A_SO8
CP = 85%*Iada ; CP = 4.07A 1 8
2 7
3 6
P2 P3 B+ CHG_B+ 5
PQ6 PQ7 PR14 0.02_2512_1% PL22
AO4407A_SO8 AO4407A_SO8 HCB4532KF-800T90_1812
4
VIN 8 1 1 8 1 4 1 2
7 2 2 7 PR16
6 3 3 6 2 3 CSIN 47K_0402_1%
5 5 1 2 VIN
CSIP
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_25V7K
10U_1206_25V6M
0.1U_0603_25V7K
5600P_0402_25V7K
VIN PreCHG
4
1 1
1
1
1
1
4
2
PC9
@ PC181
PC8
2
V1
PC10
PC11
PR15
PC7
10K_0402_1%
2
2
1
2
2
1
1
PR18
2
1
1
191K_0402_1%
0.1U_0603_25V7K
2
1
PR19 PR17 PR21
1
200K_0402_1% 200K_0402_1% 6251VDD 100K_0402_5%
PC12
2
PD5
2
2
RB751V-40_SOD323-2 ACSETIN
2.2U_0603_6.3V6K
1000P_0402_25V8J
1
2
1
PC13
1 1
1
3
1
10_1206_5%
PC14
2
47K
PR22
PR23
14.3K_0402_1%
1000P_0402_50V8-J
2 47K
2
PR24
1
2
PQ9 D
0_0402_5%
2
PDTC115EU_SOT323-3 ACPRN
1
PU1 2
PC17
39 FSTCHG 2 1
1
PC15 G
V1
DCIN
PQ8 1 24 2 1 S
3
1
/
1
VDD
2
DCIN PQ12
100K_0402_1%
PDTA144EU_SOT323-3 6251VDD PR25 47K_0402_5%
0.1U_0603_25V7K 2N7002W -T/R7_SOT323-3
1 2 ACSETIN
PR27
PR26
2 2 23 ACPRN 48
1
ACSET ACPRN
/x
150K_0402_1% PR28
PQ13 20_0402_5%
6
2
PQ10 6251_EN CSON
PDTC115EU_SOT323-3 3 22 1 2
2 EN CSON
2
PDTC115EU_SOT323-3 PC18
3
6
5
7
8
G 39 3S/4S# 2 0.047U_0402_16V7K CSOP
4 1 2 PQ15
CELLS CSOP 21 PR29
1
S AO4466L_SO8
su
1
PQ14A PC19 6800P_0402_25V7K 20_0402_5%

2
DMN66D0LDW -7_SOT363-6 PQ14B 2
1 2 2 1
DMN66D0LDW -7_SOT363-6 3 5 20
ICOMP CSIN PR30
2
3
D 4
5 PC20 PR31
PC21 1
20_0402_5%
2 TCR=50ppm / C
<40,41>
G 1 2 1 2 6 19 0.1U_0603_25V7K PR32
VCOMP CSIP PL2
p.
0.01U_0402_25V7K 10K_0402_1%
LX_CHG
2_0402_5% 10UH_PCMB104T-100MS_6A_20%
CHG
BATT+
1
2
3
S 39,49 ADP_I 4 PR34
4
1 2 1 2 1
7 ICM PHASE 18 0.02_1206_1%
PR33 100_0402_1%
6
5
7
8
1
1 2 2 3
4.7_1206_5%
6251VREF DH_CHG
om
PR38
PR35
PR36 8 UGATE 17 PR37
47K_0402_5% PC22 .1U_0402_16V7K VREF PC23
PACIN 0_0603_5%
80.6K_0402_1%
10U_1206_25V6M
10U_1206_25V6M
1 2 BST_CHG 0.1U_0603_25V7K
BST_CHGA
39 IREF 2 1 1 2 @
9 16 2 1
2
0.01U_0402_25V7K
1
CHLIM BOOT
1
4
1
PR40
1
1
PC26
PC25
6251VREF 6251aclim 6251VDDP PD8
PC24
1 2
1
PR39 RB751V-40_SOD323-2
680P_0402_50V7K
100K_0402_1% 10 ACLIM VDDP 15
2
PC27
6251VDD
2
2
12.1K_0402_1%
2.55K_0402_1%
yc
20K_0402_1%
ACOFF DL_CHG 1 2
1
2
3
1
2
39,46 ACOFF 2
2
@
2
PR42
PR43 11 VADJ LGATE 14 PR41

4.7_0603_5% PQ16
PC28
2
1
12 13 4.7U_0603_6.3V6M
AO4466L_SO8
PQ17 GND PGND
3
m
2
1
PDTC115EU_SOT323-3 D
39,49 65W/90W# 2 ISL6251AHAZ-T_QSOP24
G
PQ18 S
3
2N7002W -T/R7_SOT323-3
//
CP mode
3
39 CALIBRATE# 1 2
3
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) PR44
2
where Vaclm=1.502V, Iinput=4.07A 15.4K_0402_1%

p:
PR45
31.6K_0402_1%
6251VDD
Charging Voltage
1
tt
BATT Type CV mode CC=0.6~4.48A

(0x15) PR48
IREF=0.7224*Icharge 10K_0402_1%
1
ACIN 15,39,43,44
1
h
PR47 1 2
Normal 3S LI-ON Cells PR46
10K_0402_1%
12600mV 12.60V IREF=0.43V~3.24V 47K_0402_5%
PACIN
2
2
Ki
1
Vchlim=Iref*(PR374/(PR372+PR374))
1
PR49
=Iref*(100K/(80.6K+100K)) 14.3K_0402_1%
=Iref*0.5537
Ichanrge=(165mV/PR369)*(Vchlim/3.3V) ACPRN
2
=(165m/20m)*(1/3.3V)*Iref*0.5537 2
=1.3842*Iref
Iref=0.7224*Ichanrge =>Ki=0.7224 PQ19
PDTC115EU_SOT323-3
3
4
Kv 4
Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K

R=514K//31.6K//(15.4K+3k)=11.372K
r=514K//514K//31.6K=28.14K
Vcell=0.175*Vadj+3.99v
4.2V=0.175*Vadj+3.99V =>Vadj=1.2V
Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K))
1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899 Security Classification Compal Secret Data Compal Electronics, Inc.
1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title
A=Vref*(R/(R+514K))=0.052
Kv=9.451 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CHARGER
Custom 0.1
A B C
Date: Friday, August 27, 2010D Sheet 47 of 59
5 4 3 2 1
2VREF_8205
1U_0603_10V6K
D D
1
PC29
2
PR50 PR51
13K_0402_1% 30K_0402_1%
1 2 1 2
PIN25 is floating , not GND

PR52 PR53
RT8205_B+ (so it's fail for this circuit) 20K_0402_1% RT8205_B+
20K_0402_1%
-DVT- 1 2 1 2
PL3
/
HCB4532KF-800T90_1812
B+ 1 2 Typ: 175mA +3VLP
ENTRIP2
ENTRIP1
/x
PR54
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PR55
2200P_0402_50V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K
2200P_0402_50V7K
110K_0402_1% 154K_0402_1%
PC31
PC38
1 2 1 2
1
1
1
4.7U_0805_10V6K
1
1
PC32
PC33
PC35
PC37
PC36
PC34
6
5
8
7
6
5
7
8
3
1
5
4
6
PU2
2
2
2
su
2
2
2
PQ20 PQ21
PC39
FB1
TONSEL
ENTRIP1
FB2
REF
ENTRIP2
C C
1
AO4466L_SO8 AO4466L_SO8
25 P PAD
2
4 4
p.
7 VO2 VO1 24 SPOK 49
8 23 PR57 PC41
VREG3 PGOOD
PR56 0_0603_5% 0.1U_0603_25V7K
1
2
3
1
2
3
BST_3V BST_5V
1 21 2 9 22 21 2
om
BOOT2 BOOT1 1
4.7UH_PCMC063T-4R7MN_5.5A_20%
0_0603_5%
UG_3V
VFB=2.0V UG_5V
PC40 10 21 PL5
PL4 UGATE2 UGATE1 4.7UH_PCMC063T-4R7MN_5.5A_20%
0.1U_0603_25V7K LX_3V LX_5V
+3VALWP 1 2 11 20 1 2 +5VALWP
PHASE2 PHASE1
1
6
5
7
8
1
LG_3V LG_5V
4.7_1206_5%
4.7_1206_5%
12 19
@ PR58
PQ22 LGATE2 LGATE1
6
5
7
8
@ PR60
SKIPSEL
yc
AO4712_SO8 PR59 @
VREG5
0_0402_5%
GND
MAINPW ON
VIN
RT8205EGQW _W QFN24_4X4
NC
EN
1
2
2 1
2
1 4
+ PC43 +
PC42 4
1
1
14
18
17
16
15
13
m
680P_0402_50V7K
680P_0402_50V7K
220U_6.3V_M PR61
@ PC44
@ PC45
499K_0402_1% AO4712_SO8 220U_6.3VM_R15
2 2
PQ23
3
2
1
2
2
1 2
B+
3
2
1
//
1
VL
1U_0603_10V6K
100K_0402_1%
1
PC46
1
Typ: 175mA
PC47
4.7U_0805_10V6K
B B
PR62
2
2
p:
ENTRIP1 ENTRIP2 RT8205_B+
1
6
D
3
0.1U_0603_25V7K
PQ24A 2
G 5 2VREF_8205
tt
DMN66D0LDW -7_SOT363-6
2
G PQ24B
PC48
49 MAINPWON S DMN66D0LDW -7_SOT363-6 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
1
PR63 S (2)SMPS2=375KHZ(+3VALWP)
h 4
0_0402_5%
2 1
PR64
100K_0402_1%
VL 2 1
+3.3VALWP +5VALWP
Ipeak=5.78A ; 1.2Ipeak=6.94A; Imax=4.05A Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A
f=375KHz, L=4.7UH f=300KHz, L=4.7UH,Rentrip=154k ohm
1
2N7002W -T/R7_SOT323-3 Rdson=15~18m ohm Rdson=15~18m ohm

PQ25
PQ26
PDTC115EU_SOT323-3
1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=0.716A 1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A
PR65 Vlimit=10*10^-6*110Kohm/10=0.11V Vlimit=10*10^-6*154Kohm/10=0.15V
1
47 ACPRN D
200K_0402_5%
2 1 2 VS 1 2 2 Ilimit=0.11/(18m*1.2)~0.11/(15m)=6.34A~9.13A Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A
A
G Iocp=7.06A~9.85AA (7.06A>6.94A -> ok) -DVT- Iocp=8.44~11.57A (8.44>8.4 -> OK) A
2.2U_0603_6.3V6K
S PR66
40.2K_0402_1%
3
100K_0402_1%
1
1
PC49
PR67
3
2
39,40 EC_ON
2
2 PQ27
PDTC115EU_SOT323-3
3VALWP/5VALWP
3
Custom
P5WE0 M/B LA-6901P Schematic 0.1
5 4 3 2 1
5 4 3 2 1
PJP2
SUYIN_200275GR008G13GZR
D D
10
GND
9
GND
8
8
7 7
6 EC_SMDA
6
2
5 EC_SMCA
5 TH
4 PR68
4 PI
3 100_0402_1%
3
2 2
1
1 PH1 under CPU botten side :
1
2
PR69
CPU thermal protection at 92 degree C
<40,41> 100_0402_1% Recovery at 72 degree C
EC_SMB_DA1 39
VL
VMB
1
1
PL6 <40,41> EC_SMB_CK1 39
SMB3025500YA_2P
1 2 BATT+ PR70
/
1
1
1K_0402_5%
2
PR73 PC50 PR71 PR72
1
1
6.49K_0402_1% 0.1U_0603_25V7K VL 10K_0402_1% 21K_0402_1%
/x
PC51 PC52 2 1 +3VALWP
1000P_0402_50V7K 0.01U_0402_25V7K
2
1
2
2
2
PU3
@ PR74 1 VCC TMSNS1 8
1
100K_0402_1%
PR75 2 GND RHYST1 7 2 1
1K_0402_1%
su
1
3 OT1 TMSNS2 6 PR76
C C
48 MAINPWON 9.53K_0402_1%
2
4 5 2 1
OT2 RHYST2
BATT_TEMP 39
G718TM1U_SOT23-8 @ PR77
47K_0402_1%
p.
1
1
PH2 @ PH1
om
100K_0402_1%_NCP15WF104F03RC 100K_0402_1%_NCP15WF104F03RC
2
2
PQ28
TP0610K-T1-E3_SOT23-3
B+ 3 1 +VSBP
yc
100K_0402_1%
0.22U_0603_25V7K
1
1
1
PR78
PC53
PC54
0.1U_0603_25V7K
m
2
2
2
PR79
VL 22K_0402_1%
1 2 //
2
PR80
B 100K_0402_1% +5VALWP B
PR245
PR81 0_0402_5%
ADP_I 39,47
1
1
D
1K_0402_5%
1
p:
48 SPOK 2 PQ29 @
1 2 1 2
G 2N7002W-T/R7_SOT323-3 PR243
1U_0402_6.3V6K
S 7.15K_0402_1%
3
1
1
PC55
@
+3VS PC170
2
1
0.1U_0603_25V7K
tt
2
2
PR244 PR240
1
D
10K_0402_1% 9.09K_0402_1%
2 65W/90W# 39,47
G
1
h
2
2
PR250 S
3
@ PR239 @
100K_0402_1% PU13
5,39 H_PROCHOT# 1 2
1 8
PQ66
VCC TMSNS1 2N7002W-T/R7_SOT323-3
2
0_0402_5% 2 7 1 2
GND RHYST1
1
D
PR241
@ PQ65 2 3 6
OT1 TMSNS2 34.8K_0402_1%
2N7002W-T/R7_SOT323-3 G
S 4 5
1
OT2 RHYST2
3
G718TM1U_SOT23-8 PR242
10K_0402_1%
2
A A

PWR-BATTERY CONN/OTP
Custom 0.1
5 4 3 2 1
A B C D
PL7
HCB4532KF-800T90_1812
1.5_8209_B+ 1 2
B+
5
6
7
8
2200P_0402_50V7K
4.7U_0805_25V6-K
0.1U_0603_25V7K
4.7U_0805_25V6-K
PQ30
1
1
1
1
PC57
PC56
PC172
PC173
PR83
267K_0402_1% 4
2
2
2
2
PR84 1 2
0_0402_5%
1 2
38,39,43,45 SYSON AO4466L_SO8
3
2
1
1 1
2
47K_0402_5%
PR85 PC59 PL8
@ PR86
0.1U_0603_25V7K 1UH_FDUE1040D-1R0M-P3_21.3A_20%
15
14
0_0603_5%
+1.5VP
1
@ PU4 BST_1.5V 1 BST_1.5V-1
2 1 2 1 2
PC60
EN/DEM
NC
BOOT
.1U_0402_16V7K
2
1
2 13 DH_1.5V
TON UGATE
1
3 12 LX_1.5V 1
VOUT PHASE
5
6
7
8
@ PR87
VFB=0.75V + PC61
4 VDD CS 11 +5VALW PQ31 4.7_1206_5%
330U_6.3V_M
5 FB VDDP 10
2
2
6 9 DL_1.5V 4
PGOOD LGATE
PGND
PR88
GND
1
15K_0402_1%
100_0603_5% @ PC63
1
PR89
1 2 680P_0402_50V7K
+5VALW RT8209MGQW _W QFN14_3P5X3P5 PC62
2
3
2
1
4.7U_0805_10V6K AO4456_SO8
2
1
/
2
PC64
4.7U_0603_10V6K
/x
PR90
1 2
1
10K_0402_1%
su
2 2
PR91
10K_0402_1%
+1.5VP
2
Ipeak=19.53A;1.2Ipeak=23.44A ;Imax=13.67A
p.
Rton=267K, Fsw=298KHz ,Rdson=5.3~7mohm
Rtrip=12K
Iocp=18.17~28.98A
om
VGA@ PL9
HCB4532KF-800T90_1812
1.5VDGPU_8209_B+
1 2
B+
4.7U_0805_25V6-K
6
5
7
8
0.1U_0603_25V7K
4.7U_0805_25V6-K
2200P_0402_50V7K
1
VGA@ PC65
1
1
1
VGA@ PC66
VGA@ PC175
VGA@ PC174
yc
VGA@
PR92
2
2
2
VGA@ 267K_0402_1%
PR94 4
1 2
0_0402_5%
SYSON BST_1.5VDGPU VGA@
1 2 PQ32
m
AO4466L_SO8
1
2
3
VGA@ VGA@
VGA@ PL10
2
PC68
47K_0402_5%
PR96 1UH_FDUE1040D-1R0M-P3_21.3A_20%
0_0603_5%BST_1.5VDGPU-1 0.1U_0603_25V7K
14
15 +1.5VSDGPUP
@ PR95
@ PU5 1 2 1 2
PC69
// EN/DEM
NC
1 2
BOOT
.1U_0402_16V7K
2
DH_1.5VDGPU
1
2 TON 13
3 UGATE 3
LX_1.5VDGPU
1
1
3 12
6
5
7
8
VOUT PHASE VGA@
@ PR97 + PC70
VFB=0.75V +5VALW
p:
4 VDD 11 4.7_1206_5%
CS 330U_6.3V_M
5 FB 10 2
VDDP
2
DL_1.5VDGPU
VGA@ 6 9 4
PGOOD LGATE
PGND
tt
GND
PR98
1
1
1
VGA@ @ PC72
10K_0402_1%
100_0603_5% VGA@
PC71 680P_0402_50V7K
+5VALW
PR99
1 2 RT8209MGQW _W QFN14_3P5X3P5 4.7U_0805_10V6K PQ33
3
2
1
2
2
7
AO4456_SO8
h
VGA@
1
2
VGA@ PC73
4.7U_0603_10V6K VGA@
2
VGA@
PR100
10K_0402_1%
1 2
1
VGA@
PR101
10K_0402_1%
2
4 4
+1.5VSDGPUP
Ipeak=10.4A;1.2Ipeak=12.48A ;Imax=7.28A
Rton=267K, Fsw=298KHz ,Rdson=4.5~5.6mohm
Rtrip=10K
Iocp=14.68~26.29A
PWR-+1.5VP/+1.5VSDGPU
Custom 0.1
A B C
Date: Friday, August 27, 2010D Sheet 50 of 59
5 4 3 2 1
PU6 PL11
4
PJ22 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
2 1 10 2 LX_1.8V 1 2
+5VALW
PG
2 1 PVIN LX +1.8VSP
@ JUMP_43X118 9 3
68P_0402_50V8J
1
PVIN LX
4.7_1206_5%
1
1
PC74
PC75
8
22U_0805_6.3VAM SVIN PR103
PR102
6 FB_1.8V 20K_0402_1%
D
2
D
2
EN_1.8V FB
5
22U_0805_6.3VAM
22U_0805_6.3VAM
2
2
1
EN
NC
NC
TP
1.8VSP
PC76
PC77
FB=0.6Volt
Ipeak=3.35A ; 1.2Ipeak=4.02 ;Imax=2.345A
2
11
1
1 2
37,39,43,52 SUSP#
1
Vout=0.6*(1+(20K/10K))=1.8V
1
PR104 100K_0402_5%
0.1U_0402_10V7K
680P_0603_50V7K
-DVT-
PC79
SY8033BDBC_DFN10_3X3 PR105
PC78
1
PR106 10K_0402_1%
2
1M_0402_5%
2
2
1
PL23
/
FBMA-L11-322513-201LMA40T_1210
5603_VCCSAP_B+
1 2 B+
2200P_0402_50V7K
4.7U_0805_25V6-K
/x
4.7U_0805_25V6-K
0.1U_0603_25V7K
1
1
1
1
PC80
PC177
PC81
PC176
6
5
7
8
2
2
2
2
su
C 4 C
PR107
267K_0402_1%
1 2 PQ34
AO4466L_SO8
1
3
2
EN_VCCSAP BST_VCCSAP
p.
PR108 PL12
14
15
PR109 PC82
1
0_0402_5% PU7 2.2UH_PCMC063T-2R2MN_8A_20%

0.1U_0603_25V7K
0_0603_5% BST_VCCSAP-1
1 2 1 2 +VCCSAP
EN/DEM
NC
BOOT
52 VCCPPWRGOOD 1 2 1 2
1
UG_VCCSAP
1
om
@ PR110 2 13
TON UGATE
1
47K_0402_5% @ PC83 1
0.1U_0402_16V7K LX_VCCSAP
3 12
VOUT
2
PHASE
6
5
7
8
@ PR111 + PC84
+5VALW
2
4 11 4.7_1206_5% 330U_6.3V_M
VDD CS
PQ35
2
5 10 AO4712_SO8 2
2
FB VDDP
1
PR112 +3VS LG_VCCSAP PR113
100_0603_1% 6 9 4
PGOOD LGATE
PGND
+5VALW @ PC85 0_0402_5% PR114

GND
1 2
yc
470P_0603_50V8J VSSSA_SENSE 9
2
1 2
2
1
PR116
15K_0402_1%
10K_0402_5%
0_0402_5%
1
1
Layout Note: RT8209MGQW_WQFN14_3P5X3P5 PC86

7
1
3
2
1
PR115
Place near V5FILT Pin <BOM Structure> 4.7U_0805_10V6K
2
PC87 0_0402_5%
1
2
4.7U_0603_6.3V6K PR117
2
SA_PGOOD 39
m
2 1
PR118
2K_0402_1% PR119
1 2 1 2 VCCSA_SENSE 9 VFB=0.75V
VFB=0.75V Vo=VFB*(1+PR156/PR150)=1.1V
// 10_0402_5% Ton=19E-12*Ron*(((2/3)*Vo+150mV)/Vin)+50ns=2.4E-7
Freq=282KHz
B B
+3VS Cesr=15m ohm
Ipeak=4.60A Imax=2.70A
p:
1
Delta I=((19.5-1.0)*(1.0/19.5))/(L*Freq)=1.48A
1
PR120
Vtrip=Rtrip*10uA=0.0787V
15K_0402_1% PR121 Iocp-min=5.96A
10K_0402_5%
Iocp-max=6.01A
1 2
tt
D PR123 Iocp=5.96~6.01A
2
10K_0402_5%
1
2 2 1
G
PR122 S
3
30K_0402_1% PQ36 PQ37

h
1
2N7002W-T/R7_SOT323-3 PMBT2222A_SOT23-3
2
@ PC88 PR124 @
4700P_0402_25V7K 2 1 VCCSA_VID1 9
1
100K_0402_5% 2
2
@ PR126
2
PR125 0_0402_5%
10K_0402_5%
3
+VCCSAP
the resister change
Ipeak=6A , Imax=4.2A, 1.2Ipeak=7.2A
VID[0] VID[1] VCCSA Vout Require on 2011/ 2012 Required from @ to pop component
DCR= 9 m(typ)~10 m(max)
0 0 0.9 V Yes/Yes Rlimit=12K,Rdson=15~18mohm
Add two jumpers on the HW's output cap of the
+VCCSA's PIN(+) and PIN(-) to sense the
0 1 0.8 V Yes/Yes Ilimit=10uA feedback voltage for VCCSA_SENSE & VSSSA_SENSE.
1 1 0.75V No/Yes Iocp=Rlimit/Rdson*10^(-5)= 7.59~10.654A
1 1 0.65V No/Yes
A A
Note:Use VCCSA_SEL to switch High & Low Level for VID[1]

(ie. VCCSA_SEL) due to the VID[0] is don't care for this setting.
Security Classification
2010/07/13
Compal Secret Data
2011/07/13 Title
PWR +VCCSAP
C 0.1
5 4 3 2 1
5 4 3 2 1
D D
PU8
+1.5V 1 VIN NC 8 +3VALW
2 7
1
GND NC
2
PC90
1
PC89 3 6 1U_0603_10V6K
4.7U_0805_6.3V6K PR127 VREF VCNTL
2
1
1K_0402_1% 4 5
VOUT NC
9
2
TP
APL5336KAI-TRL_SOP8P8
PR128
.1U_0402_16V7K
+0.75VS
1
1
1
24.9K_0402_1% D
PQ39
/
43 SUSP
PC91
1 2 2 2N7002W -T/R7_SOT323-3
1
1
G D PR129 PC93
2
1
S SUSP 1K_0402_1% 10U_0603_6.3V6M
2
/x
PC92 G
2
2
1U_0402_6.3V6K PQ38 S
3
2N7002W -T/R7_SOT323-3
For shortage changed
su
C C
p.
om
PL13
HCB4532KF-800T90_1812
1.05VS_51117_B+ 1 2 B+
yc
0.1U_0603_25V7K
4.7U_0805_25V6-K
2200P_0402_50V7K
4.7U_0805_25V6-K
6
5
7
8
1
1
1
1
PC94
PC178
PR130
PC95
PC179
m
267K_0402_1%
1 2
2
2
2
2
PR131
680K_0402_5% 4
37,39,43,51 SUSP# 1 2
//
1
PQ40
14
15
PR132 PC98
1
1
PU9 0_0603_5% AO4466L_SO8 PL14

@ PR249 0.1U_0603_25V7K
1
2
B
3
BST_1.05VS_VCCP 1UH_FDUE1040D-1R0M-P3_21.3A_20% B
PC97
EN/DEM
NC
BOOT
47K_0402_5% 1 2 1 2 +1.05VS_VCCPP
4.7U_0603_6.3V6K 2 1
2
2 13 DH_1.05VS_VCCP
TON UGATE
p:
2
1
3 12 LX_1.05VS_VCCP
VOUT PHASE
6
5
7
8
@ PR133
4 11 4.7_1206_5%
VDD CS 1
tt
5 FB
VFB=0.75V VDDP 10 +5VALW + PC99
1 2
2
330U_6.3V_M
6 9 DL_1.05VS_VCCP 4
PR135 PGOOD LGATE
PGND
@ PC100 PR134 2
h
GND
100_0603_5%
680P_0402_50V7K 0_0603_5%
+5VALW 1 2
2
PQ41
1
RT8209MGQW _W QFN14_3P5X3P5 AO4456_SO8
1
1
7
3
2
1
13.7K_0402_1%
1
PR136
PC102
PC101 4.7U_0805_10V6K
4.7U_0603_10V6K 2 Change PR133 from 10 to 0ohm
2
Change PR144 from 0 to 10ohm

+1.05VS_VCCP:
Ipeak=15.608A;Imax=10.9256A;1.2Ipeak=18.7296A PR137
Rdson=4.5~5.6m ohm ; Freq=298KHz 4.02K_0402_1%
Rtrip=13.7Kohm,Vtrip<200mV 1 2
Iocp=20.04~32.11A (20.04>18.7296A->OK) PR140
1
51 VCCPPW RGOOD PR139 10_0402_5% VCCIO_SENSE 8

A A
1 2 +3VALW 2 1
PR138
10K_0402_1%
10K_0402_1%
PR141/PR142 must be lower than 10K ohm
2
by Jones(DVT)
2
PR141 @
10K_0402_1% Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title
PWR +1.05VS_VCCPP/+0.75VSP
1

Custom 0.1
5 4 3 2 1
5 4 3 2 1
VGA@ PL15
FBMA-L11-322513-201LMA40T_1210
B+ 1 2 B+_CORE
+3VS
1
VGA@ PC103 VGA@ PC104
1
10U_1206_25V6M 10U_1206_25V6M
@ PR142
2
10K_0402_5%
5
5
TPCA8030-H_SOP-ADV8-5
D D
PQ43
PQ42
18 VGA_PWROK
4 4
@
VGA@
VGA@ PR143 VGA@ PC105
PU10 0_0603_5% 0.1U_0603_25V7K
VGA@ PR145 BST_VCORE 1 2 1 2
1 10
3
2
1
3
2
1
4.7_0603_5% PGOOD VBST
1 2 DH_VCORE PL16
2 TRIP DRVH 9
0.56UH_MMD-12CE-R56M-X1A_29A_20%
+3VS SW_VCORE
3 8 1 2 +VGA_CORE
EN SW
4 7 +5VALW
VFB V5IN
1 2 DL_VCORE
5 6
2
RF DRVL
ESR=10mohm
2
@ PR146 VGA@ PR148
11
1
5
10K_0402_5% 5.11K_0402_1% TP
TPCA8028-H_SOP-ADVANCE8-5
VGA@
PQ45
PQ44
TPS51218DSCR_SON10_3X3 PC106 VGA@ PR147
1
VGA@ PR149 VFB=0.6V VGA@
/
1U_0603_6.3V6M 4.7_1206_5% 1 1
1
10K_0402_1% VGA@ PR150 VGA@ PC108

VGA_ON 1 2 0_0402_5% PC171 + + 470U_V_2.5VM
44 VGA_ON
1 2
4 470U_V_2.5VM
/x
4
VGA@
VGA@
PR151
2
1
VGA@ PC109 VGA@ PR152 2 2 VGA@

0_0402_5%
VGA@ PC110 680P_0603_50V7K 10_0402_5% 1 2
2
C .1U_0402_16V7K C
2 1 24 FB_GND
3
2
1
2
3
2
1
su
2
GCORE_SEN
GCORE_SEN 24
Rds=4.5m/5.6mOHM PR153
VGA@ 4.22K_0402_1%
1
D VGA@ PQ46
44 VGA_ON#
1
2 2N7002W-T/R7_SOT323-3
p.
G +3VSDGPU
S
2
3
1
PR157
2
VGA@ 53.6K_0402_1%
om
VGA@ PC113 VGA@ PR156 VGA@ PR158
2200P_0402_25V7K 10K_0402_1% 10K_0402_5%
1
2
VGA@ PR159
6
D
1
10K_0402_5%
VGA_CORE 2 1 2
G
F=1/(75*e-12*44.2)=300K
2
Ipeak=33A Imax=23.1A Iocp=39.6A
1
yc
1
VGA@ PQ47A S
1
Iocpmin=(5.11K*26uA)/((5.6mohm/2)*1.2)=39.54A PR160 +3VSDGPU
VGA@ PC114
@ PR161
Iocpmin=39.54A VGA@ 24K_0402_1% 4700P_0402_25V7K
10K_0402_5%
1
Follow the project of NEW70 for VGA_CORE circuit
2
m
B VGA@ PR162 B
VGA@ PR163 10K_0402_5%
3
D 10K_0402_5%
1 +3VSDGPU
2
1
// G
5
1
GPU_VID1 GPU_VID0 NVIDIA/N11P-GS
2
PQ47B S VGA@ PC115
4
VGA@ DMN66D0LDW-7_SOT363-6 4700P_0402_25V7K @ PR165
2
@ PR164 10K_0402_5%
P8/P12 1 1 0.825V
2
p:
10K_0402_5%
VGA@ PR166
1
P0(Hot) 0 1 0.90 V 10K_0402_5%
6
D
2 1 GPU_VID1 22
2
1
PQ48A G
tt
P0(Cold) 1 0 0.95 V VGA@ DMN66D0LDW-7_SOT363-6

S VGA@ PR167
1
+3VSDGPU 10K_0402_5%
0 0 0.995V
2
h
2
@ PR168
VGA@ PR169 10K_0402_5%
3
D 10K_0402_5%
5 2 1 GPU_VID0 22
1
PQ48B G
VGA@ DMN66D0LDW-7_SOT363-6 VGA@ PR170
A 10K_0402_5% A
S
2
Security Classification Compal Secret Data AP
+VGA_COREP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom P5WE0 0.1
5 4 3 2 1
5 4 3 2 1
Alert# PU resister need close CPU, PC116 @ GFX_B+ 1 2 B+

so the PU resister in HW schematic. 2 1 NTCG PL24
10U_1206_25V6M
B+
10U_1206_25V6M
GFX@ @ HCB4532KF-800T90_1812
but DAT and CLK need close PWM-IC,
5
5
GFX@ PC118
GFX@ PC119
@PR171
@ PR171 470P_0402_50V7K PQ49 PQ50
so the PU resister in POWER schematic. 3.83K_0402_1% PH3
1
220U_25V_M
2 1 2 1 1
@ UGATEG
1000P_0402_50V7K
PC117
+
8.06K_0402_1%
PR172 GFX@
DNP_470K_ERT-J0EV474J
2
PC120 GFX@
4 4
1
1 2
2
1
PR173 @ GFX@ PL18
27.4K_0402_1% 0.36UH_PCMC104T-R36MN1R17_30A_20% +VGFX_COREP
3
2
1
3
2
1
+VGFX_COREP
2
PHASEG
2
GFX@ PR174 4 1
2 1 PR175 PC122 1
@10K_0402_1%
GFX@
BOOTG
330P_0402_50V7K
5
D PC121 GFX@ D
10_0402_1% +5VS 2 1 2 1 3 2
PC125 GFX@
@
330U_X_2VM_R6M
PQ51
4.7_1206_5%
1 2 +
PR178
1
PC126 GFX@
1
PC124 GFX@
1
PQ52
GFX@ PC123
VCC_AXG_SENSE 9 0_0603_5% 0.22U_0603_10V7K
1
39P_0402_50V7K GFX@ PR177 680P_0402_50V7K 330P_0402_50V7K
PR176 @ GFX@ GFX@ PR180 GFX@
PR179
499K_0402_1% 2 1 2 1 2 1 PC127 VSS_AXG_SENSE 9 1_0402_5% 2
LGATEG
1U_0603_10V6K
422_0402_1%
GFX@
2 1 4 4
2
PH4 GFX@
2
GFX@
2
PC128 GFX@ 10K_0402_5%_TSM0A103J4302RE
2
1
2
150P_0402_50V8J 1000P_0402_50V7K GFX@ PR183 7.5K_0402_1%
PC129
1 2
680P_0402_50V7K
2 1
@ PC130
2 1 PR1841 GFX@ 2
1
2 1 2 1
0_0402_5%
GFX@ PR182
PR181 GFX@ 10_0402_1%
3
2
1
0.22U_0603_10V7K
GFX@ 11K_0402_1%
2
PR185
2.55K_0402_1%
3
2
1
1
475K_0402_1%
2
GFXVR_IMON 1 PR187 2
PR186
1
.1U_0402_16V7K
2
18.2K_0402_1%
PR189 @
ISNG
ISPG
0_0603_5%
2
+1.05VS_VCCPP GFX@ PC133
PC131
0.047U_0603_16V7K PC135 @ 16.5K_0402_1% 1 2
2
GFX@
54.9_0402_1%
PR188
1 2
1
.1U_0402_16V7K
GFX@ PC134
UGATEG
PHASEG
LGATEG
PC132 GFX@
BOOTG
2
100_0402_1%
1
PU11
470P_0402_50V7K
NTCG
.1U_0402_16V7K @ PR192
2
1
1
2 5 1
130_0402_1%
2
VSS_AXG_SENSE VCC BOOT CPU_B+ 1 2
PR191
1 2
PC137
6 8
10U_1206_25V6M
ISPG
10U_1206_25V6M
FCCM UGATE
1
PQ53
1
590_0402_1%
PR193 GFX@
PC136 @
1
PR190
5
+3VS
Parallel and tune length For shortage changed 2 7 @PQ54
@ PQ54 0.01U_0402_16V7K
PWM PHASE
2
+5VS
2
1
PC138
PC139
37
39
38
41
40
2
44
43
42
46
45
49
48
47
@
3 4 PR195
GND LGATE ISNG
1.91K_0402_1%
8 VR_SVID_DAT PR194
2
1
BOOTG
UGG
PHG
LGG
ISNG
NTCG
PROG2
GND
VSENG
RTNG
ISPG
COMPG
FBG
PR196 GFX@
4
2
PGND 9 2 1
2
0_0402_5%
/x
BOOT2 4
8 VR_SVID_ALRT# 1 VWG 36 ISL6208ACRZ-T_QFN8_3X3 OPT@
BOOT2 UGATE2
2
8 VR_SVID_CLK 0_0402_5%
2 IMONG 35
UG2 PL19
3
2
1
PHASE2
2
+5VS 0.36UH_PCMC104T-R36MN1R17_30A_20%
PR197
3
2
1
+3VS 3 34 +CPU_CORE
1 2 PGOODG PH2 4 1
SVID_SDA
1PR198
su
39 GFX_CORE_PWRGD 4 2
4.7_1206_5%
33
SDA VSSP2
5
1.91K_0402_1% 3 2
5
SVID_ALERT# LGATE2
PR202 @
C @ 0_0402_5% C
@ PQ55
PQ56
5
ALERT# LG2 32
SVID_SCLK PR200
VGATE 15,39 6 31 1 2
VSSSENSE SCLK VDDP
39 VR_ON 1 PR203 2 0_0402_5%
1_0402_5%
p.
7 30
1
4
10K_0402_1%
2
4
10K_0402_1%
VR_ON PWM3
1
LGATE1
3.65K_0402_1%
0.047U_0603_16V7K
0_0402_5%
PR207
2
PR199
10K_0402_1%
PR201
IMVP_IMON
1
PC141
PR204
680P_0402_50V7K
PC140 @
8 PGOOD 29
PR205
LG1
19.1K_0402_1%
ISL95831CRZ-T_TQFN48_6X6
1
1
9 28
2.2U_0603_10V6K
PC142
IMON VSSP1
1
2
3
PHASE1
2
1
2
3
1
om
VSUM+
VSUM-
2
ISEN2
ISEN1
ISEN3
PR206
10 27
1
2
VR_HOT# PH1 UGATE1

For shortage changed 11 26BOOT1
ISEN3/ FB2
NTC UG1
2
2
12 25
PROG1
ISUMN
ISUMP
39 VR_HOT# VW BOOT1
COMP
CPU_B+
ISEN2
ISEN1
VSEN
PC144
VDD
RTN
VIN
PR208 QC@ PR212
FB
2 1 @
1 2 590_0402_1%
1
10U_1206_25V6M
499_0402_1%
5
yc
PU12
10U_1206_25V6M
470P_0402_50V7K
PQ57
13
14
15
16
17
18
19
20
21
22
23
24
+1.05VS_VCCPP @
@ PQ58
1
PR209
PC146
1
PC145
2
1 2 1 2
UGATE2
2
3.83K_0402_1% PH5 4
2
470K_0402_5%_TSM0B474J4702RE 4
m
2 PR210 1 PR211
PC143
27.4K_0402_1%
1
8.06K_0402_1%
change from 43P to 47P

47P_0402_50V8J
1 2 CPU_B+ DC@
PL20
1
PR212
1
2
3
for shortage problem
1000P_0402_50V7K
PHASE2 0.36UH_PCMC104T-R36MN1R17_30A_20%
(Ipeak=56A)
1
2
3
4.32K_0402_1%
PR213
+CPU_CORE
1
2010-03-15 0_0603_5% (Vboot=0) 4 1

//
PC147
PC148 0_0603_5%
4.7_1206_5%
PR215 +5VS PR214 3 2
2
@ 22P_0402_50V8J BOOT2
1
2
PQ60
@ PR216
1
2 2 12 1
5
PC152
B 2 1 B
ISEN2
ISEN1
ISEN3
1_0603_5%
@ PQ59
PC149
1
1U_0603_10V6K
0.22U_0603_10V7K
1
0.22U_0402_6.3V6K PC150
10K_0402_1%
1
1_0402_5%
PC151
1
LGATE2
10K_0402_1%
2
4
10K_0402_1%
2 1
PR246
p:
PR219
0.22U_0603_25V7K
12
PR217
PC155
1
2
3.65K_0402_1%
2PR220
680P_0402_50V7K
33P_0402_50V8J
2
PR218
VSUM- VSUM+ 4
@ PC154
@ PR221 PR222 PC153
PC156
VSUM+
1 2 2 1 2 1 2 1
1
2
VSUM-
ISEN2
ISEN1
1
2
3
ISEN3
499_0402_1% 2 1 0.22U_0402_6.3V6K
2.61K_0402_1%
1
1
tt
499K_0402_1%
2
470P_0402_50V7K PC157
1
2
3
PR223
2 1
0.33U_0603_10V7K
0.068U_0402_16V7K
PC158 0.22U_0402_6.3V6K QC@ PR229

150P_0402_50V8J PR224 1.24K_0402_1%
1
2 1
11K_0402_1%
412K_0402_1% DC@ PR225 CPU_B+

PC159
1 2 B+
PR227
h
1
2 1 2 1
12
PR228
PC160
PL17
2.15K_0402_1%
1
+CPU_CORE 2 1 HCB4532KF-800T90_1812
10_0402_1% PH6
@ PQ62
2
10U_1206_25V6M
5
2
PC161 10KB_0603_5%_ERTJ1VR103J
330P_0402_50V7K
QC@ PR225
10U_1206_25V6M
2
PQ61
@
1
3.83K_0402_1% 2 1 DC@ PR229 VSUM-
1
PC163
1
@ 8 VCCSENSE 330P_0402_50V7K
PC162
UGATE1
1
2 1
2
PC164
PR248 698K_0402_1% 4
2
2K_0402_1% 8 VSSSENSE
2
1
.1U_0402_16V7K
2
PC167
2 1
2
2 1
2
PC165 @ PR231
1
2
3
@ PR232 2 1 PHASE1
1000P_0402_50V7K 100_0402_1% +CPU_CORE
1
PC180 2 1 PL21
1
2
3
100P_0402_50V8J 10_0402_1% @ PC166 0.36UH_PCMC104T-R36MN1R17_30A_20%
330P_0402_50V7K 0_0603_5% 4 1
2
BOOT1 PR233
2 1 3 2
4.7_1206_5%
5
PQ63
*Iccmax in Turbo Mode for SV (35W) is 53A
680P_0402_50V7K @ PR234
@ PQ64
2 1
1
3.65K_0402_1%
LGATE1
+CPU_CORE +VGFX_COREP
PR235 PR236
PC168
A 4 A
0.22U_0603_10V7K
1_0402_5%
10K_0402_1%
2
10K_0402_1%
2 1
10K_0402_1%
Icc-max=53A Ipeak=26A , Imax=18.2A , 1.2Ipeak=31.2A 4
PR237
1
PR247
PR238
Rdson=3.6~4.5m ohm Rdson=3.6~4.5m ohm
VSUM+
@ PC169
ISEN2
VSUM-
ISEN1
ISEN3
DCR=1.1m ohm DCR=1.1m ohm
1
2
3
2
HW output cap: HW output cap:
2
1
2
3
1
2
(1)10U_0805_4V *10 (1)22U_0805_6.3V *12
(2)22U_0805_6.3V *15 (2)470U_D2_2V *2(ESR=4.5m ohm)
(3)470U_D2_2V *4(ESR=4.5m ohm) Security Classification
2010/07/13
Compal Secret Data
2011/07/13 Title
PWR +CPU_CORE/+VGFX_CORE
*OCP setting value=71.5A *OCP setting value=37A Size Document Number Rev
Custom 0.1
5 4 3 2
Sheet 54 of 59
5 4 3 2 1
3DJHRI
9HUVLRQFKDQJHOLVW3,5/LVW IRU3:5
,WHP )L[HG,VVXH 5HDVRQIRUFKDQJH 5HY3* 0RGLI\/LVW 'DWH 3KDVH

D D
(1)Add PR638(0_0603_5%)
Shut down for IF the PWM3 no used, between PWM3 and +5VS 2010-03-29 DVT
PWM3 please pull high it for
+5VS and not floating
0.1 P.55 (2)connect the ISNG to +5VS
pin floating
OVP problem If the HW side is 0V,

with PWR and through the jumper will
/
HW side cause the sense pin to 0.1 P.55 Change the +VGFX_CORE
to +VGFX_COREP 2010-03-29 DVT
/x
over the votage setting
and it may happen OVP
problem.
su
C C
p.
om
yc
m
//

B B
p:
tt
h
A COMPAL ELECTRONICS A
Title
<Title> PIR POWER1
A PAW00(LA-6361P) 0.1
5 4 3 2 1
5 4 3 2 1
(PU1000)
VR_ON +CPU_CORE
ISL6266ACRZ-T +1.5VS_DMC
D D
TQFN48 Page 55
VGA_ON (U13) VGA_ON# (U40)

(PU998) SUSP
+VGA_CORE SI4800BDY-T1-GE3 +1.5VS AO4430L +1.5VSDGPU
APW7138NITRL Page 44
SO8 Page 44
SSOP16 Page 54
ADAPTER
SYSON (PU5) SUSP (PU8)
+1.5V
RT8209BGQW APL5331KAC-TRL +0.75VS
SO8 Page 53
B+ WQFN14 Page 51
(PU6) PJP25 L76
/
BATTERY VS_ON +1.05V_VCCP +1.05VS_PCH +CLK_1.05VS
RT8209BGQW
/x
(SUSP#)
WQFN14 Page 53
U38
+1.05VSDGPU
(PU3)
VCCPWRGOOD +VCCSA
RT8205EGQW
su
C C
CHARGER WQFN24 Page 49
(PU3)
p.
RT8205EGQW
WQFN24 Page 49
om
yc
+5VALW +3VALW
m
SUSP SYSON# SUSP PCH_PWR_EN# SUSP SUSP
(U49) (U46) (PU6) (U14) (U68) (UB1)

SI4800BDY TPS2062ADR SY8033BDBC SI4800BDY R599 (RE1) SI4800BDY RT9701-PB
SO8 Page 44 DFN10 Page 51 SO8
// Page 44 SO8 Page 44 SOT23-5 Page 45
B B
+3VALW_PCH
p:
+5VS +USB_VCCB +1.8VS +3V_LAN +3VALW_EC +3VS +3V
(U39) ENVDD ENVDD VGA_ON

tt
+CRT_VCC
BCM57780 (Q51) (Q30) (Q34)
+3VS_CK505
AO3413L AO3413L AO3413L
h
SO23-3 Page 37 SO23-3 Page 30 SO23-3 Page 24

+HDMI_5V_OUT
+1.2V_LAN +DVDD_AUDIO
+BT_VCC +LCDVDD +3VSDGPU
+5VS_HDD1
+3V_WLAN
+5VS_ODD
+3V_DMC
A A
+5VAMP +VDDA

Power Rail
Custom 0.1
5 4 3 2 1
5 4 3 2 1
D D
PCH_PWR_EN# 2
U14,+3VALW_PCH
V
AC A1
MODE VIN QH4,+5VALW_PCH
V V
A2 A3 B5
VV
A5 2
V
PU2
V
B+ PU3 +3VALW_PCH
+3VALW B7 2 3
BATT V +5VALW_PCH
BATT
MODE B1
B2
B+ B4 V
V
V 4 SYS_PWROK
EC
13
PQ2
/
PCH_RSMRST# PM_DRAM_PWRGD
V
V V PCH
/x
B3 A5 B7 5 14
PBTN_OUT# H_CPUPWRGD
CPU
V V
V
51ON# EC_ON
PM_SLP_S3#
PLT_RST# 15
su
PM_SLP_S4#
C C
PM_SLP_S5#
A4 B6 PM_SLP_A# 6
PM_SLP_SUS#
V
V
p.
ON/OFF V
SYSON 7 SYSON# +1.5V
V
PU5
om
DGPU_PWR_EN 8a (DIS) VGA_ON
+3VSDGPU
V
Q6 11
SUSP#,SUSP 8
U49
yc
V
VGATE
+5VS
V
+1.5VSDGPU
U40
V
U68
V
// +3VS +1.8VSDGPU VGA
U37
B B
V
U13
V
+1.5VS +1.05VSDGPU
p:
U38
V
PU8
tt
V
+0.75V +VGA_CORE
VCCPPWRGOOD
PU998
h
V
V
PU9 PU7
+1.05VS_VCCP +VCCSA
VGA_PWROK 8b (DIS)
U47
CK505
VR_ON 9 PU1000
V
10
V
+CPU_CORE
A A

Power sequence
Custom 0.1
5 4 3 2 1
5 4 3 2 1
V ersion Change L ist ( P. I. R . L ist ) Page 1

R equest
Item Page# Title D ate Issue D escription Solution D escription R ev.
O w ner
D D
/
/x
su
C C
p.
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//
B B
p:
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h
A A

EE P.I.R (1)
Custom 0.1
5 4 3 2 1
5 4 3 2 1
V ersion Change L ist ( P. I. R . L ist ) Page 1

R equest
Item Page# Title D ate Issue D escription Solution D escription R ev.
O w ner
D D
/
/x
su
C C
p.
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//
B B
p:
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A A

EE P.I.R (2)
Custom 0.1
5 4 3 2 1

Acer Aspire 5750 5750G Gateway NV57H - Compal - LA-6901P

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Acer Aspire 5750 5750G Gateway NV57H - Compal - LA-6901P

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A B C D E

P5WE0 M/B Schematics Document

Security Classification Compal Secret Data Compal Electronics, Inc.

100MHz PCI-E 2.0x16 5GT/s PER LANE

Sub-board ENE KB930

USB Port0,1 page 39 CPU XDP

Power Circuit DC/DC

3G SKU: 3G@ USB30 SKU: USB30@ OPTMIUS SKU: OPT@ UHCI1

PCI EXPRESS* - GRAPHICS

15 FDI_LSYNC0 J19 PEG_TX#[9] C550 1 2 DIS@ 0.22U_0402_10V6K

should not be left floating PEG_TX#[14] C560 1 2 DIS@ 0.22U_0402_10V6K

C15 PEG_TX[4] L28 PEG_HTX_GRX_P10 PEG_HTX_C_GRX_P10

PEG_TX[12] C555 1 2 DIS@ 0.22U_0402_10V6K

Security Classification Compal Secret Data

CFG0 XDP_HOOK2 43 VCC_OBS_AB 44 XDP_RST#_R

JTAG & BPM

R90 TDI R95 2 1 51_0402_5%

U7 R87 UNCOREPWRGOOD: CORE

PLT_RST# NC 1 2 PM_DRAM_PWRGD_R AL35 1 R101 2 0_0402_5%

0_0402_5% SN74LVC1G07DCKR_SC70-5 SM_DRAMPWROK:DRAM power ok XDP_BPM#0_R

BPM#[1] XDP_BPM#2_R 0_0402_5% 2 @ XDP_BPM#2

0_0402_1% BUF_CPU_RST# AR30 XDP_BPM#3_R 0_0402_5% 2 @ @ R73 XDP_BPM#3

BPM#[4] AP32 XDP_BPM#5_R XDP_BPM#5

15 SYS_PWROK PM_SYS_PWRGD_BUF PM_DRAM_PWRGD_R

Issued Date Deciphered Date

11 DDR_A_D[0..63] AB6 SA_CLK_DDR0 11 12 DDR_B_D[0..63] AE2 SB_CLK_DDR0 12

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY A

AD8 DDR_A_MA11 SB_MA[10] DDR_B_MA11

AF9 V7 SB_WE# SB_MA[15]

Follow CRB1.0 +1.5V

SM_DRAMRST# DIMM_DRAMRST#_R 1K_0402_5%

A 4.99K_0402_1% RST_GATE hgih ,MOS ON

CFG Straps for Processor

JCPU1E PEG Static Lane Reversal - CFG2 is for the 16x

RSVD28 L7 1: Normal Operation; Lane # definition matches

RSVD50 R107 R108

VCCIO_SEL RSVD25 RSVD56

1/NC : (Default) +1.05VS_VTT

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

SV type CPU JCPU1F POWER

PEG AND DDR

UMA@ UMA@ UMA@ UMA@ VAXG1 VAXG_SENSE

DDR3 -1.5V RAILS

1 1 AM18 AC4 +1.5VS

floating) if the VR is stuffed

+ C22 VCCSA_VID1 51 VID0 VID1 Vout 2011CPU 2012CPU

AL2 VSS68 W32 VSS225

VSS73 W27 VSS230

Security Classification Compal Secret Data Compal Electronics, Inc.

1 DDR_A_MA13 CAS# ODT0 SA_ODT1 1K_0402_1%

1 1 1 DDRA_CS1_DIMMA# VDD15 VDD16 SA_ODT1 6

+ 6 DDRA_CS1_DIMMA# A13 ODT1

B DDR_A_D42 DM5 DQS5 DDR_A_D46 B

DDR_A0_DM0 DM7 DQS7

0_0402_5% 2 SA0 EVENT# D_CK_SCLK 12,14

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR_B_D27 DQ26 DQ30 DDR_B_D31

DDR_B_MA3 VDD7 VDD8 DDR_B_MA2

DDR_B_D32 127 128 DDR_B_D36

1 1 DDR_B_DQS#6 DQ49 DQ53 DDR_B0_DM6