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Project : MT6572
REF_SCH TOP LEVEL EMI x32 BPI, APC FEM
EMI
TX RX

Memory
D
MCP NFI RF IQ D
NFI
BSI ctrl
RX
MT6166 balun

MSDC 4-bit MSDC1


26M_BB
micro SD 26M
26M_AUD DCXO ctrl
+ hot-plug

26M_CN
26M_CN
ABB

CMMB
EINT
SPI MT6572 CONN IQ
TCXO
Connectivity ANT

MT6627
CONN ctrl

C C

32K_BB RTC 32K


Camera IF
Camera CAM
Module (MIPI / Parallel)

Camera IF MT6323 Headset


2nd Camera (HPL, HPR, AU_VIN1)
Module
I2C
i2C_0 Class D/AB

LCD IF
LCD LCD AUD I/F Audio Receiver
module (MIPI / Parallel) Speech

I2C
i2C_1 AU_VIN0
CTP EINT
B controller B

I2C

Motion EINT
POWER
Sensor
I2C
ALS + PXS
EINT
SIM2
SPI SIM2
I2C Power
Management SIM1
Magnetic EINT SIM1
sensor
VIB
I2C
BC1.1
Gyro EINT Charger
sensor

Charger
Battery
Keypad

BJT
A
JTAG A

USB 2.0 micro USB


Debug USB
UART
port

Title
MT6572 Block diagram
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Thursday, December 27, 2012 Sheet 1 of 13


5 4 3 2 1
5 4 3 2 1

cap Close to BB IC

U101-H C108
cap Close to BB IC
0402

100nF

VIO18_PMU VIO18_PMU T25 DVDD18_MIPIRX AVDD28_DAC F1 VTCXO_PMU VTCXO_PMU


U25 DVSS18_MIPIRX
AVDD18_AP E5

R25 DVDD18_MIPITX DVDD18_PLLGP U9


P25 DVSS18_MIPITX
D D

AVDD18_MD D3 VIO18_PMU
VIO18_PMU VIO18_PMU H23 AVDD18_USB AVSS18_MD A1
VUSB_PMU VUSB_PMU G24 AVDD33_USB AVSS18_MD A4
G23 C3 100nF 100nF
AVSS33_USB AVSS18_MD 0402 0402

1uF AVSS18_MD E2 C112


100nF 0402 C140
100nF 100nF 0402
C113
0402
0402
C104
C107 C101
REFP F6 BG
REFP
1uF
0402

C109 G6 REFN

IC_CPU_MT6572

dedicate VSS ball, must return to cap then to main GND: VIO_EMI

1. REFN(G6) => C109


2. DVSS18_MIPIRX(U25) => C107
U101-B
3. DVSS18_MIPITX(P25) => C101 W9
1.8V IO for DDR1
VCC VCCIO_EMI
VCCIO_EMI W12 1.2V IO for DDR2
Memory W14
VCCIO_EMI 100nF 100nF
AC21 GND VCCIO_EMI W16 0402 0402

AB11 W19 C105 C130


GND VCCIO_EMI
AF13 GND If double-sided SMT, put C405 & C406 below BB.
AD11
C AC8
GND 100nF If single-sided SMT, put C405 & C406 around memory. C
GND DVDD
0402

AB5 GND C141


AB14 Peripheral
GND
W26 GND DVDD18_MC0 AA1 VIO18_PMU
VIO18_PMU
T15 GND DVDD18_CAM K20 VIO18_PMU
W23 GND DVDD18_VIO_1 L3 VIO18_PMU
T14 GND DVDD18_VIO_2 J19 VIO18_PMU
AF26 GND DVDD18_VIO_3 H13 VIO18_PMU R119
G3 GND DVDD18_LCD AB24 DVDD18_LCD 0402
K21 GND 0R
L11 GND
L12 GND 1uF
0402

L14 GND DVDD3_MC1 K24 VMC_PMU VMC_PMU C126


L15 GND
L16 GND DVDD3_LCD W24 DVDD18_LCD
M5 GND
M11 GND DVDD28_BPI C10 NC
M12 1uF
0402

GND 0402 C121


M13 GND C117
M14 GND VCC
M15 GND
M16 CPU P6
GND VCCK_CPU
N10 GND VCCK_CPU T7
N8 P7
N9
GND
GND
VCCK_CPU
VCCK_CPU P8 Close to BB IC, recommand < 150mil
N11 GND VCCK_CPU P9
N12 GND VCCK_CPU R6
N13 GND VCCK_CPU R7
N14 GND VCCK_CPU R8
N15 GND VCCK_CPU R9
N16 GND VCCK_CPU T6 Based on your system level
N22 U6
GND VCCK_CPU design , if better FM performance
P10 GND VCCK_CPU T9
P11 GND VCCK_CPU T8 is needed on your system ,
P12 GND VCCK_CPU U7
P13 please refer to FM desense
GND
P14 GND performance enhance proposal
P15
B
P16
GND
GND
120mil VPROC_PMU B
VCC
R10 GND
R11 Core J9
GND VCCK
R12 GND VCCK J15
R13 GND VCCK M9
R14 GND VCCK K6
R15 K7

0R
GND VCCK
R16 GND VCCK K8
T10 GND VCCK K9

R125 0402
T11 GND VCCK K11
T12 GND VCCK K14

100nF

100nF
100nF

100nF
T13 K15

1uF
GND VCCK

1uF
1uF

1uF
AF1 GND VCCK M10 2.2uF 4.7uF C106 C102 C103
2.2uF
VCCK K16 0402 0402 0402 0402 0402 0402 0402 0402 0603 0603 0603 0603 0603 0603

U10 K17 10uF 10uF 10uF

C115

C118

C120
C137

C116

C135

C119
C134
GND VCCK C114 C136 C111
U11 GND VCCK U17
V13 GND VCCK J8
W11 GND VCCK L7 Vproc remote sense :
Y21 L8
GND VCCK
L9 differential 4mil with good shielding, from the BB to PMIC
VCCK
VCCK L17
VCCK M6
M7 4mil - defferential - GND shielding [3,4,5,6,7,8,9,10,11,12,13]
GND_SIGNAL
VCCK
VCCK M8
VCCK J10
VPROC_FB [4]
VCCK J11
VCCK J14
VCCK T16
VCCK L6
VCCK K12
VCCK T17
VCCK J16
VCCK J17
VCCK U12
VCCK U13
VCCK U14
VCCK U15
A VCCK U16 A
VCCK M17
VCCK R17

A26 DUMMY

IC_CPU_MT6572
Title
BB- Power
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 2 of 13


5 4 3 2 1
5 4 3 2 1

U101-A
[7] RX_I_P D2 B12 ASM_VCTRL_A [8]
U101-D
DL_I_P BPI_BUS0
[7] RX_I_N C2 DL_I_N BPI_BUS1 B11 ASM_VCTRL_B [8]
[7] RX_Q_P B1 DL_Q_P BPI_BUS2 C12 ASM_VCTRL_C [8]
C1 DL_Q_N BPI_BUS3 A11
[7] RX_Q_N WG_GGE_PA_ENABLE [8]
[4] AUD_MISO J1 AUD_DAT_MISO
BPI_BUS4 D11 PWM_BL_EN [9] K5 AUD_CLK_MOSI
[7] TX_I_P A2 C11 [4] AUD_CLK
[7] TX_I_N B2
UL_I_P
UL_I_N
BPI_BUS5
BPI_BUS6 A13
EINT_HP [5]
[11] [4] AUD_MOSI
K1 AUD_DAT_MOSI reserve for JTAG debug
BPI6_ATV_EN
[7] TX_Q_P B4 UL_Q_P
D [4] PMIC_SPI_MOSI L2 PMIC_SPI_MOSI D
[7] TX_Q_N B3 UL_Q_N BPI_BUS7 A10 W_PA1_ON [8]
[4] PMIC_SPI_MISO L5 PMIC_SPI_MISO
BPI_BUS8 B10 W_PA2_ON [8]
[4] PMIC_SPI_SCK L4 PMIC_SPI_SCK
BPI_BUS9 D10 W_PA5_ON [8] VIO18_PMU
[4,6] K2 PMIC_SPI_CSN
E9 PMIC_SPI_CS
BPI_BUS10 LCD_EN [9]
BPI_BUS11 E8 [9] [4] R201
VBAT_EN WATCHDOG G2
B9 WATCHDOG
BPI_BUS12 I2S0_WS [4,7] H4 [3,4] SIM1_SCLK 0402
[8] VM0 A8 B8 SRCLKENA SRCLKENA
VM0 BPI_BUS13 I2S0_CK J2 2.2K
A7 E7 [4] EINT_PMIC EINTX
[8] VM1 VM1 BPI_BUS14 I2S0_DATA
BPI_BUS15 D7
GPIO_FLASH_EN [9] Normal : NC
[3,4] H5
[7] TXBPI D5 TXBPI BSI_DATA2 D6 BSI-A_DAT2 [7]
SIM1_SCLK SIM1_SCLK JTAG : 20K
[4] SIM1_SIO M3 SIM1_SIO
BSI_DATA1 C7 BSI-A_DAT1 [7]
[8] WG_GGE_PA_VRAMP F2 APC BSI_DATA0 F9
BSI-A_DAT0
BSI_EN F11 BSI-A_EN [4] SIM2_SCLK J5 SIM2_SCLK
F3 VBIAS BSI_CLK G11
BSI-A_CK [4] SIM2_SIO M1 SIM2_SIO

Reserve R footprint
for JTAG debugging

IC_CPU_MT6572 IC_CPU_MT6572

U101-E

C C
[7] CLK1_BB E1 CLK26M PWM_A D12 GPIO_ATV_RST [11]
SYSTEM PWM E12
PWM_B LCD_SHIFT_EN [9]
[4] CLK32K_BB H2 CLK32K_IN
LCD
Based on your system level design , if better [4] RESETB M2 SYSRSTB
Parallel
LPD17 N1
DPI_R5_SHIFT [9]
LPD16 N2
DPI_R4_SHIFT [9]
desense performance is needed on your G4 TESTMODE LPD15 N3
DPI_R3_SHIFT [9]
P2
system , please refer to desense AC24
LPD14
N4
DPI_R2_SHIFT [9]
FSOURCE LPD13 DPI_R1_SHIFT [9]
performance enhance proposal LPD12 R2
DPI_R0_SHIFT [9]
LPD11 N5
DPI_G5_SHIFT [9]
[4] CHD_DP J26 CHD_DP LPD10 R1
BC 1.1 DPI_G4_SHIFT [9]
[4] CHD_DM J25 CHD_DM LPD9 P5 [9]
DPI_G3_SHIFT
LPD8 T1 DPI_G2_SHIFT [9]
LPD7 R5 [9]
U101-G
DPI_G1_SHIFT
[5] USB_DM 90-ohm differential G26 USB_DM LPD6 T2
DPI_G0_SHIFT [9]
G25 USB 2.0 T5
[5] USB_DP USB_DP LPD5 DPI_B5_SHIFT [9]
USB_VRT H25 U2
NC 0402
USB_VRT LPD4 DPI_B4_SHIFT [9]
MIPI_2nd_CAM R203 5.1K T3 [9]
LPD3 DPI_B3_SHIFT
0402

L25 CMPDN2 C202


Parallel 8-bit LPD2 U5 DPI_B2_SHIFT [9]
K25 CMRST2 i2C
[3,9,11] SCL_0 C25 SCL_0 LPD1 T4 [9]
H22 DPI_B1_SHIFT
[9] CMPDN
J22
CMPDN
close to BB [3,9,11]SDA_0 C26 SDA_0 LPD0 V2
DPI_B0_SHIFT [9] MT6572 support JTAG from below :
[2,3,4,6,7,9,13] [9] CMRST CMRST [3,9,13] B24
SCL_1 SCL_1
VIO18_PMU
Y22 [9]
[3,9,13] SDA_1 B23 SDA_1 1. KP (recommand)
CMMCLK CMMCLK
MIPI_RDN0 R24
R23
RDN0 MIPI_CAM Y23 CMPCLK[9,11]
2. MC1
MIPI_RDP0 RDP0 CMPCLK AD25
LPCE0B GPIO_GPS_LNA_EN [10]
MIPI_RDN1 R22
R21
RDN1
V25
[9] DPI_G7_SHIFT F24 SPI_MISO LPTE AB26 DPI_CK_SHIFT [9] 3. CAM
NC
NC

SPI
NC

MIPI_RDP1 RDP1 RCN_A CMVSYNC [9,11] [9] DPI_G6_SHIFT F25 AC26


SPI_MOSI LRSTB [9]
MIPI_RCN R26
T26
RCN RCP_A W25
V24
CMHSYNC [9,11] [9] DPI_B7_SHIFT F23 SPI_SCK LPRDB AA22
LRSTB
DPI_HSYNC_SHIFT [9] for JTAG pin out from MC1/CAM, refer
MIPI_RCP RCP RDN1_A CMDAT7 [9,11] E23 AB23
0402

0402

0402

[9] DPI_B6_SHIFT SPI_CS LPA0 DPI_DE_SHIFT [9]


P19
RDP1_A V23
U22
CMDAT6 [9,11]
LPWRB AC25
DPI_VSYNC_SHIFT [9]
to HW design notice
R2

CMDAT5 [9,11]
R3

R4

MIPI_TDN0 TDN0 RDN0_A


P20 MIPI_LCD U21
MIPI_TDP0 TDP0 RDP0_A CMDAT4 [9,11]
[9]EINT_CTP N25 TDN1
[12] MC1CMD K23 MC1_CMD KROW0 B25 KROW0 [5]
MIPI_TDP1 N26 TDP1 CMDAT3 Y26 CMDAT3 [9,11] T-flash KP
[12] L21 A24
P23 Y25 MC1CK MC1_CK KROW1 GPIO_CTP_PWREN [9]
TDN2 CMDAT2 CMDAT2[9,11] [12] K22 B26
P24 AA25 MC1DAT0 MC1_DAT0 KROW2 GPIO1_CTP [9]
B MIPI_TDP2 TDP2 CMDAT1 CMDAT1[9,11] [12] M22 C24 B
N20 AB25 MC1DAT1 MC1_DAT1 KCOL0 KCOL0 [5]
[13] EINT_ACC TCN CMDAT0 CMDAT0[9,11] M25 D24
N19 [12] MC1DAT2 MC1_DAT2 KCOL1 KCOL1 [5]
[13] EINT_MAG TCP L26 A25
[12] MC1DAT3 MC1_DAT3 KCOL2 GPIO2_CTP [9]

R202 B7 AUX_IN0 UTXD1 E25 UTXD1


0402 MIPI_VRT P26 VRT ADC UART
B6 AUX_IN1 URXD1 D25 URXD1
1.5K C5 E26
AUX_IN2_XP UTXD2 DPI_R7_SHIFT [9]
B5 AUX_IN3_YP URXD2 F26 DPI_R6_SHIFT [9]
close to BB C4
A5
AUX_IN4_XM
AUX_IN5_YM
IC_CPU_MT6572

IC_CPU_MT6572

VCAM_IOPMU

R204
0402

2.2K
R205
0402

2.2K

[3,9,11]
SCL_0
[3,9,11]
SDA_0
Power by CAM_IO

A A
VIO18_PMU

R206
0402

2.2K
R207
0402

2.2K

[3,9,13] SCL_1 Power by CTP, MEMS sensor


[3,9,13] SDA_1
Title
BB - peripheral
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 3 of 13


5 4 3 2 1
5 4 3 2 1

Charger

1. Close to Battery Connector.


VBUS
Delete PA
(Rsense (R328) <10mm)
D 2. Main path should be 40mil. D
(VBUS -> U303's E, -> U303's C -> R328 -> VBAT)
3. Star connection from R328 to BAT Connector
R329
0402 VCDT [4]
330K
R324
0402
VCDT rating: 1.268V
U301
39K B301
B305
K1 1 +
SPK_P C399
L1 0402 2 - SPK1
40mils SPK_N 100pF B302
VBAT P1 VBAT_SPK B306
2.2uF
0402

L2 H1 SPEAKER
C313 GND_SPK AU_HSP AU_HSP [5]
R331 G1 C353 C354
AU_HSN AU_HSN [5]

VR311
VR310
CHR_LDO [4]
0402 0402

0402
33pF 33pF
3.3K AU_HPL H4 AU_HPL [5]
F2 AU_MICBIAS0 AU_HPR J4
6

MICBIAS0 AU_HPR [5]


C C E U303 MICBIAS1 G2 AU_MICBIAS1
100nF
STT818B 0402

C312
[5] AU_VIN0_P E4 AU_VIN0_P ISINK0 E9
AUDIO DRIVER LED_KEYPAD
C C B [5] AU_VIN0_N F4 AU_VIN0_N ISINK1 C9
ISINK2 E10
1
1

[5] AU_VIN1_P G3 AU_VIN1_P ISINK3 C10 FLASH_LED


U305 [5] AU_VIN1_N G4 AU_VIN1_N
3 2 SSM3K35MFV VDRV [4]
VA_PMU VA_PMU AU_VIN2_P D2 AU_VIN2_P
AU_VIN2_N D1 AU_VIN2_N

1uF J2
40mils 4mil AVDD28_ABB
ISENSE [4]
0402

C314 D3 AVDD28_AUXADC
H2 GND_ABB
Rsense R328 Differential
0805

0.2R
VBAT [4,5,8,9] E2
4mil [5] ACCDET ACCDET L301
BUCK OUTPUT C14
40mils VPROC
E1 D14 VPROC_SW
ISENSE/BSTSNS 4mil [7] CLK4_AUDIO CLK26M VPROC
E14
VPROC_PMU [2]
VPROC L_MIP25202R2MBE

Delete Diode
AUXADC_REF [6] differential to Rsense NC C330
BATTERY [4,7]

0402
VPROC_FB B12 VPROC_FB [2]
AUXADC_REF
CONNECTOR
CHARGER C12
GND_VPROC_FB GND_SIGNAL [2,3,5,6,7,8,9,10,11,12,13]
[4,5,8,9] VBAT VBAT P13 BATSNS
R334 L302 [8]
ISENSE P12 A14 VPA
0402

[4] ISENSE ISENSE VPA


40mils 16.9K 1% [4] BAT_ON BAT_ON K3 B14
BATON VPA
VCDT A12 L_MIP25202R2MBE
[4] VCDT VCDT 2.2uF
C 40mils C
[4] VDRV VDRV M13 VDRV VPA_FB D12 0603

J204
80mil [4,5,8,9]
PAD-2.5X4 VBAT C323
R317 1K
J205
PAD-2.5X4 0402 BAT_ON [4] [4] CHR_LDO CHR_LDO N13 CHRLDO L303
C305 H14 VSYS_SW
J203 0805 C302 VSYS VSYS_PMU
PAD-2.5X4 0402
1uF
22uF 100nF R335 0402
CONTROL SIGNAL L_MIP25202R2MBE
0402

C316 R316 1K
27K 1% [5] M2
PWRKEY 0402 PWRKEY
[3] WATCHDOG A1 SYSRSTB
VR301

VR302

[3] RESETB K4 RESETB


A9 ALDO OUTPUT M3
FSOURCE VA VA_PMU
A7
Close to PMIC [3] EINT_PMIC
N12
INT
N3 VCN_2V8_PMU
EXT_PMIC_EN VCN28
VTCXO L4
VTCXO_PMU
N2 PMU_TESTMODE
P3 VCAMA_AVDD
VCAMA
[3] AUD_MOSI E7 AUD_MOSI VCN33 M6 VCN_3V3_PMU
[3] AUD_CLK E8 AUD_CLK AVDD33_RTC C3 VRTC
[3] AUD_MISO B6 AUD_MISO
if battery NTC is 10kohm, R334=39K, R335=90K 1uF
C355
[3,7] SRCLKENA A2 SRCLKEN

0402
if battery NTC is 47kohm, R334=190K, R335=390K FCHR_ENB M1 FCHR_ENB
DLDO OUTPUT

VM J13 VM_PMU
Refer to MT6323 HW design notice [3] PMIC_SPI_SCK D9 H11
SPI_CLK VRF18
[3,6] PMIC_SPI_CS B7 SPI_CSN VIO18 L12 VIO18_PMU
[3] PMIC_SPI_MOSI D8 SPI_MOSI VIO28 M4 VIO28_PMU
VBAT [3] PMIC_SPI_MISO B8 SPI_MISO VCN18 J12 VCN_1V8_PMU
VCAMD K14 VCAMD_PMU
VCAM_IO L13 VCAM_IOPMU
F13 VBAT INPUT
VBAT_VPROC
80mil 30mil F14 VBAT_VPROC
G13 VBAT_VPROC VEMC_3V3 P7 VEMC_3V3_PMU
VBAT A13 VBAT_VPA VMC L6 VMC_PMU
VMCH P4 VMCH_PMU
15mil VBAT H13 VBAT_VSYS VUSB N6 VUSB_PMU
P8 VBAT_LDOS3 VSIM1 P9 VSIM1_PMU
20mil P6 VBAT_LDOS3 VSIM2 N9 VSIM2_PMU
10uF 20mil VBAT P5 VBAT_LDOS2 VGP1 L8 VGP1_PMU
20mil VBAT P2
500mW
2

1uF
0603
VBAT_LDOS1
C310 0402
M7 VIBR_PMU
VIBR
D301

C333 20mil J14 N8


VSYS_PMU AVDD22_BUCK VGP2
M14 AVDD22_BUCK VGP3 L14 VGP3_PMU
N7
1

VCAM_AF VCAM_AFPMU
DVDD18_DIG_PMIC
A8 DVDD18_DIG
VF : 4.85V~5.36V
VIO18_PMU VIO18_PMU A5 DVDD18_IO

B Between IC and IO port [4,7] AUXADC_REF C2 AUXADC B


AUXADC_VREF18
VREF
[7] AUXADC_TSX
B1 AUXADC_AUXIN_GPS VREF P14 dedicate VSS ball, must return to cap then to main GND:
[7] GND_AUXADC B2 AVSS28_AUXADC
100nF 1. GND_VREF(N14) => C320
C325
0402

0402
C320
100nF BC 1.1
0402 100 nF
C322 [3] CHD_DM A10 N14
CHG_DM GND_VREF
[3] CHD_DP A11 CHG_DP
C322 must to be close
RTC 32K : X301+C324+C319=> mount, R333=> NC
to PMIC AUXADC_TSX pin R301
RTC_32K1V8 D5 CLK32K_BB [3] 32K-less: X301+C324=> remove, C319+R333=> 0R VRTC

0402
0R SIM LVS RTC

RTC
RTC_32K2V8 C4
B5 A3 32K_IN

32.768K&SMALL
[3] SIM1_SCLK SIM1_AP_SCLK XIN
[3] SIM1_SIO M11 SIMLS1_AP_SIO XOUT A4 32K_OUT
E6 2 1
SIM1_AP_SRST
10uF

X301
10uF

1uF

1uF
1uF

C360 C303 C304 [3] SIM2_SCLK C5 SIM2_AP_SCLK GND_ISINK B10


C301
[3] SIM2_SIO K11 SIMLS2_SIO GND_VSYS G11
0603 0603 0603 0402 0402 0603 0603 0402
0402

D6 E13 18pF 18pF


4.7uF SIM2_AP_SRST GND_VPA 0402
C307

10uF
Connect TSX/XTAL GND
C308

0402
C345

10uF E11 C324


C306

C309

1uF GND_VPROC C319


[12] SCLK M9 SIMLS1_SCLK GND_VPROC F11
to AUXADC_GND first [12] SIO N11 SIMLS1_SIO GND_VPROC F10 100NF
than connect to main GND M10 0402

[12] SRST SIMLS1_SRST C328


GND_LDO K6 Close to chip
[12] SCLK2 K9 SIMLS2_SCLK GND_LDO K8
[12] SIO2 L11 SIMLS2_AP_SIO
[12] SRST2 K10 SIMLS2_SRST GND_LDO F5

VIBRATOR
VIBR_PMU GND_LDO F6
R333
GND_LDO F7 0402 DCXO_32K [7]
F8
refer to system analog LDO GND_LDO NC
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO F9
G5
performance improve proposal GND_LDO
GND_LDO G6
J10
J9
J8
J7
J6
H10
H9
H8
H7
H6
H5
G9
G8
G7
R364

0R
0402

Refer to MT6323 design notice


15mil
for Buck GND layout rule Power mgmt 6*6
1

+ MT600
VIBRATOR
C374
0402
A
100nF
-
2

A A

Refer to GPS co-clock layout rule

Title
PMIC
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 4 of 13

5 4 3 2 1
5 4 3 2 1

Handset Microphone 1 Earphone RECEIVER

MICBIAS0

D D
Close to MIC Close to BB
R401
0402
[5] HP_MIC_R J401
1K
CON_AJ_DIMA

R405

1.5K
0402
C413
Digital Microphone is reserved 0603

VR409

VR410
4.7uF

VR408
close to connector
1
close to IC C419 GND

0402
0402
AU_VIN0_P [4] B413
1 R402 0R

C430
100nF
0402

MICP NC C422 2
MIC301 100pF MIC

C440
0402

10uF
2 33pF
0402

MICN
MIC_PAD C428 B408 B410 3
[4] AU_HPL 0402

0603
CH-L
[4] 100R R434

0402
0402
AU_VIN0_N 4
0R R403

C432
100nF
CH-R
5
33pF C433
Analog MIC R406

0402
0402 0402

C441
C434 6

10uF
33pF 1.5K B411 NC
B409 C492 C490 C491
[4] AU_HPR 0402

0603
0402 0402 0402

100R R436 1nF 1nF 1nF


TV409
TV408

C423
0402

33pF
R412 R450

0402
C421 R451 [3] 47K R448

0402

0402
1K EINT_HP 0402
470R 470R
0402

NC 0R R452 [10]
tie together and single via to GND plane 0402 FM_ANT

NC R456
TV_ANT [11]
470K 0402

TV405

L420
0805
[4,9,11,13] VIO28_PMU 0402

R445
0R R453
0402 FM_RX_N_6572 [10]

USB
IO400

C
HANDSET RECEIVER CON_IO_USB5PIN
C
1
VCHG VBUS [4,5]
6
7 2
D- USB_DM [3,5]

3
D+ USB_DP [3,5]
8
9 4
NC
5
COM
close to connector C420
0603

1uF

[4] AU_HSN
AU_OUT0_N_OUT
BEAD403

+
C414
-
0402

100pF

REC1

[4] AU_HSP
BEAD405

C418 C408
VBUS [4,5]
VR411

VR412

0402 0402

33pF 33pF
USB_DM [3,5]

USB_DP [3,5]

TV403

TV402
TV401
B B

Earphone MICPHONE Side key and Power key


[4] MICBIAS1
J202
1

2
PWRKEY [4,5]
R408

1K
0402

GND of C454 and headset 3


KROW0 [3,5]
Close to BB Close to MIC
should tie together and single 4
KCOL0 [3,5]
100nF

C454
C415

via to GND plane


10uF

AU_VIN1_N1 5 [3]
[4] KCOL1
AU_VIN1_N
0603
0402

C409 40mil
40mil
R411

1.5K

USB_DM [3,5]
0402
0402

33pF Close to CON401 40mil


USB_DP [3,5]
C402 40mil VBUS [4,5]
0402
40mil

TV803

TV802

TV801

TV805
100pF
40mil
PWRKEY [4,5]
40mil [3,5]
KROW0
KCOL0 [3,5]
C416 tie together and single via to GND plane 40mil
100nF
C417

0402

33pF 40mil VBAT


[4] AU_VIN1_P HP_MIC_R [5]
0402

R410
0402

1K
[4] ACCDET

A A

Title
04 Audio,I/O,USB
Size Document Number Rev
D MT6575 PHONE V1.0

Date: Sunday, December 18, 2011 Sheet 5 of 13


5 4 3 2 1
[3,4] PMIC_SPI_CS

R502

0402
NC

U101-F HW trapping PIN


20K: VM=1.8V
DRAM DRAM
AF2 Data Ctrl
[6] ED31 ED31
AC5 AF25 VIO18_PMU
[6] ED30 ED30 ECS0_B ECS0_B [6]

NC : VM=1.2V
[6] ED29 AE4 ED29 ECS1_B AD18
ECS1_B [6]
[6] ED28 AD5 ED28

Memory MCP
[6] ED27 AF3 ED27 EWR_B AF19
[6] ED26 AF5 ED26 ERAS_B AB18 C503
[6] ED25 AE5 ED25 ECAS_B AC18

0603
[6] ED24 AB6 ED24 ECKE AB19 ECKE [6] R501 0R
VM_PMU 0402 VIO_EMI 4.7uF
[6] ED23 AB16 ED23
[6] ED22 AE13 AD12 [6] C504
[6] ED21 AE14
ED22
ED21
EDQM0
EDQM1 AE12
EDQM0
EDQM1 [6] U501

0402
[6] ED20 AC15 ED20 EDQM2 AB13 EDQM2 [6] 100nF
[6] ED19 AF16 AD8 EDQM3 [6] [6] EA0 U3 E6
ED19 EDQM3 CA0 VDD1
[6] ED18 AE15 ED18 [6] EA1 T3 CA1 VDD1 F1
[6] ED17 AE16 Y13 [6] [6] EA2 R3 V1 VIO_EMI
ED17 EDQS0 EDQS0 CA2 VDD1
[6] ED16 AF15 ED16 EDQS1 AA9 [6] [6] EA3 R2 CA3 VDD1 W6
EDQS1 C505
[6] ED15 AC7 ED15 EDQS2 AA14 [6] [6] EA4 R1 CA4
EDQS2
[6] ED14 AE7 ED14 EDQS3 Y8 [6] EA5 K2 CA5 VDD2 E5

0603
EDQS3 [6]
[6] ED13 AC9 ED13 [6] EA6 J2 CA6 VDD2 G2
AF6 AA13 [6] J3 K1 4.7uF
[6] ED12 ED12 EDQS0_B EDQS0_B [6] EA7 CA7 VDD2
AB9 Y9 [6] H3 M7
[6] ED11 ED11 EDQS1_B EDQS1_B
[6]
[6] EA8 CA8 VDD2 Put C402 & C403 between BB & memory.
[6] ED10 AF8 ED10 EDQS2_B Y14 EDQS2_B [6] EA9 H2 CA9 VDD2 U2
[6] ED9 AE8 ED9 EDQS3_B AA8 EDQS3_B [6] VDD2 W5
AE6 [6] T8 C506 100nF
[6] ED8 ED8 ED0 DQ0

0402
[6] ED7 AE11 ED7 EDCLK0_B Y18 R8 DQ1 VDDQ F7
[6] ED1
[6] ED6 AE9 ED6 EDCLK0 AA18 R7 DQ2 VDDQ F10 C507 100nF
[6] ED2

0402
[6] ED5 AF9 ED5 [6] ED3 R9 DQ3 VDDQ G5
C555 100nF
[6] ED4 AC13 ED4 EDCLK1_B AA19
[6] ED4
R6 DQ4 Power VDDQ H9

0402
[6] ED3 AF11 ED3 EDCLK1 Y19 [6] ED5 P7 DQ5 VDDQ J10
[6] ED2 AF12 ED2 [6] ED6 P8 DQ6 VDDQ L6
[6] ED1 AE10 ED1 [6] ED7 P9 DQ7 VDDQ M6 C508 1uF

0402
[6] ED0 AD15 ED0 ND0 Y4 [6] ED8 K9 DQ8 VDDQ N6
ND1 AA2 K8 DQ9 VDDQ R10
[6] ED9 C509 4.7uF
AB17 VREF1 ND2 V5 SHUTDOWN_CTP [9] [6] K7 DQ10 VDDQ T9

0603
ED10
[6] EVREF AC11 VREF0 ND3 W1 GPIO_FLASH_SEL [9] [6] J6 DQ11 VDDQ U5
ED11
ND6 Y3 [6] ED12 J9 DQ12 VDDQ V7
DRAM
ND8 Y2 [6] ED13 J7 DQ13 VDDQ V10
AE19 Address W2 J8
EA18 ND9 [6] ED14 DQ14
AE18 EA17 ND12 W4 DO NOT use these GPIO as enable signal @ eMMC boot [6] ED15 H8 DQ15 VDDCA J1
VEMC_3V3_PMU
AE17 W3 W7 L1 VIO18_PMU
EA16 ND13 (refer to design notice - GPIO selection) [6] ED16 DQ16 VDDCA
AC23 EA15 ND15 V1 [6] ED17 U6 DQ17 VDDCA T2
AF22 EA14 NCEB W5 [6] ED18 W8 DQ18
AE21 EA13 NWRB Y5 ED19 T5 DQ19 VCC A8
[6]
AD24 EA12 U7 DQ20 VCC B2
[6] ED20
AC22 EA11 W9 DQ21 VCCQ B8
[6] ED21
AE24 EA10 ED22 V8 DQ22 VDDI A5
[6]
[6] EA9 AE26 EA9 [6] ED23 T6 DQ23 4.7uF
[6] AE25 eMMC I/F H6 B5 100nF 1uF
EA8 EA8 [6] ED24 DQ24 CLKM MC0_CK [6] 0402 0402
0603

[6] EA7 AD21 AB1 MC0_RSTB [6] [6] ED25 F8 C1 MC0_RSTB [6] C510 C511 C512
EA7 MC0_RSTB DQ25 RST
[6] EA6 AD22 EA6 MC0_DAT7 AD3 MC0_DAT7 [6] [6] ED26 E9 DQ26 CMD C5
[6] EA5 AB20 EA5 MC0_DAT6 AC3 MC0_DAT6 [6] [6] ED27 G7 DQ27 eMMC [6]
[6]EA4 AE22 EA4 MC0_DAT5 AC2 MC0_DAT5 [6] H5 DQ28 DAT7 B4 MC0_DAT7
[6] ED28
[6]EA3 AF21 EA3 MC0_DAT4 AD2 MC0_DAT4 [6] [6] ED29 E8 DQ29 DAT6 A4 MC0_DAT6 [6]
[6] EA2 AE23 EA2 MC0_DAT3 AE2 MC0_DAT3 [6] [6] ED30 G6 DQ30 DAT5 A6 MC0_DAT5 [6]
[6] EA1 AF18 EA1 MC0_DAT2 AE1 MC0_DAT2 [6] [6] E7 DQ31 DAT4 B6 MC0_DAT4 [6]
ED31
[6] EA0 AE20 EA0 MC0_DAT1 AB3 MC0_DAT1 [6] DAT3 A7 MC0_DAT3 [6]
R454 240
MC0_DAT0 AB2 MC0_DAT0 [6] 0402 ZQ0 G3 ZQ0 DAT2 B7 MC0_DAT2 [6]
AC1 [6] R455 240 ZQ1 F3 B3
MC0_CK MC0_CK 0402 ZQ1 DAT1 MC0_DAT1 [6]
AF24 ERESET MC0_CMD AE3 DAT0 A3 MC0_DAT0 [6]

F6 VSSQ CS0# P1 ECS0_B [6]


F9 VSSQ CS1# P2 ECS1_B [6]
IC_CPU_MT6572 G10 VSSQ
H10 N1 [6]
VSSQ CKE0 ECKE
J5 VSSQ CKE1 N2
K10 VSSQ
M5 VSSQ CLK M3
P10 VSSQ CLK# L3
R5 VSSQ
T10 P6 EDQS0 [6]
VSSQ DQS0
U10 VSSQ DQS0# P5 EDQS0_B [6]
V6 VSSQ DQS1 K6 EDQS1 [6]
V9 VSSQ DQS1# K5 EDQS1_B [6]
Please make sure the ball map is T1
DQS2 U8
U9
EDQS2
EDQS2_B
[6]
[6]
VSSCA DQS2#
[6]
match to the MCP type you selected
M1 VSSCA DQS3 G8 EDQS3
H1 VSSCA DQS3# G9 EDQS3_B [6]

B9 VSSM DM0 N5 EDQM0 [6]


E1 L5 EDQM1 [6] VIO_EMI
VSSM DM1
F2 VSS LP-DDR2 DM2 T7 EDQM2 [6]
F5 VSS DM3 H7 EDQM3 [6]
G1 VSS R512

0402
L2 VSS VREFCA K3 [6] 8.2k
EVREF
M8 VSS VREFDQ M9
U1 VSS
V2 VSS NC C2 [6] EVREF
V5 VSS NC C4
C3 VSSQM NC C6
D1 R513 100nF

0402
NC
A1 D2 8.2k 0402

DNU NC C502
A2 DNU NC D3
A9 DNU NC D4
A10 DNU NC D5
B1 DNU NC D6
B10 DNU NC E2
E10 DNU NC E3
W1 DNU NC M2
W10 DNU NC N3
Y1 DNU NC P3
Y2 DNU NC V3
Y9 DNU NC W2
Y10 W3 Title
DNU NC
Memory
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 6 of 13


D D

SKY77590 control logic table


Enable VctC VctB VctA Modify Match
LB_GMSK_TX H L L H W_PA_OUT_B1 [8]

4.3pF
U603

C624
HB_GMSK_TX H L H H

C625
IC_SAW_SAYFP1G95CA0B00

0R
LB_EDGE_TX H H L H 3 TX ANT 6

0402
TRX1 [8]

0402
1 RX

L2
HB_EDGE_TX H H H H 8 RX

0402

NC
2nH NC
0402

C1

4.3nH
0402

L602

G
G
G
G
G
C612
TRX1 L H L L C626

0402
0402

2
4
5
7
9
NC
TRX2 L H H L

0402

4.3pF
TRX3 L H L H

C627
NC
L1
TRX4 L H H H

0402
[8]
TRX5 L L H L W_PA_OUT_B5
U602

C621
33pF
TRX6 L L L H C620 1.5nH
IC_SAW_SAYFP836MCC0F00
3 TX ANT 6 TRX5 [8]

0402

0402
1 RX

33nH
5.6nH

L613
8 RX

L614

L634
NC
0402

0402

0402

NC
0402

C622

G
G
G
G
G
0402

2
4
5
7
9
C623 1.5nH

[8]
W_PA_OUT_B2

3.9pF
C651
U601

6.8pF
C649
IC_SAW_SAYRJ1G88CA0B0A

0402
L600 12nH 3 TX ANT 6 TRX2 [8]

L633

0402
[7] 1 RX 12nH
LB_RX_P

0402

NC
0402
8 RX 0402

L636
2.7nH
Logic C628 C641

L635
XMODE VXODIG

NC
0402
MODE

G
G
G
G
G
DCXO_

0402
0402
L615

39nH
L616
0402
NC

2
4
5
7
9
0402
NC
32K_EN

0402

3.9pF
L631

C652
C600

10
22pF
L618 Z600

NC
DCXO + 32K XO 0(GND) [8] 2G_LB

GND
1(VIO18) 1(VIO18)

0402
L619 12nH

0402
0402
1 LBIN LBOUT 9 LB_RX_N [7]
NC NC 0402
C 0402
2.2nH 0402
C
DCXO + 32K-Less 1(VTXCO28) 1(VTXCO28) 1(VTXCO28) C665 C666 2 GND LBOUT 8

GGE_PA_LB_IN [8]
GGE_PA_HB_IN [8]
3 GND HBOUT 7

W_PA_LB_IN [8]
C667
22pF

W_PA_B1_IN [8]

W_PA_B2_IN [8]
L622
L623 6.2nH
[8] 2G_HB 4 HBIN HBOUT 6 HB_RX_P [7]
0402

GND
0402 0402

NC 3nH 1.5pF
0402

900 1800MHz
0402

C668 C670

7.5nH
L624

L625
0402
0402
NC

VRF18_PMU [7]

470nF
C669
L626 6.2nH
R615 NC HB_RX_N [7]
0402
VTCXO_PMU

0402
0402
DCXO_32K_EN [7]
[2,4,7]
R616

2nH
2nH
0R
0402

U600
PDET [8]

0402

0402
L617

L632
R617 0R
[2,3,4,6,7,9,13] VIO18_PMU 0402
XMODE [7]

D11
A10

A11

B11

B10
C10
D3
C3

C2

A2

A3

B3

B4

A5

B5

A6

B6

B8

A8

A9

C7

C8

C9
E3

J2

J7

J8
R618 NC
[2,4,7] VTCXO_PMU

3GB1_RXP

DET
3GB1_RXN

3GB5_RXP

3GB5_RXN

3GB2_RXP

3GB2_RXN

3GB8_RXP

2GHB_TX

3GH1_TX

3GH2_TX

3GL5_TX

2GLB_TX

VTXHF
3GB8_RXN
GND
GND
GND
GND
GND

GND
GND

GND
GND
GND
GND
GND
0402

F3 GND GND D9
G3 GND GND E9
H3 GND GND F9
J3 GND GND G9
C4 FDD RX TXO H9
R619 0R GND GND
D4 GND GND J9
[2,3,4,6,7,9,13] VIO18_PMU 0402
VXODIG [7]
TDD_B40_RXP A1 B40_RXP DETGND D10
R620 NC
TDD_B40_RXN B1 B40_RXN TMEAS C11
[2,4,7] VTCXO_PMU 0402
TMEAS
[7] LB_RX_P C1 LB_RXP V28 E10 VTCXO_PMU [2,4,7]
TDD RX
[7] LB_RX_N D1 LB_RXN 3GTX_IP G10 TX_I_P [3] C674 R639

0402
connect to main GND 0402
0R
[7] HB_RX_P E1 G11 470nF
HB_RXP 3GTX_IN TX_I_N [3]
[4] AUXADC_REF Route AUXADC_REF with 4mil trace width TX(I/Q)
[7] HB_RX_N F1 HB_RXN 3GTX_QP F10 TX_Q_P [3]

0402
[7] VRF18_PMU R645
C675

MT6166
NC R654 F2 F11 TX_Q_N [3] NCP15WF104F03RC
R656 VRXHF 3GTX_QN

0402
0402

470nF

0402
C685

0402
NC VRF18_PMU [7]
0R X600 G2 RFVCO_MON TXVCO_MON L11 R610 close to 3G PA
R657 C676
[4] AUXADC_TSX Route AUXADC_TSX with 4mil trace width 0402 4 GND HOT 3 J1 XTAL1 VTXLF J11 VRF18_PMU
470NF

0402
NC
H2 H10
XTAL2 TXBPI TXBPI [3]
XO
1 HOT GND 2 K1 VTCXO28 RCAL J10
R655 Test pin RCAL
B
Route AUXADC_GND with 24mil trace width 26MHZ [7]DCXO_32K_EN G1 32K_EN TST2 K11
B
[4] GND_AUXADC 0402

under AUXADC_REF/AUXADC_TSX trace R600

0402
NC
SRCLKENA L1 EN_BB TST1 L10 2K
R653

0402
[2,4,7] VTCXO_PMU BSI
0R
470nF SRCLKENA K2 CLK_SEL BSI_DATA2 G8 [3]
BSI-A_DAT2
0402
26M output
C677
CLK3_ATV L2 XO3 BSI_DATA1 H8 [3]
BSI-A_DAT1

E4 GND GND B7
F4 GND GND J6

AVDD_VIO18
connect to main GND G4 RX(I/Q) D8

BSI_DATA0
GND GND
H4 GND GND E8

BSI_CLK
OUT32K

VXODIG
XMODE

BSI_EN
RX_QN
RX_QP
VRXLF
[3,4,7]

RX_IN
SRCLKENA

RX_IP
GND
GND
GND
GND
GND
GND

GND
GND

GND
GND
GND
GND
XO4

XO2

XO1
[3,4,7] SRCLKENA

J4
C5
D5
E5
F5
D7

K4

K3

L4

K5

L5

K6

K7

L7

L8

K8

K10

K9

G6

H6

F8

E7
J5

C6
D6
E6
F6
CLK3_ATV
[11]

[4] CLK4_AUDIO
[10] SYSCLK_WCN

VRF18_PMU
0402
NC R621
[3] CLK1_BB
DCXO_32K

VIO18_VGPIO
[4]
[7] XMODE

[3] RX_I_P

[3]RX_Q_N
[3]RX_Q_P
[3] RX_I_N
L630
[2,3,4,6,7,9,13] VIO18_PMU 0402
VRF18_PMU [7]

470nF
0R C682

C684
0402

1uF

0402
[7] VXODIG

Reserved LC filter

A A

Title
RF-2G
Size Document Number Rev
D V1.0

Date: Friday, December 28, 2012 Sheet 7 of 13

5 4 3 2 1
RF_TX_ASM

R703
R723 0402 1K
0402
[3] ASM_VCTRL_C WG_GGE_PA_ENABLE [3]
C701 1K
C704 0402
0402

22PF 22PF
VBAT

R712
10K
0402 WG_GGE_PA_VRAMP [3]

C718

R720
C702

24K
0402
C706 C716 0402

0603 0603 0402 C734 220pF


100nF 0402

10uF 10uF 22pF

2G_HB [7]
2G_LB [7]
R701 0R TRX1 [7]
0402

R702 NC [7,8]
0402 TRX2

R708 1K 0R
[3] ASM_VCTRL_B R706
0402 0402 TRX2 [7,8]
C705 R714 NC
0402
0402

22PF

15
16
17
18
19
20
21
22
R711 NC [7,8]
TRX2
U701 0402

TRX_4/GND
GND
0R

MODE

VRAMP
TRX_1
TRX_2
TRX_3
TXEN
R707 1K R713

TRX_5/4
[3] ASM_VCTRL_A 0402 0402
TRX5 [7]
C703
0402

22PF 14 VCC 23
NC R777 NC
13 VBATT 24 R721 0402
TRX_6/GND 0402
12 25

SKY77590
BS1 GND
11 BS2 ANT 26
R709
10 TX_LB_IN GND 27 J701 3x3x1.76mm
[7] GGE_PA_LB_IN C709
0402

0402
9 TX_HB_IN GND 28
C712
56pF

0R

E702
0402

E701
C711 C722
GND 29
R710

39pF
R715

GND
GND
GND
GND
GND
GND
GND
GND
NC
0402

0402

NC

0402
0402

NC 39nH

8
7
6
5
4
3
2
1
VBAT
L702 1UF
1.5nF 0402

0402
VPA
0402
C720
C710
18pF

C719
L704 0R 1.5nF
R704 0R L705 [3,8] VM1
[7]
0402

GGE_PA_HB_IN
0402
0402
0402

NC C729

C725
18pF
0402

NC [3,8] VM0
R705

R719 0402 0R
NC
0402

R716

[7] W_PA_B1_IN

0402
NC

10
0402

4
3

1
VMODE_0
VMODE_1

VCC1
VCC2
R722

NC
0402

C726
1nH
2 RF_IN RF_OUT 9 [7]
W_PA_OUT_B1

0402
U707
NC
0.5pF
8 6
0402

CPL_IN CPL_OUT C731


0402

C732
IC_PA_RF7241DS

R727

NC
0402
5 VEN

GND
GND
7
11
[8] PDET_B2

R742
VBAT
1.5nF 1uF
0402 PDET_B2
VPA 0402 0402 [8]
C745 C717 26R
120PF R733
0402 R737
[3,8] VM0 C721 0402 0402
C733
56pF

26R 26R
10

R743 0R
4
3

R739
[7] W_PA_LB_IN

35R
0402
0402
0402

VMODE_0
VMODE_1

VCC1
VCC2

3.6nH
C724
[3] W_PA1_ON
R724

NC

2 9
0402

RF_IN RF_OUT W_PA_OUT_B5 [7]

0402
PDET [7]
NC NC
8 U706 6
0402 0402

CPL_IN CPL_OUT C739 C730

5
R744

51R

VEN
GND
GND
0402

IC_PA_RF7245
7
11

[4,8]
VPA

2.2uF [8]
0603
B5_CPL_OUT VBAT
C751 [3] W_PA5_ON
1uF 1.5nF
VPA
0402
0402

C738 C763
[3,8] VM1 1.5nF
0402

C741

10
4
3

1
C742
18pF

VMODE_0
VMODE_1

VCC1
VCC2
R726 0402 0R

1.5nH
C743
0402
[7] W_PA_B2_IN
2 RF_IN RF_OUT 9
W_PA_OUT_B2 [7]

0402
R735

NC
0402
U709 1pF NC
8 CPL_IN CPL_OUT 6 0402
0402

C746 C747
IC_PA_RF7242

R749
0402

NC
5 VEN

GND
GND
[8] B5_CPL_OUT

7
11
W_PA2_ON
[3]

R628
R748
0402 0402
PDET_B2 [8]
NC NC

Title
07 RF_TX_ASM
Size Document Number Rev
D V1.0

Date: Sunday, December 18, 2011 Sheet 8 of 13


VIO18_PMU VIO28_PMU LCD_VDD
LCD LCD_VDD [9]
BACKLIGHT DRIVER

C25
C26
R806
R803

0402
1

0402

0R
0R
LED-A

C853
0402 0402
2
[9] LEDA LED-A

1uF

RB551V-30
1uF
1uF
3
LED-K VBAT
4

0402
[9] LEDK LED-K L801

D801
5
GND
6

C3

C4
[9] VCOM

P3

P4
F3

F4
L3

L4
U809 VCOM
7
[9] LCD_VDD DVDD
8

VCC_B
VCC_B
VCC_B
VCC_B

VCC_A
VCC_A
VCC_A
VCC_A
[9] MODE MODE
9 22uH
[9] DPI_DE DE
10 C803
[9] DPI_VSYNC VS C802
11 C801 1uF
A3 A4 [9] DPI_HSYNC HS 0603

R830

27K
0603
[3,9] LCD_SHIFT_EN

0402
1DIR 1OE LCD_SHIFT_EN [3,9] 12 0402

[9] DPI_B7 B7 2.2uF 1uF LEDA [9]


H3 H4 13 25V rating
2DIR 2OE [9] DPI_B6 B6
14
J3 J4 [9] DPI_B5 B5 U810
3DIR 3OE [9] DPI_B4 15
B4
T3 T4 16

R831

1.2K
R1 [9]

0402
4DIR 4OE [9] DPI_B3 B3 LEDK
0402

17 VIH = 1.4V 6 1
[9] DPI_B2 B2 VIN LX
18
100K [9] DPI_B1 B1
[9] DPI_B0 19 4 5
B0 [3] PWM_BL_EN EN VOUT
A5 20
A2 [9] DPI_G7 G7
1B1 1A1 [9] DPI_G6 21 2 3
A6 G6 GND FB 0402
A1 [9] DPI_G5 22 CON1
1B2 1A2 G5 R804 R832

0402
B5 [9] DPI_G4 23
DPI_DE_SHIFT [3] B2 G4 47K 16K
1B3 1A3 DPI_DE [9] [9] DPI_G3 24 CON_GF_XF2M-5015-1A
IC_CP2123ST-A2
B6 G3
DPI_VSYNC_SHIFT [3] B1
1B4 1A4 [9] DPI_G2 25
G2 R833
DPI_VSYNC [9]

0402
C5 [9] DPI_G1 26 12R
DPI_HSYNC_SHIFT [3] C2
1B5 1A5 27
G1
DPI_HSYNC [9] [9] DPI_G0 G0
[3] C1 C6 28
DPI_B7_SHIFT 1B6 1A6 [9] DPI_R7
DPI_B7 [9] 29
R7
[3] D2 D5 [9] DPI_R6 R6
DPI_B6_SHIFT 1B7 1A7 DPI_B6 [9] 30
[9] DPI_R5 R5
[3] D1 D6 31
DPI_B5_SHIFT 1B8 1A8 DPI_B5 [9] [9] DPI_R4 R4
[3] E5 [9] DPI_R3 32
DPI_B4_SHIFT E2 R3
2B1 2A1 DPI_B4 [9] [9] DPI_R2 33
[3] E6 R2
DPI_B3_SHIFT E1 DPI_B3 [9] [9] DPI_R1 34
2B2 2A2 R1
[3] F5 [9] DPI_R0 35
DPI_B2_SHIFT F2 R0
2B3 2A3 DPI_B2 [9] R857 36
F6 GND
DPI_B1_SHIFT [3] F1 37
2B4 2A4 DPI_B1 [9] [9] DPI_CK 0402 DCLK
[3] G5 38
DPI_B0_SHIFT G2 0R GND
2B5 2A5 DPI_B0 [9] 39
G6 [9] LCD_L/R L/R
DPI_G7_SHIFT [3] G1 40
2B6 2A6 DPI_G7 [9] [9] LCD_U/D U/D
[3] H5 41
DPI_G6_SHIFT H2 [9] [9] VGH VGH
2B8 2A8 DPI_G6 42
H6 C888 [9] VGL VGL
DPI_G5_SHIFT [3] H1 43
2B7 2A7 DPI_G5 [9] 0402
[9] AVDD AVDD
J5 0.1uF 44
DPI_G4_SHIFT [3] J2 [9] RESET RESET
3B1 3A1 DPI_G4 [9] 45
J6 NC
DPI_G3_SHIFT [3] J1 [9] VCOM 46
3B2 3A2 DPI_G3 [9] VCOM 52
K5 47
DPI_G2_SHIFT [3] K2 [9] DITHB DITHB
3B3 3A3 DPI_G2 [9] 48
K6 GND 51
DPI_G1_SHIFT [3] K1 49
3B4 3A4 DPI_G1 [9] NC
DPI_G0_SHIFT
DPI_R7_SHIFT
[3]
[3]
L2
L1
3B5 3A5
L5
L6
DPI_G0 [9]
50
NC CTP
3B6 3A6 DPI_R7 [9]
[3] M2 M5
DPI_R6_SHIFT 3B7 3A7 DPI_R6 [9]
[3] M1 M6
DPI_R5_SHIFT 3B8 3A8 DPI_R5 [9]
[3] N2 N5
DPI_R4_SHIFT 4B1 4A1 DPI_R4 [9] CTP_VDD_2V8 [9]
[3] N1 N6 TP EINT_CTP [3,9]
DPI_R3_SHIFT 4B2 4A2 DPI_R3 [9]
P5 TP SHUTDOWN_CTP [6,9]
[3] P2

RX10 [9]
[9]

[9]
DPI_R2_SHIFT

[9]

[9]
DPI_R2 [9]

[9]

[9]
[9]
[9]
[9]
4B3 4A3 R812 4.7K TP
[3] P1 P6 [9] LCD_L/R 0402 LCD_VDD [9] TP
DPI_R1_SHIFT DPI_R1 [9]

RX9
RX8
RX7
RX6
RX5
RX4
RX3
RX2
RX1
4B4 4A4 R818 NC
[3] R2 R5 0402
DPI_R0_SHIFT 4B5 4A5 DPI_R0 [9]
[3] R6 R815 4.7K
DPI_CK_SHIFT R1 DPI_CK [9] [9] LCD_U/D 0402
4B6 4A6 R819 NC CTP_VDD_2V8
T5

VBAT [4,5,8,9]
LRSTB