CHAPTER 5

MICROPROCESSOR BASED DISTANCE RELAY FOR THE PROTECTION OF EHV/UHV

TRASMISSION LINES

5.1 INTRODUCTION
Distance relays work on the principle of measuring impedance
of the line up to the fault point. In the early days, different
types of distance relays such as impedance relays, reactance
relays, mho relays, and so on were designed and tested on the
transmission lines. Several researchers had designed and
developed different types of characteristics of these relays. A
relay characteristic which fits snugly over the fault area is the
most suitable one from the point of view of protection of
transmission line ie a quadrilateral characteristic with
independent adjustment facilities in the resistance and reactance
axes is an ideal one. This characteristic operates correctly for
faults associated with arcing and it is very little affected by
power swing. A microprocessor can be used to implement several
types of threshold characteristics with the same hardware or with
a minimum change in hardware. This equipment is also self­
checking in nature and also cost effective. So the microprocessor
based distance relays with required flexible characteristics for
the protection of EHV/UHV transmission lines are especially
preferred.

This chapter gives the development of a microprocessor based

high speed fault impedance calculation in transmission lines for
location of faults. Then it explains the development of a
microprocessor based quadrilateral characteristic realization as
 142

a combination of restricted directional and ohm and reactance

characteristics for the protection of transmission lines. Then it

explains the development of a microprocessor based 3 zone

quadrilateral distance relay for the protection of EHV/UHV

transmission line. Then it explains the development of a PC based

3 zone quadrilateral characteristic realization for the

protection of EHV/UHV transmission lines. It also explains the

development of a microprocessor based protection scheme for on

line protection of EHV/UHV transmission line. The relay

characteristics are incorporated in the software and the required

design data are taken for an existing network of Neyveli-Salem

400 KV single circuit line in Tamil Nadu, India.

5.2 MICROPROCESSOR BASED HIGH SPEED FAULT IMPEDANCE CALCULATION

IN TRANSMISSION LINE

A transmission line fault is generally accompanied with

mechanical damage that must be repaired and the line returned to

service. The restoration can be expedited if the location of a

fault is either known or can be estimated with reasonable

accuracy. It is very much essential to determine the point at

which a fault occurs in an electric power transmission line for

economic operation. The location of permanent faults will

facilitate quicker repair and restoration, while accurate

location of transient and temporary faults will aid in preventive

maintenance. It is also difficult to locate physically the fault

point on transmission lines since it runs over very long

distances.
 143

Distance relays for transmission line protection provide

some indication of the general area where a fault occured, but

they are not designed to pinpoint the location. Since the power

circuit breakers are only installed at the terminals, it is

immaterial where the line faulted for isolating the flashover.

Accurately estimating the locations of transmission line faults

has, therefore, been a subject of interest to utility engineers

and researchers for several years.

The fault location techniques proposed in the past use

fundamental frequency voltages and currents. These techniques can

be classified into two categories. In the first category voltages

and currents measured at one line terminal are used [90, 125,

207, 223, 224, 227, 231, 252-255]. The techniques of the second

category use voltages and currents measured at both line

terminals [238, 256].

With the advent of microprocessor based recording devices,

utilities have shown increased interest in implementing accurate

fault location techniques. Consequently several approaches to the

problem of transmission line fault location have been developed

and, in varying degrees, implemented. Most of the more recent

fault location algorithms involve two main approaches. One is to

transmit an electrical pulse into the line and to measure the

period from emission to return of the pulse; this method depends

on the travelling wave propagation which is a complex phenomenon

difficult to analyze perfectly. The other approach relies on

informations supplied by the line currents and voltages at some

observation points on an energized system within the first
 144

instants after fault inception. In both cases the readings of

voltage and current constitute the initial data for an estimation

problem leading to fault location. Most fault locating devices

measure impedance, or more exactly reactance [257], between the

short circuit and the end of line where the relays are installed.

The proposed scheme explains a microprocessor based high speed

fault impedance calculation for fault location in transmission

1ines.

5.2.1. PRINCIPLE OF IMPEDANCE CALCULATION

The principle of calculation of line impedance involves the

predictive calculation of peak current and peak voltage , [87 ] , the

impedance being determined by division of peak voltage by the

peak current. A digital computer sampling a sinusoidal waveform

can determine the peak value as they occur. But it is necessary

to determine the peak value before their occurrence to reduce the

time duration, ie. to predict the peak value of the waveform from

any given sample. Let us consider

V = V Sin■ w t (5.2.1)
pk
where V is the unknown quantity and V is a typical sample
pk
value. Since it is not proposed to synchronize the sampling to
the sinusoid, the value of sin w t is also unknown. The
derivative of (5.2.1) gives

V' = to V coscot (5.2.2)

pk
and assuming that V' can be determined, the peak value of the

sinusoid is determined from

 145

2 2 2
V = V + (V'/ a) ) (5.2.3)
pk
If equations (5.2.1) to (5.2.3) are applied to transmission

line current and voltage, the modulus of the line impedance can

be determined as

z' = Square root of (V /I ) (5.2.4)

pk pk

Further more, the phase difference between the voltage and

current wave forms can be determined as

a = -arc tan ( iui/i * ) + arc tan ( wv/v1) (5.2.5)

enabling complete impedance determination (see Appendix I and II

for derivation).

5.2.2. HARDWARE DETAILS

The hardware configuration of the microprocessor based high

speed impedance calculation method is shown in fig. 5.2.1.

Here the data acquisition is done after filtering all

transients and other harmonics by an active band pass filter and

then by sampling simultaneously the bus voltage and the line

currents by sample and hold circuits. These are then converted

into digital form using an A/D converter and transmitted to the

input ports of the microprocessor. A microprocessor controlled

timer is used for setting sampling internal. SDA 85 based system

is used for this realization. The hardware can be subdivided into

Data Acquisition System (DAS) and the interface with the

processor.
FIGURE 5-2.1 BLOCK DIAGRAM OF MICROPROCESSOR BASED HIGH SPEED
IMPEDANCE CALCULATION
146
 147

The circuit diagram of the Data Acquisition System (DAS) is

shown in fig. 5.2.2. The DAS consists of active band pass filter,

sample and hold and a multiplexer. The band pass filter is

designed for a pass band of 48 to 52 HZ. This eliminates the

higher harmonics and the d.c. offset. For testing purpose, the

signal was taken from a signal generator. The associated circuits

produce the voltage and current waveforms, for different

magnitudes and phase shift. The samples are taken at an interval

of 0.5 m.sec., to yield 40 samples per cycle [122]. This is

achieved by an 8253 programmable timer. The sample and hold

circuit is designed using LF 398 chip. A multiplexer CD 4051 is

used to select whether the voltage or current samples is to be

the input to the A/D converter for digitization. The selected

input of this multiplexer is driven by one bit of the output port

C of an 8255 device. This 8255 is controlled by the micro­

processor .

The interface to the microprocessor is shown in fig. 5.2.3.

The interface contains an 8255 PPI providing programmable input/

output ports, three 16 bit programmable timers obtained from an

8253 timer/counter, an ADC 0800 for analog to digital conversion,

and other supporting circuits. The start of conversion pulse is

generated using port C of 8255, and is given to the ADC. The ADC
converts the sampled voltages and currents one by one through the
multiplexer which is controlled by port C of 8255. The conversion

process is initiated by an interrupt signal from the 8253 timer,

which is fed to the RST 6.5 of the processor. This is also used
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FIGURE 5-2-2 DATA ACQUISITION SYSTEM

146
9>
 150

to trigger the sample and hold for both the voltage and current

measurements.

By feeding an appropriate signal to the multiplexer, one of

the sampled voltage or current wave form is fed to the ADC, which

starts converting this, on receiving the associated pulse of

duration 0.5m.sec. The ADC outputs an end of conversion (EOC),

equal to 1, after the conversion is complete. This is monitored

by the CPU through port C of the 8255. On finding EOC is 1, the

CPU reads the 8-bit digitized data through port B of the 8255 and

stores it in the RAM. The ADC is reasonably fast and can convert

in 40 clock cycles. The R5T 6.5 interrupt, therefore allows the

CPU to periodically sample and store digitized voltage and

current levels once in every 0.5 m.sec. It also initiates the

programme for fault detection by comparing the voltage at each

position of the present cycle with that of the corresponding

position of the previous cycle. When this signal differs in more

than the preset threshold (6.25 percent which is an arbitrary

value), the CPU starts its calculation of the apparent impedance.

5.2.3. SOFTWARE DETAILS

The data acquisition system simultaneously samples the

filtered voltages and currents of the protected line, and by the

interface system, these sampled values are taken one by one

through the multiplexer, with the help of 8255. After each sample

sweep, the voltage is compared with its equivalent sample in the

previous power cycle. If any five consecutive voltage samples are

found to have lower (or higher) value than the threshold limit,
 151

(ie. 6.25 percent), a significant disturbance is deemed to have

occured.This cycle by cycle comparison is developed by Mann and
Morrison. Fig. 5.2.4. gives the complete flow chart where voltage
samples are compared with their values in the previous cycle. On
detecting a significant disturbance, the microprocessor disables
the interrupt, predicts the peak value of the voltage and current
from the fundamental waveform and thereby calculates the apparent
impedance upto the fault point (both in magnitude and phase
angle) thus identifying the location of fault.

5.2.4 LABORATORY TESTING:

The digital impedance measuring unit was tested in the
laboratory using SDA-85 kit. The current was set at some
particular value and the voltage magnitude was varied from one
value to its higher value till the threshold limit (greater than
6.25 percent) exceeds. A light emitting diode was used for
indicating the trip signal. The procedure was repeated for
different values of current. The trip conditions were tested for
both half cycles. The device was working satisfactorily. The
impedance at which a trip signal received was calculated by
dividing V by I The three photographs show the output
pk pk
waveforms of phase shift circuit, sample and hold circuit and
start of conversion pulses respectively.

5.2.5 CONCLUSION
The digital impedance measuring unit using microprocessor
was developed and tested in the laboratory. The use of low cost
microprocessor is proposed to calculate the impedance using
 152

FIGURE 5.2-4 FLOW CHART OF SOFTWARE FOR COMPARING

VOLTAGE SAMPLES CYCLE TO CYCLE TO
________________INITIATE FAULT IMPEDANCE CALCULATION
 153

sampling technique. Total hardware requirement is less. The

impedance is calculated using both half cycles. This can be

developed for tripping of a relay having different zones

characteristics.
 154

5.3 DEVELOPMENT OF MICROPROCESSOR BASED DISTANCE RELAY

CHARACTERISTICS

With the increase in size, capacity and complexity of power

systems, the necessity of a highly reliable, sensitive and

selective high speed distance protection scheme is widely felt to

limit the equipment damage and to preserve the system stability.

Enormous work has been done on development of high speed distance

relays. Researchers have attempted to develop the operating

characteristic of a distance relay which exactly fits into the

fault characteristics of the transmission line, that is to say a

quadrilateral characteristic.

Several techniques have been reported [44] to generate

quadrilateral characteristic shape employing the Phase, Amplitude

and Hybrid comparator techniques with multi input signals.

Here the first proposed scheme presents the development of a

quadrilateral distance relay using microprocessor Intel 8085

system. The quadrilateral characteristic is realized as a

combination of a restricted directional [36], ohm and reactance

units. The restricted directional characteristic is realized

using block-spike coincidence principle of phase comparison

[31,45, 51]. The ohm and reactance characteristic are realized by

sampling technique. The details of the development of

microprocessor based quadrilateral distance relay is explained

below.
 155

5.3.1 PRINCIPLE OF FIRST QUADRILATERAL CHARACTERISTIC

DEVELOPMENT
The quadrilateral characteristic [110] has been developed as

a combination of a restricted directional, ohm and reactance

units as in fig. 5.3.1. The input signals V and V are obtained

V i
from the line voltage V and line current i through a potential
r r
transformer of ratio K and a transactor of impedance Z | 9 for
r
amplitude comparison. These are expressed as

V = K V = k V Sin wt (5.3.1)
v r m
and V = Z i = Z I Sin ( w t - <j> + 0 ) (5.3.2)
i r r r m

where p is the angle by which current lags the voltage. The

reactance characteristic is realized by taking the samples (S
1
and S in fig 5.3.2. (a) and (b) of the above signals at the
2
instant of
zero crossing of i . This instant is situated at a
r
time distance equivalent of angle 8 from the zero crossing of

i z . The samples obtained are S = K V Sin <j> and S = Z I

r r 1 m 2 r m
Sin 6 . The reactance unit gives a trip signal when S ^ S . The
1 2
characteristic offset from the origin would be Z = (Z Sin 0)/K.
0 r
That is the reactance unit gives a trip signal when the measured

reactance is less than a predetermined value Z .

0

The ohm characteristic is realized by taking one additional

sample, S , of voltage signal at an angle of (it /2 + T ) after
3
the zero crossing of i , T being the angle as shown in
r
fig.5.3.1. so that S is KV cos ( <f> + T ) . The trip condition of
3 m
ohm unit would be satisfied when S ^ S . The characteristic
3 2
offset is Z = (Z Sin 0 )/K.
0 r
 156

FIGURE 5.3.1 QUADRILATERAL CHARACTERISTIC

 157

kVr DELAY

G * 75*
p * 85*
FIGURE 5.3.2(a)
a s -io*
f = 15*

kVr

FIGURE 5.3.2 (b) MEASURING TECHNIQUE FOR

QUADRILATERAL RELAY
 158

The restricted directional characteristic is realized using

the block-spike coincidence principle of phase comparison which

is easily adaptable to realization with microprocessor.

Spikes are generated at every zero-crossing of i Z

r r
waveform. Time block corresponding to the angular limit of phase

comparison is also produced. The reference for the time block is

taken as the zero-crossing point of system voltage waveform. When

a spike occurs within the time block, it means that the angle of

the impedance seen by the relay falls within the range of phase

comparison.

From figures 5.3.1. and 5.3.2. it is understood that the

restricted directional unit should give a trip signal when the

phase difference <t> between the system voltage and current lies

anywhere between 10 degree leading and 85 degree lagging. The

angle of replica impedance is taken to be 75 degree which is same

as the line-angle. Since the line current is passed through the

replica impedance, the voltage across it will lead the line

current by 0 degree.

When d5 =10 degree leading, the negative to positive zero­

crossing of i z waveform will be at point 'A' in fig. 5.3.2.,

r r
85 degree ahead of the negative to positive zero-crossing of the
system voltage waveform. When 4> =85 degree lagging, the zero­

crossing of i Z will be at 'C', 10 degree after 'B'. Therefore,

r r
to realize the restricted directional characteristic by block

spike scheme with the prescribed angular range of phase

 159

comparison, the block should be started at point 'A', 85 degree

ahead of the negative to positive zero-crossing of the voltage

waveform or 95 degree after the point 'o', the positive to

negative zero-crossing of the voltage waveform, and ended at 'C',

10 degree after the negative to positive zero-crossing of voltage

wavef orm.

Therefore the phase angle is measured during each half cycle

separately and this unit gives trip signal only if the phase

angle is found to be in the operating range during two

consecutive half cycles. The dual phase measurement overcomes the

problem of maloperation on spurious spikes. The dual phase

measurement also eliminates transient overreach. The block width

angle here is y = $ - a which is essentially less than 180

degree. a and B are the angular limits of the restricted

directional characteristic as shown in fig. 5.3.1. The

microprocessor gives a final trip signal only when the operating

conditions exist for all the three constituent units.

5.3.2. Bf.OCK DIAGRAM OF TIIP. RELAY

The block diagram of the relay is shown in fig. 5.3.3. For

restricted directional characteristic realization, it is

necessary to produce spikes at every zero-crossing of i Z

r r
waveform and generate time blocks representing angular limit of

phase comparison. The time block is generated after certain delay

with respect to the zero-crossing of voltage waveform. To find

the zero-crossing of voltage signal, it is fed to a zero-crossing

detector (ZCD). The square wave obtained at the output of this

ZCD is fed to the microprocessor. The current proportional to

FIGURE 5-3-3 RELAY BLOCK SCHEMATIC
160
 161

voltage V Z = i obtained from the transactor is fed to

r r
another ZCD, two differentiators and an inverter to obtain spikes

at every zero-crossing of i
Z . The AND gates are enabled by
r r
the time block representing operating angular range of the relay

and these are generated by the microprocessor software with

respect to the zero-crossing of the voltage signal. A spike

passes through the AND gate only if it happens to be during the

block duration ie, if the phase angle of the transactor output is

in operating angular range represented by the time block. The OR

gate is used to interrupt the processor on either zero-crossing

to register the presence of a spike during the block.

The signals from the voltage transformer and transactor are

fed to the processor in digitized form using a sample and hold

amplifier, and an A/D converter, for reading instantaneous

amplitudes of voltage and current signals for the reactance and

ohm characteristic realization.

The A/D converter used here is able to take 0 to + SV,

signals. The precision rectifiers [258] are used to rectify the

voltage and current signals before feeding to the sample and hold

amplifier, so that no negative voltage is fed to the A/D

converter.

5.3.3 HARDWARE DETAILS

The transactor with an impedance angle of 75 degree is used

in the current signal channel assuming the line angle to be the

same. The system uses a precision rectifier. It gives full wave
 162

rectification without inversion and with a gain R/R

1
controllable by one resistor R .
1
The sample and hold circuit requires two S/H IC's (LF 398).

The value of holding capacitance is selected to match the speed

of A/D conversion, ensuring minimum data skew (Here 0.01

microfarad is chosen). The voltage and current signals can be

presented to A/D converter for sequential conversion to their

digital equivalents through the use of an analog multiplexer.

A
This device permits a single output line to mirror the signal at

the selected input channel. The IC 0809 used here combines A/D

converter as well as multiplexer. The multiplexer is of 8

channel. The switching time is about 1 microsecond.

A high accuracy of signal amplitude measurement is desired

during both normal and high level faultconditions. The problem

can be resolved by application of logarithmic A/D converter or

logarithmic amplifiers in the input circuitry. The transfer

function of such devices results in a degree of compensation for

the broad dynamic range between normal and fault current values.

However these devices are scarcely available. The most desirable

wave length for linear A/D converter would be 14 or 16 bits so

that the quantisation errors under heavy faults are

insignificant. However for the present work an 8 bit A/D

converter is used (IC 0809 which has multiplexer also).

Conversion is performed using successive approximation technique

where the unknown voltage is compared to register tie points

using analog switches. When the approximate tie point voltage

 163

matches the input voltage, the conversion completes. The digital

output word thus corresponds to the unknown voltage. The

conversion speed is 100 microseconds. For this purpose the clock

signal of 3.072 MHZ from intel 8085 system has been used by

reducing the frequency to 750 KHZ employing an IC 7474 as a

divide by 2 counter.

The circuit has also a zero-crossing detector. It converts a

sinusoidal wave form into a square wave. The pulse waveform V'
and V (fig. 5.3.4.) result if V is fed into a short time
L 0
constant RC circuit in cascade with a diode clipper. Thus a

positive spike is obtained at every negative to positive zero

crossing of
V . If an inverter circuit is used along with one
i
more RC circuit and diode clipper, a positive spike is obtained

at every positive to negative zero crossing of V . If these two

i
outputs are fed to an OR gate a positive spike is obtained at

every zero crossing of V . This circuit is used in the current

i
signal*channel to obtain spikes at every zero crossing of I Z .
r r
The complete developed circuit diagram of the relay is shown in

fig. 5.3.5. Some of the waveforms at different stages of hardware

circuit are shown in photo figures P.F. 5.3.8. to P.F. 5.3.10.

5.3.4. SOFTWARE DETAILS

The programme flow chart of fig. 5.3.6 (a) and (b) is easily

understandable. The values of a , 8 > T and 9 are respectively

taken as -10 degree, 85 degree, 15 degree and 75 degree. The K V

r
samples S and Z i sample S are taken at an angle of 0 =75
1 r r 2
degree from zero crossing of Z i for amplitude comparison to
r r
realize the reactance characteristics. The K V sample S is
r 3
 164

additionally required at an angle of 90 + T from the zero

crossing of i or 90 + ¥ + 6 = 180 degree from the zero
r
crossing of Z
i for ohm characteristic. ¥ = 15 degree is
r r
chosen to simplify the software.

After initializing various counters, registers and input-

output port mode control, the positive to negative zero crossing
ofvoltage signal is detected. This instant is marked by point
'O' in the fig. 5.3.2 (a) and (b). A delay of 95 degree is given
to reach point A. From here the time block 'a' is generated by
the processor. The spike at the negative to positive zero
crossing of I
Z interrupts the processor, to start the
r r
interrupt service routine.

First the counter 'C' is incremented by 1. The sample s ie

3
K V value at the instant of zero crossing of I Z is taken and
r r r
stored. A delay of 75 degree is given to reach the point of zero
crossing of I , the current signal. At this point the samples
r
s and s are taken and they are compared. If s is less than or
12 1
equal to s the counter is again incremented, otherwise the
2
counter C is made equal to zero. Now s and s are compared. If
3 2
s is less than or equal to s then the counter C is incremented,
3 2
otherwise it is made zero. Now the interrupt service routine ends
and returns to the main program. Here the value of the comparison
counter C is checked. If the value of C is 3, it indicates that
the t*rip conditions existed for one half cycle. Hence the trip
conditions are checked for another half cycle. Again the value of
C is checked. If the value of C is equal to 6, this indicates
 165

that the trip conditions existed for 2 consecutive half cycles

and a trip signal is given out. If the value of C is other than

6, the C value is changed to zero and the whole process starts

again.

If the spikes are not detected within the block period, then

a check for whether point B is reached, is made. If it is

reached, the counter 'C' value will be still zero and hence the

programme comes back to the starting of the process.

5.3.5. LABORATORY TESTING OF THE RELAY

For the laboratory testing of the relay, a SDA-85 kit was

used. The photograph of the test circuit is shown in fig.

P.F.5.3.11. The current was set at a particular value and the

voltage magnitude was varied from a high value to a lower value

till a trip signal was obtained. A light emitting diode was used

for indicating the trip signal. The phase angle between the

voltage and current was varied using a phase shifting circuit

incorporating an operational amplifier. The procedure was

repeated for various values of phase angles. Fig. 5.3.7. shows

the operating characteristic of the relay under steady state

conditions.

5.3.6. CONCLUSION
A quadrilateral distance relay using microprocessor is made

and tested in the laboratory. A low cost microprocessor is used

to realize the characteristics using sampling technique. Hardware

requirement is less and software is more simple.

 166

The samples of the voltage and current signals can be

additionally used to compute distance to fault location for the

assistance of maintenance personnel. The use of dual comparison

essentially make the over reach on d.c. transients almost zero by

delaying the relay operation. The transactor impedance angle is

A

made equal to that of the protected line to minimize this delay.

The relay has an operating time of one cycle when the fault

occurs just before the zero crossing of I

Z signal, and in
r r
other cases it will have a larger operating time with a maximum

value of 1.5 cycles. Note: I Z = i Z .

r r r r
 167

FIGURE 5.3.4 SPIKE GENERATING CIRCUIT

FIGURE 5.3.5 THE COMPLETE CIRCUIT DIAGRAM OF THE RELAY
 169

( START )

INITIALIZE (INT RTN)

DETECT POINT *0* C «C-H

1 r
95*DELAY TO REACH POINT V
zn
READ S3

~~r~
I
GENERATE BLOCK *a'
75 DELAY

READ Sj j S2

YES TO
INT RTN C * C+1

RET
C * 0

CsC+t

CEASE BLOCK ’o'

c-.o

YES
( RETURN )

YES
C «0 (b) INTERRUPT ROUTINE

TRIP si

(a) PROGRAMME FLOW CHART

FIGURE 5-3.6
170
 171

FIGURE 5.3.8 RECTIFIED WAVE FORMS OF If Zf AND Vp

NO-TRIP CONDITIONS

FIGURE 5.3.9 RECTIFIED WAVE FORMS OF Ip Zp AND Vp

TRIP CONDITIONS
 172

FIGURE 5.3-10 PULSES AT ZERO CROSSING OF Ir Zr WAVE

FIGURE 5-3.11 TESTING CIRCUIT CONNECTIONS FOR

QUADRILATERAL CHARACTERISTIC
DEVELOPMENT
 173

5.4 DEVELOPMENT OF MICROPROCESSOR BASED THREE STEP QUADRILATERAL

DISTANCE RELAY FOR THE PROTECTION OF EHV/UHV TRANSMISSION LINES

Rapid changes are taking place in the philosophy of power

system protection with the tremendous development in the

microprocessor application for protection purposes. The use of

microprocessor based distance relays for transmission line

protection is a challenging area which is receiving considerable

amount of attention. Development of different types of

characteristics for distance relays for the protection of EHV/UHV

transmission lines are discussed by several researchers. A

quadrilateral characteristic with independent adjustment

facilities in the resistance and reactance axes has been felt by

many researchers as an ideal one which exactly fits over the

fault area for the protection of EHV/UHV transmission lines [122,

137, 259]. The proposed scheme presents the development of a

microprocessor based 3-zone quadrilateral distance relay for the

protection of EHV/UHV transmission lines. This scheme is based on

the Fourier transform method of extracting the fundamental

components of voltage and current signals from non-sinusoidal

post-fault signals [99].

5.4.1 MATHEMATICAL FORMULATIONS FOR THE DESIGN OF THE RELAY

The waveform of current and voltage signals under fault

conditions is well presented in the following form.

I (t) = I cos ( a) t - a) + I exp (-1/ x )

11 a a
+ I exp C -1 / x ) cos (oj t - y ) (5.4.1)
p P P
V(t) = V cos (w t - a + V ) + V exp (-t/ x )
^11 a a
 174

+ V exp (-1 / t ) cos ( a) t - 6 ) (5.4.2)

p P P
First terms of the right hand side of equation (5.4.1) and
(5.4.2) are steady state fundamental components. Their amplitudes
and phases are to be determined in the initial stage of distance
fault location. The second terms are well known aperiodic

components , decaying with t ime constant t . The third terms

a
represent decaying oscillations induced by the fault which
results from travelling wa ve effect. The frequency of
oscillations is u with a decaying time constant of x
P p

The fundamental components of voltage and current are

expressed as
Y = V + j V (5.4.3)
Id q
I = I + j I (5.3.4)
Id q
For the sake of convenience a shifted time scale has been
introduced into the formula of signals to make the middle of the
window always coincide with 'O' of the new time variable t .

t = t - (t + T /2) (5.4.5)
1 W
where t - is the beginning of the data window.
1
T - data window length.
W
Angular frequency corresponding to data window is
= 2 TT / T (5.4.6)
2 W
 175

According to Fourier transform theory and correlating the

signal with sine/cosine functions which have period equal to data

window T , the equations can be written as

W
Tw/2

V = (K/T ) [ V( T ) Cos 03 T d T (5.4.7)

d W 2

-V2
T /2
w
j* V( t ) Sin
V = (P/T ) 03 T d T (5.4.8)
q w 2
-T /2
w
Tw/2
J I ( T ) Cos
I = (K/T ) 03 X d T (5.4.9)
d w 2
-T /2
w
T /2
w
I
q
= (P/T )
w J
-T /2
I( ) t Sin
03
2
T d x (5.4.10)

Where coefficients K and P are given as

K = -rr(1 -r^ ) /r sin tt r (5.4.11)

P = - 11 (1-r^ )/ sin ii r (5.4.12)

and r = oj / w
1 2

03 is the fundamental angular frequency. o> is the angular

1 2
frequency corresponding to data window.
 176

5.4.1.1. SIGNAL CORRELATION WITH HALF PERIOD DATA WINDOW

Taking the data window equal to half the period, that is

half cycle.

T = ” ' CO ,
w 1

and the coefficients become

K = 3 tt /2; P = - (3 rr /4) (5.4.13)

Hence equations (5.4.7) to (5.4.10) can be rewritten as

t +T
1 w

V = (3 tt/2T ) V(t) Cos [ to -t - (T /l) dt (5.4.14)

d W J 2 1 w

t +T
1 w
V = ( - 3 tt / 4T ) f V(t) Sin [ u> -t -(T /2) ] dt (5.4.15)
q w -* 2 1 w
t
1
t +T
1 w

I
d
= (3 tt HI W ) J f I (t) Cos [ 0)
2
-t
1
- (T / 2] dt
w
(5.4.16)
t
1
t +T
1 w

I = (- 3 tt / 4T )J I(t) Sin [ u -t -(T ID] dt (5.4.17)

q w ^ 2 1 w

The above equations are solved by simple trapezoidal method of

integration and the results are as follows.

 L77

V = A [ V( t )Cos tt - 2 V C t ) Cos (2 rr /N) - 2V(t ) cos (4 it/N)...

d 1 2 3

... - 2 V (t ) cos ((N -1) 2tt /N) + V (t ) cos tt ] (5.4.18)

N N+l

V = A[V(t )sin (tt /2) + V(t ) sin (2tt /N) + V(t ) sin(4Tr/N) ...
q 1 2 3

... +V(t )sin ((N -1) 2 tt /N) - V(t ) sin ( tt / 2 ) ] (5.4.19)

N N+l

I = A[l(t ) Co s it - 21 (t ) Cos ( 2 tt /N) - 21 (t ) cos (4 rr /N) . . .

d 1 2 3

... - 21 (t ) cos ((N -1) 2 rr / N) + I (t ) cos tt ] (5.4.20)

N N+l

I = A [ I (t )sin ( rr / 2) + I (t ) sin (2 rr / N) + I(t ) sin(4'>T/N) ...

q 1 2 3

... +I(t )sin ((N -1) 2 tt / N) -1 (t ) sin ( tt /2 ) ] (5.4.21)

N N+l

Where >N is the number of intervals over a sampling period and A

is a constant equal to 3 tt /4N.

5.4.1.2. IMPEDANCE CALCULATION

The impedance seen by the relay is obtained by dividing the

peak of the voltage by the peak of the current [88].

From equations 5.4.3 and 5.4.4,

2 2
z = R +j x = V /I = (V I + V I ) / (I + I )
L L L 1 1 d d q q d q
. , , 2 i 2 )
+ j (V I - V I ) / (I (5.4.22)
q d d q d q

The Fourier transform method gives highly accurate results

but requires longer computation time. But as this method employs

half power cycle data window, the time required has been reduced.

Signal coiielation to sine/cosine functions are made taking the

 178

period same as the data window length to reduce the errors in

calculation of fundamental components as suggested by

A.Wiszniewski [98].

Twelve samples are taken per power cycle in this work. The

time interval is about 1.66 m.sec. for a system frequency of 50

HZ. To eliminate the errors in sampling during frequency

variations, the sampling pulses are made system frequency

dependent using a frequency locked pulse generating circuit which

makes use of a phase locked loop.

5.4.2 HARDWARE DETAILS

The block diagram of the relaying scheme is shown in fig.

5.4.1. The hardware consists of frequency locked start conversion

pulse generating circuit (FLSCPGC) and a Data Acquisition System

(DAS). The complete connection diagram of the data acquisition

system employed for the relay is shown in fig. 5.4.2.

A . synchronizing signal of system frequency 'f' is input to

the FLSCPGC. It is converted to a square wave of the same

frequency using a 741 comparator and supplied as input to the

phase locked loop. IC 4046 (PLL) with a divide by 12 Counter 7492

is used. CMOS wide band phase detector of 4046 [265] on pin 13 is

used. , The frequency of the output from VCO will be 12 times the

frequency input to the phase detector. The VCO output frequency

continuously varies along with the variation in the input signal

frequency when the loop is in locked state.

179
FIGURE 5-4-2 CIRCUIT DIAGRAM OF THE DATA ACQUISITION SYSTEM
180
 181

The VCO output is inverted using 7400 with a NAND gate

connected as an inverter. The inverted output pulse width is

varied using a 555 timer operated in monostable multivibrator

mode. Thus pulses of frequency 600 HZ are obtained which is used

as start of conversion pulses for the two analog to digital

converters.
A

Two LF.398 single package IC sample and hold circuits

simultaneously sample the voltage and current signals. The

sampled signals are converted into digital form using two analog
to digital converters (ADCs 0800). The reference voltages needed

for the two ADCs are derived from a special circuit from +12VDC

using operational amplifiers of IC LM 324. The clock pulses of

500 KHZ are generated using a 555 timer operating in an astable

multivibrator mode.

The microprocessor based system comprises of an Intel 8085A

8 bit Microprocessor and the supporting peripheral ICs for

interfacing the Data Acquisition circuit. The ports A and B are

made to function as input ports. The port C upper works as an

input port and port C lowei as the output port. Three LEDs are

provided for the indication of the tripping for the three zones.

5.4.3. SOFTWARE DETAILS

Fig. 5.4.3. shows a model quadrilateral characteristic

represented on R-X diagram. The determination of the

quadrilateral characteristic is completed through software [266]

as illustrated in flow charts of figs. 5.4.4.(a), (b), (c) and

 182

t
X

FIGURE 5-4 3 QUADRILATERAL CHARACTERISTIC

REALIZATION DIAGRAM
 183

FIGURE 5.4.4(a) FLOW CHART-MAIN

 184

FIGURE 5.4.4b FLOW CHART - ZONE 1

 5>

FIGURE 5-4-4(c) FLOW CHART-ZONE 2

 166

FIGURE 5 4-4 (d)

- FLOW CHART -ZONE 3
 187

(d). The constants used in the flow charts have values

follows.

K1 _ X /R (5.4.23)
1 1

K2 —
X /R (5.4.24)
2 2

KL1 X /R (5.4.25)
L L

KL2 X /(R - R ) (5.4.26)

L L 2

All the initialization required are made at the beginning of

the programme. The samples of current and voltage are taken and

stored. These sampled values of voltage are compared with that of

the corresponding samples in the previous cycle. If the

difference of consecutive seven samples are found greater than 5

percent, a disturbance is deemed to have occured. Otherwise, the

next set of samples are taken and the process repeats.

When the fault is assumed to have occured, the values of V ,

d
V , I and I are calculated using those seven samples of
q d q
voltage and current. Subsequently values of R and X are also
1. 1*
computed.

Now a check is made to see whether the values of X and R

L L
are greater than zero and lies within zone 3. A check f or the

directional characteristics with angles 6 and 0 are also

1 2
made. When all the tests indicate the presence of a fault, a

trip signal is given to the circuit breaker. If the fault is in

zone 1, no time delay is given ie. instantaneous tripping is

 188

ordered, where as for faults in zone 2 and zone 3, time delays of

T and T are given respectively.

2 3

5.4.4. LABORATORY TESTING OF THE RELAY

The required analogue input signals of current and voltage

from the system were simulated using a specially designed phase

shift circuit. The software developed for the determination of

the characteristic was stored in the memory of the microprocessor

system and executed. The values of impedance and phase were

varied with the help of the phase shifter circuit and the

tripping characteristic of the relay was plotted.

The relay was successfully tested for a number of three step

quadrilateral characteristics. Six samples of three step

quadrilateral characteristics are shown in figures. 5.4.5, 5.4.6,

5.4.7, 5.4.8, 5.4.9 and 5.4.10 and the corresponding test results

are shown in tables I, II, III, IV, V and VI respectively.

The time required for relay operation is determined by four

considerations. Firstly, phase locked loop introduces a delay

(ie. t im«*) in phase detecting etc. Secondly, seven consecutive

samples are required for detection of occurance of disturbance.

Thirdly, the apparent impedance calculation itself will take some

additional time. Fourthly, the calculation of comparison time for

the detection of fault inside the zone or outside of all zones

will also take some time. Here the relay has an operating time of

about 15 m.sec. for first zone and any time delay can be

incorporated for other zones. Figures 5.4.11 to 5.4.16 show wave

forms at different locations in the hardware.

 RlN sk.
Rin a
FIGURE 5.4.5 FIGURE 5.4-6
QUADRILATERAL CHARACTERISTICS
189
 190

FIGURE 5.4-7 QUADRILATERAL CHARACTERISTIC

OBTAINED WITH 0! * 02 * 80-54°
191
 192

R in -n---- 9-

FIGURE 5-4.10 QUADRILATERAL CHARACTERISTIC

OBTAINED WITH 9^80-54*; Qz^0-S4°; 02=75-96° 02=74-48* )
 193

TABLE I

NO. X R 0 > Degree TRIP

1 2.0 1.0 63.43 ZONE 1

2 2.0 8.0 14.04 NO

3 7.0 2.0 74.05 NO

4 7.0 3.0 66.80 ZONE 2

5 6.0 9.0 33.69 NO

6 7.0 8.0 41.19 ZONE 2

7 11.0 3.0 74.74 NO

8 11.0 4.0 70.02 ZONE 3

9 9.0 10.0 41.99 NO

10 11.0 10.0 47.73 ZONE 3

11 5.0 8.0 31.01 ZONE 2

12 4.0 7.0 29.74 ZONE 1

QUADRILATERAL CHARACTERISTIC

RESULTS OBTAINED FOR ANGLES

71.57
 194

TABLE II

SI.NO. X R 6 , Degree TRIP

1 5.0 1.0 78.69 ZONE 1

2 2.0 4.0 26.57 ZONE 1

3 3.0 8.0 20.56 NO

4 8.0 1.0 82.87 NO

5 8.0 8.0 45.00 ZONE 2

6 10.0 1.0 84.29 NO

7 11.0 5.0 65.56 ZONE 3

8 10.0 9.0 48.02 NO

9 11.0 8.0 53.97 ZONE 3

10 7.0 8.0 41.19 ZONE 2

11 - 10.0 7.0 55.01 ZONE 3

12 5.0 8.0 31.01 NO

QUADRI LATEIt M CHARACTERISTIC

RESULTS OBTAINED FOR ANGLES

*

6 = 9 ^= 80.54
 195

TABLE III

SI.NO. X R 9 , Degree TRIP

1 3.0 4.0 36.87 ZONE 1

2 5.0 5.0 45.00 NO

3 6.0 5.0 50.19 NO

4 8.0 5.0 57.99 ZONE 2

5 10.0 7.0 55.01 NO

6 12.0 6.0 63.43 ZONE 2

7 14.0 2.0 81. 87 NO

8 16.0 6.0 69.44 ZONE 3

9 16.0 2.0 82.87 NO

10 18.0 8.0 66.04 NO

11 8.0 1.0 82.87 NO

QUADRILATERAL CHARACTERISTIC

RESULTS OBTAINED FOR ANGLES

80.54
 196

TABLE IV

SI.NO. X R 0 , Degree TRIP

1 2.0 1.0 63.43 ZONE 1

2 2.0 5.n 21.80 ZONE 2

3 3.0 7.0 23.20 ZONE 3

4 1.0 8.0 07.13 NO

5 7.0 1.0 81.87 NO

6 5.0 6.0 39.81 ZONE 2

7 6.0 8.0 36.87 ZONE 3

8 9.0 9.0 45.00 ZONE 3

9 9.0 10.0 41.99 NO

10 4.0 6.0 33.69 ZONE 2

11 7.0 8.0 41.19 ZONE 3

12 5.0 9.0 29.05 NO

QUADRILATERAL CHARACTERISTIC

RESULTS OBTAINED FOR ANGLES

72*
0X = 75.96

0 73.65 72.55
2
 197

TABLE V

SI.NO. X R 6 > Degree TRIP

1 4.0 1.0 75.96 ZONE 1

2 4.0 6.0 33.69 ZONE 2

3 5.0 8.0 32.01 ZONE 3

4 3.0 8.0 20.55 NO

S 7.0 9.0 37.87 NO

6 7.0 7.0 45.00 ZONE 2

7 10.0 2.0 78 . 69 NO

8 10.0 8.0 51.34 ZONE 3

9 10.0 10.0 45.00 NO

10 8.0 8.0 45.00 ZONE 3

11 1.0 5.0 11.31 ZONE 1

12 2.0 5.0 21.80 ZONE 1

QUADRILATERAL CHARACTERISTIC

RESULTS OBTAINED FOR ANGLES

• •
6, = 78.7 ; 0 ' =78.7
1 2
I ! . ' ' '
02 = 80.08 ; 6 2 = 77.2
 198

TABLE VI

SI.NO. X R 0 > Degree TRIP

1 1.0 1.0 45.00 ZONE 1

2 1.0 4.0 14.04 ZONE 1

3 1.0 5.0 11.31 ZONE 2

4 1.0 6.0 9.46 ZONE 3

5 1.0 7.0 8.13 NO

6 5.0 1.0 78.69 ZONE 1

7 5.0 6.0 39.81 ZONE 2

8 5.0 7.0 35.54 ZONE 3

9 5.0 8.0 32.01 NO

10 6.0 1.0 80.54 ZONE 1

11 6.0 5.0 50.19 ZONE 2

12 10.0 1.0 84.29 NO

QUADRILATERAL CHARACTERISTIC
RESULTS OBTAINED FOR ANGLES

80.54 ' 2 80.54

! t t
1 I
75.96 74.48
2
 199

FIGURE 5.4-11 SINE WAVE OF 50 HZ CONVERTED TO A

SQUARE WAVE OF 50 HZ

FIGURE 5-4-12 SQUARE WAVE OF 50 HZ (INPUT TO PLL) _TOP

CONVERTED TO A SQUARE WAVE OF 600 HZ
( VCO OUTPUT ) . BOTTOM
 200

FIGURE 5-413 SOlUARE WAVE OF 600HZ : INPUT TO

MONOSTABLE MULTIVIBRATOR (BOTTOM)
CONVERTED TO PULSES OF 600 HZ. (USED
AS SOC TO ADCs) ( TOP)

FIGURE 5-4-14 SINE WAVE OF 50HZ INPUT TO SAMPLE

AND HOLD CIRCUIT (TOP) AND SAMPLED
OUTPUT WAVE OF 50 HZ (BOTTOM)
 201

FIGURE 5-4-15 OUTPUT FROM ASTABLE MULTIVIBRATOR OF

500 KHZ USED AS CLOCK PULSES TO ADCs

FIGURE 5-4-16 SINE WAVE OF 50 HZ INPUT TO PHASE SHIFT

CIRCUIT (1) AND PHASE SHIFTED OUTPUT OF
50 HZ (2) USED AS ANALOG SIGNALS
 202

5.4.5. CONCLUSION

The ft;lay has worked perfectly for all the three step

quadrilateral characteristics assumed. The maximum operating time

of relay has been observed to be about 15 m.sec. for the first

zone protection.

Any quadrilateral characteristic can be obtained.

The proposed three zone distance relay is compact unit,

immune to transients, having ability to detect disturbance.

Quadrilateral characteristics compare with ideal protection

characteristics of transmission lines.

Figures 5.4.8, 5.4.9 and 5.4.10 have advantages over figures

5.4.5, 5.4.6 and 5.4.7 for similar distance faults with high

fault resistance in second and third zone protection.

The quadrilateral distance relay also compares very well

with the presently used digital distance relays.

 203

5.5 DEVELOPMENT OF A PC BASED FLEXIBLE THREE STEP QUADRILATERAL

DISTANCE RELAY FOR THE PROTECTION OF EHV/UHV TRANSMISSION LINES

A

With the advent of personnel computers (PC) which are also

cost effective and are comparable with microprocessors, the usage

of PCs [2fi7] in the development of distance relays have also

become more attractive [4,122,137]. The primary advantage of PCs

is the usage of easy high level languages for software

development. The PC's being a programmable device, can be used to

perform multiple functions such as memory action, complex shaping

of operational characteristics development, handling of

mathematical equations, measurements etc. Also with PCs, a single

generdl purpose hardware base can be used to perform a variety of

protection and control functions with changes in the programming

only. A PC relay can furnish post-fault analysis of all observed

transient phenomena.

Making use of all the benefits of PCs, this scheme presents

the development of a PC based flexible three step quadrilateral

distance relay for the protection of EHV/UHV transmission lines.

This scheme is based on the Fourier transform method of

extracting the fundamental components of voltage and current

signals from non-sinusoidal post-fault signals [93, 260, 99] as

explained in section 5.4.1. A card was designed for the hardware

circuit and interfaced to a personnel computer through I/O

channel. Different quadrilateral relay characteristics are

realized through a software for PC. This system gives advantages

like easier software development, easy development of flexible

 204

quadrilateral characteristics, more accurate results using the

features like floating point arithmatic of high level language

compilers, sophisticated user interface and display of results.

The relay has been tested in the laboratory for different

quadrilateral characteristics and the results are tabulated.

The mathematical formulations and impedance calculations are

made a? explained in sections 5.4.1, 5.4.1.1 and 5.4.1.2.

5.5.1 HARDWARE DETAILS

The basic block diagram of the relaying scheme is shown in

fig. 5.5.1. It resembles to fig. 5.4.1. It consists of an 8255

peripheral interface mounted on a I/O card, two analog to digital

converters and two sample and hold circuits for the two input

signals. The clock pulses and the reference voltages needed for

the two A/D converters are generated externally as shown in the

diagram 5.5.1. The detailed circuits are shown in figures 5.5.2,

5.5.3 and 5.5.4. The start of conversion pulses are generated by

the frequency locked start conversion pulse generating circuit

(FLSCPGC) as explained in section 5.4.2.

The block diagram of I/O card is shown in fig. 5.5.5. and

the circuit diagram is shown in fig. 5.5.6. The I/O card

consists of two 8255 programmable peripheral interface (PPI)

chips and one 8253 programmable timer (Appendix III). Only the

second 8255 is used in our design circuit for interfacing. The

ports A and B are made to function as input ports. The port C

upper works as an input port and port C lower as output port. CO

is used to interrupt the processor, when the A/D converters are
RELAYING SCHEME USED TRIP SIGNALS
205
206
207
 208

gQd
IOWE

;
/
10 R D ......
SW2

SW 7
SW3

SW6
IM S

VM§
SMS

BUFFERED
DATA BUS

cs

CARD CIRCUIT
___

8 2 5 5 /8 2 5 3 I/O

_j
u o V- N e>> in 10
co Q a a o a a a a
aNieui^foN*-
t.r OCt 1A

P«“ »- T" T- T- r- r- r-

' Sl7ZS1^ °
1
~i

NO<tU)IANOO^
FIGURE 5-5-6

N « in <0 N
10 RD

Q o a
a CDl Q O
m CD a s m CD

sna viva w3isas

snassaaaov w3xsas
 209

engaged in conversion. Cl, C2 and C3 are connected to LED's for

the indication of tripping for zone 3, zone 2 and zone 1
respectively. C4 is connected to the EOC signal of the A/D
converter which interrupt the processor. The connection of the
PPI with the interface circuit is made with the help of FRC
socket and a flat cable.

5.5.2 SOFTWARE DETAILS

All the initialization required are made at the beginning of
the programme. The samples of voltage and current are taken and
stored. These sampled values of voltage are compared with that of
the corresponding samples in the previous cycle. If the
difference of consecutive seven samples are found greater than 5
percent, a disturbance is deemed to have occured. Otherwise next
set of samples are taken and the process repeats. When the fault
is assumed to have occured, the values of V , V , I and I are
d q d q
calculated using those seven samples of voltage and current.
Subsequently values of R
and X are also computed. Now a check
L L
is made to see whether the values of X and R are greater than
L L
zero and lie within zone 3. When all the tests indicate the
presence of a fault, a trip signal is given to the circuit
breaker. If the fault is in zone 1, no time delay is given ie.
instantaneous tripping is ordered, where as for faults in zone 2
and zone 3, time delays of T and T are given respectively.
2 3
5.5.3 LABORATORY TESTING OF THE RELAY
The required analog input signals of current and voltage
from the system were simulated using a specially designed phase
shift circuit. The software developed for the realization of the
 210

characteristic was stored in the memory of the PC and executed.

The values of impedance and phase were varied with the help of
the phase shifter circuit and the tripping characteristic of the
relay was plotted. The relay was successfully tested for a number
of three step quadrilateral characteristics. Four samples of
three step quadrilateral characteristics are shown in figures
5.5.7/ 5.5.8, 5.5.9 and 5.5.10 and the corresponding test results
are shown in tables I, II, III and IV respectively.

The time required for the relay operation is determined by

four considerations as explained in section 5.4.4. Here the
relay has an operating time of about 15 m.sec. for the first zone
and any time delay can be incorporated for other zones.

5.5.4 CONCLUSION
As the relay is controlled by a personnel computer (IBM
PC/XT/AT), it gives rise to the following added advantages apart
from the uses already explained in section 5.5.

1. Easier in debugging.
2. Reduced complexity of software.
3. It helps to develop the program and test the performance
characteristics much faster.

The relay is working perfectly for all the three step

quadrilateral characteristics assumed. The maximum operating time
of the relay is observed to be about 15 m.sec. for the first zone
protection.
 211

Any quadrilateral characteristic can be obtained.

The proposed three zone distance relay is compact unit,

immune to transients having ability to detect disturbances.

FIGURE 5-5.7 QUADRILATERAL CHARACTERISTIC - 1
 S H

FIGURE 5.5.8 QUADRILATERAL CHARACTERISTIC - 2

 14

FIGURE 5-5-9 QUADRILATERAL CHARACTERISTI C - 3

 G H

FIGURE 5-5.10 QUADRILATERAL CH ARACTERISTI C - 4

 216

Serial No. X R TRIP

IN OHM IN OHM ZONE

1 12.59 2.14 3

2 10.32 1.01 NO

3 8.921 3.18 2

4 4.523 2.56 1

5 4.56 2.08 1

6 11.25 8.52 3

7 7.08 6.32 2

8 2.25 7.18 2

9 2.54 11.08 NO

10 9.42 13.01 NO

11 2.12 1.23 1

12 1 .21 10.23 NO

13 12.05 13.15 3

14 6.24 12.48 NO

15 2.53 6.51 1

RESULT TABLE - I
 217

Serial No. X R TRIP

IN OHM IN OHM ZONE

1 5.18 1.32 2

2 7 .21 1.02 NO

3 1.28 6.24 2

4 9.14 12.21 3

5 10.24 2.34 3

6 12.08 2 .15 NO

7 13.27 10.29 3

8 10.12 13.25 NO

9 2.56 6.50 1

10 6.24 2 .18 2

11 11.15 1.23 NO

12 6.21 11.21 3

13 15.04 2.67 NO

14 9.56 11.51 2

15 2.28 11.26 NO

RESULT TABLE - II
 218

Serial No. X R TRIP

IN OHM IN OHM ZONE

1 2.03 1.12 1

2 4.15 1.16 2

3 5.32 9.08 NO

4 8.41 5.39 2

5 3.00 3.56 1 .
6 10.14 1.12 NO
7 7.54 8.51 3

8 13.21 1.53 NO

9 8.68 8.24 2

10 1.24 7 .13 NO

11 10.13 2 .51 3

12 1.20 5.25 1

13 2.01 7.23 NO

14 3.32 4.50 1

15 2.35 6.21 2

RESULT TABLE - III

 219

Serial No. X R TRIP

IN OHM IN OHM ZONE
A

1 4.12 2.24 1

2 3.26 0.51 NO

3 3.31 1.12 1

4 4.21 3.68 1

5 9.21 2.12 NO

6 4.36 8.29 2

7 8.28 11.21 3

8 1.26 9.04 NO

9 4.56 7.13 1
10 7.01 ' 3.12 2

11 13.12 13.54 NO

12 1.10 1.23 1

13 7.5 10.51 2

1.4 4.51 10.23 NO

15 12.53 5 .58 3

RESULT TABLE - IV
 220

5.6 PC BASED RELAYING SCHEME FOR THE PROTECTION OF AN EXISTING

400 KV TRANSMISSION LINE

The EHV/UHV transmission lines need a reliable, fast,

efficient and low cost protection scheme because of its long

length and its consequent exposure to atmospheric hazards. The

proposed scheme presents the design., development and testing of a

prototype distance relaying scheme along with other interfacing

circuits for the protection of an existing 400 KV transmission

line between Neyveli and Salem in Tamil Nadu, India. Two relaying
schemes - a 3-zone mho offset with blinders [122] and a 3-zone

quadrilateral characteristic - have been implemented as these are

suitable for a longer heavily loaded transmission line. The relay

characteristics are incorporated in the software and the required

design* data are taken for the above sample network of Neyveli-

Salem 400 KV single circuit line in Tamil Nadu, India.

5.6.1 PRINCIPLE OF IMPEDANCE CALCULATION

Distance fault locating digital algorithms are often based

upon the processing of fundamental, components which are

contained in the post fault current and voltage waveforms [261].

It is assumed that the signal contain only the fundamental

components. The method of calculation of line impedance involves

the predictive calculation of peak current and peak voltage. The

modulus of the impedance is determined by the division of peak

voltage by peak current. Furthermore, the phase difference

between the voltage and current waveforms are determined,

enabling complete impedance determination ie. both modulus and

its angle.
 221

5.6.2 HARDWARE DESCRIPTION

The block diagram is illustrated in fig. 5.6.1. It consists

of 8255 I/O port, two analog to digital converters and two sample

and hold circuits for the two digital inputs. The clock pulses

and the reference voltages needed for the two A/D converters are

generated externally as shown in the diagram. The start of

conversion pulses required for the ADC are generated by frequency

locked start conversion pulse generating circuit (FLSCPGC).

The complete connection diagram employed for the relay is

shown in fig. 5.6.2. The circuit can be divided into three parts.

a) Frequency locked pulse generating circuit (FLSCPGC]

b) Data Acquisition System (DAS)

c) PC based interfacing circuit.

5.6.3. RELAY CHARACTERISTICS

Any relay characteristic can be incorporated in the

software. In this scheme, the 3 zones offset mho with blinders

and the 3 zones quadrilateral characteristic have been designed

for the existing 400 KV single circuit Neyveli - Salem line in

Tamil Nadu. The distance of the Neyveli - Salem line is 175 KM.

The impedance for the line is given below:

R 0.0264 ohm/KM = 0.3294 ohm/KM

; x
+ve + ve
i
R 0.2640 ohm/KM ; x0 = 0.9882 ohm/KM
0

The approximate X / x1 ratio for s ingle c ircuit aerial

0
transmission line without ground wire or with magnetic ground

circuits will be average 3.5 and the range will be 2.5 to 3.5.
 MONOSTABLE
FLSCPGC MULTI VIB-
TO REDUCE “I
M IPULSEWIDTH

ACTIVE
P.T.
H /S
AUX P.T. IPASS BAND
VOLTAGE
FILTER
SIGNAL FROM1 * * t
TRANSMISSION
LINE

HS. 12 V
8255
REF CLOCK
VOLTAGE
.5. PULSE I/O PORTl
SOURCE 6EN,
m

ft t
<A

AUX C.T. ANd_ ACTIVE

IPASS BANDl
ID
CURRENT TRANSACTOR!" S /H ADC
FILTER
SIGNAL FRONT
TRANSMISSION
LINE
ZONE
ZONE 2
ZONE 3
FIGURE 5-6.1 BLOCK DIAGRAM OF THE OUT OF ZONE
RELAYING SCHEME USED
222
FIGURE 5-6-2 CONNECTION DIAGRAM OF THE HARDWARE UNIT
 224

5.6.3.1 AUTO-TRANSFORMERS AT NEYVELI AND SALEM

400/230 KV Autos 2 x 250 MVA at Neyveli

and I x 315 MVA at Salem

In this scheme, the relay is designed and tested in the

laboratory for 3 phase faults at different locations.

5.6.3.2. OFFSET MHO CHARACTERISTIC WITH BLINDERS

The offset mho characteristic is shown in fig. 5.6.3.

Signals for 3 zone offset mho with blinders are

S ZR L— '1 |0i (5.6.1)

1

S li (5.6.2)
2
S ZR a - Z a (5.6.3)
3 2 1—

S ZR a - Z of (5.6.4)
4 3 2

S Z |_o_ K Z R a + 180 (5.6.5)

5 o 3 2

S K R R -a (5.6.6)
6 1 1
(5.6.7)
S K
1 R R lL_!
|-a _ - Z
7

S K R R ( - a - 180) (5.6.8)
8 1 1

S K R R ( - a3 - 180) (5.6.9)
9 1 1

The angles are measured from resistance axis i.e. X-axis in

anticlockwise direction. The segment of the blinder is set at 18

»
i.e. 6.076191 radians ( a ) and at 198
3
 226

K = 0.2 ; K = 4; R R =0.37
0 1 1

After calculation of line impedance Z and angle a , it should

1
be verified whether it lies within the desired characteristic

zones. The software is developed accordingly. When there is a

fault andthe zone is detected as out of zone, the relay does no

operation and continue to monitor the voltage andcurrent

signals. When the zone is detected as zone 1, zone 2 or zone 3,

the proper trip signal is issued to the tripping circuit and

print a message.

5.6.3.3. THREE ZONE QUADRILATERAL DISTANCE RELAY

3 zone quadrilateral distance relay characteristic for the

desired Neyveli - Salem 1 ine i s shown in fig. 5.6.4. For

simplicity X , X and X for the Neyveli Salem line are

1 2 3
approximated to 5, 7.5 and 10 ohms.

a = 60 ; a =120* ; 88* = 70* ;

a ; a
2 5 4 l
a = 24* ; 4> =30 ; 6 = 30 * ; « = 22*
3 1

K = 15, K = 20 ; K = 1.5 ; K = 2..0 ; K = 0.4 ;

1 5 3 4 6

K = 0.25.
7

The signals for 3 zone quadrilateral characteristic with offsets

are

S z1 a . -1.57 (5.6.10)
1 4

S = Z [a (5.6.11)
2
 227

FIGURE 5-6-4 THREE ZONE OFFSET QUADRILATERAL

CHARACTERISTICS
 228

s = X (5.6.12)
3 1

S = X - Z (5.6.13)
4 1

S = K R * (5.6.14)
5 1 1 1

S K R (5.6.15)
6
=
1 1 i ~
1 Ll
S = K K (5.6.16)
7 3 1

S = K X - Z [_o_ (5.6.17)
8 3 1

S = K X (5.6.18)
9 4 1

S = K X - Z I a (5.6.19)
10 4 1

S K R | (- 3 ) (5.6.20)
=
11 5 1

s K R (- 6 ) - Z [a_ (5.6.21)
=
12 5 1

S = K Z ( - a + 3.14 - 6 ) (5.6.22)
13 6 1 4

S K z ( a + 3.14 - 6 ) (5.6.23)
14 6 1 4

S K z ( a + 6 ) (5.6.24)
15 7 1 4

S = K z ( a + 0 ) - Z [_a_ (5.6.25)
16 7 1

5.6.4. SOFTWARE DESCRIPTION

The DAS simultaneously samples the filtered voltage and

current of the protected line and by the interface system, these

sampled values are stored in the memory of the PC. After each

sample sweep, the voltage is compared with its equivalent sample

in the previous power cycle (50 HZ). 40 samples are taken per
 229

cycle. If any five consecutive voltage samples are found to have

lower or higher value than the threshold limit that is 6.25

percent of old sample, a significant disturbance is deemed to

have occurred. This cycle by cycle comparison is developed by

Mann and Morrison [88]. The fig. 5.6.5. gives the flow chart

where voltage samples are compared with their values in the

previous cycle. On detecting a significant disturbance, it

predicts the peak value of voltage and current from the

fundamental waveform as per the mathematical formula used and

thereby calculates the apparent impedance upto the fault point,

both in magnitude and phase angle, thus identifying the location

of fault.

This apparent faulted impedance magnitude and angle a is

then compared with the desired relay characteristics of 3 zone

offset mho with blinders (fig. 5.6.3) or the 3 zone

quadrilateral characteristics (fig. 5.6.4) which is incorporated

in the software.

5.6.5. LABORATORY TESTING OF THE RELAY

Figures 5.6.6. to 5.6.9. show waveforms at different

locations in the hardware. The relay has been tested in the

laboratory for three phase faults at different locations using

the data available for the sample transmission line. The input
signals used to test this relay were generated by a phase shift

circuit. In this scheme, both 3 zone quadrilateral and 3 zone

offset mho relay with blinders have been realised. The scheme

possesses the following features.

 230

a) It has directional features

b) It is immune to transients
c) Different types of threshold characteristics can be
implemented using the same hardware.

5.6.6. CONCLUSION
The design, fabrication and testing of a digital distance
relaying scheme for the protection of EHV/UHV transmission line
has been described. The relay characteristics are realised
through software using the parameters of an existing single
circuit 400 KV line between Neyveli and Salem in Tamil Nadu.
232
FIGURE 5.6.5 FLOW CHART FOR IDENTIFYING
THE LOCATION OF THE FAULT
 23 4

FIGURE 5.6 6 TOP: START OF CONVERSION PULSE, WAVEFORM AT E

BOTTOM: END OF CONVERSION PULSE, WAVEFORM

at PIN 9 OF ADC

FIGURE 5.6-7 TOP : SINE INPUT AT PIN 3 OF LF396 SAMPLE

AND HOLD

BOTTOM: OUTPUT AT PIN 5 OF LF398 SAMPLE

AND HOLD
 235

FIGURE 5-6.8 TOP: VOLTAGE SIGNAL SAMPLED : ANALOG

INPUT TO TOP ADC
BOTTOM: CURRENT SIGNAL SAMPLED: ANALOG
INPUT TO BOTTOM ADC

FIGURE 5-6.9 500 KHZ CLOCK CYCLES. EXTERNAL CLOCK

INPUT TO ADC 0800