0.8 mW, 0.
1-110 GHz RF Power Detector with 6 GHz Video Bandwidth
for Multigigabit Software Defined Radios
Saad Qayyum and Renato Negra
Chair of High Frequency Electronics
RWTH Aachen University
52056 Aachen, Germany
Abstract—This work presents two compact, low power, broad-
band and high sensitivity CMOS power detectors targeted
for multi-gigabit software defined radio applications. A high
sensitivity and a video detector are implemented in standard
65 nm CMOS technology with resistive input matching. Both
designs have a measured input matching bandwidth up to
110 GHz. Measured peak detection sensitivity of the high
sensitivity detector is 67 dB whereas the video detector possesses
more than 10 GHz video bandwidth (verified up to 6 GHz
through measurements). The DC power consumption of the high
sensitivity detector and the video detector is 0.029 mW and
0.8 mW, respectively. To the best knowledge of the authors,
the proposed designs demonstrate the widest reported input
matching bandwidth while possessing a compact footprint, wide
video bandwidth and high detection sensitivity in standard
CMOS technology.
Index Terms—CMOS power detector, video detector, broad-
band, low power.
I. I NTRODUCTION
With the increasing demand in data-rates, modern mobile
communication standards are moving towards millimeter wave
frequencies to exploit the wide bandwidths available there.
For instance, radio regulatory organisations around the globe
have legislated frequency allocations for unlicensed bands
around 60 GHz. For this frequency band, six-port junction
receivers have emerged as an alternative to the conventional
mixer based receivers at mmwave frequencies. The RF front-
end of such a receiver consists of a passive six-port junction
and four power detectors. It performs frequency conversion
without requiring costly active mixers. Six-port junction re-
ceiver implementations have been demonstrated using MH-
MIC and monolithic technologies by [1], [2]. Since, the six-
port junction comprises passive microwave components, it
can be made very wideband. However, the power detectors
connected at the 50 Ω output ports of the junction limit the
receiver bandwidth. In order to maintain the required phase
relationship among the four outputs of the six-port junction,
the power detectors should provide suitable matching over
the operating bandwidth. Therefore, in order to cover several
communication bands, an SDR front-end requires the power
detectors to operate over an RF bandwidth of several tens
of gigahertz. The power detectors must also possess wide
video bandwidth and high sensitivity in order to demodulate
wideband signals with complex modulation schemes.
The power detectors implemented in bipolar and III-V
technologies are popular due to their superior performance
1722
as compared to CMOS implementations [3], [4]. CMOS
technology, on the other hand provides a low cost solution
for a complete system-on-chip (SoC) implementation. CMOS
power detectors are typically designed to operate in the strong
inversion region [5] due to the inherent square-law behaviour
as required for square-law detectors. For deep submicron
technologies, the short channel effects become dominant and
the nature of the IV curve of the transistor is not square law
anymore. Further, the second order transconductance (gm2 =
2
iout /vin ) in the strong inversion region depends on the device
size and process parameters and is much lower than in the
bipolar counterparts [3]. This results in a much lower detection
sensitivity for CMOS power detectors. It can be compensated
by using a large resistive load but this is detrimental to
the video bandwidth. A common-gate CMOS power detector
operating in subthreshold regime is demonstrated in [5] but
exhibits a high input impedance suited for automatic level
control and mmwave buit-in-test applications. As stated earlier,
the high input impedance is not required for a six-port junction
receiver application. Also, its reported video bandwidth is
limited to 700 MHz, which might originate from an increased
output capacitance.
In this paper, we demonstrate the design of a common-
source CMOS power detectors operating in subthreshold
regime, fully utilising its benefits for high data-rate receiver
applications. Two power detectors are implemented in 65 nm
standard CMOS technology showing that the power detector
can be optimised for high detection sensitivity or wide video
bandwidth. A matching resistor provides wideband RF input
matching for both designs.
II. C IRCUIT D ESIGN
The requirements of wideband input matching, high detec-
tion sensitivity and wide video bandwidth present a trade-
off for power detector designs. High values of input and
load resistance are good in terms of obtaining high detection
sensitivity but result in poor input return loss and narrow
video bandwidth, respectively. By operating the power detector
in subthreshold region, wideband input matching, wide video
bandwidth and good sensitivity are simultaneously achieved.
This is due to inherently high gm2 in the subthreshold region.
With simple mathematical manipulations, it can be shown that
gm2 = ID /VT2 , where ID is the DC drain bias current and
VT = 26 mV at room temperature.
978-1-5090-6360-4/17/$31.00 ©2017 IEEE
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The proposed power detector, shown in Fig. 1, consists 3LQ G%P
of a common-source stage for power detection. Two variants
of the power detector are designed to demonstrate the two Fig. 3. Measured output voltage vs. input power for the high sensitivity
performance aspects, i.e. high detection sensitivity and wide detector.
video bandwidth. Both designs operate the common-source
stage in subthreshold regime to boost gm2 . In order to carry out 
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video bandwidth measurements, the video detector requires a 9LGHRGHWHFWRU

common-drain stage as an output buffer to drive the 50 Ω load

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of the measurement equipment. Since the output of the power
detector is fed to the A/D converters in a communication 

receiver application, an output buffer is not needed there. A 

matching resistor, Rmatch , is used at the input for wideband

matching. DC gate bias, VGS , is applied through a large
resistor, Rbias . For each design, the DC gate bias voltage, 

together with the load resistor, RL , are set in order to maximise 

the detection sensitivity and the video bandwidth. An input 
coupling capacitor, Ccoupling , is included on chip. The total    
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area of the high sensitivity detector and the video detector,

excluding the pads is 180 μm × 105 μm and 120 μm × 80 μm, Fig. 4. Measured detection sensitivity of the proposed power detectors.
respectively.


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110 GHz. Power detection measurements are also carried out
for the two power detectors. For the high sensitivity detector,
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the input power is swept from around −42 dBm to a maximum

of 0 dBm for input frequencies up to 117 GHz. Fig. 3 shows

   
the transfer curves for the high sensitivity detector for selected
5))UHT*+] frequencies. The measured tangential signal sensitivity varies

9LGHRGHWHFWRU between −36 dBm and −32 dBm across the frequency band.

The 1 dB compression is reached at an input power between
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−15 dBm and −10 dBm, resulting in a square-law dynamic

range of at least 21 dB up to 117 GHz. Although, not shown
 here, the power detection measurements of the video detector
   
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Fig. 2. Measured input reflection coefficient, S11 , of the proposed power
detectors. III. M EASUREMENT R ESULTS
The performance of the power detectors is experimentally
verified as stand-alone components. An on-wafer measurement
setup is used and standard SOLT calibration is done before
S-parameter measurements. For the power detection measure-
ments, power calibration is done for each frequency point to
ensure constant power at the probe tips.
Fig. 2 shows the measured input reflection coefficient for
the two designs. Both designs possess an input reflection co-
efficient better than −9.5 dB from very low frequencies up to
to 0 dBm. The input frequency ranges between 10 GHz and
117 GHz. The video detector achieves a tangential signal
sensitivity of at least −22 dBm whereas its 1 dB compression
is reached at an input power of −10 dBm, yielding a square-
law dynamic range of 12 dB. Fig. 4 shows the measured
detection sensitivity at an input power of −20 dBm. The high
sensitivity design achieves a maximum sensitivity of 67 dB.
It maintains at least 65 dB of sensitivity up to 97 GHz which
reduces to approximately 59.5 dB at 117 GHz. The detection
sensitivity of the video detector varies between 36.8 dB and
42 dB across the entire frequency band.
The video bandwidth of the video detector is verified by

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 TABLE I
P ERFORMANCE COMPARISON WITH THE STATE - OF - THE - ART

Ref. Technology RF BW (GHz) Video BW Sensitivity (dB) Area (μm × μm) PDC (mW)
[3] 0.13 μm SiGe BiCMOS 79 − 102 − 92 − 95.5 − 0.225
[6] 45 nm CMOS 80 − 110 80 MHz − 340 −
[7] 65 nm SOI CMOS 60 2.5 GHz − − −
[4] 0.25 μm InP DHBT 110 − 150 13 GHz 69 − 15
[5] 55 nm BiCMOS 50 − 66 0.7 GHz − 80 × 80 −
0.1 − 110 − 67 180 × 105 0.029
This Work 65 nm CMOS
0.1 − 110 6 GHz* 36.8 − 42 120 × 80 0.8
* Simulated 3 dB bandwidth of more than 10 GHz

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Fig. 5. Video bandwidth measurements for the video detector.
applying a two-tone input signal and measuring the power
of the IF tones. The power of the two input tones is set
between −10 dBm and −15 dBm depending upon the input
frequency. The RF frequency is varied from 10 GHz to 67 GHz
whereas the second tone is offset by 100 MHz to 10 GHz
for each instance of RF frequency. Fig. 5 shows the output
power of the resulting IF tone from 100 MHz to 10 GHz
for different RF frequencies. According to simulations, the
3 dB video bandwidth of the proposed detector is more than
10 GHz but could only be verified up to 6 GHz due to the
bandwidth limitation of the available oscilloscope. The DC
power consumption of the high sensitivity detector is only
0.029 mW whereas that of the video detector is 0.8 mW, not
including the output buffer. Table I presents the comparison
of this work with the state-of-the-art. The proposed design
has wider video bandwidth than the other power detectors
implemented in CMOS technologies. The only design with
better video bandwidth is [4] which uses an expensive InP
DHBT process. However, our design has far lower DC power
consumption than the power detector in [4]. Fig. 6 shows the
chip microphotograph of both power detectors.
IV. S UMMARY & C ONCLUSION
Low power, broadband, and high sensitivity CMOS power
detectors targeted for multigigabit software defined radio ap-
plications are presented. Two power detectors are implemented
Detector
High
sensitivity
detector


Fig. 6. Microphotograph of the chip.
in standard 65 nm CMOS technology with resistive input
matching demonstrating a measured input matching bandwidth
up to 110 GHz. The first is a high sensitivity design with
measured peak detection sensitivity of 67 dB. The second
design is a video detector possessing more than 10 GHz video
bandwidth. The video bandwidth could only be verified up to
6 GHz due to the bandwidth limitation of the available oscil-
loscope. The DC power consumption of the high sensitivity
detector and the video detector is 0.029 mW and 0.8 mW,
respectively. To the best knowledge of the authors, the pro-
posed designs demonstrate widest reported input matching
bandwidth while possessing small size, wide video bandwidth
and high detection sensitivity in standard CMOS technology.
ACKNOWLEDGMENT
The authors would like to acknowledge Higher Educa-
tion Commission (HEC), Pakistan and German Academic
Exchange Service (DAAD), Germany for their support. The
authors would also thank Mr. Benedikt Welp and Dr. Nils Pohl
from Fraunhofer Institute for High Frequency Physics and
Radar Techniques (FHR), Germany for providing the measure-
ment facility above 67 GHz and help with the measurement
setup. The authors are also thankful to Dr. Souheil Ben Smida
from University of Bristol, UK for the fruitful discussions.
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 R EFERENCES
[1] S. O. Tatu, E. Moldovan, K. Wu, and R. G. Bosisio, “A new direct
millimeter-wave six-port receiver,” IEEE Trans. Microw. Theory Tech.,
vol. 49, no. 12, pp. 2517–2522, Dec 2001.
[2] C. H. Wang, H. Y. Chang, P. S. Wu, K. Y. Lin, T. W. Huang, H. Wang,
and C. H. Chen, “A 60 GHz low-power six-port transceiver for gigabit
software-defined transceiver applications,” in ISSCC Dig. Tech. papers,
Feb 2007, pp. 192–596.
[3] R. Jonsson, S. B. Reyaz, R. Malmqvist, and M. Kaynak, “A W-band
power detector RFIC design in 0.13 um SiGe BiCMOS process,” Microw.
Opt. Techn. Let., vol. 57, no. 2, Feb. 2015.
[4] M. Bao, J. Chen, R. Kozhuharov, and H. Zirath, “A high-speed power
detector for D -band communication,” IEEE Trans. Microw. Theory Tech.,
vol. 62, no. 7, pp. 1515–1524, July 2014.
[5] A. Serhan, E. Lauga-Larroze, and J. M. Fournier, “Common-
base/common-gate millimeter-wave power detectors,” IEEE Trans. Mi-
crow. Theory Tech., vol. 63, no. 12, pp. 4483–4491, Dec 2015.
[6] C. Lee, W. Choi, R. Han, H. Shichijo, and K. K. O, “Broadband root-
mean-square detector in CMOS for on-chip measurements of millimeter-
wave voltages,” IEEE Electron Device Lett., vol. 33, no. 6, pp. 752–754,
June 2012.
[7] A. Siligaris, F. Chaix, M. Pelissier, V. Puyal, J. Zevallos, L. Dussopt,
and P. Vincent, “A low power 60-GHz 2.2-Gbps UWB transceiver with
integrated antennas for short range communications,” in Proc. IEEE Radio
Frequency Integrated Circuits Symposium (RFIC), June 2013, pp. 297–
300.

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