Memory and Digital Electronics Concepts Explained

1.
The number of memory locations in which 14 address bits can access is
A. 1024 B. 2048
C. 4096 D. 16384
Answer & Explanation
Answer: Option D
Explanation:
214 = 16384.
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2. What will be conversion rate for a counter type A/D converter contains a 4 bit binary ladder and a counter driven by a 2 MHz
clock. Then conversion time
A. 125
B. 125 x 103
C. 125 x 106
D. None
Answer: Option B
Explanation:
FSV of the A/D is determined by the FSV of D/A used internally.
3. A 6 bit R-2R ladder D/A converter has a reference voltage of 6.5 V. It meets standard linearity then resolution in percent and
volts.
A. 3% 7 V
B. 6.4 V, 2%
C. 0.1%, 1.57 V
D. 1.57%, 0.1 V
Answer: Option D
Explanation:
R-2R ladder, resolution =
Resolution in volts = .
4. What will be output for decimal input 82?
A. 0.82 V
B. 8V
C. 0.1 V
D. 10 mV
Answer: Option A
Explanation:
Output for decimal input 82/(10000010) = 0.01 x 82 = 0.82 V.
5. The circuit of the given figure gives the output Y =
A. AB
B. A+B
C. AB
D. A+B
Answer: Option D
Explanation:
When any input is High, the corresponding transistor conducts and output is Low. Hence it is a NOR gate.
6. In a 4 bit ripple counter using flip flops with tpd = 40 ns, the maximum frequency can be
A. 1.25 MHz
B. 3.25 MHz
C. 6.25 MHz
D. 12.5 MHz
Answer: Option C
Explanation:
Total time delay = 40 x 4 = 160 x 100-9s. Hence .
7. What will be FSV in 2 bit BCD D/A converter is a weighted resistor type with E R = 1V, R = 1 MΩ and Rf = 10KΩ
A. 0.99 V
B. 0.9 V
C. 0.1 V
D. 0
Answer: Option A
Explanation:
FSV for BCD = (10d - 1)VR. = (102 -1) x .

8. The number of product terms in the minimized sum of product expression obtained through the following K-map, where d, don't
care.
A. 2 B. 3
C. 4 D. 5
Answer: Option A
Explanation:
y = B C + ACD.
9. BCD equivalent of - 810 is
A. 00110 B. 10110
C. 11000 D. 01000
Answer: Option C
Explanation:
Decimal 8 = 1000 and - 8 = 11000.
10. The number of inputs and outputs in a full adder are
A. 2 and 1
B. 2 and 2
C. 3 and 3
D. 3 and 2
Answer: Option D
Explanation:
11. A + A . B =
A. B
B. A.B
C. A
D. A or B
Answer: Option C
Explanation:
A.B= 1 or 0, A + A.B = 0 if A is zero and A + A.B = 1 if A = 1. Hence A + A.B = A.
12. The device 'one shot' has
A. two stable states
B. one stable state
C. either 1 or 2 stable states
D. no stable state
Answer: Option B
Explanation:
One shot means one stable state.
13. For the logic circuit of the given figure the simplified Boolean expression is
A. A + BC
B. A + BC
C. A+BC
D. A + BC
Answer: Option B
Explanation:
= A + BC.
14. If number of information bits is 4, the parity bits in Hamming code are located at bit positions __________ from the LSB.
A. 1, 2, 5
B. 1, 2, 4
C. 1, 2, 3
D. 1, 2
Answer: Option B
Explanation:
The number of parity bits is 3. These bits are located at 2 0, 21, 22, i.e., 1, 2, 4th bits starting from LSB.
15. A certain JK FF has tpd = 12 n sec the largest MOD counter that can be constructed from these FF and still operate up to 10 MHz
is
A. any B. 8
C. 256 D. 10
Answer: Option C
Explanation:
Clock period() = = 10-7 sec
Number of FF =
mod counter 28 = 256.
16. Two 2's complement number having sign bits X and Y are added and the sign bit of the result is Z. then, the occurrence of
overflow is indicated by the Boolean function.
A. XYZ
B. XYZ
C. X YZ + XY Z
D. XY + YZ + ZX

Answer: Option D
Explanation:
carry of a one bit full order is given by expression XY + YZ + ZX.
17. If A = 0101, then A' is
A. 1010 B. 1011
C. 1001 D. 0110
Answer: Option B
Explanation:
A' = 1010 + 1 = 1011.
18. 11011 in gray code = __________ .
A. 100102 B. 111112
C. 111002 D. 100012
Answer: Option A
Explanation:
Change to decimal and then to binary.
19. In the circuit of the given figure, Y =
A. 0
B. 1
C. X
D. X
Answer: Option A
Explanation:
XX = 0.
20. A . 0 =
A. 1
B. A
C. 0
D. A or 1
Answer: Option C
Explanation:
1.0 = 0 and 0.0 = 0.
21. The complement of exclusive OR function is
A. AB + A B
B. AB + A B
C. AB+A
D. AB + A B
Answer: Option B
Explanation:
Complement of XOR is X NOR.

22. Decimal -90 equals __________ in 8 bit 2s complement
A. 1000 1000
B. 1010 0110
C. 1100 1100
D. 0101 0101
Answer: Option B
Explanation:
+90 in binary is 01011010. Its 2's complement is 10100110.
23. 23.610 = __________ 2
A. 11111.1001 B. 10111.1001
C. 00111.101 D. 10111.1
Answer: Option B
Explanation:
23= 10111 and 0.6 =10011 Hence 10111 . 10011 .
24. In a shift left register, shifting a bit by one bit means
A. division by 2
B. multiplication by 2
C. subtraction of 2
D. None of the above
Answer: Option B
Explanation:
In binary shift one bit left means multiplication by 2.

25. If A = B = 1, the outputs P and Q in the given figure are
A. P=Q=0
B. P = 0, Q = 1
C. P = 1, Q = 0
D. P=Q=1
Answer: Option B
Explanation:
It is a half adder 1 + 1 = 10. Therefore SUM = P = 0 and Carry = Q = 1.
26. In the given figure, Y =
A. (A + B)C + DE
B. AB + C(D + E)
C. (A + B)C + D + E
D. none of the above
Answer: Option A
Explanation:
.
27. Assertion (A): The access time of memory is lowest in the case of DRAM
Reason (R): DRAM uses refreshing cycle.
A. Both A and R are correct and R is correct explanation of A
B. Both A and R are correct but R is not correct explanation of A
C. A is true, R is false
D. A is false, R is true
Answer: Option D
Explanation:
DRAM has lower speed than SRAM.
28. In a 3 input NOR gate, the number of states in which output is 1 equals
A. 1 B. 2
C. 3 D. 4
Answer: Option A
Explanation:
Only one input, i.e., A = 0, B = 0 and C = 0 gives 1 as output.
29. Assertion (A): Even if TTL gates and CMOS gates used in a realization have the same power supply of + 5 V, suitable circuit is
needed to interconnect them
Reason (R): VOH, VOL, VIH and VIL of a TTL gave are respectively 2.4, 0.4, 2 and 0.8 V respectively. If supply voltage is + 5 V.
VIL and VIH for CMOS gate for the supply voltage of + 5 V are 1.5 V and 3.5 V respectively.

Answer: Option A
Explanation:
Interfacing is necessary and interfacing depends on gate parameters like V OH, VOL, IIH, IIL.
30. The series 54 H/74 H denotes
A. Standard TTL
B. High speed TTL
C. Low Power TTL
D. High Power TTL
Answer: Option B
Explanation:
It denotes high speed TTL.
31. For a 4096 x 8 EPROM, the number of address lines is
A. 14 B. 12
C. 10 D. 8
Answer: Option B
Explanation:
4096 = 212 .
32. Assertion (A): A PROM can be used as a synchronous counter
Reason (R): Each memory location in a PROM can be read synchronously.

Answer: Option D
Explanation:
PROM is a memory. It is not a counter.
33. ABCD + AB C D =
A. ABC
B. ABCD
C. ABD
D. ABCD
Answer: Option C
Explanation:
A B C D + A B C D = A B D(C + C) = A B D .
34. Find the output voltage for 011100 in a 6 bit R-2R ladder D/A converter has a reference voltage of 6.5 V.
A. 6.4 V
B. 2.84 V
C. 0.1 V
D. 8V
Answer: Option B
Explanation:
(an-1 2n-1 + an-2 2n-2 + .....a121 + a020)
(24 + 23 + 22) = 6.5 x = 2.84 .
35. Binary number 1101 is equal to octal number
A. 17 B. 16
C. 15 D. 14
Answer: Option C
Explanation:
1101 = 13 in decimal = 15 (i.e., 8 + 5) in octal.
36. Logic analyser is
A. a multichannel oscilloscope
B. similar to logic pulser
C. similar to current tracer
Answer: Option A
Explanation:
It is a multichannel oscilloscope.
37. The minimized version of logic circuit in the given figure is

A.
B.
C.
D.
Answer: Option A
Explanation:
The Boolean equation is The circuit
in the given figure gives .
38. In the given figure shows a negative logic AND gate. If positive logic is used this gate is equivalent to
A. AND gate
B. OR gate
C. NOR gate
D. NAND gate
Answer: Option C
Explanation:
Y=AB=A+B.
39. The function Y = A B C + AB C + A B C + A BC is to be realized using discrete gates. The inputs available are A, B, C. We need
a total of
A. 8 gates
B. 6 gates
C. 10 gates
D. 5 gates
Answer: Option A
Explanation:
Three NOT gates, four AND gates and one OR gate, i.e., total of 8 gates.
40. A 10 bit D/A converter gives a maximum output of 10.23 V. The resolution is
A. 10 mV
B. 20 mV
C. 15 mV
D. 25 mV
Answer: Option A
Explanation:
Resolution = V or 10 mV.
41. As applied to a flip flop the word edge triggered's means
A. flip flop can change state when clock transition occurs
B. flip flop can change state when clock signal goes from LOW to HIGH only
C. flip flop can change state when clock signal goes from HIGH to LOW only

Answer: Option A
Explanation:
Edge triggering means the instant when clock transition occurs.
42. A NOR gate is a combination of
A. OR gate and AND gate
B. AND gate and NOT gate
C. OR gate and NOT gate
D. two NOT gates
Answer: Option C
Explanation:
OR and NOT = NOR.
43. The 2's complement representation of - 17 is
A. 01110 B. 01111
C. 11110 D. 10001
Answer: Option B
Explanation:
(17)10 = (10001)2 = (-17)10 = 1's complement of (17)2 + 1
the MSB is 0, hence (-17)2 cannot represented in 2's complement representation with 5 bit, therefore (-17) in 2's complement
is simply (10001)2 = (17)10 .
44. TTL inverter has
A. one input
B. two inputs
C. one or two inputs
D. three inputs
Answer: Option B
Explanation:
Data input and control input.
45. 4 bit ripple counter and 4 bit synchronous counter are made using flip-flop having a propagation delay of 10 ns each. If the
worst case delay in the ripple counter and the synchronous counter be R and S respectively, then
A. R = 10 ns, S = 40 ns
B. R = 40 ns, S = 10 ns
C. R = 10 ns, S = 30 ns
D. R = 30 ns, S = 10 ns
Answer: Option B
Explanation:
In synchronous counter time delay is constant while in Ripple it is additive.
46. The number of digits in hexadecimal system
A. 15 B. 16
C. 10 D. 8
Answer: Option B
Explanation:
It has 16 digits 0 to 15.
47. Which of these is the most recent display device?
A. LED
B. LCD
C. VF
D. (a) and (c)
Answer: Option C
Explanation:
VF display can operate at very low voltages, has low power consumption and very long life.
48. A NOR gate has 3 inputs A, B, C. For which combination of inputs is output HIGH
A. A=B=C=0
B. A=B=C=1
C. A = B = 1 and C = 0
D. A = C = 1 and B = 0
Answer: Option A
Explanation:
NOR gate gives High output when all inputs are Low.
49. In 2's complement form, - 2 is
A. 1011 B. 1110
C. 1100 D. 1010

Answer: Option B
Explanation:
A = 1110,
A = 0001,
A + 1 = 0001 + 1 = 0010 = 2
Therefore A = -2.
50. The Boolean function/implemented in the figure using two I/P multiplexers is
A. ABC + ABC
B. ABC + AB C
C. ABC + ABC
D. ABC + AB C
Answer: Option A
Explanation:
when B = 1, f1 = ABC
B = 0, f2 = ABC
f = f1 + f2 = ABC + ABC.

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1.

The number of memory locations in which 14 address bits can access is

Answer & Explanation

View Answer Workspace Report Discuss in Forum

Answer & Explanation

FSV of the A/D is determined by the FSV of D/A used internally.

View Answer Workspace Report Discuss in Forum

Answer & Explanation

R-2R ladder, resolution =

View Answer Workspace Report Discuss in Forum

4. What will be output for decimal input 82?

Answer & Explanation

Output for decimal input 82/(10000010) = 0.01 x 82 = 0.82 V.

View Answer Workspace Report Discuss in Forum

5. The circuit of the given figure gives the output Y =

Answer & Explanation

View Answer Workspace Report Discuss in Forum

Answer & Explanation

Total time delay = 40 x 4 = 160 x 100-9s. Hence .

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Answer & Explanation

FSV for BCD = (10d - 1)VR. = (102 -1) x .

View Answer Workspace Report Discuss in Forum

Answer & Explanation

View Answer Workspace Report Discuss in Forum

9. BCD equivalent of - 810 is

Answer & Explanation

Decimal 8 = 1000 and - 8 = 11000.

View Answer Workspace Report Discuss in Forum

10. The number of inputs and outputs in a full adder are

Answer & Explanation

View Answer Workspace Report Discuss in Forum

Answer & Explanation

View Answer Workspace Report Discuss in Forum

12. The device 'one shot' has

A. two stable states

B. one stable state

C. either 1 or 2 stable states

Answer & Explanation

One shot means one stable state.

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Answer & Explanation

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Answer & Explanation

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Answer & Explanation

Clock period() = = 10-7 sec

mod counter 28 = 256.

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Answer & Explanation

carry of a one bit full order is given by expression XY + YZ + ZX.

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17. If A = 0101, then A' is

Answer & Explanation

A' = 1010 + 1 = 1011.

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18. 11011 in gray code = __________ .

Answer & Explanation

Change to decimal and then to binary.

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19. In the circuit of the given figure, Y =

Answer & Explanation