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UNIT-IV

TRANSISTOR BIASING

Introduction:
The basic function transistor is to do amplification. The process of raising the strength of a
weak signal without any change in its shape is known as faithful amplification.

For faithful amplification, the following three conditions must be satisfied:

i) The emitter-base junction should be forward biased,

ii) The collector-base junction should be reverse biased.
iii) Three should be proper zero signal collector current.
The proper flow of zero signal collector current (proper operating point of a transistor) and
the maintenance of proper collector-emitter voltage during the passage of signal is known as
‘transistor biasing’.

When a transistor is not properly biased, it work inefficiently and produces distortion in the
o m
output signal. Hence a transistor is to be biased correctly. A transistor is biased either with the
help of battery (or) associating a circuit with the transistor. The latter method is generally

. c
ls
employed. The circuit used with the transistor is known as biasing circuit.

In order to produce distortion-free output in amplifier circuits, the supply voltages and
resistances in the circuit must be suitably chose. These voltages and resistances establish a set of

ir a
d.c. voltage VCEQ and current ICQ to operate the transistor in the active region. These voltages and
currents are called quiescent values which determine the operating point (or) Q-Point for the
transistor.

e
The process of giving proper supply voltages and resistances for obtaining the desired Q-

Jn
t
tu
Point is called biasing.

m
at
DC Load Line:

a
er
ia
Consider common emitter configuration circuit shown in figure below:

ls.
co
m
u M
n t
J
In transistor circuit analysis generally it is required to determine the value of IC for any
desired value of VCE. From the load line method, we can determine the value of IC for any desired
value of VCE. The output characteristics of CE configuration is shown in figure below:

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By applying KVL to the collector circuit

−VC + IC RC + VCE = 0

o m
⇒ VCC = IC RC + VCE
. c
⇒V
CE
=V −I R
CC C C
ls
ir a
If the bias voltage VBB is such that the transistor is not conducting then IC=0 and VCE= VCC.
Therefore, when IC=0, VCE= VCC this point is plotted on the output characteristics as point A.

If VCE=0 then

e
Jn
t
tu
0 =V −I R

m
CC C C

at
a
er
V

ia
⇒ I = CC

ls.
C

co
R

m
C

Therefore, VCE=0,
V
RC

u M
IC = CC this point is plotted on the output characteristics as point B.

The line drawn through these points is straight line ‘d.c load line’.

n t
The d.c. load line is plot of IC versus VCE for a given value of RC and a given level of VCC.

Operating Point (or) Quiescent Point:

J
Hence from the load line we can determine the IC for any desired value of VCE.

In designing a circuit, a point on the load line is selected as the dc bias point (or) quiescent
point. The Q-Point specifies the collector current IC and collector to emitter voltage VCE that exists
when no input signal is applied.

The dc bias point (or) quiescent point is the point on the load line which represents the
current in a transistor and the voltage across it when no signal is applied. The zero signal values of
IC ad VCE are known as the operating point.

Biasing:

The process of giving proper supply voltages and resistances for obtaining the desired Q-
point is called ‘biasing’.
How to choose the operating point on DC load line:
The transistor acts as an amplifier when it is operated in active region. After the d.c.
conditions are established in the circuit, when an a.c. signal is applied to the input, the base

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current varies according to te amplitude of the signal and causes IC to vary consequently producing
an output voltage variation. This can be seen from output characterizes.

Fig. Operating point near saturation region gives clipping at the positive peak.
Consider point A which is very near to the saturation point, even though the base current is
varying sinusoidally the output current and output voltage is seen to be clipped at the positive

o m
peaks. This results in distortion of the signal.
Consider point B which is very near to the cut-off region. The output signal is now clipped

. c
ls
at the negative peak. Hence this two is not a suitable operating point.

ir a
e
Jn
t
tu
m
at
a
er
ia
ls.
co
m
u M
t
Fig. Operating point near cut-off region given clipping at the negative peak.

n
J
Consider point C which is the mid point of the DC load line then the output signal will not
be distorted.

Fig. Operating point at the centre of active region is most suitable.

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A good amplifier amplifies signals without introducing distortion. Thus always the operating
point is chosen as the mid point of the DC load line.

Stabilization:

The maintenance of operating point stable is known as ‘Stabilization’.

There are two factors which are responsible for shifting the operating point. They are:
i) The transistor parameters are temperature dependent.
ii) When a transistor is replaced by another of same type, there is a wide spread in
the values of transistor parameters.

So, stabilization of the operating point is necessary due to the following reasons:
i) Temperature dependence of IC.
ii) Individual variations and
iii) Thermal runaway.
Temperature dependence of IC:

o m
The instability of IC is principally caused by the following three sources:

i) The ICO doubles for every 10oC rise in temperature.

. c
ii)
iii)
Increase of β with increase of temperature.
The VBE decreases about 2.5mV per oC increase in temperature.
ls
Individual variations:

When a transistor is replaced by another transistor of the same type, the values of β and ir a
e
Jn
VBE are not exactly the same. Hence the operating point is changed. So it is necessary to stabilize

t
tu
the operating point irrespective of individual variations in transistors parameters.

m
at
a
er
Thermal Runaway:

ia
ls.
co
Depending upon the construction of a transistor, the collector junction can withstand

m
maximum temperature. The range of temperature lies between 60oC to 100oC for ‘Ge’ transistor
and 150oC to 225oC for ‘Si’ transistor. If the temperature increases beyond this range then the
transistor burns out. The increase in the collector junction temperature is due to thermal runaway.

u M
n t
When a collector current flows in a transistor, it is heated i.e., its temperature increases. If
no stabilization is done, the collector leakage current also increases. This further increases the
transistor temperature. Consequently, there is a further increase in collector leakage current. The
action becomes cumulative and the transistor may ultimately burn out. The self-destruction of an
unstabilized transistor is known as thermal runaway.

1)
J
The following two techniques are used for stabilization.

Stabilization techniques:

The technique consists in the use of a resistive biasing circuit which permits such a
variation of base current IB as to maintain IC almost constant in spite of ICO, β and VBE.

2) Compensation techniques:

In this technique, temperature sensitive devices such as diodes, thermistors and

sensistors etc., are used. Such devices produce compensating voltages and current in such
a way that the operating points maintained stable.
Stability factors:
Since there are three variables which are temperature dependent, we can define three
stability factors as below:
i) S: The stability factor ‘S’ is defined as the ration of change of collector current IC with
respect to the reverse saturation current ICO, keeping β and VBE constant

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∂I ∂I
i.e., S= C ≈ C VBE, β constant
∂I ∂I
CO CO
ii) S’: The stability factor S’ is defined as the rate of change of IC with respect to VBE,
keeping ICO and β constant i.e.,
∂I
∂I
S' = C ≈ C ICO, β constant
∂VBE ∂VBE
iii) S’’: The stability factor S’’ is defined as the rate of change of IC with respect to β,
keeping ICO and VBE constant i.e.,

∂I ∂I
S' = C ≈ C
∂β
Ideally, stability factor should be perfectly zero to keep operating point stable.
∂β
ICO, VBE constant

o m
Practically, stability factor should have the value as minimum as possible.

Derivation of Stability Factor (S):

. c
For a common emitter configuration collector current is given as,

= β IB + I
ls
ir a
I
C CEO
⇒ I = β I B + (1 + β ) I ………….. (1)
C CO

te
Differentiating equation (1) w.r.t. IC keeping β constant, we get

Jn
tu
m
∂I B ∂I

at
1= β + (1 + β ) CO

a
er
∂I ∂I

ia
ls.
C C

co
m
∂I B ∂I
⇒ 1− β

u M ∂I
C
= (1 + β ) CO
∂I
C

n t ⇒
∂I
∂I
C = 1+ β
CO 1 − β B
∂I

J ⇒S =
1+ β
∂I

∂I
1− β B
C
………… (2)

∂I
C
To obtain S’ and S’’:

In standard equation of IC, replace IB in terms of VBE to get S’.

Differentiating equation of IC w.r.t. β after replacing IB in terms of VBE to get S’’.

Methods of Biasing:
Some of the methods used for providing bias for a transistor are as follows:

1) Fixed bias (or) base resistor method.

2) Collector to base bias (or) biasing with feedback resistor.
3) Voltage divider bias.

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1). Fixed bias (or) base resistor method:

A CE amplifier used fixed bias circuit is shown in figure below:

Fig. Fixed bias circuit.

In this method, a high resistance RB is connected between positive terminal of supply VCC
and base of the transistor. Here the required zero signal base current flows through RB and is
o m
provided by VCC.

. c
ls
In figure, the base-emitter junction is forward biased because the base is positive w.r.t.
emitter. By a proper selection of RB, the required zero signal base current (and hence IC=βIB) can
be made to flow.

ir a
Circuit Analysis:
Base Circuit:

e
Consider the base-emitter circuit loop of the above figure.

Jn
t
tu
Writing KVL to the loop, we obtain

m
at
a
er
−VCC + I B RB + VBE = 0

ia
ls.
co
⇒ VCC = I B RB + VBE

m
u M V
⇒ I B = CC
− VBE

n t But
RB

IC = β I B + I CEO

As ICEO is very small,

J IC ≈ β I B
 V − VBE
∴ IC = β  CC
 RB



 
⇒ β, VCC, VBE are constant for a transistor ∴ IC depends on RB.

Choose suitable value of RB to get constant IC in active region.

(VCC − VBE ) β β VCC

∴ RB =
IC
(or) RB =
IC
(QVBE << VCC )
Collector Circuit:

Consider the collector-emitter circuit loop of the circuit.

Writing KVL to the collector circuit, we get

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−VCC + I B RB + VCE = 0

⇒ VCE = VCC − I C RC
Stability factor S:

The stability factor S is given by, S = 1 + ∂βI

1− β B
∂I
C
V − VBE ∂I B
We have I B = CC = constant ∴ =0
RB ∂IC

If β=100 then S=101. This shows that IC changes 101 times as much as any changes in
∴ S = 1+ β

o m
c
ICO. Thus IC is dependent upon ICO and temperature.

Stability factor S’:

The value of S is high and has very poor stability.

= β I B + (1 + β ) I
ls .
ir a
We have I
C CO
V − VBE
But I B = CC
RB

e
Jn
t
tu
 V − VBE 

m
∴ I C = β  CC  + (1 + β ) ICO

at
 

a
er
 RB 

ia
ls.
co
Differentiating the above equation w.r.t. IC,

m
We get 1= −
β ∂VBE
RB ∂IC

u M
⇒ S' = −
n t R
β

Stability factor S’’:

We have I
C
J = β I B + (1 + β ) I
B

CO
Differentiating the above equation w.r.t. β,

∂IC
We get = I B + ICO
∂β
I I
⇒ S '' = C (Q ICO is very small & IB = C )
β β
Problem:

1) Figure below shows a silicon transistor with β=100 and biased by base resistor method.
Determine the operating point.

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Solution:

Given VCC=10V, VBE=0.7V (Silicon transistor), β=100, RB=930kΩ.

Applying KVL to base-emitter loop,

V

o
VCC − VBE = I B RB ⇒ I B = CCm− VBE

c
RB
 V − VBE
IC = β I B = β  CC

 RB



 10 − 0.7 
 = 100 

ls .
 = 1mA
 930 × 103 

ir a
Applying KVL to collector-emitter loop,

VCC − VCE = IC RC ⇒ VCE = VCC − IC RC

( )
e
Jn
⇒ VCE = 10 − 1 × 10−3 × 4 × 103 = 6V

t
tu
m
at
∴ Operating point is (6V, 1mA)

a
er
ia
ls.
2. For the following circuit shown in figure below, find the operating point.

co
m
u M
n t
J
Solution:

DC equivalent of above circuit is shown below.

KVL to base-emitter loop is

−VCC + I B RB + VBE + IC + I B RE = 0 ( )
I B RB + β I B RE + I B RB = VCC − VBE

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VCC − VBE
IB =
RB + (1 + β ) RE

20 − 0.7
∴ IB = = 40.1µ A
( 430 + 51) × 103
IC = β I B = 2.01mA

KVL to collector-emitter loop is

−VCC + IC RC + VCE + IC RE = 0

⇒ VCE = VCC − IC RC + RE ( )
VCE = 20 − 2.01 × 10−3 (2 + 1) × 103 =20-6.03 = 13.97V

o m
∴
Advantages of fixed bias circuit:
Operating point is Q (13.97V, 2.01mA)

. c
ls
1. This is a simple circuit which uses very few components.
2. The operating point can be fixed anywhere in the active region of the characteristics by

ir a
simply changing the values of RB. Thus, it provides maximum flexibility in the design.

Disadvantages of fixed bias circuit:

e
1. With the rise in temperature the operating point if not stable.

Jn
t
tu
2. When the transistor is replaced by another with different value of β, the operating point

m
at
with shift i.e., the stabilization of operating point is very poor in fixed bias circuit.

a
er
ia
Because of these disadvantages, fixed bias circuit required some modifications. In the modified

ls.
co
circuit, RB is connected between collector and base. Hence the circuit is called ‘collector to base’

m
M
bias circuit.

u
2). Collector to Base bias (or) Biasing with feedback resistor:

biasing resistor is connected between the collector and the base of the transistor.

n t
A CE amplifier using collector to base bias circuit is shown in the figure. In this method, the

Fig. Collector–to–Base bias circuit.

Circuit Analysis:
Base Circuit:

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Consider the base-emitter circuit, applying the KVL to the circuit we get,

(
VCC − I B + I C RC − I B RB − VBE = 0 )
( )
⇒ VCC = I B RC + RB + IC RC + VBE

V − VBE − IC RC
⇒ I B = CC …………….. (1)
RC + RB

But IC = βIB

(
β VCC − IC RC − VBE )
∴ IC =
RC + RB
m
…………….. (2)

o
Collector circuit:

. c
ls
Consider the collector-emitter circuit, applying the KVL to the circuit we get

−VCC + I B + IC RC + VCE = 0 ( )
(
⇒ VCE = VCC − IC + I B RC
ir a ) ……………. (3)

e
Jn
Stability factor S:

t
tu
m
The stability factor S is given by,

at
a
er
ia
ls.
S = 1 + ∂βI

co
m
u M1− β B
∂I
C

We have

n t V
I B = CC
− VBE − IC RC
RB + RC
= constant

J
Differentiating the above equation w.r.t. IC we get

∂I B
=−
RC
∂IC RC + RB

1+ β
∴S = ……………… (4)
RC
1+ β
RC + RB

The stability factor S is smaller than the value obtained by fixed bias circuit. Also ‘S’ can be
made smaller by making RB small (or) RC large.

Stability factor S’:

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We have IC =
(
β VCC − VBE − IC RC )
RC + RB

Differentiating the above equation w.r.t. IC,

β ∂VBE RC
We get 1= − −β
RB + RC ∂IC RB + RC

RC β ∂VBE
1+ β =−
RB + RC RB + RC ∂IC

RC + RB + β RC β ∂VBE
RC + RB
=−
RC + RB ∂I C

β
o m
⇒ S' = −
R + (1 + β ) R
B C
. c
………………….. (5)

ls
Stability factor S’’:

( )
ir a
β VCC − VBE − IC RC
We have IC =
RC + RB

te
Differentiating the above equation w.r.t. β,

Jn
tu
m
∂IC − VBE  ∂IC 

at
V RC
= CC  IC + β
−

a
er
We get 

ia
∂β RC + RB RC + RB  ∂β 

ls.
co
m
∂I 
⇒ C 1 + β
∂β 
RC  VCC − VBE − IC RC
=
RC + RB  RC + RB

u M
⇒
∂IC
 R (1 + β ) R  = V − V − I R
∂β  B C CC BE C C

n t
J V
⇒ S '' = CC
− VBE − IC RC
RB + (1 + β ) RC

⇒ S '' =
I
C ( RC + RB ) ……………… (6)
RB + (1 + β ) R
C
Problems:
3. An N-P-N transistor with β=50 is used in a CE circuit with VCC=10V, RC=2kΩ. The bias is
obtained by connecting a 100kΩ resistance from collector to base. Assume VBE=0.7V. Find
i) the quiescent point and
ii) Stability factor ‘S’
Solution:
i) Applying KVL to the base circuit,

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(
VCC = I B + IC RC + I B RB + VBE )
⇒ VCC = I B RC + RB + IC RC + VBE ( )
V
∴ I B = CC
− VBE − IC RC
∴ IC =
(
β VCC − VBE − IC RC )
RC + RB RC + RB

∴ IC =
(
50 10 − 0.7 − 2 × 10−3 IC ) ⇒ IC = 2.3mA
102 × 103
Applying KVL to the collector circuit,

( ) ( )
VCC = I B + IC RC + VCE ∴VCE = VCC − I B + I C RC

( ) o m
= 10 − 46 × 10−6 + 2.3 × 10−3 × 2 × 103

⇒ VCE = 5.308V ∴ The quiescent point is (5.308V, 2.3mA)

. c
ii) Stability factor, S:

ls
ir a
1+ β
S=
RC
1+ β
RC + RB

e
Jn
t
tu
m
51
⇒S = = 25.75

at
a
er
 20 ×103 

ia
1 + 50  

ls.
 102 ×103 

co
 

m
4. A transistor with β=45 is used with collector to base resistor RB biasing with quiescent value of
5V for VCE. If VCC=24V, RC=10kΩ, RE=270Ω, find the value of RB.

u M
Solution:
Applying KVL to collector and emitter loop, we have

VCC − IC RC − VCE − I E RE = 0
n t
⇒ VCC − VCE = IC RC + IC + I B RE

⇒ VCC − VCE =  β RC + (1 + β ) RE  I B
J ( )

VCC − VBE 24 − 5
⇒ IB = =
β RC + (1 + β ) RE 45 × 10 + 50 × 0.27

=0.041 mA

Further, VCC − IC RC − I B RB − VBE − I E RE = 0

⇒ VCC − VBE = RC β I B + I B RB + (1 + β ) RE I B `

⇒ 24 − 0.7 = I B  45 × 10 + RB + 50 × 0.27  ⇒ 23.3 = 0.041  450 + RB + 12.42 

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∴ RB = 105.87 K Ω
3). Voltage Divider Bias (Or) Self-Bias (Or) Emitter Bias:
The voltage divider bias circuit is shown in figure.

o m
. c
ls
Fig. Voltage divider bias circuit.
In this method, the biasing is provided by three resistors R1, R2 and RE. The resistors R1
and R2 acts as a potential divider giving a fixed voltage to the base.

If collector current increases due to change in temperature (or) change in β, the emitter
current IE also increases and the voltage drop across RE increases, reducing the voltage difference
between base and emitter (VBE).
ir a
e
Jn
Due to reduction in VBE, base current IB and hence collector current IC is also reduces.

t
tu
Therefore, we can say that negative feedback exists in the emitter bias circuit. This reduction in

m
at
collector current IC components for the original change in IC.

a
er
ia
ls.
Circuit Analysis:

co
m
M
Let current flows through R1. As the base current IB is very small, the current flowing
through R2 can also be taken as I.
The calculation of collector current IC is as follows:

The current ‘I’ flowing through R1 (or) R2 is given by

t u I=
VCC
…………………… (1)

The voltage V2 developed across R2 is given by,

J n  V
R1 + R2

V2 =  CC  R2 ………….……. (2)
R +R 
 1 2
Base Circuit:

Applying KVL to the base circuit, we have

V2 = VBE + VE = VBE + I E RE ⇒ V2 = VBE + IC RE (Q I E ≈ IC )

V − VBE
∴ IC = 2 …………….. (3)
RE

Hence IC is almost independent of transistor parameters and hence good stabilization is

ensured.

Collector Circuit:
Applying KVL to the collector circuit, we have

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VCC = IC RC + VCE + I E RE ⇒ VCC = I C RC + VCE + IC RE (Q I E ≈ IC )

⇒ VCE = VCC − IC RC + RE ( ) ………………. (4)

Circuit analysis using Thevenin’s Theorem:

The Thevenin equivalent circuit of voltage-divider bias is as shown below:

o m
. c
ls
ir a
e
Jn
t
tu
m
at
a
er
ia
ls.
co
m
u M
n t Fig. Simplified equivalent circuit.

J
From above figure we have,

 R 
V2 = V =  2 V ………………… (5)
Th  R + R  CC
 1 2

RR
R = R1 R2 = 1 2 ………………… (6)
Th R1 + R2

Applying KVL to the base-emitter circuit, we have

V = I B R + VBE + I B + IC RE
Th Th ( ) ……………….. (7)

Applying KVL to the collector-emitter circuit, we have

VCE = VCC − IC RC + RE ( ) (Q IC >> I B )

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………….…….. (8)
From equation (8), we have

V − VCE
∴ IC = CC
RC + RE
Substituting this value of IC in equation (7), we have

 V − VCE 
V = I B R + VBE + RE  I B + CC 
Th Th RC + RE 
 
R V R V
(or) V = I B R + VBE + RE I B + E CC − E CE
Th Th RC + RE RC + RE

Stability factor (S):

From equation (9) we can calculate the value of collector voltage VCE for each value of IB.

o m
For determining stability factor ‘S’ for voltage divider bias, consider the Thevenin’s
equivalent circuit.

. c
ls
Hence, Thevenin’s equivalent voltage VTh is given by
R2
V = V

ir a
Th R + R CC
1 2
and the R1 and R2 are replaced by RB which is the parallel combination of R1 and R2.

e
Jn
R1R2

t
tu
∴ RB =

m
R1 + R2

at
a
er
( )

ia
V = I B RB + VBE + I B + I C RE

ls.
Applying KVL to the base circuit, we get
Th

co
m
Differentiating w.r.t. IC and considering VBE to be independent of IC we get,

∂I B ∂I B
u M
0=
∂IC
× RB +
∂IC

n t ( ) RE + RE

∴
∂I B
∂IC
( RE + RB ) = − RE
J
We have already seen the generalized expression for stability factor ‘S’ given by
∴
∂I B
∂IC
=
− RE
RE + RB

1+ β
S=
∂I
1− β B
∂I C
∂I B
Substituting value of in the above equation, we get
∂I C

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___________________________________________________________________________

1+ β
∴S =
 R 
1+ β  E 
R +R 
 E B 

(1 + β ) ( RE + RB ) (1 + β ) ( RE + RB )
⇒S= =
RB + RE + β RE RB + (1 + β ) RE
 RB 
 1+ 
RE
S = (1 + β )  
 R 
 1 + β + B 

The ratio
 RE
RB

controls value of stability factor ‘S’.

o m
RE

. c
ls
RB  1 
If << 1 then above equation reduces to S = (1 + β )   =1
RE  1+ β 

Practically
RB
RE
R
≠ 0 But to have better stability factor ‘S’, we have to keep ration B as
RE ir a
e
Jn
small as possible.

t
tu
m
at
Stability factor ‘S’ for voltage divider bias (or) self bias is less as compared to other biasing

a
er
ia
circuits studied. So, this circuit is most commonly used.

ls.
co
m
Stability factor (S’):

Stability factor S’ is given by

u M S'=
∂IC
∂VBE
ICO, β constant

It is the variation of IC with VBE when ICO and β are considered constant.

IC = β I B + (1 + β ) ICO
n t
J
We know that,

I − (1 + β ) ICO
IB = C
β
and V = I B RB + VBE + I B + I C RE
Th ( )
VBE = V − RE + RB I B − RE IC
Th ( )
By substituting IB in the above equation, we get
 I − (1 + β ) ICO 
VBE = VTh − RE + RB  C
 β
(
 − RE IC )
 

=V −
( RE + RB ) IC + ( RE + RB ) (1 + β ) ICO − R
Th β β E IC

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___________________________________________________________________________

⇒ VBE = V − 
(1 + β ) R + R  I
E (
B  C + RE + RB (1 + β ) ICO )
Th β β
Differentiating the above equation w.r.t VBE with ICO and β constant, we get

 R + (1 + β ) RE  ∂I C
1= 0− B  +0
 β  ∂VBE
∂IC −β
⇒ =
∂VBE RB + (1 + β ) RE

−β
∴S ' =

Stability Factor S’’:

RB + (1 + β ) RE

∂IC
o m
Stability factor S’’ is given by S '' =
∂β
. c
ICO, VBE constant

VBE = VTh −
 B +
 (
ls )
E  C  RE + RB (1 + β ) 
 R + (1 + β ) R  I 

ir a
We have, I
β  β  CO
 
 R + (1 + β ) R  I
=V −  B E  C +V '

e
Jn
Th β

t
tu
m
( )
 R + R (1 + β ) 

at
( )
a
er
V '= 
E B I = RE + RB ICO (Q β >> 1)

ia
Where

ls.
 β  CO

co
 

m
Therefore, we write the above equation in terms of IC, we get

M
β VTh + V '− VBE 

u
n t
Differentiating above equation w.r.t. taking V’ independent of β, we get,
IC =
RB + RE (1 + β )

∂I C
∂β J=
Th
 R + R (1 + β )
 B E 
(
RB + RE (1 + β ) V + V '− VBE − β V + V '− VBE  RE
 Th
2
 )

Multiplying numerator and denominator by (1+β) we get,

∂IC (1 + β ) ( RB + RE ) (VTh + V '− VBE )

=
∂β (1 + β )  RB + RE (1 + β )  RB + RE (1 + β )

=
(
S VTh + V '− VBE )  (
(1 + β ) RB + RE  )
Q S = 
(1 + β )  RB + RE (1 + β )   R + R (1 + β ) 
 B E 
Multiplying numerator and denominator by β, we get

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∂I C
=
(
β VTh + V '− VBE S ) =
IC S
∂β β (1 + β )  RB + RE (1 + β ) β (1 + β )


Q I =
β VTh + V '− VBE ( )  ∴S " =
∂IC
=
IC S
where S=
1+ β
.
 C  R + R (1 + β )   ∂β β (1 + β )  R 
  B E   1+ β  E 
R +R 
 E B
Problems:

5. For the circuit shown in figure, determine the value of IC and VCE. Assume VBE=0.7V and
β=100
5 × 103

m
R1
Solution: VB = V = × 10 = 3.33V
R1 + R2 CC 10 × 103 + 5 × 103

VE = VB − VBE = 3.33 − 0.7 = 2.63V

V
We know that

2.63V
. c o
ls
and I = E = = 5.26mA
E R 500
E
2.63 × 10−3

ir a
I
We know that I = E = = 52.08µ A
B 1+ β 101
and IC=βIB=100x52.08x10-6 = 5.208mA

e
Jn
Applying KVL to the collector circuit we get

t
tu
m
VCC − IC RC − VCE − I E RE = 0

at
a
er
ia
ls.
co
⇒ VCE = VCC − I C RC − I E RE =10-5.208x10-3x1x103- 5.26x10-3x500

m
⇒V
CE
= 2.162V

u M
6. In the circuit shown, if IC=2mA and VCE=3V, Calculate R1 and R3.

n t
J
Solution:

From collector circuit,

15 = ICR3 + VCE + IER4

= 2x10-3xR3+3+(1+β)IBx500

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___________________________________________________________________________

2 × 10−3
⇒ 12 = 2 × 10−3 × R3 + 101 × × 500
100
⇒ R = 5.495k Ω
3
R2
From Base circuit, V2 = V
R1 + R2 CC

10 × 10−3
⇒ V2 = × 15
R1 + 10 × 10−3

But, V2 = VBE + VE = 0.6 + I E R4 = 0.6 + (1 + β ) I B R4

⇒ V2 = 0.6 + 101 ×
2 × 10−3
100
× 500 = 1.61V

o m
∴1.61 =
1 × 10−3
× 15
. c
ls
R1 + 10 × 10−3

⇒ R1 + 10 × 10−3 = 93.17 × 103

⇒ R1 = 83.17k Ω
ir a
e
7. For the circuit shown below, calculate VE, IE, IC and VC. Assume VBE=0.7V.

Jn
t
tu
m
Solution:

at
a
er
ia
From Base circuit,

ls.
co
m
4 = VBE + VE = 0.7 + VE

⇒ VE = 3.3V

u M
I E RE = 3.3

⇒ IE =
n t 3.3
= 1mA

But IE=IB+IC = (1+β)IB

Assume β=100,
J 3.3 ×103

1mA
⇒ IB = = 0.0099mA
101
IC=βIB = 100x0.0099mA = 0.99mA

From Collector circuit,

VC = 10 − IC RC = 100 − 0.99mA × 4.7 K Ω = 5.347V

Bias Compensation Techniques:

The biasing circuits provide stability of operating point in case variations in the transistor
parameters such as ICO, VBE and β.

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The stabilization techniques refer to the use of resistive biasing circuits which permit IB to
vary so as to keep IC relatively constant.

On the other hand, compensation techniques refer to the use of temperature sensitive
devices such as diodes, transistors, thermistors, sensistors etc., to compensate for the variation in
currents. Sometimes for excellent bias and thermal stabilization, both stabilization as well as
compensation techniques are used.

The following are some compensation techniques:

1) Diode compensation for instability due to VBE variation.
2) Diode compensation for instability due to ICO variation.
3) Thermistor compensation.
4) Sensistor compensation.

1) Diode compensation for instability due to VBE variation:

For germanium transistor, changes in ICO with temperature contribute more serious

o m
c
problem than for silicon transistor.

On the other hand, in a silicon transistor, the changes of VBE with temperature possesses
significantly to the changes in IC.

A diode may be used as compensation element for variation in VBE (or) ICO.
ls .
The figure below shows the circuit of self bias stabilization technique with a diode
compensation for VBE. The Thevenin’s equivalent circuit is shown in figure.
ir a
e
Jn
t
tu
m
at
a
er
ia
ls.
co
m
u M
n t
J
Fig. Self bias with stabilization and compensation Fig. Thevenin’s equivalent circuit

The diode D used here is of the same material and type as the transistor. Hence the
voltage VD across the diode has same temperature coefficient (-2.5mV/oC) as VBE of the transistor.
The diode D is forward biased by the source VDD and resistor RD.

Applying KVL to the base circuit, we get

−V + I B R + VBE + I E RE − VD = 0
Th Th
⇒ V − VBE + VD = I B R + RE I E + I C
Th Th ( ) …………………. (1)

But IC = β I B + (1 + β ) ICO ………………... (2)

From equation (1), we get

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V − VBE + VD = RE IC + R + RE I B
Th Th ( )
Substituting the value of IB from equation (2), we get

 I − (1 + β ) ICO 
VTh − VBE + VD = RE IC + RTh + RE  C
 β
 ( )
 
( ) ( )
⇒ β V − VBE + VD = β RE IC + R + RE IC − (1 + β ) ICO R + RE
Th Th Th ( )
⇒ β (V − VBE + VD ) = (1 + β ) ICO ( R + RE ) = IC ( R + (1 + β ) RE )
Th Th Th
β (VTh − VBE + VD ) = (1 + β ) ICO ( RTh + RE )
⇒I = …………… (3)
C RTh + (1 + β ) RE

Since variation in VBE with temperature is the same as the variation in VD with temperature,

o m
c
hence the quantity (VBE-VD) remains constant in equation (3). So the current IC remains constant

.
in spite of the variation in VBE.

ls
2) Diode compensation for instability due to ICO variation:

Consider the transistor amplifier circuit with diode D used for compensation of variation in

ir a
ICO. The diode D and the transistor are of the same type and same material.

e
Jn
t
tu
m
at
a
er
ia
ls.
co
m
u M
n t
J
In this circuit diode is kept in reverse biased condition.

The reverse saturation current IO of the diode will increase with temperature at the same as
the transistor collector saturation current ICO.

V − VBE VCC
From figure I = CC ≈ = constant.
R R
The diode D is reverse biased by VBE. So the current through D is the reverse saturation
current IO. Now base current IB=I-IO

But IC = β I B + (1 + β ) ICO

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⇒ IC = β I − IO + (1 + β ) I CO ( )
If β>>1, IC ≈ β I − β IO + β ICO
In the above expression, I is almost constant and if IO of diode D and ICO of transistor track
each other over the operating temperature range, then IC remains constant.

3) Thermistor Compensation:

This method of transistor compensation uses temperature sensitive resistive elements,

thermistor rather than diodes (or) transistors:

It has a negative temperature coefficient, its resistance decreases exponentially with

increasing temperature as shown in the figure.

Slope of this curve =

∂RT
∂T

o m
∂RT
∂T
. c
is the temperature coefficient for thermistor, and

ls
the slope is negative. So we can say that thermistor
has negative temperature coefficient of resistance.

ir a
e
Jn
t
tu
Figure below shows thermistor compensation technique.

m
at
a
er
As shown in figure, R2 is replaced by thermistor RT in self bias circuit.

ia
ls.
co
m
u M
n t
J
Fig. Thermistor compensation technique.

With increase in temperature, RT decreases. Hence voltage drop across it also decreases.
This voltage drop is nothing but the voltage at the base with respect to ground. Hence, VBE
decreases which reduces IB. This behavior will tend to offset the increase in collector current with
temperature.
We know, IC = β I B + (1 + β ) ICO

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In this equation, there is increase in ICBO and decreases in IB which keeps IC almost
constant.
Consider another thermistor compensation technique shown in figure. Here, thermistor is
connected between emitter and VCC to minimize the increase in collector current due to change in
ICO, VBE (or) β with temperature.

o m
. c
ls
ir a
e
Fig. Thermistor compensation technique.

Jn
t
tu
m
IC increase with temperature and RT decreases with increase in temperature. Therefore,

at
a
er
current flowing through RE increases, which increases the voltage drop across it. Emitter to Base

ia
junction is forward biased. But due to increase in voltage drop across RE, emitter is made more

ls.
positive, which reduces the forward bias voltage VBE. Hence, base current reduces.

co
IC = β I B + (1 + β ) ICO

m
M
IC is given by,
As ICBO increases with temperature, IB decreases and hence IC remain fairly constant.

4) Sensistor Compensation:

t u
with increasing temperature.
J n
This method of transistor compensation uses sensistor, which is temperature sensitive
resistive element.
Sensistor has a positive temperature coefficient, i.e., its resistance increases exponentially

∂RT
Slope of this curve =
∂T
∂RT
is the temperature coefficient for sensistor, and the
∂T
slope is positive.

So we can say that sensistor has positive temperature

coefficient of resistance.

As shown in figure R1 is replaced by sensistor RT in self bias

circuit.

As temperature increases, RT increases which decreases the current flowing through it. Hence
current through R2 decreases which reduces the voltage drop across it.

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o m
. c
ls
Fig. Sensistor compensation technique.

As voltage drop across R2 decreases, IB decreases. It means, when ICBO increases with
increase in temperature, IB reduces due to variation in VBE, maintaining IC fairly constant.
ir a
e
Jn
t
tu
Thermal Runaway:

m
at
a
er
The collector current for the CE circuit is given by

ia
IC = β I B + (1 + β ) ICO

ls.
co
m
The three variables in the equation, β, IB and ICO increase with rise in temperature. In
particular, the reverse saturation current (or) leakage current ICO changes greatly with
temperature. Specifically, it doubles for every 10oC rise in temperature.

u M
n t
The collector current IC causes the collector-base junction temperature to rise which, in
turn, increase ICO, as a result IC increase still further, which will further rise the temperature at the
collector-base junction. This process is cumulative and it is referred to as self heating.

transistor. This situation is called “Thermal Runaway” of the transistor.

Thermal Resistance:
Transistor is a temperature dependent device.
J
The excess heat produced at the collector-base junction may even burn and destroy the

In order to keep the temperature within the limits, the heat generated must be dissipated
to the surroundings.
Most of the heat within the transistor is produced at the collector junction.
If the temperature exceeds the permissible limit, the junction is destroyed.
For Silicon transistor, the temperature is in the range 150oC to 225oC.
For Germanium, it is between 60oC to 100oC.
Let TAoC be the ambient temperature i.e., the temperature of surroundings air around
transistor and TjoC, the temperature of collector-base junction of the transistor.
Let PD be the power in watt dissipated at the collector junction.

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The steady state temperature rise at the collector junction is proportional to the power
dissipated at the junction. It is given by
∂T = T j − TA = θ PD Where θ = constant of proportionality

The θ, which is constant of proportionality, is referred to as thermal resistance.

T j − TA
θ=
PD
The unit of θ, the thermal resistance, is oC/watt.
The typical values of θ for various transistors vary from 0.2oC/watt for a high power
transistor to 1000 oC/watt for a low power transistor.
Heat Sink:

m
As power transistors handle large currents, they always heat up during operation.
The metal sheet that helps to dissipate the additional heat from the transistor is known as
heat sink. The heat sink avoids the undesirable thermal effect such as thermal runaway.
The ability of heat sink depends on the material used, volume, area, shape, constant
between case and sink and movement of air around the sink.

. c o
ls
The condition for Thermal Stability:

As we know, the thermal runaway may even burn and destroy the transistor, it is necessary

ir a
to avoid thermal runaway.
The required condition to avoid thermal runaway is that the rate at which heat is released
at the collector junction must not exceed the rate at which the heat can be dissipated. It is given
∂PC ∂P
< D

e
Jn
by ………………(1)
∂T j ∂T j

t
tu
m
at
But we know, from thermal resistance

a
er
ia
T j − TA = θ PD …………….. (2)

ls.
co
m
Differentiating equation (2) w.r.t. Tj we get

1=θ
∂PD
∂T j

u M
⇒
∂PD
∂T j
=

n t θ
1
………………. (3)

∴
∂PD
∂T j
J
Substituting equation (3) in equation (1), we get

<
θ
1
……………… (4)

This condition must be satisfied to prevent thermal runaway.

By proper design of biasing circuit it is possible to ensure that the transistor cannot
runaway below a specified ambient temperature (or) even under any condition.
Let us consider voltage divider bias circuit for the analysis.

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o m
. c
ls
From fig., PC = heat generated at the collector junction.
ir a
Fig. Voltage divider bias circuit.

e
= DC power input to the circuit – the power lost as I2R

Jn
t
tu
in RC and RE.

m
IC ≅ I E we get

at
If we consider

a
er
( )

ia
PC = VCC IC − IC2 R +R

ls.
……………….. (6)

co
C E

m
M
Differentiating equation (6) w.r.t IC we get
∂PC
= VCC − 2 IC RC + RE ( )
From equation (4)
∂IC

t u ……………….. (7)

In the above equation

∂PC ∂IC 1
. <
∂IC ∂T j θ

J n ∂IC
can be written as
……………….. (8)

∂T j
∂IC ∂ICO ∂VBE ∂β
=S +S' + S" ………………. (9)
∂T j ∂T j ∂T j ∂T j
Since junction temperature affects collector current by affecting ICO, VBE, and β. But as we
are doing analysis for thermal runaway the affect of ICO dominates. Thus we can write
∂IC ∂ICO
=S …………………….. (10)
∂T j ∂T j
As the reverse saturation current for both Silicon and Germanium increases about 7
percent per oC, we can write

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∂ICO
= 0.07 ICO ……………………. (11)
∂T j
Substituting equation (11) in equation (10), we get
∂IC
= S × 0.07 ICO ……………………. (12)
∂T j
Substituting equations (7) and (12) in equation (8), we get

V
 CC
− 2 I R
C C + R  ( S ) 0.07 I
E  CO <
1
θ
( ) ( ) ………………….. (13)

As S, ICO and θ are positive; we see that the inequality in equation (13) is always satisfied
provided that the quantity in the square bracket is negative.
∴ VCC < 2 IC RC + RE ( )
V
⇒ CC < IC RC + RE ( ) ……………….. (14)
o m
.s c
2
Applying KVL to the collector circuit of voltage divider bias circuit we get,
VCE = VCC − IC RC + RE ( ) (Q IC ≅ I E )
(
∴ IC RC + RE = VCC − VCE )
a l
Substituting the value of

V
(
IC RC + RE in equation (14), we get )
ir
⇒ CC = VCC − VCE

e
Jn
t
tu
2

m
at
a
er
V

ia
⇒ VCC < VCE − CC

ls.
co
2

m
V
⇒ VCE < CC
2

u M
Thus if
V
VCE < CC , the stability is ensured.
2
n t
J

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205
VARDHAMAN COLLEGE OF ENGINEERING, SHAMSHABAD, HYDERABAD

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