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Analysis and Evaluation of DC-Link Capacitors for High-Power-Density

Electric Vehicle Drive Systems

Article  in  IEEE Transactions on Vehicular Technology · September 2012

DOI: 10.1109/TVT.2012.2206082

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 1

Analysis and Evaluation of DC-Link Capacitors for High Power

Density Electric Vehicle Drive Systems

H. Wen1, W. Xiao1, and Xuhui Wen2, P.R. Armstrong1,3

1
Electrical Power Engineering Program, Masdar Institute of Science and Technology, Abu

Dhabi, United Arab Emirates (Email: hwen@masdar.ac.ae).

2
Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, China (e-mail:

wxh@mail.iee.ac.cn)
3
Massachusetts Institute of Technology, Cambridge, MA 02139, USA

Abstract - In electric vehicle (EV) inverter systems, dc-link capacitors, which are bulky,

heavy and susceptible to high temperature, can become a critical obstacle to high power

density. This paper focuses on comprehensive analysis and comparative evaluation for dc-link

capacitor applications to minimize the volume and capacitance. The models of equivalent series

resistance (ESR) that are valid over a range of frequency and operating temperature are derived

and experimentally validated. The RMS value and frequency spectrum of the capacitor current

are analyzed with regards to various modulation strategies and operating conditions, over

practical ranges of load power factor and modulation index in EV drive systems. The modeling

and analysis also consider the self-heating process and resulting core temperature of the dc-link

capacitors, which impacts the lifetime of EV inverters. Based on an 80kW permanent-magnet

(PM) motor drive system, the application of electrolytic capacitors and film capacitors has been

evaluated by both simulation and experimental tests. The inverter power density is improved

from 2.99 kW/L to 13.3 kW/L without sacrificing system performance in terms of power loss,

core temperature, and lifetime.

Index Terms - Electric Vehicle (EV); Power Density; Dc-Link Capacitor; Ripple Current

Stress; Equivalent Series Resistance (ESR); Parasitic Inductance.

 2

I. INTRODUCTION

Electric Vehicle (EV) research has intensified recently due to the global warming and other

environmental concerns surrounding the existing petroleum-based transportation infrastructure

[1-2]. In EVs, the most common power interface between batteries and traction motors is the

voltage source inverter (VSI), as shown in Fig. 1. Currently, EV inverter research is mainly

concerned with aspects of compact design [3-5], low cost [6-7], high reliability [8-10] and long

lifetime [11]. Several topologies and optimization strategies have been investigated to meet

multiple objectives under the stringent operation requirements of EV inverters [12-15]. For

example, overload conditions of 2-2.5 times rated capacity can last 1-3 minutes and power

electronic components are expected to tolerate inlet coolant temperatures up to 105ºC [16].

Other design requirements include high efficiency and high power density [17].

ibat iinv ic1 ic 3 ic 5

id 1
icap S1 S3 S5
iq1 ia
ib Motor
Vin Cdc ic
ic 4 ic 6 ic 2

S4 S6 S2

Fig. 1 Schematic of a typical electric vehicle drive system including a battery bank, VSI,
traction motor, and dc-link capacitors.

Many efforts have been directed toward improving the power density, which is quantified as

the power density by weight (PDW) and the power density by volume (PDV). For example, the

FreedomCAR and Vehicle Technologies (FCVT) group is a U.S. national office of energy

efficiency and renewable energy program to develop energy efficient and environmentally

friendly highway transportation systems[18-19]. The FCVT program reports that the PDW and

the PDV of EV inverters have been increased from 4.08 to 10.04 kW/kg and from 2.03 to 8.82

kW/L, respectively [3]. Further improvement is expected to achieve more than 14.1 kW/L in
 3

PDV of EV inverters according to the FCVT technology roadmap [18]. A corresponding

technology roadmap has been defined in China in terms of cost, efficiency, and power density

[20]. In an example of high performance possibilities, the latest SiC JFETs-based inverter

shows a potential 51 kW/L PDV while achieving 97.8% efficiency [21]. Table I summarizes

main technical parameters and objectives corresponding to the road maps and timelines of EV

drive systems developed by U.S. and China.

TABLE I
SUMMARY OF TECHNICAL PARAMETERS ROAD MAPS OF ELECTRIC VEHICLE DRIVE SYSTEMS
Sic JFET-based
FreedomCar FreedomCar Chinese Goals FreedomCar FreedomCar
Subsystem Parameters Converter
phase I [3] phase II [3] in 2006 [22] Goals in 2006 [18] Goals in 2020*[19]
[21, 23]
PDW (kW/kg) 4.08 10.04 2~5 >12 >14.1 >51
PDV (kW/L) 2.03 8.82 ~ >12 >13.4 >51
Inverter
Efficiency
80~88% 80~88% 90~92% 92% 94% 97.8%
@maximum load

Motor types IM IM PM, IM and SRM PM PM PM

PDW (kW/kg) 0.5~1 0.5~1 0.5~1 >1.2 >1.6 >1,3
Motor
PDV (kW/L) 1.01~ 1.01~ 1.01~ >3.7 >5.7 >5
Efficiency 90 90 92~95% >93% >94% >93%
Efficiency 72~84% 76~86% 90~92% 92% 94% >92%
Cooling mode Forced air Liquid Liquid Liquid Liquid or air Natural air
System Ambient Temp. -25~50 °C -25~50 °C ~70 °C ~105 °C 105 °C 120 °C
Cost($/kW) - - 70 <105 <62.7 -
Total Mileage (km) - - 241402 (15 yrs) 241402 (15 yrs) 241402 (15 yrs) 241402 (15 yrs)
* Based on a maximum coolant or air temperature of 105°C

In EV inverter systems, the dc-link capacitors are essential to provide reactive power,

attenuate ripple current, reduce the emission of electro-magnetic interference, and suppress

surge voltage caused by leakage inductance and switching operations [24]. DC-link capacitors

are bulky, heavy and expensive [25]. One typical design comprises five electrolytic capacitors,

which are connected in parallel with the battery bank to supply a 80 kW motor drive system

[26]. Each capacitor is 9.4 cm in diameter and 14.6 cm in height. Since the five dc-link

capacitors occupy more than 40% of the volume, the achievable PDV is limited to 2.99 kW/L.

Furthermore, the height of dc-link capacitors is higher than most IGBT modules and requires a

crooked busbar to make the connection. Thus, the induced parasitic inductance is more than
 4

100 nH and causes voltage spikes, which are recognized as the main factor in the failure of

power electronic devices. For all of reasons mentioned above, an optimum design of dc-link

capacitor is critical to achieve the goals shown in Table I. Some basic requirements for

choosing and comparing different capacitors for EV inverter applications include the following.

• The dc-link capacitors should be able to handle the ripple current under all VSI operating

conditions for EV applications.

• The ripple voltage across the dc bus should be limited to 10% of the rated voltage for all

expected load conditions. Low inductance capacitors are preferred to avoid overvoltage failure

of IGBTs.

• The AC ripple current should never exceed 10% of the rated battery current to avoid

significant degradation on the lifetime of battery.

• Hot spot temperature should be below 105°C under maximum ambient temperature for

any expected load condition.

Ripple current is usually a main consideration in sizing and selecting dc-link capacitors.

Approaches have been proposed to reduce the capacitor current ripple and minimize the

capacitor size without violating other constraints by coordinating the modulation strategies

between the active rectifier and the PWM inverter stages [27-28]. The coordinating modulation

method has been shown to cancel most of the dc-link capacitor ripple current in Hybrid EV

DC-DC converters and inverter system applications [29]. However, the implementation of

coordinating control strategies is infeasible for the EV drive system shown in Fig. 1, where the

dc-link capacitors are connected directly in parallel with the battery bank without any power

stages in between [30-31]. For the EV drive system shown in Fig. 1, research mainly focuses on

the ripple current analysis and current harmonics calculation [31-34]. Most analysis has been

based on an ideal capacitor model, which cannot accurately predict power loss and capacitor

lifetime. The ideal capacitor model does not properly account for the effects of variation of load

power factor and modulation index in a practical EV system. Models that include equivalent

series resistances (ESR) and show the effects of temperature and frequency are investigated in
 5

[35-37]. Their modeling approach concentrates on only the characteristic analysis for

electrolytic capacitors. A systematic comprehensive evaluation of the benefits and drawbacks

of film capacitors for EV inverter applications has not been reported. As outlined above, we

conclude that, the base requirements, system constraints, and performance indices have not

been fully and systematically addressed. In EV inverter systems, the capacitor ripple current

consists of various frequency components corresponding to different pulse width modulation

(PWM) strategies. Therefore, the frequency spectrum analysis of the capacitor current and an

accurate model of ESR with consideration of the temperature and frequency response are

important to properly account for the self-heating process of dc-link capacitors. Further, the

electro-thermal coupling dynamics must be evaluated to estimate the true core temperature of

the dc-link capacitors, which is critical to predict capacitor lifetime.

This paper focuses on analysis and evaluation of dc-link capacitors in EV inverter systems

to improve the power density. The analysis starts with ESR models of both electrolytic and film

capacitors. The derived mathematical models are verified by experiments. The voltage and

current stresses are analyzed with respect to three common modulation strategies including

sinusoidal PWM (SPWM), space vector modulation (SVM) and third harmonics injection (THI).

The frequency spectrum of the capacitor ripple current is also investigated corresponding to

these modulation strategies over the practical ranges of load power factor, and the modulation

index. Based on the above analysis, the self-heating process and the resulting core temperature

are modeled and analyzed. Two design schemes using electrolytic and film capacitors are

compared through simulation and experiments in terms of power loss, core temperature,

lifetime and battery current harmonics. The proposed design has been tested in an 80kW

permanent-magnet (PM) motor drive system.

II. CAPACITOR CHARACTERISTICS

This section investigates the ESR models of electrolytic and film capacitors and shows the

characteristics of frequency and temperature.

 6

A. Electrolytic capacitor

Electrolytic capacitors are commonly used as the dc-link capacitors due to their large

capacitance per unit volume. The ESR model of an electrolytic capacitor is illustrated in Fig. 2

[38], where the resistance R0 accounts for the sum of resistances of foil, tabs, and terminals, R1

symbolizes the electrolyte resistance, C1 represents the terminal capacitance, and the parallel

combination of R2 and C2 presents the dielectric dynamics. The ESR of the capacitor in terms of

the frequency responses is derived accordingly.

R2
ESRe = R1 + R0 + (1)
1 + ( 2π fR2C2 )
2

For electrolytic capacitors, the rise of temperature causes a decrease in ESR because the

resistance R1 is reduced by the increased conductivity of electrolyte. The effect of temperature

on R1 is described as by (2) [35, 39].

Tbase −T
R1 = R1b e F (2)

where R1b represents the value of R1 at the base temperature Tbase (27 oC), T is the capacitor core

temperature (oC), and F is a temperature sensitivity factor [40].

C1

C2 R2

R1

R0

Fig. 2 ESR model of an electrolytic capacitor.

B. Film capacitor

A R-L-C series equivalent circuit that includes the equivalent inductor Lc, capacitor Cc and

resistor Rc is used to model film capacitors. When the operating frequency is higher than 1 kHz,

the ESR value can be modeled as a function of frequency based on [41].

 7

ESR ( f ) = ( Rs − As ) + K ( f ) ⋅ As (3)

Where Rs is the base resistance, f represents the frequency, and As is a given value depending on

the capacitor size. K(f) is the predefined function showing the effect of frequency, which is

usually given by plots in manufacturer datasheets. In this analysis, it is mathematically

expressed as a cubic polynomial function, as shown in (4), of which the coefficients k0-3 can be

extracted by using least square curve fitting.

K ( f ) = k3 ⋅ f 3 + k2 ⋅ f 2 + k1 ⋅ f + k0 (4)

In contrast with the electrolytic capacitor, the ESR value of film capacitors increases with

the frequency. Its temperature-sensitivity is less than that of electrolytic capacitors [41] because

the ESR of film capacitors results mainly from the tabs and contact resistances, but not from the

electrolyte [42].

C. Ripple current multiplier

Since the ESR values of electrolytic and film capacitors show frequency-dependent

characteristics, a ripple current multiplier Mf is defined as in (5) to address the ripple current

that capacitors can absorb at a given frequency.

If ESR100
=
M f = (5)
I100 ESR f

where I100 and ESR100 are defined as the rated ripple current and the ESR value at 100Hz, which

are usually given by manufacturers. The If and ESRf represents the ripple current and the ESR

value at a specific frequency, respectively. The electrolytic capacitors show the capability to

absorb more high-frequency ripple current than the low-frequency component. On the contrary,

the film capacitors usually handle less high-frequency ripple current because the Mf value is

reduced by the growing value of ESRf.

 8

III. CAPACITOR RIPPLE CURRENT AND VOLTAGE

The battery current (ibat) is the sum of capacitor current (icap) and dc-link current (iinv), as

shown in Fig. 1. These current waveforms are greatly affected by the load power factor cos φ ,

which determines the amount of current flow into IGBT devices or the free-wheeling diodes of

the VSI. As a result, these practical EV operating conditions, load power factor and modulation

index, must be considered in evaluating the capacitor ripple current and voltage.

A. Capacitor ripple current analysis

Based on the formation of the inverter input current modulation by SVM [34], the RMS

value of capacitor ripple current Icap can be expressed by (6).

M 
=I cap I N 4 3 ( 4cos 2φ + 6 ) − 9π ⋅ M ⋅ ( cos 2φ + 1)  (6)
32π 

where, M is the modulation index, IN is the output phase current amplitude, and φ is the phase

delay of output current with respect to the voltage.

Fig. 3 illustrates the ratio of Icap over IN corresponding to the modulation index M and the

power factor cosφ . The modulation index corresponding to the maximum RMS value of

capacitor ripple current is denoted as MIcap(max), which varies from the modulation strategies.

The SPWM and SVM share the same expression as (7), and the expression for THI is given by

(8).

 4 3(2cos 2φ + 3) 
M Icap (max) = min  ,1 (7)
 9π ( cos 2φ + 1) 

 4 3(2cos 2φ + 3) 
M Icap (max) = min  ,1.15 (8)
 9π ( cos 2φ + 1) 
 9

0.5

0.4

0.3
cap N
THI
/I

0.2
I

SPWM & SVM

0.1

0
1
0.8
0.6 1 1.15
0.8
0.4 0.6
0.2 0.4
0.2
cos φ 0 0 M

Fig. 3 Ratio of Icap over Il corresponding to modulation index M and power factor cosφ .

Shown in Fig. 3, the blue line illustrates the maximum RMS value of capacitor ripple current

corresponding to the THI modulation strategy, of which the modulation index ranges from 0 to

1.15. The black line indicates the upper bound (M = 1) of MIcap(max) with respect to SPWM and

SVM methods. In order to address typical operation conditions, the distribution of MIcap(max) in

relation to the load power factor is plotted in a two-dimensional space, which is shown in Fig.

4. When the cosφ is lower than a certain value of the power factor φth , the ratio increases with

M and reaches to the maximum at the upper bound of modulation range. When cosφ is larger

than φth , MIcap(max) is located in the middle of the modulation range, no longer at the upper

bound. It is noticeable that THI shows a different φth value from SPWM and SVM since the

modulation index is up to 1.15. In the case of THI, the threshold value of the power factor φth is

0.43, while the corresponding threshold value of the power factor φth is 0.49 in the cases of

SPWM and SVM. Based on the above analysis, five typical operating conditions symbolized as

P1-P5 are defined and demonstrated in Table II.

 10

TABLE II
PREDEFINED OPERATING CONDITIONS P1-P5
Operating condition Modulation index M Load power factor cosφ
P1 1.15 0.43
P2 1 0.49
P3 1.15 0.23
P4 1 0.23
P5 0.625 0.954

1.2 P1 (0.43,1.15)
P3 (0.23,1,15) THI
1.1
SPWM&SVM
P2 (0.49,1)
1 P4 (0.23,1)
Icap(max)

0.9

0.8
M

0.7
P5 (0.954, 0.625)
0.6

0.5
0 0.2 0.4 0.6 0.8 1
cos φ

Fig. 4 The distribution of MIcap(max) corresponding to power factor cosφ .

The maximum current stress on the dc-link capacitor can be estimated by using (6) for

different load conditions. In the practical EV drive system, the 80kW permanent-magnet (PM)

motor is supplied by a 312V battery pack. Thus, the capacitor maximum current stress is

calculated as 105A, which is used as a base parameter for capacitor evaluation. In practice, the

ripple current varies with operating conditions.

B. Capacitor voltage ripple analysis

Table III summarizes the dc-link capacitor voltage ripple RMS expressions (in per unit) for

different modulation strategies [43]. The base value is given by (9), where Cd is the dc-link

capacitance and f1 is the inverter switching frequency.

IN
Vb _ volrip = (9)
Cd f1
 11

TABLE III
DC-LINK CAPACITOR VOLTAGE RIPPLE EXPRESSIONS FOR SPWM, SVM AND THI

Modulation Strategies Voltage ripple of dc-link capacitor (p.u.) [43]

0.5
M  96 3 9  8 3 
SPWM  6 − M + M 2  cos 2 φ + M
16  5π 2  5π 
0.5
M  96 3 108π − 81 3 2  8 3 
SVM  6 − M+ M  cos 2 φ + M
16  5π 16π  5π 
0.5
M  96 3 63 2  8 3 
THI  6 − M+ M  cos 2 φ + M
16  5π 16  5π 

Fig. 5 illustrates the characteristic of dc-link ripple voltage in per unit with regard to the

modulation index M, the power factor cosφ and three modulation strategies. When the load

power factor is zero, the ripple voltage levels are the same among the three modulation

strategies of SPWM, SVM and THI. When the power factor is non-zero, the SPWM shows the

largest voltage ripple, the THI gives the lowest voltage ripple, and the SVM demonstrates

relatively low voltage ripple.

8
(p.u. %)

6
4
2
cap
v

0
0
SPWM
0.2
SVM
0.4 THI
0.6
0.4 0.2 0
0.8
1 0.8 0.6
cos φ 1.151 M

Fig. 5 Characteristics of the voltage ripple across the dc link as a function of modulation index
M, power factor cosφ and modulation strategies including SPWM, SVM, and THI.

C. Frequency Spectrum of Capacitor Ripple Current

Fast Fourier transforms (FFT) used to analyze the frequency spectrum of the capacitor

current icap for different load power factor, modulation methods, and modulation indices are

illustrated in Fig. 6. The comparison of the spectrum distribution is summarized in Table IV to

 12

demonstrate the interactions of modulation strategies and the predefined operating conditions.

The current spectrum contains significant switching frequency f1 multiples and their sidebands

(sbs). At low cosφ , switching frequency sidebands are usually the biggest harmonic

components and the current spectrum is evenly distributed along f1 sbs, 3f1 sbs and 2f1. At high

cosφ (larger than 0.49 for SVM), 2f1 is the dominant component and its amplitude increases

with cosφ . For instance, the largest harmonic component is nearly 21% of output current

amplitude at cosφ =0.49, while the corresponding harmonic component reaches as high as

48.8% at cosφ =0.954. Moreover, the impact of modulation strategy on current spectrum

distribution is obvious at high cosφ and the major harmonics for SVM will extend to higher

frequency such as 6f1. Besides, since the ESR characteristic of the dc-link capacitor is highly

affected by the frequency for both electrolytic and film capacitors. The FFT results shown in

Fig. 6 and Table IV provide the fundamental information to size the dc-link capacitors.

60 60

50 50
Mag (% of IN)

Mag (% of IN)

40 40

30 30

20 20

10 10

0 0
0 2 4 6 8 10 0 2 4 6 8 10
Frequency (kHz) 4 Frequency (kHz) 4
x 10 x 10

(a) P5 (M=0.625, cosφ =0.954), SVM (b) P5 (M=0.625, cosφ =0.954), SPWM

60 60

50 50
Mag (% of IN)

Mag (% of IN)

40 40

30 30

20 20

10 10

0 0
0 2 4 6 8 10 0 2 4 6 8 10
Frequency (kHz) 4 Frequency (kHz) 4
x 10 x 10

(c) P5 (M=0.625, cosφ =0.954), THI (d) P1 (M=1.15, cosφ =0.43), THI
 13

60 60

50 50
Mag (% of IN)

Mag (% of IN)
40 40

30 30

20 20

10 10

0 0
0 2 4 6 8 10 0 2 4 6 8 10
Frequency (kHz) 4 Frequency (kHz) 4
x 10 x 10

(e) P2 (M=1, cosφ =0.49), SVM (f) P3 (M=1.15, cosφ =0.23), THI

60 60

50 50
Mag (% of IN)

Mag (% of IN)
40 40

30 30

20 20

10 10

0 0
0 2 4 6 8 10 0 2 4 6 8 10
Frequency (kHz) 4 Frequency (kHz) 4
x 10 x 10

(g) P4 (M=1, cosφ =0.23), SVM (h) P4 (M=1, cosφ =0.23), SPWM

Fig. 6 Frequency spectra of the capacitor current based on the modulation strategies and the
predefined operating conditions including the load power factor and modulation index.

TABLE IV
COMPARISON OF SPECTRAL DISTRIBUTION FOR THE THREE MODULATION STRATEGIES AND
FIVE OPERATING CONDITIONS

Operating Major three components sorted by magnitude (% of IN)

Modulation
condition frequency magnitude frequency magnitude frequency magnitude
P4 SPWM 3f1 sbs 19.2 f1 sbs 17.2 2f1 10.2
P4 SVM f1 sbs 16.6 3f1 sbs 15.9 2f1 11.7
P1 THI f1 sbs 20.2 3f1 sbs 12.3 2f1 7.3
P1 THI f1 sbs 19.7 2f1 13.6 3f1 sbs 11.4
P2 SPWM 2f1 21.7 f1 sbs 15.4 3f1 sbs 14.7
P2 SVM 2f1 21.7 3f1 sbs 17.4 f1 sbs 17
P5 SPWM 2f1 49.2 4f1 13.1 3f1 sbs 11.1
P5 SVM 2f1 52 4f1 14 6f1 9.9
P5 THI 2f1 48.8 3f1 sbs 9.9 4f1 8.7
 14

IV. PERFORMANCE INDICES

Based on the above analysis, four indices are proposed to evaluate the performance of dc-

link capacitors.

A. Power Loss and Core Temperature

The power loss of dc-link capacitors is the sum of the power dissipation of ESR from

individual frequency current components that can be calculated by using the ripple current

multiplier Mf. The expression is shown in (10), where ESR fi represents the ESR value

corresponding to the specific frequency fi and I cap is the RMS current absorbed by the capacitor
fi

at a certain frequency fi.

2
 I cap fi 
Pcap ∑ (
ESR100 ∑  )
2
= = ESR fi I cap f  (10)
 Mf
 
i

The self-heating process of dc-link capacitors can be numerically evaluated by using the

electro-thermal coupling method. The flowchart shown in Fig. 7 depicts the iterative solving

process. The computation starts with a given ambient temperature Ta. The capacitor core

temperature Tj_C is initially calculated by using the capacitor power loss and the equivalent

thermal model [41, 44]. Ta is the working ambient temperature (°K) and Rhc, Rca, Rbp, and Rha

denote the thermal resistances from hot spot to can, can to ambient, can base to mounting plate,

and mounting plate to ambient air. The equivalent thermal resistance from the core of capacitor

to the ambient is expressed by:

 Rca ⋅ ( Rbp + R pa ) 
Req =  Rhc +  (11)
Rca + Rbp + R pa 
_ cap
 
Then, the values of ESR and ripple current are updated using the historical value of Tc. The

iterative corrections are repeated until the process converges to a steady state with a given

tolerance. The core temperature Tj_C and the temperature rise ∆T j _ C are used for predicting the

capacitor lifetime.
 15

Start

Initial Temperature Ta=65℃

ESR model of capacitors

I cap f from circuit simulation Necessary info.

i
From datasheet

On-line power loss calculation

2
 I cap fi 
Pcap ∑ (
ESR100 ∑  )
2
= =ESR fi I cap f 
M
 f 
i

Tj _ C Thermal model of capacitors

T j _ c Rhc Tc Rbp R pa
Pcap Rca
Ta

No T j _ C − T j _ C −1
If <ε ?
∆t
Yes

Calculated T j _ C , ∆T j _ C

Fig. 7 Flowchart for iterative solving process of core temperature and ESR.

B. Lifetime

The capacitor lifetime is influenced by the capacitor core temperature and the ripple current.

Thus, the lifetime expression for both kinds of capacitors is given by [17]:

  2  ∆T
T j _ C −Ta 1−  I   ⋅ j _ C
  I 0   10
Le =
Lb ⋅ 2 10
⋅K  
(12)
Where, Lb is the capacitor lifetime under its maximum temperature and commonly given by

manufacture datasheets. I0 and I denote the allowable maximum ripple current at a given

frequency and the actual ripple current value. The K is a constant, which is typically assigned to

2 [17].

C. Battery ripple current analysis

Twenty-six valve-regulated lead-acid (VRLA) batteries are series connected to form the

battery pack, of which the DC bus voltage is rated as 312V. The battery model is 6-DM-150

VRLA, which is specially designed for EV applications and manufactured by FENGFAN Co.
 16

Ltd.. The product specification is shown in Table A-I. The battery internal resistance is a

nonlinear function of the states of charge (SOC). The measured internal resistance of the

battery pack is ranged from 46 mΩ to 182 mΩ.

Studies show that ripple current affects battery lifetime due to the internal temperature rise

[45]. Therefore, the battery ripple current should be maintained under a certain limit to avoid

the harmful effect. The dc-link capacitor is represented by an equivalent circuit including Rc, Lc

and Cc, as shown in Fig. 8. The switching frequency is 20 kHz, and that the ESR of battery

pack and interconnects can be neglected since the impedance of interconnects is dominated by

the inductance component, which is expression in symbol L1 in Fig. 8. It includes the

inductance introduced by the battery pack and interconnects between the battery pack and the

inverter. The battery ripple current can be obtained as (13) according to the equivalent circuit

shown in Fig. 8.

L1
Lc
I cap
I bat ,ac I inv
Rc

Cc

Fig. 8 Equivalent AC circuit of the EV inverter for the battery ripple current analysis.

Lc Cc s 2 + Rc Cc s + 1
ac ( s )
I bat ,= I inv ( s ) × (13)
( Lc + α L1,base )Cc s 2 + Rc Cc s + 1

α = L1 L1b (14)

The reference values of inductance (L1b) are assigned to 10 µH considering the practical

component layout and the parameters of interconnects. The RMS battery ripple current in

percentage can be defined by the division of AC RMS value (Ibat, ac) over the DC RMS current

(Ibat, dc), as shown in (15).

∆=
I bat
∑I bat , ac
× 100%
I bat , dc
(15)
 17

V. EVALUATION RESULTS AND DISCUSSION

This section includes the validations of the derived capacitor ESR models by experimental

tests and the analysis of dc-link capacitor current. Then two configurations of dc-link capacitors

are comparatively investigated through simulation and experimentation tests for an 80 kW PM

motor drive system in terms of the defined four performance indices.

Two dc-link capacitor designs are used for the comparative evaluation with main parameters

compared in Table V. Scheme I uses five 3300µF electrolytic capacitors (ALS332QP500) and

scheme II includes two 220µF film capacitors (AVX FFVE6K0227K). The capacitor

specifications are given in the Appendix. Both capacitors meet the base requirements shown in

section I and are comparable considering product availability, effect of ripple frequency,

temperature, etc.

TABLE V
MAIN PARAMETERS FOR TWO DESIGN SCHEMES
Parameters Scheme I Scheme II
Quantity 5 2
Manufacturer Part ALS332QP500 FFVE6K0227K
Total Capacitance(µF) 16500 440
Volume (L×W×H, cm) 38×7.7×15 16.8×8.2×8
Ripple current limit (A) 132 200
*
Cost($) 566 176
*
Source: http://eu.mouser.com, Date: Feb. 20, 2012

A. Validation of Capacitors Model

The ESR values using the derived model are plotted together with the experimental results

as shown in Fig. 9. The ESR values are measured using a HP4263B LCR meter. The

mathematical model shown in (1) matches the experiment evaluation regarding to the

frequency effect. Table VI summarizes the model parameters for the electrolytic capacitor.
 18

50
measurement
40 math model

ESR (mΩ)
30

20

10

0
-1 0 1
10 10 10
Frequency (kHz)
Fig. 9 Comparison of measured and modeled ESR for the electrolytic capacitor ALS332QP500
at 300°K.

TABLE VI
MODEL PARAMETERS OF THE ELECTROLYTIC CAPACITOR ALS332QP500
Parameters Value
Resistance of foil, tabs, and terminals R0 (mΩ) 5.03
Resistance of electrolyte R1b @ 300 K (mΩ) o
6
o -1
Temperature sensitivity factor F ( K ) 21
Dielectric loss resistance R2 (mΩ) 38.35
Terminal capacitance C1 (µF) 3300
Dielectric loss capacitance C2 (µF) 11.6
The modeling process of the film capacitor is described in Section 2B, which includes the

polynomial expression of the frequency dependent parameter K(f) and the parameter extraction

through the comparison with the measured impedance. Fig. 10 shows that the mathematical

model matches the experimentally measured frequency response for the 500V/220µF film

capacitor AVX FFVE6K0227K. Table VII summarizes the equivalent circuit parameters of

film capacitors.

40
1.5 measured measured
20
math model math model
0
1
Zc (mΩ)

-20
ϑ(°)

-40
0.5 -60

-80

0 -100
-2 -1 0 1 2 -2 -1 0 1 2
10 10 10 10 10 10 10 10 10 10
Frequency (kHz) Frequency (kHz)

(a) (b)

Fig. 10 Comparison of measured and modeled impedance for the film capacitor AVX
FFVE6K0227K at 300°K; (a) Amplitude characteristic; (b) Phase characteristic.
 19

TABLE VII
MODEL PARAMETERS OF THE FILM CAPACITOR AVX FFVE6K0227K
Parameters Value Parameters Value
Equivalent series inductance Lc (nH) 40 Coefficient of K expression f3 0.0000003173
Equivalent series capacitance Cc (µF) 210 Coefficient of K expression f2 -0.000124
Base resistance Rs (mΩ) 1 Coefficient of K expression f1 0.02369
Parameter defined by height As (mΩ) 0.24 Coefficient of K expression f0 1.014

The ESR characteristics of two schemes are compared in Fig. 11. It shows the ESR of

scheme II is always lower than that of the scheme I through the frequency span. Furthermore,

the ESR of scheme I decreases remarkably when the temperature increases from 27°C to 70°C.

4 scheme I(T a=27o C)

scheme I(T a=70o C)

3
scheme II(T a=27o C)
ESR (mΩ)

0
0 1 2
10 10 10
Frequency (kHz)

Fig. 11 ESR comparison of the two design schemes for dc-link capacitors with respect to the
operating frequency and temperature.

The capacitor ripple current multiplier Mf was defined in (5) and used to evaluate the

capacitor power loss by using (10). Based on the verified mathematical models, the estimated

Mf values are summarized in Table VIII corresponding to both design schemes.

TABLE VIII
RIPPLE CURRENT MULTIPLIER MF OF TWO DESIGN SCHEMES FOR DC-LINK CAPACITORS

Frequency Mf for Mf for Frequency Mf for Mf for

(kHz) Scheme I Scheme II (kHz) Scheme I Scheme II
0.1 1 1 5 2.04 0.98
0.2 1.08 1 10 2.05 0.97
0.5 1.39 1 20 2.05 0.95
1 1.74 1 50 2.06 0.90
2 1.95 0.99 100 2.06 0.86

B. Validation of Ripple Current Analysis

 20

The RMS value of the capacitor ripple current is evaluated by Pspice simulation. The load is

a 0.2Ω resistor connected with a variable inductor, which accounts for different load power

factors. The inverter is modulated by the SVM algorithm and the switching frequency is 20

kHz. One test case is to maintain the constant output current and the constant input voltage,

which is corresponding to the constant power operation mode of motors. The test condition is

designed that IN is constant at 84A and Vin = 312V with a adjusted modulation indexes, M. The

simulated capacitor current RMS value is compared with the value estimated from the

mathematical model in (6). Table IX presents the comparison results, which include the

simulated capacitor current RMS value (Icap), the estimated capacitor RMS current (Icap_est), and

the estimation error ( ε I ) under different operating conditions. The root-mean-square deviation
cap

(RMSD) is used to evaluate the differences between the mathematical modeling results and the

simulation results. This indicates that the RMSD value is 0.36 A, which is low relative to the

average capacitor current RMS value 22.77 A.

TABLE IX
CAPACITOR CURRENT COMPARISON BETWEEN THE SIMULATION AND MODEL ESTIMATION FOR
CONSTANT OUTPUT CURRENT (84A) AND INPUT VOLTAGE (312V)

L (mH) cosφ M Icap (A) Icap_est (A) ε I (A)

cap

4 0.16 0.729 27.74 26.97 0.77

2.7 0.23 0.497 23.34 23.11 0.23
1 0.54 0.211 19.72 19.78 -0.06
0.5 0.79 0.145 20.97 20.97 0
0.2 0.95 0.119 22.10 22.04 0.06

TABLE X
CAPACITOR CURRENT COMPARISON BETWEEN THE SIMULATION AND THE MODEL
ESTIMATION FOR CONSTANT OUTPUT CURRENT (84A) AND MODULATION INDEX (0.84)
L (mH) cosφ Vin (V) Icap (A) Icap_est (A) ε I (A) cap

4 0.16 261.7 26.79 27.44 -0.65

2.7 0.23 184.8 29.52 28.99 0.53
1 0.54 77.5 31.54 30.83 0.71
0.5 0.79 53.1 33.92 33.32 0.60
0.2 0.95 43.4 35.76 35.22 0.54

The second test case keeps the output current and modulation index constant, where IN =

84A and M = 0.84. The input voltage is tuned according to the variation of the load power
 21

factor. Table X presents the comparison between the simulation results and the model

estimation. The RMSD result is 0.61A and the average capacitor ripple current RMS value is

31.51 A. The simulation verified the proposed mathematical models and indicated a 1.85%

relative modeling error based on the two cases. Furthermore, it demonstrates the same trend as

the analysis derived in Section 2A and illustrated in Fig. 3.

C. Evaluation of Performance Indices

The power loss and core temperature are calculated and illustrated in Fig. 12. The main

parameters of two design schemes are defined in Table V. As shown in Fig. 12a, the capacitor

power loss of the scheme II is significantly lower than the scheme I due to the reduction of ESR

value. It shows that the capacitor power loss increases with the power factor and decreases with

the ambient temperature Ta in scheme I. The power loss is nearly constant when Ta varies from

45°C to 85°C in scheme II due to the insensitive temperature factor of film capacitors. The

estimated core temperature of both schemes is compared and demonstrated in Fig. 12b. The

scheme II shows a lightly higher core temperature considering the volume difference of dc-link

capacitors. The thermal resistance is calculated as 1.02 for both electrolyte and film capacitors

considering the outer diameters and air flow rate.

50 100

40 90
(oC)

80
(W)

30
cap

70
j-C

Scheme I
P

20
T

60
Scheme II
10 50
0.23 0.23
Scheme I
0.49 0.49 Scheme II

55 45 45
65 65 55
0.954 75 0.954 75
cos φ 85 o cos φ 85
Ta ( C) Ta (oC)

(a) (b)

Fig. 12 Performance comparison between two schemes; (a) Power loss; (b) Core temperature.

The impact of modulation strategies on the capacitor power loss is analyzed and illustrated

in Fig. 13, where the load power factor is constant ( cosφ = 0.23). Among three modulation
 22

strategies, the THI modulation shows the highest power loss due to the frequency spectrum

distribution of the capacitor current, which is about 10% higher than that of the SVM. The SVM

shows moderate impact on the power loss of dc-link capacitors, which is roughly 3% higher

than the SPWM. Shown in Fig. 13a, the power loss decreases with the increased temperature,

which is the characteristic of electrolyte capacitors. For scheme II, the power loss of dc-link

capacitors is lower as shown in Fig. 13b and the temperature variation shows insignificant

impact to the power loss, which is the characteristic of film capacitors.

36 17
THI THI
34 SVM SVM
SPWM 16.5 SPWM
32
Pcap (W)

Pcap (W)

30 16

28
15.5
26

24 15
45 50 55 60 65 70 75 80 85 45 50 55 60 65 70 75 80 85
o
T a ( C) T a (o C)

(a) (b)

Fig. 13 Power loss of dc-link capacitors among three switching modulation strategies. (a)
Scheme I – five 3300µF electrolytic capacitors; (b) Scheme II – two 220µF film capacitors.

The lifetime of the two design schemes can be predicted using the verified mathematical

models of capacitors ESR and ripple current. Fig. 14 shows the life expectancy of the two

schemes for the ambient temperature spanning from 45°C to 85°C. The lifetime estimation is

based on the expression (12), where the key parameters are derived from the product datasheet

and shown in Appendix. Apparently, the temperature and its variation significantly affect the

lifetime of dc-link capacitors, as shown in Fig. 14. The results are corresponding with the rule

of thumb, which the life expectancy of capacitors is approximately reduced by half when the

ambient temperature rises 10°C. Moreover, the life expectancy of film capacitor is about 180

kilo hours and ten times longer than that of the electrolytic capacitor when the operating

ambient temperature is constant at 65°C. The film capacitor demonstrates the significant

advantage regarding to the long lifetime requirement in EV drive applications.

 23

Lifetime (kilo hours) 80 800

Lifetime (kilo hours)

60 600

40 400

20 200

0 0
45 50 55 60 65 70 75 80 85 45 50 55 60 65 70 75 80 85
o
T a ( C) T a (o C)

(a) (b)

Fig. 14 Life expectancy of the two design schemes for dc-link capacitors with the ambient
temperature spanning from 45°C to 85°C. (a) Scheme I – five 3300µF electrolytic capacitors;
(b) Scheme II – two 220µF film capacitors.

The battery current harmonics are analyzed and based on the two design schemes. The upper

bound of the AC ripple current is defined as 10% of the rated battery current to avoid

significant degradation on the lifetime of battery. Main parameters of two schemes are defined

in Table V. The RMS battery ripple current in percentage is calculated by using the expression

in (15) and the equivalent circuit shown in Fig. 8. Fig. 15 shows the analysis results of battery

ripple current, where the symbol α is predefined in (14) and determined by the equivalent

circuit shown in Fig. 8. The battery ripple current in scheme II is higher than the ripple current

in scheme I due to the vast reduction of capacitance. The capacitance in scheme II is 440µF,

which is about 2.6% of the capacitance in scheme I. Therefore, to meet the 10% upper bound, α

must be larger than 0.6 in scheme II with consideration of various combinations of modulation

index and load power factor. In practical EV system, the cable interconnect provides enough

impedance to guarantee α larger than 0.6 since the inverter and the battery bank are located at

some distance.
 24

8 15

6
10
∆ Ibat (%)

∆ Ibat (%)
4

5
2

0 0
0 0.23 0 0.2
0.2 0.49 0.2 0.4
0.4 0.4
0.6 0.625
0.6 0.6
0.8 0.8 0.8
0.8
1 0.954 cos φ 1 1
α M
α

(a) (b)

150 200

150
100
∆ Ibat (%)

∆ Ibat (%)

100
50
50

0 0
0 0.23 0 0.2
0.2 0.49 0.2 0.4
0.4 0.4
0.6 0.625
0.6 0.6
0.8 0.8 0.8
0.8
1 0.954 cos φ 1 1
α M
α

(c) (d)

Fig. 15 Battery ripple current analysis for two design schemes (five 3300µF electrolytic
capacitors and two 220µF film capacitors). (a) ΔIbat with cosφ and α in scheme I; (b) ΔIbat with
M and α in scheme I; (c) ΔIbat with cosφ and α in scheme II; (b) ΔIbat with M and α in scheme II.

D. Experiment with 80kW PM Motor

The EV drive system is finally tested with a 80kW permanent magnet AC motor, of which

the key parameters are summarized in Appendix. Fig. 16 shows a corner of the inverter

assembly with the two film capacitors.

Fig. 16 Photo of the EV inverter assembly with two film capacitors.

 25

The experimental switching frequency is 20 KHz and the output current frequency is 93 Hz.

Fig. 17 shows the experimentally measured waveforms with respect to the proposed schemes II.

Shown in the oscilloscope screen, the traces CH1 and CH2 represent the output current (upper

waveform) and capacitor current (lower waveform), respectively. Fig. 17b illustrates a detailed

look of the output current (upper) and the capacitor current (lower), of which the overall views

are shown in Fig. 17a. The current signals are sensed by Rogowski coils, which are transducers

for measuring alternating current (AC) or high frequency current pulses. The current

waveforms are represented voltage signals and shown in the oscilloscope screen. The

calibration factors are 2 mV/A and 1 mV/A for the CH1 and CH2, respectively.

The experiment shows that the ripple current spectrum contains significant switching

frequency multiples and their sidebands, which agrees with the mathematical analysis discussed

in Section 3C. Each film capacitor absorbs 38A ripple current, as shown in Fig. 17a and Fig.

17b. Thus, the test shows the total ripple current through the film capacitor banks are 76A,

when the inverter output current is 135A in RMS value. Considering the high power factor

(cosϕ> 0.9) of the PM motor and the modulation index (M = 0.6), the measured ratio of Icap and

IN is 0.4. The result is agreeable with theoretical analysis expressed in (6), which is graphically

illustrated in Fig. 3.

(a)
 26

(b)

Fig. 17 The experimental waveforms of scheme II using two film capacitors. (a) the output
phase current (upper: 2mV/A) and film capacitor current (lower: 1mV/A) in scheme II; (b)
Zoom-in detailed look of the output phase current (upper: 2mV/A) and film capacitor current
(lower: 1mV/A) in scheme II.

Fig. 18 shows the experimentally measured waveforms with respect to the proposed

schemes I. Shown in the oscilloscope screen, the CH1 and CH2 represent the capacitor current

(upper waveform) and output current (lower waveform), respectively. The current waveforms

are transformed to voltage signals and shown in the oscilloscope screen. The calibration factors

are 5 mV/A and 2 mV/A for the CH1 and CH2, respectively. The individual electrolytic

capacitor ripple current is 16.2A. Thus, the five electrolytic capacitors share the total 81A

ripple current through the parallel interconnected capacitor bank. It demonstrates that each film

capacitor can handle more ripple current due to the low ESR characteristics.
 27

Fig. 18 The experimental dc-link capacitor current (upper: 5mV/A) and output phase current
(lower: 2mV/A) waveforms of scheme I using five electrolytic capacitors for 80kW PM motor.

The DC bus voltage ripple is recorded and shown in Fig. 19 at the rated capacity of 80kW.

The oscilloscope screen show the measured RMS voltage and the peak value is 1.81V and

1.925V respectively. These values correspond that the calibrated RMS voltage of the DC bus is

317V and the ripple peak reaches 337V. Therefore, the ripple magnitude is recorded as the

6.31% of the dc bus voltage.

Fig. 19 Measured DC bus voltage ripple for EV inverter with proposed design scheme with the
calibration factor of 35V/div.

Table XI summarizes performance comparison between the two design schemes. Main

parameters of two schemes are defined in Table V. The scheme II show the significant

advantages regarding to the small size, low parasitic inductance, long lifetime, reduced bus

voltage spikes, and improved power density. It is shown that the power density is increased to
 28

13.3 kW/L by applying scheme II in contrast of 2.99 kW/L by using the scheme I. For battery

ripple current, the constraint of α > 0.6 is required for the scheme II. This is achievable by

considering the practical layout of electric vehicles.

TABLE XI
PERFORMANCE COMPARISON OF TWO DESIGN SCHEMES
Parameters Scheme I Scheme II
Measured parasitic inductance (nH) 124 34
Measured ripple current (A) 81 76
Power loss (W) for Ta=65 C and cosφ =0.954
o
40.8 20.6
Core temperature ( C) for Ta=65 C and cosφ
o o
73.3 75.5
o
Life expectancy (Hours) for Ta=65 C 16092 181530
ΔIbat for α=0.6 1.8% 8.7%
*
Switching voltage spike across IGBT modules (V) 57V 35V
PDW(kW/kg) 4.67 11
PDV (kW/L) 2.99 13.3
* With 2µF snubber capacitor

VI. CONCLUSION

This paper presents a comprehensive analysis and comparative evaluation of dc-link

capacitors to meet EV system requirements of long lifetime, high reliability, low cost, and high

power density. The main findings and contributions of the research are summarized as

following:

1) Modulation strategy: regarding the dc-link capacitor ripple current, three modulation

strategies of SPWM, SVM and THI show the same RMS values. Considering the ripple voltage,

THI modulation shows the lowest value across the dc-link capacitors and then followed by the

SVM. However, THI results in the highest capacitor power loss, which is 10% higher than that

of the SVM. The losses correspond to the frequency spectrum, which is different among

modulation strategies. The SVM shows moderate impact on the capacitor power loss, which is

roughly 3% more than that of the SPWM.

 29

2) Influence of operating conditions: operating conditions of EV inverters may be expressed

in terms of the practical ranges of load power factor ( cosφ ) and modulation index M. When

cosφ is less than 0.43, the peak ripple current always results from the upper bound of M. After

the threshold (0.43), increasing of load power factor cosφ causes a decreasing of MIcap(max),

which is the modulation index referring to the maximum RMS value of capacitor ripple.

Furthermore, the power factor has great impact on the frequency spectrum of the dc-link

capacitor ripple current. For low cosφ , the ripple current spectrum is evenly distributed along

the switching frequency (f1) sidebands (sbs), 3f1 sbs and 2f1. For high cosφ (larger than 0.49 for

SVM), 2f1 is the dominant component and its amplitude increases with cosφ . Besides, the

largest harmonic component is nearly 21% of output current amplitude at low cosφ , while the

corresponding harmonic component reaches as high as 48.8% at the high cosφ .

3) Modeling of ESR and self-heating characteristics: the ESR models of electrolytic

(ALS332QP500) and film capacitors (AVX FFVE6K0227K) are mathematically derived and

experimentally validated. Two dc-link capacitor designs are used for the comparative

evaluation. It shows the ESR of scheme II is always lower than that of scheme I through the

frequency span. The ESR value of scheme I decreases with increasing temperature, which is

more significant than that of the scheme II. Furthermore, the RMS values and frequency spectra

of the dc-link capacitor current are analyzed. The self-heating effect is subsequently considered

and numerically evaluated by using the iterative simultaneous solution for approximation core

temperature and ESR by electro-thermal coupling method to predict the core temperature and

lifetime.

Experimental evaluation of two design schemes: The applications and performance of

electrolytic capacitors (scheme I) and film capacitors (scheme II) were tested and compared and

evaluated in terms of power loss, core temperature, lifetime and battery current harmonics

based on a practical 80kW permanent-magnet motor drive system. The comparison verifies that

the film capacitor application shows significant advantages shown by the improved power
 30

density, low power loss, low parasitic inductance, and long lifetime. The capacitor power loss

introduced by the scheme II is roughly half of the value of scheme I due to the lower ESR value.

The analysis shows that the values of capacitor core temperature are close to each other in both

schemes. At the rated ambient temperature of 65 oC, the lifetime of the film capacitors is ten

times longer than that of scheme I. Further, the parasitic inductance is reduced to 34 nH in

contrast with the value of 100 nH for scheme I. Regarding to the battery ripple current, both

schemes meet the 10% upper bound limit considering the practical EV system layout.

APPENDIX

TABLE A-I
SPECIFICATION OF THE VRLA BATTERY (6-DM-150)
Parameters Value
C20(Ah) 150
Cold Cranking Amperes defined by BCI (A) 300
Rated voltage (V) 12
Weight (kg) 32.5

TABLE A-II
SPECIFICATION OF EVOX RIFA ALS332QP500AND AVX FFVE6K0227K
Expected
Max Impedance Ripple Life time
Comparison Max ESR(mΩ) ambient
(mΩ) at 20oC / current(A) at Lb at 85°C
Items at 20 oC/ 100hz temperature
10 khz 85°C & 10 khz (hrs)
Ta(oC)
ALS332QP500 51 32 26.4 4000 65
FFVE6K0227K 1 - 100 30000 65

TABLE A-III
MAIN PARAMETERS OF AC INDUCTION MOTOR
Parameters Value
Stator resistor (mΩ) 6.8
Stator leakage inductance (mH) 0.071789
Rotor resistor (mΩ) 4.23
Rotor leakage inductance (mH) 0.0921067
Mutual inductance (mH) 2.2857359
Pairs of poles 3
Rated speed(rpm) 1860
 31

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