LIST OF FIGURES

Figure No. Title Page No.

Figure 4.1 SELECTIVE ACTIVATION APPROACH 21

Figure 4.2 PARTITIONING MULTIPLIER ARCHITECTURE 22

Figure 4.3 AREA REQUIREMENTS OF THE PROPOSED ARCHITECTURES AS A
FUNCTION OF PAIR(n,m) 23

Figure 4.4 DELAY OF PROPOSED ARCHITECTURES 24

Figure 4.5 AREA REQUIREMENTS OF THE PROPOSED ARCHITECTURES FOR n= 16

AS A FUNCTION OF m 24

Figure 4.6 DELAY FOR THE PROPOSED ARCHITECTURES FOR n= 16 AS A

FUNCTION OF m 25

Figure 4.7 AREA AS A FUNCTION OF DELAY FOR N=16 26

Figure 5.1 SPARTAN-3 Family Architecture 36

Figure 6.2 Behavioral, Structural and Physical 40

Figure6.3.1 RTL SCHIMATICS 48

Figure6.3.2 TECHNOLOGY SCHIMATICS 48

Figure6.3.3 SIMULATION RESULTES 49

Figure6.3.4SYNTHASIS REPORT 49

Figure6.3.5 PROJECT SUMMARY 50