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A Major Project

Report On

DESIGINE AND IMPLIMENTATION OF LOW POWER


MULTIPLIERS
Submitted to the
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY, HYDERABAD
BACHELOR OF TECHNOLOGY
In
ELECTRONICS AND COMMUNICATION ENGINEERING
By

K SAI KISHORE (13WJ1A04J8)


K RAMA RAO (13WJ1A04L3)
J NAVEEN KUMAR (14WJ5A0418)

Under the guidance of

M SWETHA
Associate Professor

Department of Electronics and Communication Engineering


School of Engineering & Technology
GURU NANAK INSTITUTIONS-TECHNICAL CAMPUS
(Permanently Affiliated to JNTU, Hyderabad)
Ibrahimpatanam, Ranga Reddy District -501506
2016-2017
College Letter Head

CERTIFICATE

This is to certify that the project entitled “PAPER BATTTERY” being submitted by

Mr. D.NAVEEEN bearing Roll Number 13WJ1A0489, Mr. D.NAVEEEN bearing Roll

Number 13WJ1A0489, Mr. D.NAVEEEN bearing Roll Number 13WJ1A0489, in partial

fulfillment of the requirements for the award of the degree of Bachelor of Technology in

Electronics & Communication Engineering, Guru Nanak Institutions Technical Campus,

Hyderabad to the J.N.T.U. Hyderabad is bonafide work carried out by them under my guidance

and supervision. The result provided in this report has not been submitted to any other University

or Institution for the award of any degree.

D. SURENDRA RAO D. SURENDRA RAO


Associate Professor Project Coordinator
Internal Guide

Prof. S. MAHESWARA REDDY


Head of the Department External Examiner
ACKNOWLEDGEMENT

At the outset, we express our deepest sense of gratitude to guide Mr . D. SURENDRA RAO,
Associate Professor Electronics and Communication Engineering Department, G.N.I.T.C.,
Hyderabad, for giving us an opportunity to work on a project that was so challenging and
interesting for us. We remember with great emotion, the constant encouragement and help
extended to us by him that went even beyond the realm of academics.

We express our profound gratitude to Mr. V. BHAGYA RAJU, and Mr.


D. SURENDRA RAO Project Coordinators, A.Y. 2016-17 of Electronics and Communication
Engineering department, G.N.I.T.C., Hyderabad.

We express our profound gratitude to Dr. M.A. KHADAR BABA and Prof.
S. MAHESWARA REDDY, Heads of the Department, G.N.I.T.C., Hyderabad.

We would like to express our sincere thanks and gratitude to our Associate Director, Prof.
R.K.SINGH, Guru Nanak Institutions Technical Campus, Hyderabad.

Our sincere thanks go to all the faculty members of the Department for the voluntary
help, direct and indirect, extended to us during the course of the project work.

We are very much thankful to our Director, Managing Director and Management GNI
Group of Institutions for the facilities and opportunities provided in campus.

On a more personal note we thank our beloved parents and friends for their moral support
during the course of our project.

B. VIDHULATHA (13WJ1A0444)
A. SANDEEP (14WJ5A0403)
M. SURESH (14WJ8A0401)
CANDIDATE’S DECLARATION

I hereby declare that the work which is being presented in this dissertation
entitled, "Delay Efficient Carry-Select adder ”, submitted towards the partial
fulfillment of the requirements for the award of the degree of Bachelor of
Technology in Electronics and Communication Engineering, Guru
Nanak Institutions Technical Campus, Hyderabad is an authentic record of our
own work carried out During 2016-17 under the guidance of Mr. D.
SURENDRA RAO, Associate Professor, Electronics and Communication
Engineering Department, GNITC, Hyderabad.

The matter embodied in this mini project report has not been submitted by us
for the award of any other degree or diploma. Further, the technical details
furnished in the various chapters in this thesis are purely relevant to the above mini
project.

B. VIDHULATHA (13WJ1A0444)
A. SANDEEP (14WJ5A0403)
M. SURESH (14WJ8A0401)
ABSTRACT
The multipliers are mainly focusing for low power. Here proposed two architectures for two inputs
signed multipliers namely selective activation multiplier and partitioned multiplier. The proposed
technique is mainly applied in DCT and DWT Application. This Power is reduced. The proposed
multiplier is applied to all low power techniques with moderate area and time overhead.
.
Contents
Acknowledgement i
Candidate’s Declaration ii
Abstract iii
List of Figures iv
List of Tables v
Abbreviations vi

Chapter No Title of the Chapter Page No

Chapter-1 Introduction
1.1 general 1
1.2 Objective 2
1.3 Block Diagram 3
1.4 Organization of report 4
Conclusion 4

Chapter-2 Literature Survey


2.1MULTIPLIER ARCHITECTURES FOR MEDIA PROCESSING
2.2. ENERGY REDUCTION IN VLSI COMPUTATION MODULES: AN
INFORMATION THEORETIC APPROACH
2.3ARCHITECTURAL POWER ANALYSIS: THE DUAL BIT TYPE METHOD
2.4. HIGH-SPEED ARITHMETIC IN BINARY COMPUTERS

Chapter-3 Hardware Description


3.1 GENERAL
3.2 VLSI AND SYSTEMS
3.3 INTRODUCTION TO ASICS AND PROGRAMMABLE LOGIC
3.4 FIELD PROGRAMMABLE LOGIC

Chapter-4 Software Description


4.1 INTRODUCTION TO MODELSIM
4.2 INTRODUCTION TO XILINX
Chapter-5 Result Analysis
5.1
5.2
5.3

Chapter-6 Conclusions and Future Scope


6.1 Advantages and Disadvantages
6.2 Applications
6.3 Future Scope
Conclusion

References
Appendix-A