Escolar Documentos
Profissional Documentos
Cultura Documentos
Reference Manual
Release v2018.2
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Chapter 1
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SystemVerilog-VHDL Assistant Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SystemVerilog-VHDL Assistant Quick Tour Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Design Understanding Tour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Design Creation Tour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SystemVerilog-VHDL Assistant UVM Workbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chapter 2
SystemVerilog-VHDL Assistant Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Projects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Accessing the Projects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Using the Projects Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Outline Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Accessing the Outline Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Using the Outline Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
File Explorer Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Accessing the File Explorer Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Using the File Explorer Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Design Objects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Accessing the Design Objects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Using the Design Objects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Design Hierarchy Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Accessing the Design Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Using the Design Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Class Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Accessing the Class Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Using the Class Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Build Libraries Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Accessing the Build Libraries Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Using the Build Libraries Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Errors and Warnings Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Accessing the Errors and Warnings Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Using the Errors and Warnings Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Bookmarks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Accessing the Bookmarks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Using the Bookmarks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Console Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Accessing the Console Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Using the Console Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
History Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chapter 3
SystemVerilog-VHDL Assistant Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SystemVerilog-VHDL Assistant Standard Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
File Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
New Project Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Accessing the New Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Accessing the Settings Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Accessing the Add Files Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
New Template Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
New Template Project Wizard - Add Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Add File Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Add Files to Project Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Import From Questa Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Import From Questa - Import File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Import From Questa - Import Settings (_info) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Import From Questa - Import Settings (.ini). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Create New Virtual Folder Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Save As Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Edit Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Search Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Search Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Replace Text Matches Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Find/Replace Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Navigate Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Open Resource Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Open Module Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Open Class Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Go to Line Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Build Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
New Build Library Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Edit Include Search Path List Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Edit Linked Libraries List Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Tools Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Export to Image File Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Project Settings Dialog Box - Build Settings Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Project Settings Dialog Box - QuestaSim Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Project Settings Dialog Box - Questa vsim Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Project Settings Dialog Box - Default Clean Command Page . . . . . . . . . . . . . . . . . . . . . . 147
Project Settings Dialog Box - Check Settings Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Window Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Chapter 4
Working With Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Creating a Project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Opening a Project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Closing a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Ensuring SystemVerilog-VHDL Assistant Project Portability . . . . . . . . . . . . . . . . . . . . . . . 177
SystemVerilog-VHDL Assistant Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Reloading a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Reloading a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Creating a Virtual Folder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Removing a Virtual Folder From a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Adding a New File to a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Adding Existing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Importing Files Using Questa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Removing Files From a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Detecting Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Documenting Your Project Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Checking a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Defining Project Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Building a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Example - Simulating a Project in QuestaSim Using a Test File . . . . . . . . . . . . . . . . . . . . . 189
Multiple SystemVerilog-VHDL Assistant Sessions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Chapter 5
Working With Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Showing and Hiding Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Undocking Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Docking Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Maximizing Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Restoring Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Customizing Browser Content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Showing and Hiding Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Grouping and Ungrouping Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Showing and Hiding Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Expanding and Collapsing Nodes Within Browsers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Creating Custom Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Chapter 6
Navigating and Finding Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Finding Class Parents and Declarations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Finding Object Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Finding the Design Unit of an Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Finding the Binding Aspect of an Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Finding External Function and Task Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Cross-Highlighting Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Using Filters to Locate Objects Within Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Navigating to Objects in a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Searching for Text in SystemVerilog-VHDL Assistant Projects . . . . . . . . . . . . . . . . . . . . . 210
Accessing Files Referenced by Include Statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Accessing Files Referencing a Selected File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Changing File Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Opening Package Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Highlighting Package Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Opening Module/Interface Instances Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Tracing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Chapter 7
Working With Design Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Working With Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Viewing Classes in SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . 217
Exploring Classes Separately . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Showing Classes Inheritance Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Showing Inherited Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Extending Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Finding Class Parents and Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Visualizing a Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Class Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Working With Visualization Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Exploring Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Working With Annotation Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Showing/Hiding Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Expanding and Collapsing Class Declarations and Methods . . . . . . . . . . . . . . . . . . . . . . . 238
Showing Missing Parent Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Toggling Between Component and Class Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Updating Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Printing Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Saving Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Example - Visualizing a Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Working With Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Marking the Top-Level Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Showing/Hiding the Hierarchy of a Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Working With Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Generating Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Chapter 8
Automating Test Bench Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
SystemVerilog-VHDL Assistant Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
SystemVerilog-VHDL Assistant Template Sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
MetaData Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Body Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Pre-Processing and Post-Processing Sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Adding Templates to Design Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Creating a Template Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Referencing a Template Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Adding Template Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Using Templates to Create Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Specifying a Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Template Parameters Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Sub-Templates Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Template Syntax Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Upper and Lower Case Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Script Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
TCL Scripts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Include Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Create Calls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Template Syntax Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Chapter 9
Using SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Using SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Working With Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Creating a New File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Opening Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Closing a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Saving a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Saving All Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Setting Design Files Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Printing a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Editing Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Undo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Redo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Chapter 10
Understanding UVM/OVM Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Using OVM Test Benches With a UVM Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Exploring UVM/OVM Test Bench Hierarchies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Displaying UVM/OVM Components in SystemVerilog-VHDL Assistant Browsers. . . . . . 334
Understanding UVM/OVM Connecting Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Understanding UVM/OVM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Identifying Elements of a UVM/OVM Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Identifying the Hierarchical Level of the Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Identifying Peer-to-Peer Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Identifying Hierarchical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
UVM/OVM Coding Assistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Instancing UVM/OVM Classes by Drag and Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Adding seq_item Class Declarations to “do_” Methods . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Completing UVM/OVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Changing the UVM/OVM Factory Registry Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Example - Dynamically Creating UVM/OVM Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Chapter 11
Building a SystemVerilog-VHDL Assistant Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Creating a Build Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Modifying Library Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Adding Content to a Build Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Specifying Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Editing Command Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Setting Build Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Creating a Project Makefile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Running a Project Makefile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Simulating and Optimizing a Design Through the Top-Level Module. . . . . . . . . . . . . . . . . 366
Chapter 12
Setting Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Preferences Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Editors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Verilog Template Syntax Coloring and Verilog Syntax Coloring . . . . . . . . . . . . . . . . . . 374
VHDL Syntax Coloring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
VHDL Construct Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
VHDL Scalability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Project Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Build Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Class Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Project Settings Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Project Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Build Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Verilog/SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Standard Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Check Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
RTL Instancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
RTL Instancing — Verilog/SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
RTL Instancing — VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Build Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Chapter 13
Working with External Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
External Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Process Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Appendix A
Internal Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
System Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Build Manager Internal Variables (Macros) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Using Internal Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Appendix B
Command Line Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Running SystemVerilog-VHDL Assistant in Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Preparing Working Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Opening Intended Project and Configuring Its Top Level . . . . . . . . . . . . . . . . . . . . . . . . . 434
Checking the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Compiling and Simulating (Building) the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Visualizing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Creating a Coverage Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Appendix C
Error and Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Miscellaneous Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Glossary
Index
End-User License Agreement
Table 12-13. Project Settings Dialog Box - Project Management Page Contents . . . . . . . . 397
Table 12-14. Project Settings Dialog Box - Build Management Page Contents . . . . . . . . . 400
Table 12-15. Project Settings Dialog Box - Verilog/SystemVerilog Page Contents . . . . . . 402
Table 12-16. Project Settings Dialog Box - Standard Libraries Page Contents . . . . . . . . . . 403
Table 12-17. Project Settings Dialog Box - Check Settings Page Contents . . . . . . . . . . . . . 405
Table 12-18. Project Settings Dialog Box - Verilog/SystemVerilog Instancing Page Contents
409
Table 12-19. Project Settings Dialog Box - VHDL Instancing Page Contents . . . . . . . . . . 412
Table 12-20. Project Settings Dialog Box - Build Settings Page Contents . . . . . . . . . . . . . 415
Table 13-1. External Tools Variable Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Table 13-2. Process Console Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Table A-1. List of SystemVerilog-VHDL Assistant System Variables . . . . . . . . . . . . . . . . 427
Table A-2. List of Build Manager Internal Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Table B-1. Command Line Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Overview
SystemVerilog-VHDL Assistant is an EDA tool that provides an excellent environment for
creating, testing, viewing, modifying, and analyzing VHDL, Verilog and SystemVerilog
designs. Through its rich built-in libraries, SystemVerilog-VHDL Assistant grants all the
needed classes and modules for easily creating professional UVM/OVM test benches. In
addition to its Verilog RTL design editing support, SystemVerilog-VHDL Assistant provides
advanced editing capabilities for creating text-based VHDL RTL designs.
SystemVerilog-VHDL Assistant presents a variety of generic browsers that help analyze your
design. Each browser has its default settings but, adopting the concept of generic browser,
SystemVerilog-VHDL Assistant provides a capability of creating new browsers and
customizing their view to control the visibility and grouping settings.
The Design and Class Hierarchy browsers help you analyze entities, architectures,
configurations, modules, classes and instances in a simple manner and demonstrate the
inheritance relationships between them. The Projects browser displays your active projects and
presents their contents in organized trees. Furthermore, the Design Objects browser groups all
objects in separate folders according to their type.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Getting Started
Overview
Moreover, browsing through the contents of a file is easily achieved through the Outline
browser which enhances code navigation and organization by combining the browsers’
capabilities while focusing on the current file. In addition to its several browsers,
SystemVerilog-VHDL Assistant lets you create your own browser. It also allows you to focus
on a certain part of your design by viewing it alone in a separate browser for further
investigation and analysis. You can also compile, check, and simulate your design in
SystemVerilog-VHDL Assistant. SystemVerilog-VHDL Assistant offers several options that
allow you to customize your workspace.
Note
It is assumed that SystemVerilog-VHDL Assistant users have previous knowledge of
SystemVerilog and OVM/UVM testbench structures. For information, refer to
www.mentor.com and https://verificationacademy.com/.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Getting Started
SystemVerilog-VHDL Assistant Window
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Getting Started
SystemVerilog-VHDL Assistant Window
Objects
Table 1-1. SystemVerilog-VHDL Assistant - Default Workspace Contents
Element Name Description
Standard Toolbar Provides quick access for common operations, such as
creating a new project, adding existing files, and so on.
Projects/ Design Objects/ Has three tabs: the Projects browser tab, the Design
Build Libraries Browsers Objects browser tab, and the Build Libraries browser
tab.
SystemVerilog-VHDL Allows you to create, view or modify designs and test
Assistant Text Editor benches.
Outline Browser Displays all code objects in the file opened by
SystemVerilog-VHDL Assistant text editor.
Design/ Class Hierarchy Displays the design structure from a design instance
Browsers hierarchy point of view.
Console, Bookmarks, These tabs are used respectively to display log
Errors and Warnings, messages and run Tcl & API (Application Program
Properties and Tasks Interface) commands, display bookmarks added to files
Tabs in the opened project(s), display errors found in files in
the opened project(s) and display all the tasks added to
files in the opened project(s).
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Getting Started
SystemVerilog-VHDL Assistant Quick Tour Guide
2. You can open files in SystemVerilog-VHDL Assistant text editor, for example top.sv.
You can find it by typing the word top in the filter in the Projects Browser. The nodes
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Getting Started
Design Understanding Tour
that lead to files named top expand in the Projects browser and only those branches are
visible in the browser.
Double-click to open the desired file. You can also open this file by choosing the Open
Resource option from the Navigate menu and typing top in the Select an item to open
field of the Open Resource dialog box. Choose the desired file from the names displayed
in the Matching items pane and click Open.
Figure 1-3. top.svOpened in SystemVerilog-VHDL Assistant Text Editor
3. You can view the contents of any file. See top’s contents in the Outline Browser.
4. SystemVerilog-VHDL Assistant maps objects in different browsers to their
declarations. Find multadd_if by typing its name in the filter of the Design Objects
Browser. Double-click it to highlight the declaration of multadd_if in the text editor.
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Getting Started
Design Understanding Tour
5. The Design Objects browser classifies objects by type. In this browser, select coverage
under classes. Right-click and choose Explore from Here to explore coverage in a new
browser.
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Getting Started
Design Understanding Tour
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Getting Started
Design Understanding Tour
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Getting Started
Design Creation Tour
7. You may want to take a general look at the UVM/OVM test bench schematic diagram.
In the Projects Browser, right-click the project’s name, then choose Visualize UVM/
OVM Static structure from the popup menu.
8. You can also check the design by selecting Tools > Checks > Using TB Policy
[Verification_UVM_Policy].
9. SystemVerilog-VHDL Assistant provides a complete build management solution by
automatically understanding your design, generating dependencies, and generating a
Makefile.
10. SystemVerilog-VHDL Assistant uses QuestaSim to simulate designs. Right-click the
project’s node in the Projects browser and select Build > Simulate.
Tip
In addition to opening multiple projects within the same session, you can open
multiple SystemVerilog-VHDL Assistant sessions on the same machine at the same
time.
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Getting Started
Design Creation Tour
4. You can create new files in SystemVerilog-VHDL Assistant by selecting Add New File
from the project’s popup menu. The Add File dialog box opens.
5. Enter the File name and save the file with any valid SystemVerilog-VHDL Assistant
extension, for example file1.svh. Save the file on your machine by entering a path in the
Location field, then click OK.
The file is created and added to the project.
6. You can add files to a project by selecting Add Existing File(s) from the project’s
popup menu.
Added files are only referenced in your project, and removing them from the project
does not delete them from disk.
7. SystemVerilog-VHDL Assistant automatically generates child classes. Find the
coverage class in the Design Objects browser. Right-click then choose Extend This
Class. Enter the file name and path where the child class will be declared.
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Getting Started
Design Creation Tour
8. You can create Virtual Folders in the project. Right-click the project’s node in the
Projects browser, then select Add New Virtual Folder. Enter the folder’s name, F1,
then click OK.
9. Drag the file extension1.svh to the virtual folder F1 to organize your project.
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Getting Started
SystemVerilog-VHDL Assistant UVM Workbook
10. SystemVerilog-VHDL Assistant allows you to add file references automatically. Open
file1.svh in SystemVerilog-VHDL Assistant text editor. Drag any file from the Projects
browser into the text editor to reference it in file1.sv.
Figure 1-10. ‘include Statement Added to file1.sv
11. You can also instantiate objects automatically by dragging classes from the Projects
browser to the destination file in the SystemVerilog-VHDL Assistant text editor. Make
sure that the destination location is valid for instantiating objects, for example,
instantiate objects as data members in a class.
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Getting Started
SystemVerilog-VHDL Assistant UVM Workbook
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Chapter 2
SystemVerilog-VHDL Assistant Browsers
Projects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Accessing the Projects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Using the Projects Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Outline Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Accessing the Outline Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Using the Outline Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
File Explorer Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Accessing the File Explorer Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Using the File Explorer Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Design Objects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Accessing the Design Objects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Using the Design Objects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Design Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Accessing the Design Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Using the Design Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Class Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Accessing the Class Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Using the Class Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Build Libraries Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Accessing the Build Libraries Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Using the Build Libraries Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Errors and Warnings Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Accessing the Errors and Warnings Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Using the Errors and Warnings Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Bookmarks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Accessing the Bookmarks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Using the Bookmarks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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SystemVerilog-VHDL Assistant Browsers
Console Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Accessing the Console Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Using the Console Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
History Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Accessing the History Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Search Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Accessing the Search Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Using the Search Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Properties Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Accessing the Properties Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Browser Toolbars. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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SystemVerilog-VHDL Assistant Browsers
Projects Browser
Projects Browser
The Projects browser is the most significant browser in SystemVerilog-VHDL Assistant
because it provides a global view of your designs.
To be able to work on your designs through SystemVerilog-VHDL Assistant, you have to create
a project and add to it your design files. Projects allow you to assemble all the relevant design
files together in one whole, which enables you to easily manage all your source files through a
single entity.
When you add design files to a project, SystemVerilog-VHDL Assistant performs a rapid
analysis of those files to extract the available code objects. Furthermore, SystemVerilog-VHDL
Assistant identifies the relationships between those code objects across different files.
Through a tree view, the Projects browser lists all the projects created in SystemVerilog-VHDL
Assistant, the source files within each project, and the code objects within each file. Also,
besides showing the source files within each project, the browser shows any available
associated files such as documentation files, Visualization Files, Makefiles, and so on.
The Projects browser enables you to manage your source files and to explore their content. You
can easily traverse through the entire source files of your designs to identify the available code
objects and how they are interrelated.
Tip
Creating a project leads to the creation of a project file with the extension (.svap). When you
add design files to the project, the project file keeps a list of references to the location of
files on the hard disk.
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SystemVerilog-VHDL Assistant Browsers
Accessing the Projects Browser
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SystemVerilog-VHDL Assistant Browsers
Using the Projects Browser
Tip
There could be a case, when you resize SystemVerilog-VHDL Assistant browsers, in which
there would not be enough space to view both a browser’s tab and its adjacent browser tabs
at the same time. In this case, you can use the Show List icon in any tab’s toolbar to display a
list of the opened browsers for you to choose from. The number shown under the arrows on the
icon indicates the number of opened browsers that are not visible. Refer to Browser Toolbars.
Objects
Table 2-1. Projects Browser Columns
Column Name Description
Name Displays the name of the project, virtual folder, file, or code object.
Language Displays the coding language used in the corresponding file.
Line Number Displays the line number of the object in its file.
UVM/OVM Displays the UVM/OVM property of the construct if available and
only if an UVM/OVM library is added to the project.
File Path Displays the path of the referenced file on the hard disk.
File Type Displays the type of the file (source, include...).
Library Displays the build library’s name where the file is added.
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SystemVerilog-VHDL Assistant Browsers
Using the Projects Browser
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SystemVerilog-VHDL Assistant Browsers
Using the Projects Browser
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SystemVerilog-VHDL Assistant Browsers
Outline Browser
Outline Browser
The Outline browser shows the code objects available only in the active (text or visualization)
file, which is the file currently opened in the text editor. A list of the available objects along
with relevant information on each object are displayed in the browser.
The Outline browser enables you to directly navigate to the objects within your source code by
simply clicking on the required object.
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SystemVerilog-VHDL Assistant Browsers
Accessing the Outline Browser
Objects
Table 2-2. Outline Browser Columns
Column Name Description
Name Displays the name of the code object.
Scope Displays the name of the parent object that contains the current
object.
UVM/OVM Displays the UVM/OVM property of the construct if available and
only if an UVM/OVM library is added to the project.
Type Displays the type of the object. For example: Module, Instance,
Package Import, and so on.
Line Number Displays the line number of the object in the active file.
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SystemVerilog-VHDL Assistant Browsers
Using the Outline Browser
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SystemVerilog-VHDL Assistant Browsers
File Explorer Browser
Through a tree view, the File Explorer browser lists all the projects, folders and files with the
same sequence on your disk. Note that any virtual folders will not be shown in this browser.
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SystemVerilog-VHDL Assistant Browsers
Accessing the File Explorer Browser
Objects
Table 2-3. File Explorer Browser Toolbar
Name Description
Collapse All Collapses all the nodes in the browser.
Link with Editor Pressing this button highlights the file that is already active in
your editor.
View Menu Allows you to display the Available Customizations dialog box
by choosing Customize View from the drop-down list that is
shown when you click on it.
Minimize Minimizes the browser.
Maximize Maximizes the browser to fit the whole window.
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SystemVerilog-VHDL Assistant Browsers
Using the File Explorer Browser
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SystemVerilog-VHDL Assistant Browsers
Design Objects Browser
• Classes
• Interfaces
• Modules
• Packages
Accessing the Design Objects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Using the Design Objects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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SystemVerilog-VHDL Assistant Browsers
Accessing the Design Objects Browser
Note
By default, the classes shown in the Design Objects browser include only the user-created
classes of the design. To display the UVM/OVM classes, click the Show/Hide UVM/OVM
Classes button in the browser’s toolbar.
Objects
Table 2-4. Design Objects Browser Columns
Column Name Description
Name Displays the name of the project, virtual folder, file, or code object.
Line Number Displays the line number of the object in its file.
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SystemVerilog-VHDL Assistant Browsers
Using the Design Objects Browser
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SystemVerilog-VHDL Assistant Browsers
Using the Design Objects Browser
The Design Objects browser also enables you to perform operations related to linting and
downstream tools:
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SystemVerilog-VHDL Assistant Browsers
Design Hierarchy Browser
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SystemVerilog-VHDL Assistant Browsers
Accessing the Design Hierarchy Browser
Objects
Table 2-5. Design Hierarchy Browser Columns
Column Name Description
Name Displays the name of the project, virtual folder, file, or code object.
Type Displays the object’s type (project, class, module, object handle...).
UVM/OVM Displays the UVM/OVM property of the construct if available and only if
an UVM/OVM library is added to the project.
File Name Displays the name of the file where the object is included.
Library Displays the build library’s name where the file is added.
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SystemVerilog-VHDL Assistant Browsers
Using the Design Hierarchy Browser
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SystemVerilog-VHDL Assistant Browsers
Using the Design Hierarchy Browser
Related Topics
Working With Browsers
Browser Toolbars
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SystemVerilog-VHDL Assistant Browsers
Class Hierarchy Browser
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SystemVerilog-VHDL Assistant Browsers
Accessing the Class Hierarchy Browser
Objects
Table 2-6. Class Hierarchy Browser Columns
Column Name Description
Name Displays the name of the project, virtual folder, file, or code object.
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SystemVerilog-VHDL Assistant Browsers
Using the Class Hierarchy Browser
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SystemVerilog-VHDL Assistant Browsers
Using the Class Hierarchy Browser
Related Topics
Working With Browsers
Browser Toolbars
Working With Design Objects
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SystemVerilog-VHDL Assistant Browsers
Build Libraries Browser
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SystemVerilog-VHDL Assistant Browsers
Accessing the Build Libraries Browser
Objects
Table 2-7. Class Hierarchy Browser Columns
Column Name Description
Name Displays the name of the project, virtual folder, file, or code
object.
For each SystemVerilog-VHDL Assistant project, there is a default library in the Build
Libraries browser titled “work” that includes all the files that are part of the project. Whenever
you add a file to the project, this file is automatically added to the “work” library.
The files that are shown in the Build Libraries browser are only the files that contain
Compilation Units such as modules, packages, interfaces, and program blocks in
SystemVerilog; include files and class definitions would not be considered Compilation Units.
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SystemVerilog-VHDL Assistant Browsers
Using the Build Libraries Browser
It is also worth noting that a file cannot exist in more than one Library. For example, if you
create your own new library and add a file to it, this file will be automatically removed from the
“work” library. Refer to “Creating a Build Library” on page 360.
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SystemVerilog-VHDL Assistant Browsers
Errors and Warnings Tab
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SystemVerilog-VHDL Assistant Browsers
Accessing the Errors and Warnings Tab
Objects
Table 2-8. Errors and Warnings Tab Contents
Column Name Description
Description Displays a description of the error.
Resource Displays the name of the file that contains the error.
Type Displays a type of the error.
Location Displays the line number of the error within its file.
Context Displays the name of the file where the erroneous file is included.
Right-clicking an entry in the Errors and Warnings tab and choosing Go to from the displayed
popup menu opens the file containing the error in the text editor and highlights the exact
location.
The popup menu also displays other options that can be performed on entries of the Errors and
Warnings tab: Go To, Copy, Delete, Select All, Show In, and Properties.
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SystemVerilog-VHDL Assistant Browsers
Using the Errors and Warnings Tab
In addition to the Errors and Warnings tab, the detection of errors and warnings is reflected on
other SystemVerilog-VHDL Assistant browsers. SystemVerilog-VHDL Assistant reports errors
as follows:
*On the level of projects, SystemVerilog-VHDL Assistant flags the project’s node with a red
cross overlay in all browsers.
*Within the text editor, SystemVerilog-VHDL Assistant underlines the line containing the error
in red. A red cross displays next to the line containing the error, and a red mark displays in the
outline bar.
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SystemVerilog-VHDL Assistant Browsers
Using the Errors and Warnings Tab
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SystemVerilog-VHDL Assistant Browsers
Bookmarks Tab
Bookmarks Tab
The SystemVerilog-VHDL Assistant text editor allows you to add bookmarks to files in your
projects. These bookmarks appear in the Bookmarks tab. This tab opens by default when
SystemVerilog-VHDL Assistant opens.
Accessing the Bookmarks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Using the Bookmarks Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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SystemVerilog-VHDL Assistant Browsers
Accessing the Bookmarks Tab
Objects
Table 2-9. Bookmarks Tab Contents
Name Description
Description Displays the name of the bookmark as you specified it in the Add Bookmark
dialog box. Refer to “Using Bookmark Commands” on page 308
Resource Displays the name of the file where the bookmark is added.
Path Displays the path to the file where the bookmark is added.
Location Displays the number of the line where the bookmark is added in the file.
Note
Double-clicking on a line showing a bookmark’s details in the Bookmarks tab opens the
file where this bookmark is added in SystemVerilog-VHDL Assistant text editor.
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SystemVerilog-VHDL Assistant Browsers
Using the Bookmarks Tab
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SystemVerilog-VHDL Assistant Browsers
Console Tab
Console Tab
The Console tab mainly acts as a log that displays the messages issued by the tool while
opening projects, and output messages from the build tools.
Accessing the Console Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Using the Console Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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SystemVerilog-VHDL Assistant Browsers
Accessing the Console Tab
Objects
Table 2-10. Console Tab Toolbar
Button Name Description
Clear Console Deletes all data written in the Console tab.
Note
You can right-click anywhere in the Console tab and a popup menu displays showing the
various operations that can be performed on the contents of the tab such as Cut, Copy, Paste,
Select All, Find/Replace, Open Link, Clear, and Scroll Lock.
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SystemVerilog-VHDL Assistant Browsers
Using the Console Tab
1 >
For more information about the API commands supported in SystemVerilog-VHDL Assistant,
refer to SystemVerilog-VHDL Assistant API Reference Manual by choosing Help > API
Reference Manual. Information about standard Tcl commands can be found on the Tcl
Developer Xchange website at http://www.tcl.tk.
The Console tab also displays the output messages raised by Build Tools during the process of
building your projects.
Errors and warnings that are raised by build tools, such as Questa vlog and Questa vsim errors,
are parsed by the Console and then displayed in red and blue respectively.
Similarly, after running design checks, this tab reports any produced violations. The violations
are displayed as single error, warning, or note colored entries.
You can double-click on the build tool messages and design checking violations to cross-
reference to the corresponding file and line number in the text editor.
Related Topics
Building a SystemVerilog-VHDL Assistant Project
Process Console
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SystemVerilog-VHDL Assistant Browsers
History Tab
History Tab
The History tab displays older versions of a file which you can open for viewing and
comparing. Every time a file is modified and saved, the older version is not lost, it is saved for
future reference.
The History tab opens displaying the available older versions of the file.
Refer to “Checking Local History of a File” on page 301for more details on using the History
tab.
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SystemVerilog-VHDL Assistant Browsers
Accessing the History Tab
Objects
Table 2-11. History Tab Contents
Column Name Description
Revision Time Shows the revision time of the file versions.
Related Topics
Checking Local History of a File
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SystemVerilog-VHDL Assistant Browsers
Search Tab
Search Tab
The Search tab displays the search results organized into a hierarchical tree of files with the top
node holding the searched project’s name. You can expand or collapse files’ nodes to show/
hide the search results.
Accessing the Search Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Using the Search Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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SystemVerilog-VHDL Assistant Browsers
Accessing the Search Tab
Objects
Table 2-12. Search Tab Toolbar
Button Name Description
Show Next Match Goes to the next entry matching your search in the Search tab.
Show Previous Goes to the previous entry matching your search in the Search
Match tab.
Remove Selected Deletes the selected entry from the Search tab.
Matches
Remove All Deletes all the entries from the Search tab.
Matches
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SystemVerilog-VHDL Assistant Browsers
Using the Search Tab
By clicking on the View Menu button , you can choose to display the search results in a List
or Tree view by choosing Show As List or Show As Tree from the dropdown menu.
Related Topics
Search Dialog Box
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SystemVerilog-VHDL Assistant Browsers
Properties Tab
Properties Tab
The Properties tab displays some properties and their corresponding values for a selected
object.
Note
By passing the mouse over any object in one of SystemVerilog-VHDL Assistant browsers, a
tooltip displays giving information.
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SystemVerilog-VHDL Assistant Browsers
Accessing the Properties Tab
Objects
Table 2-13. Properties Tab Columns
Column Name Description
Property Displays the property name.
Value Displays the value of the corresponding property.
Browser Toolbars
The following table lists all the buttons found in SystemVerilog-VHDL Assistant browsers and
their functions:
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SystemVerilog-VHDL Assistant Browsers
Browser Toolbars
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Chapter 3
SystemVerilog-VHDL Assistant Menus
SystemVerilog-VHDL Assistant contains a number of menus with commands that help you
manage your projects and files, and perform various operations on them. All project-related
menu options are disabled if no projects are opened.
SystemVerilog-VHDL Assistant Standard Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
File Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
New Project Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Accessing the New Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
New Template Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Add File Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Add Files to Project Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Import From Questa Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Import From Questa - Import File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Import From Questa - Import Settings (_info) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Import From Questa - Import Settings (.ini). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Create New Virtual Folder Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Save As Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Edit Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Search Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Search Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Find/Replace Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Navigate Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Open Resource Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Open Module Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Open Class Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Go to Line Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Build Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
New Build Library Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Edit Include Search Path List Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Edit Linked Libraries List Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Tools Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Export to Image File Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Project Settings Dialog Box - Build Settings Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Project Settings Dialog Box - QuestaSim Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Project Settings Dialog Box - Questa vsim Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Project Settings Dialog Box - Default Clean Command Page . . . . . . . . . . . . . . . . . . . . . . 147
Project Settings Dialog Box - Check Settings Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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SystemVerilog-VHDL Assistant Menus
SystemVerilog-VHDL Assistant Standard Toolbar
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SystemVerilog-VHDL Assistant Menus
SystemVerilog-VHDL Assistant Standard Toolbar
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SystemVerilog-VHDL Assistant Menus
SystemVerilog-VHDL Assistant Standard Toolbar
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SystemVerilog-VHDL Assistant Menus
SystemVerilog-VHDL Assistant Standard Toolbar
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SystemVerilog-VHDL Assistant Menus
File Menu
Related Topics
Creating a Project
Saving All Files
Creating a Template Project
Printing a File
Creating a New File
Editing Operations
Adding Existing Files
Using Bookmark Commands
Adding Template Files
Searching for Text in SystemVerilog-VHDL Assistant Projects
Opening a Project
Help Menu
Opening Design Files
SystemVerilog-VHDL Assistant Text Editor
Saving a File
File Menu
The File menu contains several commands that mostly affect your design files.
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SystemVerilog-VHDL Assistant Menus
File Menu
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SystemVerilog-VHDL Assistant Menus
File Menu
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SystemVerilog-VHDL Assistant Menus
New Project Wizard
Note
If the project file (.svap) is set as read-only, you will not be able to perform any operations
on the project through SystemVerilog-VHDL Assistant such as adding files, removing files,
checking, building, visualization, and so on.
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SystemVerilog-VHDL Assistant Menus
Accessing the New Project Wizard
Objects
Table 3-4. New Project Wizard Contents - New SystemVerilog-VHDL Assistant
Project Page
Name Description
Project name Define the name of the new project in the text field. SystemVerilog-
VHDL Assistant provides the following default name “my_projectn”
where “n” is a number that increments on adding more projects.
Allowed characters are letters, digits and underscore.
Location Specify the location of the new project. SystemVerilog-VHDL
Assistant provides a default location as follows “HDS_home\
svassistant”. You can enter the location by using a pre-defined
environment variable, absolute path or relative path.
File path This label displays the location and the name of the project according
to your entries.
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SystemVerilog-VHDL Assistant Menus
Accessing the New Project Wizard
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SystemVerilog-VHDL Assistant Menus
Accessing the New Project Wizard
Objects
Table 3-5. New Project Wizard Contents - Settings Page
Name Description
I want to add the UVM/ Allows you to choose one of the supplied source libraries to the
OVM source files now project.
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SystemVerilog-VHDL Assistant Menus
Accessing the New Project Wizard
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SystemVerilog-VHDL Assistant Menus
Accessing the New Project Wizard
Objects
Table 3-6. New Project Wizard Contents - Add Files Page
Name Description
From directory Directory from which you want to add files
Filter selection Drop-down list of file extensions to filter files by file type.
Browse button Browse for files you want to add
Filter selection Choose which file types to search; the default is .svt
Click Finish and the new project and added files (if any) appear in the Projects browser.
Related Topics
File Menu
Projects Browser
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SystemVerilog-VHDL Assistant Menus
Accessing the New Project Wizard
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SystemVerilog-VHDL Assistant Menus
New Template Project Wizard
Objects
Table 3-7. New Template Project Wizard Contents
Name Description
Project name Enter the name of the new template project. Allowed characters are
letters, digits and underscore.
Location Specify the location in which the new template project will be saved.
You can click the adjacent Browse button to do that.
File path This label displays the location and the name of the template project
according to your entries.
Description Enter an optional description for the new template project.
Cancel Clicking this button closes the wizard and discards your entries.
Click the Finish button to create your project and add files to it later. Click the Next button to
display the New Template Project Wizard - Add Files page.
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SystemVerilog-VHDL Assistant Menus
New Template Project Wizard
Objects
Table 3-8. New Project Template Wizard Contents - Add Files Page
Name Description
From directory Directory from which you want to add files
Filter selection Drop-down list of file extensions to filter files by file type
Browse button Browse for files you want to add
Filter selection Choose which file types to search; the default is .svt
Click Finish and the new project and added files (if any) appear in the Projects browser.
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SystemVerilog-VHDL Assistant Menus
New Template Project Wizard
Related Topics
Creating a Template Project
Adding Template Files
Add Files to Project Dialog Box
Referencing a Template Project
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SystemVerilog-VHDL Assistant Menus
Add File Dialog Box
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SystemVerilog-VHDL Assistant Menus
Add File Dialog Box
Objects
Table 3-9. Add File Dialog Box Contents
Name Description
File name Enter the name of the new file and use the adjacent drop-down list to select
the file’s extension. Allowed characters for the file’s name are letters, digits
and underscore. If you do not choose an extension, the default will be
file_name.svh. If you are adding a file to a template project, the default
extension will be file_name.svt.
Location Specify the location on which the new file shall be saved. You can use the
adjacent Browse button. The default location is the current project’s location,
that is, the location on which the (.svap) file is saved.
File path This label displays the location and the name of the file according to your
entries.
Virtual folder Allows you to specify the virtual folder in which the new file will be added.
You can use the adjacent Browse button.
Opens the help page of Adding a New File from the tool’s documentation. A
pane opens in the right-hand side of the Add File dialog box where the content
displays. See Figure 3-7
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SystemVerilog-VHDL Assistant Menus
Add File Dialog Box
Tip
If the enter path does not exist, SystemVerilog-VHDL Assistant creates it in addition to
creating a file with your given extension. SystemVerilog-VHDL Assistant also identifies the
language of the file through the extension.
Related Topics
File Menu
Removing Files From a Project
Add Files to Project Dialog Box
Creating a Virtual Folder
Adding a New File to a Project
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SystemVerilog-VHDL Assistant Menus
Add Files to Project Dialog Box
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SystemVerilog-VHDL Assistant Menus
Add Files to Project Dialog Box
Objects
Table 3-10. Add Files to Project Dialog Box Contents
Name Description
From directory Browse for the directory of the files you intend to add. The default path
is that on which the project is saved. Note that you can enter a Network
path if the files you intend to add are on a remote place. You can also use
a pre-defined environment variable, absolute path or relative path.
Filter Selection Filters the content of the folder, from which you intend to select your
files, to display “Verilog Files”, “Template Files”, “Visualization Files”
or “All Files”. This field is editable; you can modify the settings.
Adjacent panes Displays an expanded tree of the path specified in the “From directory”
field. You can do one of two actions:
1. Specify the required folder by selecting its adjacent check box. By
that, all the folder’s contents (files or subfolders) on the right-hand
side are automatically selected. Yet, you can individually uncheck
any unwanted files or
subfolders.
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SystemVerilog-VHDL Assistant Menus
Import From Questa Dialog Box
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SystemVerilog-VHDL Assistant Menus
Import From Questa - Import File
Objects
Table 3-11. Import from Questa - Import File Dialog Box Contents
Name Description
ModelSim file Allows you to browse to the path of the .ini file or the _info file.
Root folder name Allows you to specify the virtual folder where the imported files
will be added by clicking on the Browse button and choosing the
virtual folder. Allowed characters are letters, digits and
underscore.
Create Virtual Folders If selected, this option automatically creates Virtual Folder for
Automatically each directory level in the source path.
Overwrite Current Existing If selected, the imported libraries overwrite already existing
Libraries libraries.
Opens the help page of the import file page of the Import from
Questa dialog box from the tool’s documentation. A pane opens
in the right-hand side of the dialog box where the content
displays.
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SystemVerilog-VHDL Assistant Menus
Import From Questa - Import File
Clicking the Next button takes you to the Import From Questa dialog box, Import Settings page
corresponding to the chosen ModelSim_info/ .ini file.
Related Topics
Add Files to Project Dialog Box
Importing Files Using Questa
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SystemVerilog-VHDL Assistant Menus
Import From Questa - Import Settings (_info)
Objects
Table 3-12. Import from Questa - Import File (_info) Dialog Box Contents
Name Description
Build Library A drop-down menu which allows you to specify the name of the
Build library to which files will be added. By default, files are
added to a build library with the same name as the parent
directory of the _info file.
Specify associated Enables you to specify the path of the ModelSim.ini file in the Ini
modelsim.ini file file path text box.
Opens the help page of the import settings (_info) page of the
Import from Questa dialog box from the tool’s documentation. A
pane opens in the right-hand side of the dialog box where the
content displays.
Related Topics
File Menu
Import From Questa - Import File
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SystemVerilog-VHDL Assistant Menus
Import From Questa - Import Settings (.ini)
Objects
Table 3-13. Import from Questa - Import Settings (.ini) Dialog Box Contents
Name Icon Description
Import as Source Allows you to import the selected libraries as Source
button libraries.
Import as External Allows you to import the selected libraries as External
button libraries.
Don’t Import button Allows you not to import the selected libraries in your
project.
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Import From Questa - Import Settings (.ini)
Table 3-13. Import from Questa - Import Settings (.ini) Dialog Box Contents
Name Icon Description
Select All Allows you to select all the available libraries.
Restore Defaults Allows you to restore all build libraries to their original
import settings.
Help Opens the help page of the import settings (_ini) page of the
Import from Questa dialog box from the tool’s
documentation. A pane opens in the right side of the dialog
box where the content displays.
Note
You can also import the selected libraries through the library popup menu.
Related Topics
File Menu
Import From Questa - Import File
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SystemVerilog-VHDL Assistant Menus
Create New Virtual Folder Dialog Box
Objects
Table 3-14. Create New Virtual Folder Dialog Box Contents
Name Description
Virtual Folder Name Define the name of the new virtual folder. Allowed characters
are letters, digits and underscore.
Related Topics
Removing a Virtual Folder From a Project
Add Files to Project Dialog Box
Add File Dialog Box
Creating a Virtual Folder
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SystemVerilog-VHDL Assistant Menus
Save As Dialog Box
Objects
Table 3-15. Save As Dialog Box Contents
Name Description
File name Enter the name of the file. Allowed characters are letters, digits
and underscore.
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SystemVerilog-VHDL Assistant Menus
Edit Menu
Note
SystemVerilog-VHDL Assistant enables you to save a file even when no project opens. In
such a case, the Virtual folder field is dimmed, the Add new file to project option is not
displayed and the default file location is $SVASSISTANT_HOME.
Related Topics
File Menu
Saving All Files
Saving a File
Edit Menu
The Edit menu contains several data management commands that mostly apply to the text
editor.
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SystemVerilog-VHDL Assistant Menus
Edit Menu
Related Topics
Undo
Cut, Copy, Paste, and Paste Column
Redo
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SystemVerilog-VHDL Assistant Menus
Search Menu
Search Menu
The Search menu contains commands that help you navigate through the contents of the file
currently opened in the text editor.
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SystemVerilog-VHDL Assistant Menus
Search Dialog Box
Objects
Table 3-18. Search Dialog Box Contents
Name Description
Containing text Enables you to enter the search string you want to look for.
Case sensitive Enables you to run a case-sensitive search.
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SystemVerilog-VHDL Assistant Menus
Search Dialog Box
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SystemVerilog-VHDL Assistant Menus
Search Dialog Box
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SystemVerilog-VHDL Assistant Menus
Search Dialog Box
Objects
Table 3-19. Replace Text Matches Dialog Box Contents
Name Description
With Enter the new text string from the drop-down list to replace the
original source.
Preview View changes before applying them. The Refactored Source
pane displays a preview of the file after the changes are applied,
as shown in Replace Text Matches - Preview Page.
Related Topics
Search Menu
Search Tab
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SystemVerilog-VHDL Assistant Menus
Find/Replace Dialog Box
Objects
Table 3-20. Find/Replace Dialog Box Contents
Name Description
Find Enter the search string you need to look for within the file.
Replace with Enter the replacement text string.
Direction Enables you to specify the direction of your search. Choose
Forward if you are searching for instances of the text that are
found after the cursor’s location, or Backward if you are
searching for instances of the text that are found before the
cursor’s location.
Scope Allows you to limits the search only to the text you have
selected or all the text in the file.
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Find/Replace Dialog Box
Related Topics
Search Menu
Finding Text in Files
Search and Navigation
Replacing a Text String
Navigating and Finding Design Objects
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SystemVerilog-VHDL Assistant Menus
Navigate Menu
Navigate Menu
The Navigate menu contains commands that help you navigate through the contents of the
opened projects.
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SystemVerilog-VHDL Assistant Menus
Open Resource Dialog Box
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SystemVerilog-VHDL Assistant Menus
Open Resource Dialog Box
Objects
Table 3-22. Open Resource Dialog Box Contents
Name Description
Select an item to open This is where you type the name of the item you want to open.
Matching items Displays a list of found items that match what is written in the
Select an item to open text box. As you type more letters in the
Select an item to open text box, this list becomes shorter. Choose
an item to open.
Status bar Choosing an item in the Matching items pane activates the status
bar which displays the path to that item.
Open Clicking it opens the resource chosen from the Matching items
pane. By clicking the arrow next to the Open button, a list displays
from which you choose the editor to open your file with;
SystemVerilog-VHDL Editor, Text Editor, System Editor, In-Place
Editor, Default Editor or Other which you specify.
Opens the help page of the Open Resource dialog box from the
tool’s documentation. A pane opens in the right-hand side of the
dialog box where the content displays.
Note
When you click the Open button, the selected file displays in the text editor and highlighted
in the Projects browser.
Related Topics
Open Module Dialog Box
Opening Design Files
Open Class Dialog Box
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SystemVerilog-VHDL Assistant Menus
Open Module Dialog Box
Objects
Table 3-23. Open Module Dialog Box Contents
Name Description
Select an item to open This is where you type the name of the Module you want to open.
Matching items Displays a list of found items that match what is written in the
Select an item to open text box. As you type more letters in the
Select an item to open text box, this list becomes shorter. Choose
an item to open.
Status bar Choosing an item in the Matching items pane activates the status
bar which displays the Module’s name and the project where it’s
found.
Opens the help page of the Open Module dialog box from the tool’s
documentation. A pane opens in the right-hand side of the dialog
box where the content displays.
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SystemVerilog-VHDL Assistant Menus
Open Module Dialog Box
Related Topics
Open Resource Dialog Box
Opening Design Files
Open Class Dialog Box
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SystemVerilog-VHDL Assistant Menus
Open Class Dialog Box
Objects
Table 3-24. Open Class Dialog Box Contents
Name Description
Select an item to open This is where you type the name of the Class you want to open.
Matching items Displays a list of found items that match what is written in the
Select an item to open text box. As you type more letters in the
Select an item to open text box, this list becomes shorter. Choose
an item to open.
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SystemVerilog-VHDL Assistant Menus
Open Class Dialog Box
Related Topics
Open Resource Dialog Box
Opening Design Files
Open Module Dialog Box
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SystemVerilog-VHDL Assistant Menus
Go to Line Dialog Box
Objects
Table 3-25. Go to Line Dialog Box Contents
Name Description
Enter line number (1..n) Type the line number you need to go to in the currently active file.
Related Topics
Search Menu
Navigating and Finding Design Objects
Search and Navigation
Using the Go to Line Command
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SystemVerilog-VHDL Assistant Menus
Build Menu
Build Menu
The Build menu contains the settings and commands that manage the integration of
SystemVerilog-VHDL Assistant with your downstream tools.
After finishing your work on the project, the next step would be to build the project and
integrate with your downstream tools (such as Questa® or ModelSim®). This process starts by
creating logical libraries and adding files to them, configuring the project build settings,
generating the Makefile, and then finally building the project.
The Build menu enables you to handle the larger part of that process through the following
commands:
Table 3-26. Build Menu Contents
Name Description
Build Target This menu lists the main targets for build tools which are
available in the generated Makefile. When you select one of the
targets from the cascaded menu, SystemVerilog-VHDL
Assistant will run the “Make” utility to build that target.
Build Project (Ctrl+B) Compiles the selected project. This command runs based on the
compilation targets of the active downstream provider.
• For example, if the active downstream provider is
QuestaSim, then this command will build the project using
the “compile_all” target.
Clean Project Removes any unwanted output that might have resulted from
previously building the selected project (such as .dat files that
resulted from previous compilations). This command runs the
clean target of the active downstream provider.
• For example, if the active downstream provider is
QuestaSim, then this command will run the “clean_all”
target which uses the Questa Clean utility.
Clean and Build Project Runs both the Build Project (Ctrl+B) and Clean Project
commands explained above.
Compile File Compiles the selected file individually. This command runs the
compilation targets of the active downstream provider.
• For example, if the active downstream provider is
QuestaSim, then this command will build the project using
the “compile_all” target.
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SystemVerilog-VHDL Assistant Menus
Build Menu
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SystemVerilog-VHDL Assistant Menus
New Build Library Dialog Box
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SystemVerilog-VHDL Assistant Menus
New Build Library Dialog Box
Objects
Table 3-27. New Build Library Dialog Box Contents
Name Description
Library Name Define a name for the new library. Allowed characters are letters,
digits and underscore.
Library Type Specify whether the library is a User Library or an External
Library. A new Library is set as a user library by default,
however, you can set it as an external library if it shall contain
pre-compiled objects (rather than SystemVerilog-VHDL
Assistant HDL files).
Library Mapping Specify a location on your hard disk for the downstream tool to
place the output of this library. For example: $(PROJ_DIR)/
libraries/<library_name>. You can use the built-in variable
$(PROJ_DIR) which refers to the directory of the project. You
can use the Browse button to navigate to the desired location.
Note: Library mapping does not accept relative paths.
Include Search Path For Verilog projects, SystemVerilog-VHDL Assistant
automatically detects the search paths of the `include files within
the current project. Yet, you can explicitly set your search paths
by doing one of the following:
• Manually type the paths separated by spaces. If a single path
already includes spaces, it should be enclosed in double-
quotes or curly braces.
for example, {C:/temp folder} D:/temp
• Specify the paths using the Edit Include Search Path List
dialog box opened by clicking Edit. Refer to “Edit Include
Search Path List Dialog Box” on page 132 for details.
Linked Libraries If your library needs to refer to objects from other libraries, then
define your libraries by doing one of the following:
• Manually type the names of those libraries separated by
spaces. If a single library name already includes spaces, this
name should be enclosed in double-quotes or curly braces.
for example, {MY UVM LIB} MY_ASSERTION_LIB
• Specify the library names through the Edit Linked Libraries
List dialog box. Refer to “Edit Linked Libraries List Dialog
Box” on page 134 for details.
Note that SystemVerilog-VHDL Assistant can automatically
detect the linked libraries as long as their resources are managed
by the current project.
Opens the help page from the tool’s documentation regarding
this topic. A pane opens in the right-hand side of the New Build
Library dialog box where the content displays.
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SystemVerilog-VHDL Assistant Menus
New Build Library Dialog Box
Tip
: After creating a library, you have the ability to modify the entries you have made in the
New Build Library dialog box. This can be done through the Edit Build Library dialog box
which is accessed by right-clicking on the library’s node in the Build Libraries browser and
selecting Library Properties from the popup menu. The contents of the Library Settings dialog
box is the same as that of the New Build Library dialog box. See Modifying Library Properties.
Related Topics
Build Menu
Building a SystemVerilog-VHDL Assistant Project
Build Libraries Browser
Creating a Build Library
Project Settings Dialog Box - Build Settings Page
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SystemVerilog-VHDL Assistant Menus
Edit Include Search Path List Dialog Box
Objects
Table 3-28. Edit Include Search Path List Dialog Box Contents
Name Description
Edit Include Search Path List This list displays the `include search paths which have been
added to the library using the Add button. Note that the list
also displays the search paths that were manually defined for
the library through the New Build Library Dialog Box (if
any).
New Opens the File Location dialog box through which you can
add the paths where SystemVerilog-VHDL Assistant should
search for `include files.
Remove If you need to remove a path from the list, select it and click
Remove.
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SystemVerilog-VHDL Assistant Menus
Edit Include Search Path List Dialog Box
Table 3-28. Edit Include Search Path List Dialog Box Contents (cont.)
Name Description
Up/Down Use these buttons to determine the priority of the paths, that
is, the order by which SystemVerilog-VHDL Assistant
should search for the `include files. Select the required path
from the list and then click Up or Down as needed until it is
placed in the correct position.
Opens the help page from the tool’s documentation
regarding this topic. A pane opens in the right-hand side of
the Edit Include Search Path List dialog box where the
content displays.
Related Topics
New Build Library Dialog Box
Creating a Build Library
Building a SystemVerilog-VHDL Assistant Project
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SystemVerilog-VHDL Assistant Menus
Edit Linked Libraries List Dialog Box
Objects
Table 3-29. Edit Linked Libraries List Dialog Box Contents
Name Description
Edit Include Libraries List This list displays the linked libraries which you have added
through the New button. Note that the list also displays the
linked libraries that were manually defined for the library
through the New Build Library Dialog Box (if any).
As mentioned earlier, linked libraries are those which
contain the objects that your library needs to refer to.
New Opens the Add New Library dialog box through which you
can add the name of each linked library to the list.
Remove If you need to remove a linked library from the list, select it
and click Remove.
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SystemVerilog-VHDL Assistant Menus
Edit Linked Libraries List Dialog Box
Table 3-29. Edit Linked Libraries List Dialog Box Contents (cont.)
Name Description
Up/Down Use these buttons to determine the priority of the linked
libraries, that is, the order by which SystemVerilog-VHDL
Assistant should search for objects in those libraries. Select
the required linked library from the list and then click Up or
Down as needed until it is placed in the correct position.
Opens the help page from the tool’s documentation
regarding that topic. A pane opens in the right-hand side of
the Edit Include Libraries List dialog box where the content
displays.
Related Topics
New Build Library Dialog Box
Creating a Build Library
Building a SystemVerilog-VHDL Assistant Project
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SystemVerilog-VHDL Assistant Menus
Tools Menu
Tools Menu
The Tools menu contains different commands that enable you to visualize your test bench,
check your code to make sure it adheres to your coding standards, create new browsers, and set
your font options.
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SystemVerilog-VHDL Assistant Menus
Tools Menu
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SystemVerilog-VHDL Assistant Menus
Export to Image File Dialog Box
• Use the Export to Image File button from the standard toolbar.
The Export to Image File dialog box enables you to export your visualization file to an image
file and save it anywhere on your hard disk with a file extension .jpg, .gif, or .png. You can then
insert it into your own documentation files.
Figure 3-25. Export to Image File Dialog Box
Objects
Table 3-31. Export to Image File Dialog Box Contents
Name Description
File name Specifies a name for your file
Save as type Specifies the type of file from the drop-down list
Tip
: For a high quality image, choose the default option Portable Network Graphics (*.png)
from the drop-down list of the Save as type field.
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Export to Image File Dialog Box
Related Topics
Tools Menu
Statically Visualizing UVM/OVM Projects and Classes
SystemVerilog-VHDL Assistant Standard Toolbar
Dynamically Visualizing UVM/OVM Test Benches
Visualizing a Class
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SystemVerilog-VHDL Assistant Menus
Project Settings Dialog Box - Build Settings Page
• You specify which one of the available downstream tools is active for building the
project (for example: QuestaSim, ModelSim, and so on). These are also referred to as
downstream providers.
• You define the command template of each utility within the downstream tool (for
example, within QuestaSim, you get to define the command template of the Questa vlog
utility, the Questa vsim utility, and so on).
Note
A downstream tool is more likely to be a family that consists of several utilities. For
example, QuestaSim would be the family whereas Questa vlog and Questa vsim
would be the utilities (which are also referred to in SystemVerilog-VHDL Assistant as
build tools).
When you build the project later, it is built based on one of these utilities according to
your choice (see “Running a Project Makefile” on page 365). Each utility is run using
the command template configured in the Project Settings Dialog Box - Build Settings
Page.
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SystemVerilog-VHDL Assistant Menus
Project Settings Dialog Box - Build Settings Page
Objects
Table 3-32. Project Settings Dialog Box - Build Settings Page Contents
Name Description
Active build configuration Use the drop-down list to select the name of the downstream
family you will use to build the project (such as QuestaSim).
Also you can use a pre-defined environment variable, absolute
path or relative path.
Project build defines Instead of adding `define directives in your HDL code, you
can use this table to specify the define macros that need to be
passed during building the project.
To make an entry in the table, single-click in the cell, type
your entry, and then press Enter. You can alternatively press
the New button and type your entries.
To delete an entry, select the entry, and press Delete or the
Remove button.
Restore Defaults Disregards any modifications you have made and reverts to
the default define macros.
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SystemVerilog-VHDL Assistant Menus
Project Settings Dialog Box - Build Settings Page
Table 3-32. Project Settings Dialog Box - Build Settings Page Contents (cont.)
Name Description
Apply Click it after Choosing the Active build configuration and
adding or removing an entry to apply the new changes.
OK Closes the dialog box after saving the new modifications.
Cancel Cancels the operation and closes the dialog box.
Having selected the downstream family, you now select its corresponding node from the tree.
For example, you can open the QuestaSim page.
Related Topics
Running a Project Makefile
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SystemVerilog-VHDL Assistant Menus
Project Settings Dialog Box - QuestaSim Page
Objects
Table 3-33. Project Settings Dialog Box - QuestaSim Page Contents
Name Description
Downstream Provider Displays the name of the downstream tool family you are
configuring.
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SystemVerilog-VHDL Assistant Menus
Project Settings Dialog Box - QuestaSim Page
Table 3-33. Project Settings Dialog Box - QuestaSim Page Contents (cont.)
Name Description
Location Specify the location of the build tools’ executable files on
your hard disk, that is, the location of the utilities such as
Questa vlog and Questa vsim. SystemVerilog-VHDL
Assistant automatically detects this location and stores it in
the variable $(QUESTA_BIN_DIR), but you can change the
value of this variable if necessary.
Variable Name Use the table to set the variables that are applicable to all
Value the build tools of the current downstream family. The
variables defined in this table will apply to the project on
building it. Define a Variable Name and give it a Value, or
you can edit existing variables.
To use the table, single-click in the cell, type your entry,
and then press Enter. You can alternatively press the New
button and type your entries.
To delete an entry, select the entry, and press Delete or the
Remove button. Refer to “Setting Build Variables” on
page 364.
Note
The variables you define are the switches passed later to the command used in building the
project.
Related Topics
Setting Build Variables
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Project Settings Dialog Box - Questa vsim Page
Objects
Table 3-34. Project Settings Dialog Box - “Questa vsim” Page Contents
Name Description
Command template Shows the command template of the utility. This template
mimics the command needed to run the utility. The command
template constitutes of a series of variables, some are user-
defined variables and some are internal variables. You can
change the values of existing variables through the table, group
variables, or add new ones according to your build needs. Refer
to “Editing Command Templates” on page 363.
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Project Settings Dialog Box - Questa vsim Page
Table 3-34. Project Settings Dialog Box - “Questa vsim” Page Contents (cont.)
Name Description
Variable Name This table shows the user-defined variables and their default
Value values. You can edit these values according to your needs, or you
can add new variables as required (refer to “Editing Command
Templates” on page 363 and to “Setting Build Variables” on
page 364).
To edit in the table, single-click in the cell, type your entry, and
then press Enter. You can alternatively press the New button and
type your entries.
To delete an entry, select the entry, and press Delete or the
Remove button.
For each downstream family, a page exists for editing the template of the default clean
command. The settings in this page apply to all the utilities in the family that produce output
that might require cleaning at some point. For example, in case of the QuestaSim family, the
Questa vlog utility produces (.dat) files that can require cleaning. Refer to “Project Settings
Dialog Box - Default Clean Command Page” on page 147.
Related Topics
Editing Command Templates
Setting Build Variables
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SystemVerilog-VHDL Assistant Menus
Project Settings Dialog Box - Default Clean Command Page
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SystemVerilog-VHDL Assistant Menus
Project Settings Dialog Box - Default Clean Command Page
Objects
Table 3-35. Project Settings Dialog Box - Default Clean Command Page
Contents
Name Description
Command template Shows the template of the default clean command for all the
build tools (that is, the utilities) that produce output. The
command template constitutes of a series of variables, some are
user-defined variables and some are internal variables. You can
change the values of existing variables through the table, group
variables, or add new ones according to your build needs. Refer
to “Editing Command Templates” on page 363.
Variable Name This table shows the user-defined variables and their default
Value values; you can edit these values according to your needs. You
can also add new variables as required (refer to “Editing
Command Templates” on page 363 and to “Setting Build
Variables” on page 364).
To edit in the table, single-click in the cell, type your entry, and
then press Enter. You can alternatively press the New button and
type your entries.
To delete an entry, select the entry, and press Delete or the
Remove button.
Apply Stores both the library and project build settings information that
will be used to generate a Makefile. The information is stored in
XML format in a file named <project_name>.bld that resides in
the same location as the project <project>.svap.
Related Topics
Tools Menu
Internal Variables
Building a SystemVerilog-VHDL Assistant Project
Build Settings
New Build Library Dialog Box
Specifying Project Settings
Build Libraries Browser
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SystemVerilog-VHDL Assistant Menus
Project Settings Dialog Box - Check Settings Page
Objects
Table 3-36. Project Settings Dialog Box - Check Settings Page Contents
Name Description
Policy Location Specify or browse to the path location of your policy.
TB Policy Allows you to choose from the drop-down menu the policy
you want to apply to the DesignChecker analysis of your test
bench. The default policy for test benches is
Verification_UVM_Policy/Verification_OVM_Policy.
RTL Policy Allows you to choose from the drop-down menu the policy
you want to apply to the DesignChecker analysis of your RTL
design. The default policy for RTL designs is
My_Essentials_Policy.
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Project Settings Dialog Box - Check Settings Page
Table 3-36. Project Settings Dialog Box - Check Settings Page Contents (cont.)
Name Description
RuleSet Location Specify or browse to the path location of your ruleset.
Exclusion File Location Specify or browse to the path location of your exclusion file.
Enable pragma exclusions Check/Uncheck this option to enable/disable pragma
exclusions. On checking this option, you can skip RTL code
blocks while running a DesignChecker analysis.
Manage Policies/ RuleSets Clicking this button invokes the DesignChecker tool in order
to set up policies and rules.
Restore Defaults Disregards any modifications you have made and reverts to
the default define macros.
Apply Click it to apply the new changes.
Related Topics
Tools Menu
Check Settings
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SystemVerilog-VHDL Assistant Menus
Window Menu
Window Menu
The Window menu contains several commands that mostly affect your browsers.
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SystemVerilog-VHDL Assistant Menus
Window Menu
Note
If you want to bring a specific browser to focus, you can easily click its name in the
Windows > Show Browser menu.
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SystemVerilog-VHDL Assistant Menus
Create New Browser Dialog Box
Objects
Table 3-38. Create New Browser Dialog Box Contents
Name Description
Name Enter the name of the new browser.
Opens the help page of ‘Create New Browser’ from the tool’s
documentation. A pane opens in the right-hand side of the Create
New Browser dialog box where the content displays.
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Create New Browser Dialog Box
On clicking OK, the new browser displays in SystemVerilog-VHDL Assistant with the name
you specified and the same content of the original browser.
Note
Custom browsers are remembered throughout a SystemVerilog-VHDL Assistant session;
they are shown in the Window > Show Browser cascaded menu. The custom browsers’
names are cleared from the cascaded menu when the session is closed except the ones that were
still opened; these are restored on the next invocation.
Related Topics
Window Menu
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SystemVerilog-VHDL Assistant Menus
Help Menu
Help Menu
This menu provides links to SystemVerilog-VHDL Assistant online help, Tutorials, Release
Notes, support and contact information.
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SystemVerilog-VHDL Assistant Menus
Help Browser
Help Browser
To access: Help > Search Help
The Help browser enables you to search for any word, expression, topic within the tool’s
documentation. This browser is not displayed by default when SystemVerilog-VHDL Assistant
is invoked.
Figure 3-32. Help Browser
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SystemVerilog-VHDL Assistant Menus
Help Browser
Objects
Table 3-40. Help Browser Contents
Name Description
Search Expression This is where you enter the expression that you wish to search
for in the tool’s documentation. Click Go to start your search.
Contents Clicking on it takes you to the contents page of the Online
Help.
Related Topics Displays help topics related to the searched for expression.
Bookmarks Searches within the topics that contain bookmarks.
Index Displays the Index of the Online Help where you can type a
word to find.
Related Topics
Help Menu
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SystemVerilog-VHDL Assistant Menus
Popup Menus
Popup Menus
In SystemVerilog-VHDL Assistant, some dialog boxes/tabs are only accessible through popup
menus in the standard browsers.
New Interface Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Extend Class Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Preferences (Filtered) Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Available Customizations Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Switch to Editor Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Import From Filelist - File Location Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Class Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
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SystemVerilog-VHDL Assistant Menus
New Interface Dialog Box
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SystemVerilog-VHDL Assistant Menus
New Interface Dialog Box
Objects
Table 3-41. New Interface Dialog Box Contents
Name Description
File name Enter the name of the new interface file and then use the adjacent
drop-down list to select the file’s extension in order for
SystemVerilog-VHDL Assistant to determine the file type. The
default extension is file_name.sv. Allowed characters for the
file’s name are letters, digits and underscore.
Location Specify the location in which the new file shall be saved. The
default location is the current project’s location, that is, the
location in which the (.svap) file is saved.
File path This label displays the locations and the names of the files
according to your entries.
Virtual folder Allows you to specify the virtual folder in which the new file will
be added.
Template File Allows you to specify the path to template file used.
You can include another template file from your project using
one of these formats.
%INCLUDE(-templatePath "<templateFilePath>")
%INCLUDE(-templateCategory "Header" -
templateName "file_header.svt" -templateProject
"default_templates")
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New Interface Dialog Box
Related Topics
Add Files to Project Dialog Box
Generating Interfaces
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SystemVerilog-VHDL Assistant Menus
Extend Class Dialog Box
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SystemVerilog-VHDL Assistant Menus
Extend Class Dialog Box
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Extend Class Dialog Box
Objects
Table 3-42. Extend Class Dialog Box Contents
Name Description
Base Class Parameters Edit parameters extended in the new class. These parameters are
carried over from the base class.
Class name Enter the name of the new Class. If not specified, Class Name
will be the same as the File Name.
Create class in Allows you to create the class either in the active file in the text
editor or in a newly created file.
File name Enter the name of the file and then use the adjacent drop-down
list to select the file’s extension in order for SystemVerilog-
VHDL Assistant to determine the file type. The default
extension is file_name.svh. Note that this option is only
available if New File option is selected or the active file is
“Untitled”.
Location Specify the location in which the new file shall be saved. You
can use the Browse button for that. The default location is the
current project’s location, that is, the location in which the
(.svap) file is saved. Note that this option is only available if
New File option is selected or the active file is “Untitled”.
File path This label displays the locations and the names of the files
according to your entries.
Virtual folder Allows you to specify the virtual folder in which the new file
will be added.
Template File Allows you to specify the path to template file used.
You can include another template file from your project using
one of these formats.
%INCLUDE(-templatePath "<templateFilePath>")
%INCLUDE(-templateCategory "Header" -
templateName "file_header.svt" -templateProject
"default_templates")
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Extend Class Dialog Box
Related Topics
Extending Classes
Class Hierarchy Browser
Working With Design Objects
Add Files to Project Dialog Box
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SystemVerilog-VHDL Assistant Menus
Preferences (Filtered) Dialog Box
The Preferences (Filtered) dialog box primarily lets you control the display and grouping of
object types within a browser. That is, you can choose which objects to show or hide within a
browser and which objects to group in folders.
This dialog box is available in all browsers, whether in SystemVerilog-VHDL Assistant
standard browsers or in cloned and custom browsers.
Figure 3-35. Preferences (Filtered) Dialog Box
Objects
Table 3-43. Preferences (Filtered) Dialog Box Contents
Name Description
Object Type This column lists all the objects you can display in the browser.
Show Selecting the check box will display the current object in the
browser. Otherwise, the object will be hidden.
Group Selecting the check box will lead to grouping the current object
type in folders within the browser.
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SystemVerilog-VHDL Assistant Menus
Preferences (Filtered) Dialog Box
Related Topics
Customizing Browser Content
Design Hierarchy Browser
Projects Browser
Class Hierarchy Browser
Outline Browser
Build Libraries Browser
Design Objects Browser
Errors and Warnings Tab
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SystemVerilog-VHDL Assistant Menus
Available Customizations Dialog Box
Objects
Name Description
Select the filters to apply Allows you to enter the name of the filters you
want to hide.
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SystemVerilog-VHDL Assistant Menus
Switch to Editor Dialog Box
Objects
Table 3-44. Switch to Editor Dialog Box Contents
Name Description
Name Displays the names of the files currently opened in
the text editor.
Path Displays the path to these files.
Select Clean Editors Selects the non-modified editors.
Invert Selection Inverts your selection, for example, if you’ve clicked on a file
in the table then clicked on Invert selection, this file will be
deselected and the rest of the files will be selected.
Select All Selects all the files in the table.
Activate Selected Editor Makes the selected editor the currently active file in the
SystemVerilog-VHDL Assistant text editor.
Close Selected Editors Closes the selected file from the text editor.
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SystemVerilog-VHDL Assistant Menus
Import From Filelist - File Location Dialog Box
Related Topics
Opening Design Files
Saving a File
Closing a File
Saving All Files
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SystemVerilog-VHDL Assistant Menus
Import From Filelist - File Location Dialog Box
Note
If a corrupted or a non-filelist is chosen, an error message displays.
Related Topics
Opening a Project
Importing Files Using Questa
Adding a New File to a Project
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SystemVerilog-VHDL Assistant Menus
Class Info
Class Info
To access: Right-click on an UVM/OVM-based class in one of the standard browsers, and
choose Class Info from the popup menu. Note that the Class Info option is only visible in
the popup menu of UVM/OVM-based classes.
An internal browser titled <the class’s name> opens in the editor area displaying all the
available information on the chosen class.
Figure 3-39. The Class Info Browser
Related Topics
Working With Classes
Finding Class Parents and Declarations
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Chapter 4
Working With Projects
This chapter explains the main tasks related to SystemVerilog-VHDL Assistant projects starting
from creating a project to building a project.
Creating a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Opening a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Closing a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Ensuring SystemVerilog-VHDL Assistant Project Portability . . . . . . . . . . . . . . . . . . . . 177
SystemVerilog-VHDL Assistant Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Reloading a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Reloading a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Creating a Virtual Folder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Removing a Virtual Folder From a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Adding a New File to a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Adding Existing Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Importing Files Using Questa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Removing Files From a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Detecting Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Documenting Your Project Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Checking a Project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Defining Project Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Building a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Example - Simulating a Project in QuestaSim Using a Test File . . . . . . . . . . . . . . . . . . 189
Multiple SystemVerilog-VHDL Assistant Sessions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Creating a Project
In SystemVerilog-VHDL Assistant, you always work on a project. A SystemVerilog-VHDL
Assistant project is a group of referenced design source files and their associated files.
Projects are used to manage files, that is, in order to work with files you need to add them to a
new or existing project. When you create a project, you specify a location for it in the file
system. The project file takes the extension .svap and is simply a list of files located anywhere
on your file system that work together to describe a design.
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Working With Projects
Creating a Project
Procedure
1. Do one of the following:
• Select File> New> Project.
• Click the New> New Project button from the standard toolbar.
The New Project wizard opens.
Figure 4-1. The New Project Wizard - Create SystemVerilog-VHDL Assistant
Project Page
2. In the Project name field, type a name for your new project.
Note
You cannot create a new project with the same name of a currently opened project in
SystemVerilog-VHDL Assistant.
3. In the Location field, specify the path to your new project. You can specify the location
by using a pre-defined environment variable, absolute path or relative path.
4. In the Description field, optionally specify a description for your project.
5. You can now do one of the following:
• Click Finish. The New Project wizard is closed and your new project displays in the
Projects, Design Objects, Build Libraries, Class Hierarchy and Design Hierarchy
browsers. The default templates folder is added to the project by default.
• Click Next to display the Settings page which allows you to add standard libraries to
your project.
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Working With Projects
Creating a Project
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Working With Projects
Opening a Project
9. On the Add Existing Files page, browse for the files you want to add to your new
project.
10. Check the files to add them to the new project.
11. Click Finish.
Your project will appear in all browsers. After creating a project in SystemVerilog-
VHDL Assistant, the project file with the extension .svap is created in the path that you
specified for your new project. It is simply a list of files that work together to describe a
design.
Note
If the project file (.svap) is set as read-only, you will not be able to perform any
operations on the project through SystemVerilog-VHDL Assistant such as adding
files, removing files, checking, building, visualization, and so on.
Related Topics
New Project Wizard
Creating a Virtual Folder
Adding Existing Files
Opening a Project
Opening a project displays its contents in SystemVerilog-VHDL Assistant browsers and allows
you to view and edit them.
Procedure
1. Do one of the following:
• Select File> Open Project.
• From the standard toolbar, click the button Open > Project.
The Open Existing Project dialog box displays.
2. Browse to your required project then click Open. The project opens and displays in all
the browsers.
Tip
: You can open any project by double-clicking on the project’s file from Windows
Explorer. SystemVerilog-VHDL Assistant opens and this project is loaded in it.
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Working With Projects
Closing a Project
Note
You can open any number of projects at the same time. But, you cannot open two
projects with the same name in SystemVerilog-VHDL Assistant at the same time.
You can find a list of recent projects under the File menu.
Related Topics
Closing a Project
Adding a New File to a Project
Closing a Project
Follow this procedure to close an opened project.
Procedure
Do one of the following:
• In one of the design browsers, click the project’s node then, select File> Close
Project.
• Right-click the project in any of the design browsers and select Close.
Related Topics
Opening a Project
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Working With Projects
Ensuring SystemVerilog-VHDL Assistant Project Portability
In this procedure, you will ensure that SystemVerilog-VHDL Assistant saves all design source
and Questa data file locations relative to the SystemVerilog-VHDL Assistant project file (.svap)
and the SystemVerilog-VHDL Assistant created Makefile, respectively, by setting a few
preferences.
Procedure
1. Define where you want to create your SystemVerilog-VHDL Assistant projects
Tools > Preferences > Project Management page> “Default Location for New
Projects” > $(OVERALL_PROJECT)/tools/SystemVerilog-VHDL Assistant
This option only applies if the new project is only created from within SystemVerilog-
VHDL Assistant. Also, the variable “OVERALL_PROJECT” should be defined.
2. Make sure your project is configured to attempt to store project paths relatively and/or
using soft paths by setting the options below
Tools > Preferences > Project Management page > “Store paths in relative form”
“Store paths using matching environment variables”
If the path is more than 5 levels up, it will be saved using the best matching pre-defined
environment variable from the specified list, if found.
3. Define where you want to add UVM/OVM files and create new design files.
Tools > Preferences > Project Management page > “Default Location for New
Files” > $(OVERALL_PROJECT)/source or $(PROJ_DIR)/../../source
4. Configure your build settings and Questa compilation directories.
Tools > Preferences > Build Management page > “Default Directory in which to
generate Makefile and perform Build > (OVERALL_PROJECT)/tools/questa or
$(PROJ_DIR)/../tools/questa
On defining your Makefile location, the tool automatically sets the library mapping of
any new build library to that location.
5. To ensure your SystemVerilog-VHDL Assistant project portability despite of the
organization of your overall project, you can choose to use soft paths to store design
files and simulation tool data locations.
Tip
You can keep your projects backward compatible by disabling the use of relative
paths to store project data by setting the following API ::setUseRelativePaths 0 or
RMB on the project’s name and select Project Settings > Project Management page
and uncheck the “Store paths in relative form (./../) where possible” option.
Related Topics
Setting Preferences
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Working With Projects
SystemVerilog-VHDL Assistant Data Map
Note
In the Projects browser the Makefile always appears in the build-Files/Questasim
virtual folder irrespective of its location on disk.
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Working With Projects
Reloading a Project
• Visualization Reports
Default location: Project directory/Visualization
Related Topics
Setting Preferences
Reloading a Project
Follow this procedure to reload any files in the project whether modified or unmodified in
addition to files that contain errors. It also updates the browsers if any modification has been
found.
Procedure
Do one of the following:
• In one of the design browsers, click the project’s node then, select File > Reload
Project.
• Right-click the project in any of the design browsers and select Reload.
Related Topics
Opening a Project
Reloading a File
Reloading a File
Follow this procedure to reload and re-parse a single file in the project.
Procedure
Right-click the file in the Projects browser and select Reload.
Related Topics
Opening a Project
Reloading a Project
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Working With Projects
Removing a Virtual Folder From a Project
directory structure of the added content. You can also create your own logical folders and copy
or add files to them.
Procedure
1. In the Projects browser, right-click the project or folder where you want to create the
new virtual folder.
2. Select Add New Virtual Folder from the popup menu.
The Create New Virtual Folder dialog box displays.
3. Enter the name of the new folder and click OK.
Related Topics
Removing a Virtual Folder From a Project
Adding a New File to a Project
Creating a Project
Adding Existing Files
Procedure
Right-click on the virtual folder you want to delete and choose Remove from the popup menu.
Tip
You can remove multiple virtual folders at the same time by holding down the Shift
or Ctrl keys while selecting the required virtual folders.
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Working With Projects
Adding a New File to a Project
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Working With Projects
Importing Files Using Questa
• In the Projects browser, right-click the project or folder where you want to add files
then select Add Existing File(s) from the popup menu.
The Add Files to Project dialog box displays.
2. In the From directory field, browse for the directory of the files you want to add to the
project. You can browse to the location by using a pre-defined environment variable,
absolute path or relative path.
3. In the left pane, select the folders you want to add. On clicking on one of the folders, its
content displays in the adjacent pane. Check the files you want to add to the project.
4. Click OK.
The files are listed under the project’s node in SystemVerilog-VHDL Assistant
browsers. If the files you added are of unknown type, they are added but will have the
unknown file format icon .
Related Topics
Adding a New File to a Project
Add Files to Project Dialog Box
Creating a Project
Detecting Errors
Procedure
1. Do one of the following:
• Select File > New > Import from Questa.
• Right-click on the project’s node in any browser, and then select Import from
Questa from the popup menu.
The Import from Questa dialog box displays.
2. In the ModelSim File field, browse to the path of the .ini file or _info file.
3. Specify whether to import your design files into a virtual folder similar to the hierarchy
of the directory level in the source path or in a newly created virtual folder by checking/
unchecking the Create Virtual Folders Automatically check box.
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Working With Projects
Removing Files From a Project
4. Click Next.
5. If you choose to use the design .ini file, do the following:
a. Select the libraries you want to import.
b. Specify whether you want to import your libraries as Source or External.
If you choose to use the design _info file, do the following:
a. Specify the name of the Build library to which files will be added.
b. You can also specify the path of the ModelSim .ini file in the Ini file path text box.
6. Click Finish.
Related Topics
Import From Questa Dialog Box
• Select the file you want to remove from the project then, select File > Remove
From Project or press the Delete button.
• In the Projects browser, right-click the file you want to remove from the project, then
select Remove From Project from the popup menu.
The file is removed from the project but is not deleted from the hard disk.
Related Topics
Adding Existing Files
Adding a New File to a Project
Detecting Errors
SystemVerilog-VHDL Assistant performs automatic analysis of files in two cases: when new
files are added to a project and when file edits are saved. Any syntax errors detected by
SystemVerilog-VHDL Assistant are immediately reported.
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Working With Projects
Documenting Your Project Contents
Procedure
Add files to a project or save a file that has been edited. If any of the files contain syntax errors,
they can be detected either:
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Working With Projects
Documenting Your Project Contents
follows:
Related Topics
Visualizing a Class
Exploring Classes Separately
Statically Visualizing UVM/OVM Projects and Classes
Cross-Highlighting Design Objects
Dynamically Visualizing UVM/OVM Test Benches
Showing Classes Inheritance Relationships
Finding Class Parents and Declarations
Showing Inherited Contents
Finding Object Declarations
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Working With Projects
Checking a Project
Extending Classes
Finding External Function and Task Implementations
Checking a Project
Follow this procedure to check your design. Checks analyzes the code to make sure it adheres to
the rules previously set in the Project Settings Dialog Box - Check Settings page.
Procedure
Select the project’s node then do one of the following:
Note
Clicking a violation in the Results tab in DesignChecker tool highlights its
corresponding line of code in SystemVerilog-VHDL Assistant text editor.
The project is checked and the analysis results are displayed in DesignChecker Results
tab.
Related Topics
Project Settings Dialog Box - Check Settings Page
Procedure
1. Select File > New > Project.
The New Project wizard opens.
2. In the Name and Location fields, type a name for your new project and specify the path
to your new project.
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Working With Projects
Building a Project
3. Click Next to display the Settings page, which allows you to add standard libraries to
your project.
4. Click the Advanced Settings button to display the “Project Settings Dialog Box” on
page 396, which allows you to specify the settings of your project.
5. Open the Verilog/SystemVerilog page and specify your list of global macro definitions
required for your project in the Macro Definitions field.
Tip
To define compilation arguments other than macro definitions, you have to add them
directly through the “Project Settings Dialog Box - Build Settings Page” on
page 140.
6. Click OK.
Note
Any edits in the saved project macro definitions should be followed by a Project
Reload for the changes to become effective.
Related Topics
Project Settings Dialog Box - Build Settings Page
Project Settings Dialog Box
Building a Project
Having finished working on a project, you have the ability to build the design using a specific
downstream tool such as Questa.
Prerequisites
Before building, you need to go through the following steps first:
Procedure
Right-click the project’s node and then from the Build cascade menu select the required target.
The results are displayed in the Console tab and the downstream tool is invoked.
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Working With Projects
Example - Simulating a Project in QuestaSim Using a Test File
This example shows how to simulate the project in QuestaSim using a test file.
Procedure
1. Right-click the project’s node in the Projects browser.
2. Select Project Settings from the popup menu.
The Project Settings dialog box displays. For steps 3, 4, 5, 6 and 7, refer to Figure 4-4.
Figure 4-4. Preferences - Adding a Test File to the vsim Command
3. In the Project Build Settings dialog, expand the Build Settings tree at the left pane as
follows: Build Settings > QuestaSim > Build Tools > Questa vsim.
4. Enter TESTFILE as a new variable name in the variables table.
5. Specify the path of the test file you want to include in your simulation as the value of
TESTFILE. You can use absolute or relative paths. You can also use variables such as
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Working With Projects
Multiple SystemVerilog-VHDL Assistant Sessions
$(PROJ_DIR). For example, a value of “$(PROJ_DIR)/test1” indicates that the test file
test1 is saved in the project’s directory.
6. Append the test file argument to the vsim command by adding the following at the end
of the Command Template text box:
+ testfile = $(TESTFILE)
The test file defined in the variable TESTFILE is passed to QuestaSim the next time you
simulate the project.
7. Click OK.
8. Right-click the project’s node in the Projects browser.
9. Select Build > Simulate from the popup menu.
QuestaSim is invoked and your project is loaded in it.
10. Click the Run -All button from QuestaSim toolbar to begin the simulation.
Related Topics
Building a SystemVerilog-VHDL Assistant Project
Adding Content to a Build Library
Specifying Project Settings
Project Settings Dialog Box - Build Settings Page
Creating a Project Makefile
Running a Project Makefile
Procedure
1. Invoke a new SystemVerilog-VHDL Assistant session by clicking the SystemVerilog-
VHDL Assistant button from HDS Tasks menu bar.
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Working With Projects
Multiple SystemVerilog-VHDL Assistant Sessions
2. A lock file is detected that might be the result of an actual running session or the
presence of a lock file from a previous session. The following dialog box displays.
Specify the folder’s path in the Workspace field. You can use the adjacent Browse
button to specify the location. Then click OK.
Note
If you accidentally enter the path of a workspace that was already in use, you
will be prompted again with the Multiple Instances Detected dialog box but with
the new workspace’s path instead.
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Working With Projects
Multiple SystemVerilog-VHDL Assistant Sessions
SystemVerilog-VHDL Assistant is invoked and you now have more than one
session running.
• Click the Clear Lock button. If the lock cannot be removed, an error message will
be displayed alerting you to double check whether a session is already running.
Click OK.
Note
The Multiple Instances Detected dialog box appears when you are invoking
more than one SystemVerilog-VHDL Assistant session on the same machine for
Windows OS. The same dialog box appears when you are trying to invoke more than
one SystemVerilog-VHDL Assistant session even when doing so on different
machines for Linux OS.
Related Topics
Creating a Project
Design Understanding Tour
Checking a Project
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Chapter 5
Working With Browsers
SystemVerilog-VHDL Assistant contains a number of browsers that help you manage your
projects and files, and perform various operations on them.
Showing and Hiding Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Undocking Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Docking Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Maximizing Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Restoring Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Customizing Browser Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Showing and Hiding Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Grouping and Ungrouping Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Showing and Hiding Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Expanding and Collapsing Nodes Within Browsers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Creating Custom Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Cloning SystemVerilog-VHDL Assistant Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
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Working With Browsers
Undocking Browsers
Undocking Browsers
You can pop up any of the SystemVerilog-VHDL Assistant browsers in a separate window
except the text editor.
Procedure
1. Click the browser’s tab.
2. Drag the browser and drop it outside the SystemVerilog-VHDL window.
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Working With Browsers
Docking Browsers
Note
If you close an undocked browser, you can open it again by choosing
Window > Show Browser > <browser name>.
Related Topics
Docking Browsers
Docking Browsers
You can restore browsers you previously undocked back into the SystemVerilog-VHDL
Assistant window.
Prerequisites
• You should have a previously undocked browser.
Procedure
1. Click the browser’s tab.
2. Drag the browser and drop it in the location you want in SystemVerilog-VHDL
Assistant.
The browser is restored inside SystemVerilog-VHDL Assistant.
Related Topics
Undocking Browsers
Maximizing Browsers
The Maximizing operation is used to maximize the selected browser into the whole application
window.
Procedure
Do one of the following:
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Working With Browsers
Restoring Browsers
Related Topics
Restoring Browsers
Restoring Browsers
The Restoring operation is used to restore the selected browser back to its original size in the
main window.
Prerequisites
A “Maximizing Browsers” on page 195 operation must have been performed.
Procedure
Do one the following:
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Working With Browsers
Customizing Browser Content
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Working With Browsers
Showing and Hiding Objects
The Preferences (Filtered) dialog box displays the page of the corresponding browser/
tab.
2. Scroll through the list of objects and select the Show check box for the objects required
to be displayed in the browser’s tree. Conversely, uncheck the Show check box for the
objects required to be hidden.
3. Click OK.
Tip
You can display all the listed object types in the browser by selecting Show All. You
can always go back to the original SystemVerilog-VHDL Assistant settings of a
browser/tab through the Restore Defaults button.
Results
Objects of the selected types will be displayed in the browser/tab’s tree or removed according to
your settings.
Related Topics
Preferences (Filtered) Dialog Box
Creating Custom Browsers
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Working With Browsers
Grouping and Ungrouping Objects
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Working With Browsers
Grouping and Ungrouping Objects
2. Scroll through the list of objects and select the Group check box for the object types
required to be grouped in folders. Conversely, uncheck the Group check box for the
object types you need to ungroup.
3. Click OK.
Tip
You can group all the listed object types in folders by selecting Group All. You can
always go back to the original SystemVerilog-VHDL Assistant settings of any
browser/tab through the Restore Defaults button.
Related Topics
Preferences (Filtered) Dialog Box
Creating Custom Browsers
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Working With Browsers
Showing and Hiding Columns
The columns are displayed or hidden in the browser according to your choice.
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Working With Browsers
Expanding and Collapsing Nodes Within Browsers
Related Topics
Creating Custom Browsers
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Working With Browsers
Creating Custom Browsers
2. Type the name of the new browser in the Name text box and then click OK.
A new browser opens in SystemVerilog-VHDL Assistant with the name you entered in
the Create New Browser dialog box.
Related Topics
Customizing Browser Content
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Working With Browsers
Cloning SystemVerilog-VHDL Assistant Browsers
Procedure
1. Do one of the following:
a. Select Window> New Browser.
b. Press the New Browser button.
2. Select the browser type from the cascaded menu: Design Objects, Design Hierarchy,
Class Hierarchy, or Projects browser.
The Create New Browser dialog box displays.
3. In the dialog box, type the new duplicate browser’s name in the Name field and then
click OK.
The new browser displays in SystemVerilog-VHDL Assistant having the same name
you specified and the same content of the original browser.
Related Topics
Customizing Browser Content
SystemVerilog-VHDL Assistant Browsers
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Chapter 6
Navigating and Finding Design Objects
SystemVerilog-VHDL Assistant provides a Goto feature to quickly find and open class parents,
object declarations, and external functions and task implementations to use in your design, and
automatically identify objects in all browsers and the text editor.
Finding Class Parents and Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Finding Object Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Finding the Design Unit of an Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Finding the Binding Aspect of an Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Finding External Function and Task Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Cross-Highlighting Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Using Filters to Locate Objects Within Browsers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Navigating to Objects in a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Searching for Text in SystemVerilog-VHDL Assistant Projects. . . . . . . . . . . . . . . . . . . 210
Accessing Files Referenced by Include Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Accessing Files Referencing a Selected File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Changing File Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Opening Package Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Highlighting Package Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Opening Module/Interface Instances Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Tracing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Procedure
Do one of the following:
• Right-click the class you want to examine in one of the design browsers and select
Go To > Parent/Declaration from the popup menu.
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Navigating and Finding Design Objects
Finding Object Declarations
• In the text file place the cursor anywhere in the class name and right-click. Select
Go To > Parent/Declaration from the popup menu.
• Click on the class name in one of the design browsers. Choose Navigate > Go To >
Parent/Declaration from the menu bar.
The file containing the class parent or declaration opens and the corresponding lines are
highlighted.
Related Topics
Finding Object Declarations
Navigate Menu
• In case of Verilog/SystemVerilog or VHDL code, you can use one of the following
methods:
o In one of the browsers, right-click the object whose declaration you want to find
and select Go to> Declaration from the popup menu.
o In the text file, place the cursor on the object name and press F3 or Alt-D.
• In case of Verilog/SystemVerilog code, you can use one of the following methods:
o In the text file, place the cursor just before the object name, right-click and select
Go to > Declaration from the popup menu.
o Click on the object in one of the design browsers and choose Navigate > Go To
> Declaration from the menu bar.
• In case of VHDL code, select the object name in the text file and select Go To from
the popup menu.
The file containing the object declaration opens and the specified line of code is
highlighted.
Related Topics
Finding Class Parents and Declarations
Navigate Menu
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Navigating and Finding Design Objects
Finding the Design Unit of an Instance
• Right-click the instance whose declaration you want to find and select Go
to > Design Unit from the popup menu.
• Select the component name and press Alt-U.
Note
In case of the occurrence of more than one design unit, you go to the architecture of
the bound entity from the hierarchy of the default top.
• Select the component, right click the instance and select Go to > Binding Aspect
from the pop up menu.
• Select the component and press Alt-B.
Note
In case of the occurrence of more than one binding aspect, you go to the
configuration specification in the same architecture, if available, or to the first line in
the binding configuration.
In case of binding by name, Goto feature does not go to any binding aspect.
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Navigating and Finding Design Objects
Cross-Highlighting Design Objects
Procedure
Do one of the following:
Related Topics
Finding Class Parents and Declarations
Navigate Menu
Procedure
1. Right-click the object you wish to identify in any browser.
2. From the popup menu, select Cross Highlight.
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Navigating and Finding Design Objects
Using Filters to Locate Objects Within Browsers
Results
The text is highlighted in the regular fashion in SystemVerilog-VHDL Assistant text editor, as
well as in other browsers.
Related Topics
Finding Class Parents and Declarations
Working With Design Objects
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Navigating and Finding Design Objects
Navigating to Objects in a File
• Right-click the object in any browser then select Open from the popup menu.
• Double-click the object in any browser.
• In the Outline browser, click the object.
Results
The file containing the selected object opens in the text editor and the object’s declaration is
highlighted.
Related Topics
SystemVerilog-VHDL Assistant Browsers
Navigate Menu
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Navigating and Finding Design Objects
Accessing Files Referenced by Include Statements
4. If you want to customize your search options, click the Customize button.
5. Click the Search button.
Results
The results are displayed in the Search Tab.
Related Topics
Search Dialog Box
Search Tab
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Navigating and Finding Design Objects
Changing File Types
Note
If the file is not referenced in any other files, the Is Included by menu item is not
displayed.
Results
The including file opens in the text editor.
Related Topics
Accessing Files Referenced by Include Statements
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Navigating and Finding Design Objects
Highlighting Package Declarations
Procedure
1. In the Projects browser, expand the design file node and select the node for the package
you want to open.
2. Do one of the following:
• Right-click the package node and select Goto > Package from the popup menu.
• Choose Navigate > Go To > Package from the menu bar.
The file containing the package opens in the text editor.
Related Topics
Highlighting Package Declarations
Opening Module/Interface Instances Declarations
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Navigating and Finding Design Objects
Tracing Errors
Procedure
1. Right-click the Module/Interface instance.
2. Select Goto > Definition from the popup menu.
The file containing the Module/Interface declarations opens in the text editor.
Related Topics
Opening Package Files
Highlighting Package Declarations
Tracing Errors
SystemVerilog-VHDL Assistant reports any syntax error in the Errors and Warnings tab. It
allows you to open files that contain errors using the Go To feature.
Procedure
1. In Errors and Warnings tab, right-click the error.
2. Choose Go to from the popup menu to display the file that contains the error.
Results
The file that contains the corresponding error opens in SystemVerilog-VHDL Assistant text
editor.
Related Topics
Errors and Warnings Tab
Detecting Errors
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Chapter 7
Working With Design Objects
SystemVerilog-VHDL Assistant provides several tasks that facilitate the manipulation of your
design objects. This chapter explains the different tasks that can help you manage classes,
modules and interfaces, in addition to other general tasks that are common to all design objects.
Working With Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Viewing Classes in SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . 217
Exploring Classes Separately . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Showing Classes Inheritance Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Showing Inherited Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Extending Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Finding Class Parents and Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Visualizing a Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Class Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Working With Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Exploring Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Working With Annotation Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Showing/Hiding Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Expanding and Collapsing Class Declarations and Methods . . . . . . . . . . . . . . . . . . . . . . . 238
Showing Missing Parent Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Toggling Between Component and Class Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Updating Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Printing Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Saving Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Example - Visualizing a Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Working With Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Marking the Top-Level Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Showing/Hiding the Hierarchy of a Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Working With Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Generating Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
RTL Object Instancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Instancing RTL Objects by Drag and Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
RTL Instancing Coverage and Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
General Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Exploring the Design from a Specific File/Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Cross-Highlighting Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Removing Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
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Working With Design Objects
Working With Classes
Members and methods in classes are distinguished and listed under the class in the Projects
browser. Moreover, SystemVerilog-VHDL Assistant can represent any SystemVerilog as a
group of related classes in the Class Hierarchy browser. See Figure 7-1.
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Working With Design Objects
Viewing Classes in SystemVerilog-VHDL Assistant Text Editor
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Working With Design Objects
Exploring Classes Separately
Results
A new browser opens containing the tree under the selected class.
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Working With Design Objects
Showing Classes Inheritance Relationships
Related Topics
Viewing Classes in SystemVerilog-VHDL Assistant Text Editor
Results
A new browser opens containing the Inheritance tree of the selected class.
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Working With Design Objects
Showing Inherited Contents
Related Topics
Showing Inherited Contents
Procedure
1. Select Show Inherited Contents from the popup menu of a SystemVerilog Class in any
SystemVerilog-VHDL Assistant browser.
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Working With Design Objects
Showing Inherited Contents
2. A new tab opens listing the class’ contents and the inherited contents from the selected
SystemVerilog Class.
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Working With Design Objects
Showing Inherited Contents
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Working With Design Objects
Extending Classes
Related Topics
Showing Classes Inheritance Relationships
Extending Classes
Follow this procedure to create a new class that inherits from, or extends, an existing class.
Procedure
1. Select Extend This Class from the popup menu of a SystemVerilog Class in the
Projects browser.
The Extend Class dialog box displays.
2. Type the name of the new class in the Class name field.
3. Choose the Active file option if you want to create the class in the currently active file in
the text editor, or choose New file if you want to create the class in a new file. For filling
the other fields, refer to “Extend Class Dialog Box” on page 162.
4. Click OK.
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Working With Design Objects
Extending Classes
This appends the declaration of the class in the active file in SystemVerilog-VHDL
Assistant text editor.
Related Topics
Viewing Classes in SystemVerilog-VHDL Assistant Text Editor
Extend Class Dialog Box
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Working With Design Objects
Finding Class Parents and Declarations
Procedure
Do one of the following:
• Right-click the class you want to examine in one of the design browsers and select
Go To > Parent/Declaration from the popup menu.
• In the text file place the cursor anywhere in the class name and right-click. Select
Go To > Parent/Declaration from the popup menu.
• Click on the class name in one of the design browsers. Choose Navigate > Go To >
Parent/Declaration from the menu bar.
Results
The file containing the class parent or declaration opens and the corresponding lines are
highlighted.
Related Topics
Finding Class Parents and Declarations
Finding Object Declarations
Visualizing a Class
Visualization in SystemVerilog-VHDL Assistant allows you to document, understand, and
analyze different elements of your test bench. Classes is an important element in the test bench
that SystemVerilog-VHDL Assistant enables you to visualize.
There are two methods through which a class can be visualized in SystemVerilog-VHDL
Assistant, each method illustrates the class from a different perspective. The first method
produces a component diagram which provides a functional perspective of the class as a
component inside the test bench, that is to say, this method focuses on the abstract structure and
connectivity of the test bench’s components. The second method produces a class diagram
which provides an implementation perspective of the class, that is to say, this method focuses on
the class only in terms of code as it focuses on the declarations of the class, its methods, the
inheritance relationships and so on.
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Working With Design Objects
Visualizing a Class
Procedure
1. To obtain a component diagram, do the following:
a. Select a specific class in any browser.
a. Do one of the following:
o Right-click on the class and select Visualize UVM/OVM Static structure from
the popup menu.
o In Tools menu, choose Visualize UVM/OVM Static structure.
A .ctv file opens showing the visualization of the class in terms of a component
diagram. See Figure 7-3.
Figure 7-2. Component Diagram “ma_agent_req.ctv”
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Working With Design Objects
Visualizing a Class
preference, any UVM/OVM classes in the class diagram will have their declarations and
methods displayed. See “Class Diagram” on page 392.
Figure 7-3. Class Diagram “ma_agent_req.ctcv”
The Outline browser displays all the objects available in the diagram. The browser also
shows the columns “File Path” and “Package” when showing the contents of a
visualization view.
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Working With Design Objects
Class Diagram Notation
When you click on any item in the class diagram, it is automatically highlighted in the
Outline browser and vice versa. Also, by passing the mouse over any item in the class
diagram or in the Outline browser, a tooltip displays giving information. The code
comments of the item are also displayed in the tooltip if you have the preference “Enable
Comment Extraction” set in the Preferences Dialog Box (see “Class Diagram” on
page 392). Refer to “Class Diagram Notation” on page 228 for information on the
contents of class diagrams.
Note
Figure 7-3 and Figure 7-3provide different representations of the same class
ma_agent_req (from the multadd_uvm example project available in SystemVerilog-
VHDL Assistant).
Both class and component diagrams are placed in a folder names visualization under the
project’s node in the Projects browser.
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Working With Design Objects
Class Diagram Notation
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Working With Design Objects
Class Diagram Notation
Caution
To make comments appear in the diagram, you need to set the preference “Enable Comment
Extraction” in the Preferences Dialog Box (see “Class Diagram” on page 392).
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Working With Design Objects
Class Diagram Notation
Declaration Format:
As illustrated in Figure 7-5 (pane 3), the declaration of the class is shown using the following
format:
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Working With Design Objects
Class Diagram Notation
As illustrated in Figure 7-5 (pane 4), class methods are shown using the following format:
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Working With Design Objects
Class Diagram Notation
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Working With Design Objects
Working With Visualization Views
Popup menu options available for Class Diagram are: Add Annotation, Hide Object, Hide
Declaration, Hide Method, Show All Relationships, Explore From Here, Visualize UVM/
OVM Static structure, Visualize Class Diagram, Go to Declaration, Go to Parent Class,
Go to Enclosing Package, Cross Highlight, Remove Cross Highlight, Expand Class
Diagram and Collapse Class Diagram.
Popup menu options available for Static Visualization are: Add Annotation, Hide, Show All
Connections, Toggle Hierarchy, Explore From Here, Go to Declaration, Go to Definition,
Cross Highlight and Remove Cross Highlight.
For example, the following procedure explains how you can perform Cross Highlight through a
class diagram.
Procedure
1. Expand the project’s folder in the Projects browser, expand the visualization folder, and
then open the .ctcv file.
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Working With Design Objects
Working With Annotation Comments
2. Select a class node in the .ctcv file and then choose Cross Highlight from the popup
menu.
The class will be highlighted in yellow in all browsers. This enables you to keep track of
the class across all browsers and to identify its location in the design and class hierarchy.
You can also select a class node and choose Expand Class Diagram from the popup
menu. This feature is available in class diagrams only. It enables you to create a new
class diagram for the class node you select in the existing diagram.
Procedure
1. To add a comment:
a. Select the object you want to add a note to from the diagram.
b. Do one of the following:
o Press Alt+N.
o Right-click on the selected object and choose Add Annotation from the popup
menu.
The Annotation box displays.
c. Add the text in the Annotation box, then click the Add button or press the Enter key.
The Annotation is added to the selected object. Notice that the object is marked by a
cross overlay in the Outline browser.
2. To edit a comment:
a. Select the object whose annotation you want to edit then press Alt+N.
The Annotation box displays. It can also be displayed by clicking on the annotation
itself.
a. Edit the text in the Annotation box then press the OK button or the Enter key.
The Annotation is updated.
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Working With Design Objects
Showing/Hiding Objects
3. To remove a comment:
a. Click the Close button on the annotation.
The Annotation is removed.
4. To move a comment:
a. Select the annotation then press Shift and drag with the left mouse button to move
the comment from one location to another.
The Annotation is re-located.
5. To show a comment:
a. Right-click on the object whose annotation you want to show then choose Show
Annotation from the popup menu.
The Annotation is visible.
6. To hide a comment:
a. Select the object whose annotation you want to hide from the diagram then press
Alt+N. The Annotation box displays.
b. Check the Hide check box, then press the Edit button or the Enter key.
The selected note is removed from the selected object.
Showing/Hiding Objects
SystemVerilog-VHDL Assistant automatically shows all the objects in the diagram. You can
hide a specific object according to your preference. This feature can be very handy when
dealing with large designs.
Procedure
1. To show/hide classes:
a. Select the class you want hide in the diagram, then do one of the following:
o Choose Hide Object from the popup menu.
o Select the Hide Selected button from the visualization toolbar.
o Press Alt+H.
a. The selected class is hidden. You can re-show hidden classes by right-clicking on
the white area inside the editor’s browser and choosing Unhide All option from the
popup menu, or by selecting the Unhide All button from the visualization toolbar.
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Working With Design Objects
Showing/Hiding Objects
Note
From the Outline browser, you can hide classes by selecting Hide in Diagram from
the classes popup menu. Hidden classes will be marked by a cross overlay. You can
re-show them by selecting Show in Diagram from the classes popup menu.
2. To show/hide relationships:
a. Select the relationship you want hide in the diagram, then do one of the following:
o Choose Hide Relationship from the popup menu.
o Select the Hide Selected button from visualization toolbar.
o Press Alt+H.
Note
You can re-show all hidden relationships by selecting Show All Relationships
from the class popup menu in the diagram.
3. To show/hide instances/pins:
a. Select the instance/pin you want hide in the diagram, then do one of the following:
o Choose Hide from the popup menu.
o Select the Hide Selected button from visualization toolbar.
o Press Alt+H.
The selected instance/pin will be hidden.
Note
You can re-show all hidden instances/pins by selecting Show All Connections
from the class popup menu in the diagram.
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Working With Design Objects
Expanding and Collapsing Class Declarations and Methods
Caution
You cannot hide a separate connection. You can only hide its connected pins.
The connection is automatically hidden when its all connected pins are hidden.
Note
Hidden objects can be shown by selecting the Unhide All button from the
visualization toolbar.
Tip
You can hide multiple objects from the Outline browser by holding down the
Ctrl key and selecting the objects followed by choosing the Hide in Diagram
option from the popup menu. You can reshow hidden objects by selecting them and
choosing the Show in Diagram option from the popup menu.
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Working With Design Objects
Showing Missing Parent Class
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Working With Design Objects
Updating Visualization Views
Note
When the visualization file is closed, it loses its connection with the source code, that is, any
updates in the source code are not reflected in the diagram.
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Working With Design Objects
Example - Visualizing a Class
• Press Ctrl+S.
The design is saved.
Procedure
1. Open the multadd_uvm.svap project.
2. From the Design Objects browser, expand the Classes folder, then right-click the
ma_agent_req’s node.
3. Select Visualize Class Diagram from the popup menu.
The file ma_agent_req.ctcv opens displaying a class diagram showing the class
ma_agent_req and all associated classes (ma_agent_req_config, ma_agent_req_driver,
ma_agent_req_monitor and ma_agent_req_item) that are extracted from the code.
The Outline browser opens showing all the class information as declarations and
methods.
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Working With Design Objects
Example - Visualizing a Class
Note
The file ma_agent_req.ctcv shows the first level of inheritance, including any UVM/
OVM classes and all levels for non-UVM/OVM classes.
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Working With Design Objects
Example - Visualizing a Class
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Working With Design Objects
Example - Visualizing a Class
c. Pane 3 shows all class methods/tasks. The figure below shows the details of the
build method syntax:
5. The diagram shows not only the visualized class, but all its related objects. In the
example, notice the enumeration and interface objects.
6. The file ma_agent_req.ctcv graphically outlines relationships between the
ma_agent_req class and other design code objects. Notice the following:
a. ma_monitor_req, maagent_req_config, ovm_sequencer, ma_driver_req and
ovm_analysis_port are instanced in the ma_agent_req class. The relationship is
represented by a blue solid line with a filled arrow at the end and an empty diamond
at the source. Notice how the instance name is shown on the connector.
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Working With Design Objects
Example - Visualizing a Class
Now that we have gone through the diagram and understood its details, let’s see how we
can further understand and debug the ma_agent_req code.
7. In the ma_agent_req.ctcv, right-click the ma_agent_req class and select Cross
Highlight from the popup menu. The ma_agent_req class is highlighted in all browsers.
In the Design Hierarchy browser, make sure that the ma_agent_req is instanced in
ma_env.
Related Topics
Dynamically Visualizing UVM/OVM Test Benches
Documenting Your Project Contents
Statically Visualizing UVM/OVM Projects and Classes
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Working With Design Objects
Working With Modules
Procedure
Right-click the module that you want to mark as the top-level module and choose Mark As Top
from the popup menu.
Note
In case of multiple top modules, it is recommended to choose a default top for your
design by clicking Mark As Default Top from the popup menu of the selected
module after marking it as a top module. If you do not choose one, SystemVerilog-
VHDL Assistant will choose one for your design. A SystemVerilog-VHDL Assistant
project cannot contain more than one Default Top unit.
Results
The selected module is marked with the top module indicator . In addition, a check appears
next to the Mark As Top option in the popup menu.
If you choose Mark As Default Top, the selected module is marked with the default top
module indicator . In addition, a check appears next to the Mark As Default Top option in the
popup menu.
Tip
Clicking Mark as Top/Mark As Default Top again toggles the module to its previous
state.
Related Topics
Showing/Hiding the Hierarchy of a Module
Design Hierarchy Browser
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Working With Design Objects
Showing/Hiding the Hierarchy of a Module
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Working With Design Objects
Working With Interfaces
Generating Interfaces
SystemVerilog-VHDL Assistant allows you to automatically generate a SystemVerilog
interface between the DUT and the test bench. This procedure creates a new file containing the
code template of the interface with the ports necessary for setting up the communication.
Procedure
1. Right-click on the module containing the DUT in any browser and select Generate
Interface from the popup menu.
The New Interface dialog box displays. See Figure 3-33.
2. Type the file name in the File name field and then choose its extension from the
dropdown list.
3. Enter the path of the file on the hard disk in the Location field. You can use the Browse
button.
4. Specify the virtual folder under which your new file will be added in the Virtual Folder
field or use the Browse button.
5. Optionally, you can set the Add new file to Project option to add the new file to the
current project.
Results
The generated interface file opens in SystemVerilog-VHDL Assistant text editor and is also
added in the Projects browser.
Related Topics
New Interface Dialog Box
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Working With Design Objects
RTL Object Instancing
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Working With Design Objects
Instancing RTL Objects by Drag and Drop
Results
An instance of the dragged object is created in your file according to the settings defined in the
RTL Instancing options. See RTL Instancing — Verilog/SystemVerilog and RTL Instancing —
VHDL for more details.
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Working With Design Objects
RTL Instancing Coverage and Limitations
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Working With Design Objects
RTL Instancing Coverage and Limitations
• RTL instancing uses proper rules and algorithms to create ports mappings.
• Objects can only be dropped within the same project.
• An object cannot be dropped inside itself.
RTL instancing supports the following drag and drop scenarios in Verilog/SystemVerilog files:
Note
UDP port mapping style is always “Positional” irrespective of the RTL instancing
settings. See RTL Instancing — Verilog/SystemVerilog.
• Package to entity
• Package to another package
• Package to architecture
• Package to empty file
• Entity to architecture
• Configuration to architecture
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Working With Design Objects
RTL Instancing Coverage and Limitations
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Working With Design Objects
General Tasks
General Tasks
SystemVerilog-VHDL Assistant provides tasks that can help you manage any design object
regardless of its type.
Exploring the Design from a Specific File/Object. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Cross-Highlighting Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Removing Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Results
A new browser opens containing only the tree under the selected file or object.
Related Topics
Exploring Classes Separately
Customizing Browser Content
Procedure
1. Right-click the object you wish to identify in any browser.
2. From the popup menu, select Cross Highlight.
Results
The text is highlighted in the regular fashion in SystemVerilog-VHDL Assistant text editor, as
well as in other browsers.
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Working With Design Objects
Removing Objects
Related Topics
Finding Class Parents and Declarations
Working With Design Objects
Navigating and Finding Design Objects
Removing Objects
Follow this procedure to delete methods and classes from the active design file.
Prerequisites
This procedure is applicable only in the Outline browser with methods and classes.
Procedure
1. Right-click any function, task or class in the Outline browser and choose Remove from
the popup menu.
2. Save the file.
Results
The selected function, task, or class is removed from the active file in SystemVerilog-VHDL
Assistant text editor.
Related Topics
Outline Browser
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Working With Design Objects
Removing Objects
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Chapter 8
Automating Test Bench Creation
The new SystemVerilog-VHDL Assistant Template objects allow you to quickly and easily
create a complete test bench. This chapter provides an overview of the shipped templates and
guidance on how to create your own template objects.
SystemVerilog-VHDL Assistant Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
SystemVerilog-VHDL Assistant Template Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
MetaData Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Body Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Pre-Processing and Post-Processing Sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Adding Templates to Design Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Creating a Template Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Referencing a Template Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Adding Template Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Using Templates to Create Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Specifying a Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Template Parameters Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Sub-Templates Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Template Syntax Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Upper and Lower Case Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Script Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
TCL Scripts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Include Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Create Calls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Template Syntax Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
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Automating Test Bench Creation
SystemVerilog-VHDL Assistant Template
Using SystemVerilog-VHDL Assistant templates ensures that all team members are conforming
to the same coding practices and are focused on the creative aspects of developing design
objects.
Now lets take a closer look on SystemVerilog-VHDL Assistant templates and see them in
action.
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Automating Test Bench Creation
SystemVerilog-VHDL Assistant Template Sections
Before going into more detail, you can have a quick look at SVATemplateExample.pdf located
at <install path>/docs/pdfdocs/SVA_Examples.
MetaData Section
The metadata section is placed between the %metadata_begin %metadata_end tags.
It may contain the following:
• A listing of the template properties. The properties may include its name, type, category,
version, description, etc.
Template properties are specified using the setTmplProperties API
::setTmplPropertiesOp propertyName propertyValue
• The naming rule for the object file to be generated.
The file naming rule is set using the setTmplFileNamingRuleOp API
::setTmplFileNamingRuleOp rule
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Automating Test Bench Creation
MetaData Section
• Declarations for variables used in the template. The declarations allows you to provide
descriptions and values for the used variables.
Template variables are specified using the addTmplVariableOp API
::addTmplVariableOp name desc default values required type
In the metadata section, the user should specify the svt version. The svt version is the version of
the svt template syntax. The first released version is “1.0”. The svt version is set using
“::SetTmplSvtVersionOp Version” API.
Note
If the svt version is not specified, the following warning is reported to the user:
Svt version is not specified, Use “::SetTmplSvtVersionOp” API in Metadata section to specify
svt version.
In the code sample in Example 8-1, the template creator wants the template users to know that
the template is of category “Agent” and describes its function as “Create a UVM Agent Class”.
He specifies five variables he intends to use in the template: “AGENT”, “DRIVER”,
“MONITOR”, “SEQUENCER”, “TRANSACTION” and “VIF” and provides a description and
value for each.
Finally he sets a naming rule for the file generated from the template.
%metadata_begin
::TemplateApi::setTmplSvtVersionOp "1.0"
# Optionally declare the variables used in the template with defaults &
descriptions
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Automating Test Bench Creation
MetaData Section
# Specify the File naming rule for the file generated from this template
::TemplateApi::setTmplFileNamingRuleOp "%(AGENT)_agent/%(AGENT).svh"
::TemplateApi::setTmplVirtualFolderNamingRuleOp "%(AGENT)_agent"
%metadata_end
On referencing or adding a template in your project, you can easily refer to its properties by
hovering over it in the Projects browser, as shown in Figure 8-2.
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Automating Test Bench Creation
Body Section
Body Section
The body section is placed between the %text_begin %text_end tags. It contains the design
boilerplate text that will be generated from this template. The boilerplate text contains data
placeholders embedded within design code. The placeholders are replaced by text in the finally
produced design object.
The place-holders can be:
• Include file calls — Used to include the body section of a template i.e header template
into that of another. The following syntax is used for the INCLUDE command:
%INCLUDE templateName templateProject templateCategory templatePath
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Automating Test Bench Creation
Body Section
Tip
You can use the %Upper(variable name) or %Lower(variable name) functions to
convert the variable string to uppercase or lowercase, respectively
Variables can be used in any part of the template file apart from the metadata section,
the Include file calls of the body section, and the Create calls of the preprocessing and
post-processing sections.
Note
%INCLUDE adds in all variables declared in the meta-data section of an included
template along with its body section.
Figure 8-3 shows the body section of a sample template file and the design file generated from
it.
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Automating Test Bench Creation
Body Section
Note
Ensure you only use API Calls inside the boilerplate text area that return a value.
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Automating Test Bench Creation
Pre-Processing and Post-Processing Sections
The preprocessing code snippet below is part of an “Agent” template object. The template
developer wants to create a monitor, driver, and sequencer before creating the Agent object.
Apart from API calls, individual Tcl commands can be executed in the pre-processing and post-
processing sections. For instance, using the Tcl “set” command to set a global Tcl variable to
the value of a template variable, for example:
where TMPNAME is a global Tcl variable that you plan to access from within a Tcl script
(which can be called from within the body of the template).
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Automating Test Bench Creation
Pre-Processing and Post-Processing Sections
Note
Executing individual Tcl commands cannot be done in the Meta-data or Body sections.
For more information, refer to “Templates APIs” in the SystemVerilog-VHDL Assistant API
Reference Manual.
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Automating Test Bench Creation
Adding Templates to Design Projects
Tip
: You can reference one or more template projects in your design project. Moreover, you can
assign a default template project to your design project.
Caution
SystemVerilog-VHDL Assistant does not prevent a template user from editing a template as
long as he has write permissions to the template location, thus it is recommended that the
template project creator removes write permissions from the template project directory/files to
protect shared template projects from being altered by mistake.
Procedure
1. Do one of the following:
• Select New> Template Project from the File menu.
• Use the New Template Project option from the drop-down menu of the New button
on the standard toolbar.
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Automating Test Bench Creation
Creating a Template Project
2. Type the name in the Project name field. Specify the location in the Location field.
You can browse to the desired location where you want to save the new project by
clicking on the Browse button.
3. Click Next.
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Automating Test Bench Creation
Creating a Template Project
4. Browse for the files you want to add to your new Template project by clicking on the
Browse button next to the From directory field or by expanding the nodes in the left
pane of the wizard.
5. The Filter Selection field filters the content of the folder, from which you intend to
select your files, to display “Template Files (*.svt)” or “All Files (*.*)”.
6. Check the files you want to add to the new Template project.
7. Click Finish.
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Automating Test Bench Creation
Referencing a Template Project
The files are added under the project’s node as in the figure below.
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Automating Test Bench Creation
Referencing a Template Project
2. Choose the Project Management page and browse to a default Template Project.
Note
If you are creating a new project, set the default template project path from the Tools
> Project Settings > Project Management page.
3. You can always change the default template project or add another template project by
clicking the Add or Remove buttons.
4. Click OK.
The template project is added to your design project and can be viewed in the Projects
browser.
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Automating Test Bench Creation
Adding Template Files
Notice how the referenced files appear under the default_templates node. They are
organized into folders based on what has been defined in the category meta data.
Note
If the same template project opens as a standalone one, the template files will be
grouped into virtual folders.
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Automating Test Bench Creation
Adding Template Files
Notice how the added files appear under the _Templates node and directly under the
project node.
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Automating Test Bench Creation
Using Templates to Create Design Objects
Specifying a Template
Specify a template to create design objects.
Procedure
1. To specify your template, do one of the following:
a. Select the template and choose New Using Template from the popup menu.
b. Select a project node in the Projects browser, then choose File > New > Using
Template.
c. Right-click on a project’s node in the Projects browser and choose New Using
Template from the popup menu.
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Automating Test Bench Creation
Specifying a Template
The New Using Template dialog box displays showing the Select a template page.
Note
If no referenced template projects exist, an error message is displayed and the dialog
box will not be invoked. To change the project settings in order to reference template
projects, use the Project management page of the Project Settings dialog box. Refer to
“Referencing a Template Project” on page 270.
2. From the Template Project dropdown list, choose one of the template projects
available for this design project.
Notice how the template files included in this project are organized in the pane.
3. Expand the nodes and choose the template type you want.
4. Click Next.
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Automating Test Bench Creation
Specifying a Template
Note
A description of the file displays when you select a file type.
The Template Parameters page of the New Using Template dialog box displays.
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Automating Test Bench Creation
Template Parameters Page
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Automating Test Bench Creation
Template Parameters Page
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Automating Test Bench Creation
Sub-Templates Page
Procedure
1. Enter or change the values of the variables in the Value column.
If the file naming and virtual folder naming rules are related to one or more variables,
changing the variable values will automatically update the file name and sub virtual
folder fields to substitute in the naming rules.
2. Click Next.
The Sub-templates page displays.
Note
When a variable is defined as “user”, “system” or “environment” variable, you are
not prompted to enter a value, and they are directly generated with their
corresponding defined values.
Sub-Templates Page
The Sub-templates page of the New Using Template wizard shows all the templates that can
possibly be triggered from the main template. Whether the triggering of child templates from
the main template is conditional or does not affect the list of child templates displayed.
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Automating Test Bench Creation
Sub-Templates Page
For each template, the wizard will show the file naming rule for that design object as well as the
variables used in that object template.
Procedure
1. Uncheck/check the nodes of the child templates from which you want to create design
objects.
2. Add or change the values of their available variables.
3. Click Finish.
Note
A Checked child template that does not comply to the creation rules specified in the
main template code will not be triggered. Un-checking a child template overrides the
code creation rules.
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Automating Test Bench Creation
Sub-Templates Page
The files are generated and added directly under the project node.
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Automating Test Bench Creation
Template Syntax Reference
Variables
Variables can be system, property, environment or user-defined. User-defined variables can be
declared and given values in the metadata section. Missing variable values will be prompted for
on template generation.
You cannot use variables in ‘include’ and ‘create’ calls.
Syntax
%(variableName) or $(variableName)
Properties
• Variable names should include no spaces.
• Variable names are not case sensitive.
Syntax
%UPPER(varName)
%LOWER(varName)
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Automating Test Bench Creation
Script Calls
Script Calls
Used inside the body section to enable the user to call a Tcl API that returns text values.
Syntax
%do(::API::Call) : For an API call
TCL Scripts
Used to specify actions to be done before or after running the body section code of the template
file holding them.
TCL scripts are allowed anywhere outside the metadata and body sections.
Syntax
Variables %() & $() can be used in the script and all the previously mentioned variable rules
apply to them.
Directives
Directives can be used inside the body section to switch between alternative text blocks or
outside the body section to switch between two different syntax calls, for example, using
directives to switch between two create calls.
%IF (-----)
%CREATE(x)
%ELSE
%CREATE(y)
The directive condition is written in tcl syntax & can include variables.
Syntax
%If(condition)
%else
%endif
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Automating Test Bench Creation
Include Calls
%endif
Include Calls
They are used to include the body section of a template into the body section of another
template. If variables exist in the included text, they will be prompted for with the rest of the
template variables.
Syntax
%INCLUDE(Switches)
Note
%INCLUDE adds in all variables declared in the meta-data section of an included template
along with its body section.
Create Calls
They are used to call and trigger other template objects from within a parent template objects. A
parent template may contain a create call for a template that itself is a parent for other templates
i.e contains create calls.
Syntax
%Create(Switches)
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Chapter 9
Using SystemVerilog-VHDL Assistant Text
Editor
This chapter describes the operations supported by SystemVerilog-VHDL Assistant text editor.
SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Using SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Working With Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Creating a New File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Opening Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Closing a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Saving a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Saving All Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Setting Design Files Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Printing a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Editing Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Undo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Redo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Cut, Copy, Paste, and Paste Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Commenting and Uncommenting Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Increasing and Decreasing Indentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Setting Format Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Checking Local History of a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Search and Navigation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Searching for Text in SystemVerilog-VHDL Assistant Projects . . . . . . . . . . . . . . . . . . . . 304
Replacing Text in SystemVerilog-VHDL Assistant Projects. . . . . . . . . . . . . . . . . . . . . . . 305
Finding Text in Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Replacing a Text String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Using the Go to Line Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Using Bookmark Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Using the Folding Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Organizing Tasks and TODO Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Tasks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Adding a Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Removing a Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
View Customization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Showing/Hiding Line Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Highlighting Current Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Showing Print Margin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
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Using SystemVerilog-VHDL Assistant Text Editor
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Using SystemVerilog-VHDL Assistant Text Editor
SystemVerilog-VHDL Assistant Text Editor
Objects
Table 9-1. SystemVerilog-VHDL Assistant Text Editor Contents
Field Description
Text Editor Pane This is where the opened files are displayed for viewing, editing, and
performing all the possible actions that the text editor permits.
Outline Bar This is where marks that indicate the presence of bookmarks, tasks, and
errors in the active file are displayed.
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Using SystemVerilog-VHDL Assistant Text Editor
Using SystemVerilog-VHDL Assistant Text Editor
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Using SystemVerilog-VHDL Assistant Text Editor
Using SystemVerilog-VHDL Assistant Text Editor
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Using SystemVerilog-VHDL Assistant Text Editor
Working With Files
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Opening Design Files
Tip
If you are creating VHDL files, when editing your VHDL file in the text editor, you have
the ability to hover over objects and constructs to view tooltips with relevant information.
Related Topics
Closing a File
Opening Design Files
Saving a File
Related Topics
Creating a New File
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Using SystemVerilog-VHDL Assistant Text Editor
Closing a File
Closing a File
Follow this procedure to close the active file.
Procedure
1. Do one of the following:
• Choose File > Close.
• Press Ctrl + W.
• Use the Close toolbar button of the file.
You will be prompted whether to save the file if there are any unsaved changes.
2. You can close all the opened files by right-clicking any file’s tab and choosing Close
All.
3. If you want to leave the active file opened and close all other files, right-click the active
file’s tab and choose Close Others.
Related Topics
Creating a New File
Switch to Editor Dialog Box
Saving a File
Saving a File
Follow this procedure to save the active file.
Procedure
Do one of the following:
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Saving All Files
Note
If the file you are saving contains an error, a warning sign displays in
SystemVerilog-VHDL Assistant text editor next to the line containing the error.
A red mark appears in the Outline bar and the Errors and Warnings tab
automatically displays the error. Refer to “Detecting Errors” on page 184 for more
information.
If you attempt to modify/save a read-only file, you will be prompted that the file is
read only, and asked whether you want to make it writable.
Related Topics
Saving All Files
Save As Dialog Box
Detecting Errors
Switch to Editor Dialog Box
Note
If any of the files you are saving contains an error, a warning sign displays in
SystemVerilog-VHDL Assistant text editor next to the line containing the error.
A red mark appears in the Outline bar and the Errors and Warnings tab
automatically displays the error. Refer to “Detecting Errors” on page 184 for more
information.
Related Topics
Saving a File
Save As Dialog Box
Detecting Errors
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Using SystemVerilog-VHDL Assistant Text Editor
Setting Design Files Language
Note
Unknown file types are marked by a red “?” overlay on the files’ icons in SystemVerilog-
VHDL Assistant browsers.
Procedure
1. In the Projects browser, right-click the file that you want to change its language.
2. From the popup menu, select Set Language and choose an option from the supported
languages shown in the cascaded menu.
Caution
Changing the language of a SystemVerilog file that contains SystemVerilog
constructs from SystemVerilog to Verilog 2005 or Verilog 95 will generate errors.
Results
By setting the language of a selected design file, the file is parsed, its language constructs are
checked and the file is stored.
Furthermore, the Language column in SystemVerilog-VHDL Assistant browsers will display
the newly set language.
Tip
You can choose multiple files and follow the same procedure to change their language at the
same time.
Related Topics
Opening Design Files
Creating a New File
Printing a File
Follow this procedure to print the active file.
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Printing a File
Procedure
Do one of the following:
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Editing Operations
Editing Operations
Standard editing commands are available from the standard toolbar and the Edit menu.
Undo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Redo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Cut, Copy, Paste, and Paste Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Commenting and Uncommenting Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Increasing and Decreasing Indentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Setting Format Preferences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Undo
The Undo action is used to cancel the last unsaved change you have performed.
Prerequisites
An action must have been performed after the last save of the file.
Procedure
Do one of the following:
Redo
Follow this procedure to return the last change you have undone.
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Cut, Copy, Paste, and Paste Column
Prerequisites
An Undo operation must have been performed.
Procedure
Do one of the following:
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Cut, Copy, Paste, and Paste Column
The cursor changes into a cross sign which indicates that it’s now in the select column
mode.
13. Copy or cut the column that you want to paste by dragging the cursor while clicking the
left mouse button.
14. Select the destination in which you want to paste the column.
15. Do one of the following:
• Press Ctrl + V.
• Choose Edit > Paste.
• Right-click and choose Paste from the popup menu.
The column will be pasted in the selected destination.
16. Press the Alt + Shift + A buttons or click on the Toggle Block Selection button again to
restore the cursor back into its original selection mode.
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Commenting and Uncommenting Lines
Note
SystemVerilog-VHDL Assistant text editor enables you to copy text and paste it in
another file type, such as an email message or a MicroSoft Word document, while
retaining its format (font, syntax highlighting, size, and so on).
Related Topics
Undo
SystemVerilog-VHDL Assistant Standard Toolbar
Redo
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Setting Format Preferences
Procedure
1. To increase indentation:
2. Select the lines that you want to indent to the right.
3. Do one of the following:
• Use the Increase indentation button from the standard toolbar.
• Right-click on the selected lines and choose Increase Indentation from the popup
menu.
The selected text will be indented to the right.
4. To decrease indentation:
5. Select the lines that you want to indent to the left.
6. Do one of the following:
• Use the Decrease indentation button from the standard toolbar.
• Right-click on the selected lines and choose Decrease Indentation from the popup
menu.
The selected text will be indented to the left.
Related Topics
Undo
Setting Format Preferences
Redo
SystemVerilog-VHDL Assistant Standard Toolbar
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Checking Local History of a File
3. On the Editors page, you can choose to show/hide line numbers, whether or not to
highlight current line and show/hide print margin. If you’re satisfied with your choices,
click Apply then OK, otherwise click Cancel.
4. In the VHDL Syntax Coloring and the Verilog Syntax Coloring pages, you can choose
different colors and font styles for keywords, characters, strings and comments. If
you’re satisfied with your choices, click Apply then OK, otherwise click Cancel.
Related Topics
Increasing and Decreasing Indentation
Preferences Dialog Box
View Customization
Editors
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Checking Local History of a File
3. Choose the version you want to compare your file with by clicking on it in the History
tab.
Results
A new tab opens in SystemVerilog-VHDL Assistant text editor displaying the older version of
the file that you chose. You can split the editor’s view by moving one of the tabs to view then
next to each other and review the differences. See Figure 9-3.
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Checking Local History of a File
Related Topics
History Tab
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Search and Navigation
Note
When selecting the string in SystemVerilog-VHDL Assistant text editor’s pane, the
Containing text text box is already populated.
4. Choose the File name patterns from the drop down list.
5. If you want to customize your search options, click the Customize button.
6. Click the Search button.
Results
The Search tab is invoked displaying all the search results.
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Replacing Text in SystemVerilog-VHDL Assistant Projects
Related Topics
Search Dialog Box
Search Tab
Note
When selecting the string in SystemVerilog-VHDL Assistant text editor’s pane, the
Containing text text box is already populated.
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Finding Text in Files
Related Topics
Search Dialog Box
Searching for Text in SystemVerilog-VHDL Assistant Projects
Search Tab
Note
If you select text in SystemVerilog-VHDL Assistant text editor, then press Ctrl + F,
the Find/Replace dialog box will open with the selected text automatically in the
Find text box.
3. Select the Direction of your search. Choose Forward if you are searching for instances
of the text that are found after the point where the cursor is placed in the editor, or
Backward if you are searching for instances of the text that are found before the point
where the cursor is placed in the editor.
4. Select the Scope of your search. Choose All for searching in all the file, or Selected
lines for searching within certain selected lines.
5. You can customize your search by choosing options from the Options check box.
6. Click the Find button.
Note
You can go through the file to search for the text by clicking the Find button as
many times as needed until all instances of the text are found in that file.
Results
The text is highlighted in SystemVerilog-VHDL Assistant text editor if it is found. If it is not
found, an alert prompts on the SystemVerilog-VHDL Assistant status bar to inform that the
string was not found.
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Replacing a Text String
Related Topics
Replacing a Text String
Using the Go to Line Command
Find/Replace Dialog Box
Note
If you select text in SystemVerilog-VHDL Assistant text editor and then press Ctrl +
F, the Find/Replace dialog box will open with the selected text automatically in the
Find text box.
3. Select the Direction of your search. Choose Forward if you are searching for instances
of the text that are found after the point where the cursor is placed in the editor, or
Backward if you are searching for instances of the text that are found before the point
where the cursor is placed in the editor.
4. Select the Scope of your search. Choose All for searching in all the file, or Selected
lines for searching within certain selected lines.
5. You can customize your search by choosing options from the Options check box.
6. Click the Find button.
The first found instance of the text matching the string is highlighted in SystemVerilog-
VHDL Assistant text editor.
7. Do one of the following:
• Click Replace to replace the first found instance of the text matching the string.
• Click Replace/Find to replace the first found instance of the text matching the string
and find the next one.
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Using the Go to Line Command
• Click Replace All to replace all instances of the text in the file matching the string.
Related Topics
Finding Text in Files
Using the Go to Line Command
Find/Replace Dialog Box
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Using Bookmark Commands
4. Enter the bookmark name in the Enter Bookmark name text box
5. Click OK.
A blue mark displays in the context bar of SystemVerilog-VHDL Assistant text editor
next to the line where you chose to add your bookmark. A green mark displays in the
outline bar of SystemVerilog-VHDL Assistant text editor indicating the presence of a
bookmark in the active file. See Figure 9-5.
Note
The number of green marks displayed in the Outline bar of SystemVerilog-VHDL
Assistant text editor indicates the number of bookmarks available in the active file.
See Figure 9-5.
Figure 9-5. Inserting a Bookmark Using the Add Line Bookmark Option
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Using Bookmark Commands
6. To remove a bookmark:
Do one of the following:
• Right-click in SystemVerilog-VHDL Assistant text editor on the line number from
which you want to remove a bookmark. Choose Remove Bookmark from the
popup menu.
• Go to the Bookmarks tab. Click on the line showing the bookmark details to
highlight it. You may press the Ctrl key and click on another line in the tab to delete
more than one bookmark at the same time. Then right-click and choose Delete from
the popup menu or press the Delete key on your keyboard.
7. To move between bookmarks:
8. If the bookmarks are in different files:
Do the following:
• Go to the Bookmarks tab. Double-click on a line showing a bookmark’s details.
This will automatically open the file containing the bookmark (if not already
opened) in SystemVerilog-VHDL Assistant text editor. The line where the
bookmark is added is highlighted in SystemVerilog-VHDL Assistant text editor.
• Double-click on another line showing a bookmark’s details in the Bookmarks Tab.
The file containing the bookmark opens in a new tab in SystemVerilog-VHDL
Assistant text editor. The line where the bookmark is added is highlighted in
SystemVerilog-VHDL Assistant text editor.
9. If the bookmarks are in the same file:
Do one of the following:
• Double-click on lines with different bookmarks’ details in the Bookmarks tab.
• Click on the different green marks in the outline bar of SystemVerilog-VHDL
Assistant text editor.
The line where the bookmark is added is highlighted in SystemVerilog-VHDL Assistant
text editor.
Related Topics
Using the Go to Line Command
Opening Design Files
Bookmarks Tab
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Using the Folding Option
Objects
Table 9-2. Folding Option Contents
Field Description
Plus (+) sign Its presence next to a line means that some lines of the code are hidden/
collapsed; this part of the code is folded. When clicking on it, the code
expands revealing the hidden part. A vertical folding line appears and the
plus sign turns into a minus sign.
Minus (-) sign Its presence next to a line means that you are viewing the full code. When
clicking on it, the code is collapsed/folded back and the minus sign turns into
a plus sign.
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Using the Folding Option
Note
An alternative way of collapsing the folding region is by double-clicking the vertical folding
line.
Related Topics
Opening Design Files
Searching for Text in SystemVerilog-VHDL Assistant Projects
Saving a File
Replacing a Text String
Finding Text in Files
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Organizing Tasks and TODO Lists
Tasks Tab
Through the Tasks tab, you can view all the tasks recorded within your project and use it to
access the files associated with the tasks by double-clicking on the required entry.
Figure 9-7. Tasks Tab
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Adding a Task
Related Topics
Adding a Task
Opening Design Files
Removing a Task
Adding a Task
You have the ability to add tasks to a file in the text editor, which enables you to organize and
keep track of your work. There are two ways to add a task: either through the Properties dialog
box or through the text editor.
Prerequisites
• The file where you want to add your task must be open.
Procedure
1. Add a task using the Properties dialog box as follows:
a. Right-click on the context bar of the opened file in the text editor.
b. Choose Add Task from the popup menu.
The Properties dialog box displays.
c. Enter the task’s name, details or description in the Description text box.
d. Choose the task’s priority; High, Normal or Low, from the Priority dropdown list.
e. If the task is done, check the Completed option.
f. Click OK.
Note
The On element, In folder, and Location text boxes are automatically
populated with the name of the file where you want to add your task, path to the
folder containing the file and the line number where the task is added in the file,
respectively.
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Removing a Task
Removing a Task
Follow this procedure to remove a task from a file in the text editor.
Procedure
Do one of the following:
• Right-click on the check mark where the task is added in the context bar in the text
editor. Choose Remove Task from the popup menu.
• Right-click on the task entry in the Tasks tab. Choose Delete from the popup menu
or press the Delete key on your keyboard.
Results
The task is removed from the Tasks tab, the check mark is removed from the context bar of the
text editor and the blue mark is removed from the outline bar.
Related Topics
Tasks Tab
Opening Design Files
Adding a Task
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View Customization
View Customization
You can customize the way you view your file in SystemVerilog-VHDL Assistant text editor in
terms of showing/hiding line numbers, highlighting current line, and showing/hiding the print
margin.
Showing/Hiding Line Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Highlighting Current Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Showing Print Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
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Highlighting Current Line
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Showing Print Margin
Results
As you work with a file in SystemVerilog-VHDL Assistant text editor, the line you are then
currently working on will be highlighted.
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Code Completion
Code Completion
You can type a few characters in SystemVerilog-VHDL Assistant text editor and the auto-
complete feature automatically completes the code. This feature displays, for example, a list of
all possible functions, packages, classes, instances, reserved words, methods, as well as a
template for an empty function that you can insert in your code and fill to create a new function
and a template for entities and architectures.
Note
When you click on an option in the displayed list, a tool tip appears indicating the name,
description and the file where the chosen option is found.
Depending on the typed construct, SystemVerilog-VHDL Assistant can aid you in completing
your Verilog/SystemVerilog code as listed below:
• Typing a package name followed by “::” then pressing Ctrl + Space displays all the
constructs in both the package and the references it includes.
• Typing a class name followed by “::” then pressing Ctrl + Space displays all the
available constructs in this class.
• Typing an instance name followed by a period “.” displays all the current instances/
constructs.
• Typing a module instance followed by a period “.” displays all the ports of the module
from which it is instanced.
• Typing the first few letters of a word followed by Ctrl + Space displays all the reserved
words, modules, interfaces and classes that are declared in the opened project and have
the same prefix.
• Typing the first letter of an argument followed by Ctrl + Space or pressing Ctrl + Space
in an empty line in a function displays all the arguments defined in this function.
• Typing the special character $ followed by Ctrl + Space displays all the SystemVerilog
defined functions and tasks.
• Typing the left brace to a pre-defined function displays all the arguments that matches
this parameter.
• Typing the first few letters of a function followed by Ctrl + Space displays all the pre-
defined functions with their parameters.
Note
If you typed a function that does not take parameters, auto-complete automatically
displays the left and right braces “()”.
For more information, refer to “Example of Code Completion” on page 321 and “Completing
UVM/OVM Connections” on page 346.
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Using SystemVerilog-VHDL Assistant Text Editor
Editor Templates
SystemVerilog-VHDL Assistant can aid you in completing your VHDL code as listed below:
• Pressing Ctrl + Space in an empty file displays all keywords applicable to start a
description, in addition to the templates for Entity and Architecture.
• Typing library keyword then pressing Ctrl + Space displays all the available standard
and built-in packages.
• Typing use keyword then pressing Ctrl + Space displays all ieee/std packages with
suffix “.all”.
• Typing use keyword followed by a library name and a period “.” displays all the
packages in the entered library.
• Typing use keyword followed by a library name and a period “.” then followed by a
package name and a period “.” displays all the declarations in the entered package.
• Typing the first few letters of an identifier followed by Ctrl + Space displays all the
visible identifiers that have the same prefix. If the expected identifier is an entity/
component, the displayed list contains only entity/component names.
Editor Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Example of Code Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Editor Templates
Through the autocomplete feature, SystemVerilog-VHDL Assistant text editor enables you to
insert a template for a function and fill it with your variables and values in order to create a new
function.
Procedure
1. Move your cursor to the line where you want to add your function in the text editor.
2. Press Ctrl + Space.
A list displays with a template for creating a function on top of it, function - Create A
Function. A tool tip appears listing the contents of the template.
3. Double-click on the template to insert it.
Results
An empty function template is inserted in your code. You can proceed by filling in the
function’s name, parameters and the function’s body.
Related Topics
Example of Code Completion
Code Completion
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Using SystemVerilog-VHDL Assistant Text Editor
Example of Code Completion
Within the file ma_env.svh is a class called ma_env that inherits from the uvm_env base class,
which in turn inherits from a class called uvm_component.
Procedure
1. To call the function get_type() from its direct parent uvm_env:
2. Open the multadd_uvm project.
3. In the Projects Browser, double-click on the file ma_env.svh. It will be displayed in the
SystemVerilog-VHDL Assistant Text Editor.
4. Search for the ma_env declaration. In the following line, type super then type a period.
5. A list will appear displaying all the functions available from the direct parent uvm_env.
6. Select get_type() from the list.
7. To call the function get_type() from uvm_agent:
8. Type “uvm_agent::” then press Ctrl + Space after the declaration of ma_env.
9. A list will appear displaying all the functions of the class uvm_component.
10. Select get_type() from the list.
11. To auto-complete an object handle:
12. Just before the endfunction for the build_phase method, type “m_printer” then type a
period “.” .
A list will appear displaying all the public members of this object handle’s class.
13. Choose the object handle you want to connect to the instance m_printer from the popup
menu.
Note
m_printer is an instance from the class coverage.
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Using SystemVerilog-VHDL Assistant Text Editor
Example of Code Completion
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Using SystemVerilog-VHDL Assistant Text Editor
VHDL-Specific Editing Features
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Using SystemVerilog-VHDL Assistant Text Editor
Applying Quick Fixes to Semantic Errors
When semantic checks are violated, the tool also provides quick fix suggestions according to
the semantic errors. Refer to “Applying Quick Fixes to Semantic Errors” on page 324 for more
information.
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Using SystemVerilog-VHDL Assistant Text Editor
Applying Quick Fixes to Semantic Errors
The fix you chose is applied to the code to resolve the semantic error.
Below are the quick fix suggestions that SystemVerilog-VHDL Assistant provides for
semantic checks:
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Using SystemVerilog-VHDL Assistant Text Editor
Refactoring Declaration Names
For further information on VHDL semantic checks performed by the tool, refer to
“VHDL Semantic Checks” on page 323.
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Using SystemVerilog-VHDL Assistant Text Editor
Using Pair Matching
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Using SystemVerilog-VHDL Assistant Text Editor
Using Pair Matching
Procedure
1. Open the required VHDL file.
2. Click on the required start token. That is to say, click on an opening bracket or click on a
Begin keyword.
By doing that, the corresponding end token is selected as well.
For example, if you have selected the start token as an opening bracket, then when you
click on the opening bracket, the corresponding closing bracket is automatically
selected.
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Using SystemVerilog-VHDL Assistant Text Editor
Using Pair Matching
Similarly, if you have selected the start token as a Begin keyword, then when you click
on the Begin keyword, the corresponding End keyword is automatically selected.
Note
The same behavior is applicable if you click on the end token: the corresponding
start token is automatically selected.
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Using SystemVerilog-VHDL Assistant Text Editor
Using Pair Matching
By doing that, the entire code is highlighted up to the corresponding end token.
Note
The same behavior is applicable if you click on the end token: the code is
highlighted up to the corresponding start token.
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Chapter 10
Understanding UVM/OVM Designs
UVM/OVM test benches are software programs that connect to an RTL DUT through an
interface. The program drives signals to the DUT and reads the resulting signals from the
interface.
Using OVM Test Benches With a UVM Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Exploring UVM/OVM Test Bench Hierarchies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Displaying UVM/OVM Components in SystemVerilog-VHDL Assistant Browsers. . . 334
Understanding UVM/OVM Connecting Components . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Understanding UVM/OVM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Identifying Elements of a UVM/OVM Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Identifying the Hierarchical Level of the Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Identifying Peer-to-Peer Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Identifying Hierarchical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
UVM/OVM Coding Assistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Instancing UVM/OVM Classes by Drag and Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Adding seq_item Class Declarations to “do_” Methods . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Completing UVM/OVM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Changing the UVM/OVM Factory Registry Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Example - Dynamically Creating UVM/OVM Objects . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Statically Visualizing UVM/OVM Projects and Classes . . . . . . . . . . . . . . . . . . . . . . . . . 348
Dynamically Visualizing UVM/OVM Test Benches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Procedure 1: First Time Dynamic Visualization of a Project Using UVM 1.0 or Later . . 351
Procedure 2: First Time Dynamic Visualization of a Project Using OVM 2.01 or Later
353
Procedure 3: First Time Dynamic Visualization of a Project Using OVM Earlier than 2.01
355
Procedure 4: Dynamically Visualizing a Project that has been Previously Dynamically
Visualized. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
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Understanding UVM/OVM Designs
Exploring UVM/OVM Test Bench Hierarchies
This however is not the case for UVM, which is considered a completely different library with
no compatibility with OVM. So, you will need to migrate your OVM design; you need to
change your test bench to work with UVM.
For the migration, you need to take into consideration the following naming changes:
Table 10-1. OVM vs. UVM
OVM UVM
ovm_ uvm_
OVM_ UVM_
tlm_ uvm_tlm_
TLM_ UVM_TLM_
A script is provided for you to automatically change O’s to U’s in your OVM test bench. The
script is located at:
UVM_ROOT_FOLDER\uvm-2af9b8d\distrib\bin\ovm2uvm.pl
After running this script, you can then use your OVM test bench with a UVM library.
Note
Some functions’ declarations have changed in UVM which contributes to the
incompatibility with OVM. For more details, you can check the UVM documentation.
• Environment Perspective: The top nodes of the hierarchy tree are the environments
detected in the project. The nodes underneath are the component instantiations inside the
environments.
• Module Perspective: Shows the top-level design units at the top of the hierarchy tree and
the hierarchy of instances below.
• Tests Perspective: For UVM/OVM test benches, SystemVerilog-VHDL Assistant
automatically detects any UVM/OVM test classes, if any is used. UVM/OVM test
classes are classes that extend the uvm_test/ovm_test class. If test classes are used in the
test bench, SystemVerilog-VHDL Assistant displays the hierarchy of test classes in the
Design Hierarchy browser under the Tests folder.
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Understanding UVM/OVM Designs
Exploring UVM/OVM Test Bench Hierarchies
Each perspective of hierarchy displays in the Design Hierarchy browser under a separate folder.
Procedure
In the Design Objects browser, expand the node of the hierarchy perspective that you want to
display.
Related Topics
Design Hierarchy Browser
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Understanding UVM/OVM Designs
Displaying UVM/OVM Components in SystemVerilog-VHDL Assistant Browsers
Note
The UVM/OVM column displays by default in the Outline browser. You can follow
the same procedure above to hide it.
Related Topics
Projects Browser
Design Hierarchy Browser
Outline Browser
Design Objects Browser
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Understanding UVM/OVM Designs
Understanding UVM/OVM Connecting Components
Procedure
1. In the Projects browser, expand an UVM/OVM based class node and then expand the
UVM/OVM Port List node.
The UVM/OVM component ports are displayed.
2. Identify the port type by following the guidelines in Table 10-2.
3. Expand the port node. You can now identify the port’s parent class and the port
constructor.
Figure 10-3. Exploring an UVM Port
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Understanding UVM/OVM Designs
Understanding UVM/OVM Connecting Components
4. As can be done with any class instance, right-click the port’s parent class node and
choose to view its declaration, instantiation or definition in the SystemVerilog-VHDL
Assistant editor.
5. Right-click any port and choose GoTo > UVM Connections from the popup menu to
view the port connections.
Note
A Red Cross Overlay indicates a blocking port, an arrow pointing to the icon
indicates a get port while an arrow pointing away from the icon indicates a put port.
Related Topics
Understanding UVM/OVM Connections
Finding Class Parents and Declarations
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Understanding UVM/OVM Designs
Understanding UVM/OVM Connections
The UVM/OVM Connections folder can be shown either as a child of a class (if the class is
connected to its child instances) or as a child of an instance (if that instance is connected to other
instances through ports/exports).
Procedure
1. In the Projects browser, expand an UVM/OVM based class node and then expand the
UVM/OVM Connections folder.
2. Examine the list of connections. Each connection has a node under it representing the
other end of the connection.
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Understanding UVM/OVM Designs
Identifying Elements of a UVM/OVM Connection
By examining Figure 10-4, you can see that the UVM Connections folder is shown as a
child of a class.
3. Double-click any of the connection ends.
The connect() function is highlighted in the text editor.
4. Explore the connect() method in the text editor.
5. In the Projects browser, expand a UVM/OVM based class node and then expand the
Instances folder. Expand an instance’s node inside that folder and then expand the
UVM/OVM Connections folder.
6. Examine the list of connections. Each connection has a node under it representing the
other end of the connection.
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Understanding UVM/OVM Designs
Identifying the Hierarchical Level of the Connection
By examining Figure 10-5, you can see that the UVM Connections folder is shown as a
child of an instance.
7. Double-click any of the connection ends.
The connect() function is highlighted in SystemVerilog-VHDL Assistant Text Editor.
Then explore the connect() method in the text editor.
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Understanding UVM/OVM Designs
Identifying Peer-to-Peer Connections
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Understanding UVM/OVM Designs
Identifying Hierarchical Connections
Port-to-export and export-to-export connections are used to connect a component with another
one at a different level of hierarchy. You can figure out through SystemVerilog-VHDL
Assistant browsers whether this transactional level connection connects a component with
another one on the same level of hierarchy, a higher level (a parent), a lower level (a child) or
even within itself.
For example, Figure 10-8 shows an example of a hierarchical connection depicted from the
Projects browser. The class coverage contains the instances cache_rsp_fifo and req_fifo. These
two instances connect to their parent class through export-to-export hierarchical connections.
You can visualize the class to have a clearer view of these hierarchical connections as in
Figure 10-8.
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Understanding UVM/OVM Designs
Identifying Hierarchical Connections
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Understanding UVM/OVM Designs
UVM/OVM Coding Assistance
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Understanding UVM/OVM Designs
Adding seq_item Class Declarations to “do_” Methods
The appropriate code is added to all the existing class do_ methods and the class macro
definitions.
Note
To add variables to the do_compare method, ensure you declare the return variable
first, then use it in the return statement.
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Understanding UVM/OVM Designs
Adding seq_item Class Declarations to “do_” Methods
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Understanding UVM/OVM Designs
Completing UVM/OVM Connections
Note
On attempting to add the declaration related code to the sequence_item class do_
methods before saving the declared variables, you will be prompted to save your file.
The generated code follows the latest UVM/OVM guidelines. If you want to generate
your code using older guidelines, you can use the following preference API:
::PrefsApi::setAllowOvmGuidelinesInGeneration $allowOvmGuidelines
$projectName
Note
Currently, the supported data types are: _array_int, _queue_int, _array_string,
_queue_string, _array_object, _queue_object, _int, _object_, _string, _enum.
Prerequisites
• The project must be an UVM/OVM project.
• There has to be valid UVM/OVM connections for the list of allowed connections to be
displayed.
Procedure
1. In the text editor, place the cursor in between the parenthesis of the connect() function
call.
2. Press Ctrl + SpaceBar.
A list of allowed connections displays in a menu. An adjacent list opens describing the
chosen item in the list of allowed connections.
3. Click a connection from the list of allowed connections to insert it between the
parenthesis of the connect() method call.
Related Topics
Understanding UVM/OVM Connections
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Understanding UVM/OVM Designs
Changing the UVM/OVM Factory Registry Settings
Code Completion
• Registration Through Macros— This is the default method for registering extended
UVM/OVM classes. It adds a macro call to uvm_component_utils/
ovm_component_utils(type_name) or uvm_object_utils/ovm_object_utils(type_name) in
the newly created UVM/OVM class.
• Manual Registration — This method of registration adds get_type() and
get_type_name() functions and a dummy object handle of the registry type in the newly
created UVM/OVM class.
Follow this procedure to change the UVM/OVM factory registry method in SystemVerilog-
VHDL Assistant.
Prerequisites
The project must be an UVM/OVM project.
Procedure
1. For manual OVM factory registration, enter the following API command in the Console
tab:
::Ovm::setManualRegistration 1
2. To restore OVM factory registration to be through macros, enter the following API
command in the Console tab:
::Ovm::setManualRegistration 0
Note
The default settings for OVM registration are restored back to through macros when
you restart SystemVerilog-VHDL Assistant.
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Understanding UVM/OVM Designs
Example - Dynamically Creating UVM/OVM Objects
You need to cast the created object with the desired class because create_component()
and create_object() return objects of type ovm_component and ovm_object,
respectively.
Related Topics
Extending Classes
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Understanding UVM/OVM Designs
Statically Visualizing UVM/OVM Projects and Classes
Caution
Static visualization does not visualize objects created at runtime. Refer to
Dynamically Visualizing UVM/OVM Test Benches for more information.
Results
A new folder titled “visualization” and containing the visualization file is created under the
project’s tree, and a graphical pane is automatically opened in the text editor. The Outline
browser displays a list of the available objects in the currently opened visualization file along
with relevant information on each object.
Related Topics
Outline Browser
Dynamically Visualizing UVM/OVM Test Benches
Documenting Your Project Contents
SystemVerilog-VHDL Assistant Standard Toolbar
Visualizing a Class
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Understanding UVM/OVM Designs
Dynamically Visualizing UVM/OVM Test Benches
Because dynamic visualization depends on your last simulation results, you need to simulate
your design before dynamically visualizing your project. You also need to set up your
environment. Refer to the flowchart shown in Figure 10-10 to find out the procedure you have
to follow to successfully dynamically visualize your project.
Tip
Instructions on dynamic visualization are displayed in the Console log every time you run
dynamic visualization. You may refer to these instructions for quick help.
Procedure 1: First Time Dynamic Visualization of a Project Using UVM 1.0 or Later 351
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Understanding UVM/OVM Designs
Procedure 1: First Time Dynamic Visualization of a Project Using UVM 1.0 or Later
Procedure 2: First Time Dynamic Visualization of a Project Using OVM 2.01 or Later 353
Procedure 3: First Time Dynamic Visualization of a Project Using OVM Earlier than 2.01
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Procedure 4: Dynamically Visualizing a Project that has been Previously Dynamically
Visualized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Procedure
1. Right-click your project’s node in the Projects browser and select Visualize UVM/
OVM Simulated Structure from the popup menu.
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Understanding UVM/OVM Designs
Procedure 1: First Time Dynamic Visualization of a Project Using UVM 1.0 or Later
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Understanding UVM/OVM Designs
Procedure 2: First Time Dynamic Visualization of a Project Using OVM 2.01 or Later
You should now see svassist_pkg added under the project’s name in the Projects
browser.
4. Right-click any test node in the Design Hierarchy browser then select Build > Simulate
from the popup menu to simulate your test bench in QuestaSim.
5. After the design is loaded in QuestaSim, select the Run -All button from Questa’s
toolbar.
6. In SystemVerilog-VHDL Assistant’s Window, right-click your project’s node in the
Projects browser once more and select Visualize UVM/OVM Simulated Structure
from the popup menu.
The visualization of your project displays in SystemVerilog-VHDL Assistant’s editor.
Tip
If you are not able to successfully visualize your project dynamically, regenerate the
Makefile, simulate the project then run dynamic visualization again.
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Understanding UVM/OVM Designs
Procedure 2: First Time Dynamic Visualization of a Project Using OVM 2.01 or Later
Procedure
1. Right-click your project’s node in the Projects browser and select Visualize UVM/
OVM Simulated Structure from the popup menu.
SystemVerilog-VHDL Assistant displays a message with the detected UVM/OVM
version and asks you to select the UVM/OVM library that you want to compile. See
Figure 10-11.
Figure 10-11. Select the UVM/OVM Library to be Compiled for Dynamic
Visualization
2. In the dialog shown in Figure 10-11, select one of the two options:
Using Questa Precompiled UVM/OVM:
By selecting this option, you choose the precompiled UVM/OVM library provided with
Questa to be compiled in your simulation for dynamic visualization. This means that the
UVM/OVM library you have actually imported in your project will not be used for
dynamic visualization. You are recommended to use this option.
• Using Source UVM/OVM:
If you choose to use the source UVM/OVM library you imported in your project, go
to Procedure 3: First Time Dynamic Visualization of a Project Using OVM Earlier
than 2.01.
Tip
You can always revert back to using Questa Precompiled UVM/OVM by setting/
unsetting the option in Tools > Project Settings > Build Management.
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Understanding UVM/OVM Designs
Procedure 3: First Time Dynamic Visualization of a Project Using OVM Earlier than 2.01
4. Right-click the project’s node in the Projects browser, then select Build > Simulate
from the popup menu to simulate your test bench in QuestaSim.
5. After the design is loaded in QuestaSim, select the Run -All button from Questa’s
toolbar.
6. In the main window, right-click your project’s node in the Projects browser once more
and select Visualize UVM/OVM Simulated Structure from the popup menu.
The visualization of your project displays in the text editor.
Tip
If you are not able to successfully visualize your project dynamically, regenerate the
Makefile, simulate the project then run dynamic visualization again.
or
‘include “svassist_inc.svp”;
super.end_of_elaboration();
endfunction : end_of_elaboration
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Understanding UVM/OVM Designs
Procedure 3: First Time Dynamic Visualization of a Project Using OVM Earlier than 2.01
3. Add the following function call to the end of the end_of_elaboration() function:
svassist_extract();
The method svassist_extract() dumps the simulation results to be used later in dynamic
visualization.
Note
Make sure that the environment you are editing now is the same environment that
will be visualized later.
4. Right-click your project’s node in the Projects browser and select Visualize UVM/
OVM Simulated Structure from the popup menu.
SystemVerilog-VHDL Assistant displays a message with the detected OVM version and
displays a list of changes that need to be made to your environment for successful
dynamic visualization.
5. Click Update to allow SystemVerilog-VHDL Assistant to update your OVM
environment for dynamic visualization.
At this stage, SystemVerilog-VHDL Assistant adds the packages svassist_pkg.sv and
svassist_inc.svp to your project’s tree under the QuestaSim folder. These files are saved
in a default directory: $(HDS_HOME)/svassistant/resources/lib/svassistant_ovm_libs/
svassistant_pkg_x.x, where x.x is the OVM version of your project.
Tip
: For OVM 1.x, SystemVerilog-VHDL Assistant as well uses the modified OVM
source files, saved under the same directory mentioned above and adds this directory
to the include search paths of your library. SystemVerilog-VHDL Assistant then updates
the Makefile to include these changes.
SystemVerilog-VHDL Assistant is shipped with distinct folders for every OVM version
prior to 2.01. When updating the environment of a project using OVM version earlier
than 2.01, SystemVerilog-VHDL Assistant uses the files in the folder corresponding to
that OVM version.
For example, when updating the environment for dynamic visualization of a project
using OVM 1.1, SystemVerilog-VHDL Assistant updates the environment by adding
the following string to the Include Search Path list of your work library:
“$(HDS_HOME)/svassistant/resources/lib/svassist_ovm_libs/svassist_pkg_1.1”
By doing that, SystemVerilog-VHDL Assistant has added the files in the
svassist_pkg_1.1 folder under: $(HDS_HOME)/svassistant/resources/lib/
svassist_ovm_libs to your environment. This folder contains the file svassist_pkg.sv and
another folder named base; which contains the modified source files of OVM 1.1
especially created for dynamic visualization use.
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Understanding UVM/OVM Designs
Procedure 4: Dynamically Visualizing a Project that has been Previously Dynamically Visualized
7. Right-click the project’s node in the Projects browser then select Build > Simulate from
the popup menu to simulate your test bench in QuestaSim.
8. After the design is loaded in QuestaSim, select the Run -All button from Questa’s
toolbar.
9. In the main window, right-click your project’s node in the Projects browser once more
and select Visualize UVM/OVM Simulated Structure from the popup menu.
The visualization of your project displays in the text editor.
Tip
If you are not able to successfully visualize your project dynamically, regenerate the
Makefile, simulate the project then run dynamic visualization again.
Procedure
1. Right-click the project’s node in the Projects browser then select Visualize UVM/OVM
Simulated Structure from the popup menu.
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Understanding UVM/OVM Designs
Procedure 4: Dynamically Visualizing a Project that has been Previously Dynamically Visualized
2. Right-click the project’s node in the Projects browser then select Build > Simulate from
the popup menu to simulate your test bench in QuestaSim.
3. After the design is loaded in QuestaSim, select the Run -All button from Questa’s
toolbar.
4. In the main window, right-click your project’s node in the Projects browser once more
and choose Visualize UVM/OVM Simulated Structure from the popup menu.
The visualization of your project displays in the text editor.
Tip
If you are not able to successfully visualize your project dynamically, regenerate the
Makefile, simulate the project then run dynamic visualization again.
Related Topics
Building a SystemVerilog-VHDL Assistant Project
Build Libraries Browser
Statically Visualizing UVM/OVM Projects and Classes
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Chapter 11
Building a SystemVerilog-VHDL Assistant
Project
Overview
After completing your work on a project you will need to compile and simulate your design
using your preferred downstream tool. The typical approach would be through writing your own
Makefile to invoke and run the chosen downstream tool.
Writing your own Makefile may require a lot of effort in detecting the dependencies between
compilation units which is exactly where SystemVerilog-VHDL Assistant becomes very useful.
SystemVerilog-VHDL Assistant allows you to automatically integrate with downstream tools
through its Build Manager, which produces a Makefile with all the dependencies auto-generated
and integrated into the generated Makefile.
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Building a SystemVerilog-VHDL Assistant Project
Creating a Build Library
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Building a SystemVerilog-VHDL Assistant Project
Modifying Library Properties
Procedure
1. Click the project’s node in the Projects browser then do one of the following:
• On the main menu bar, click Build > Add New Build Library.
• In the Projects browser, right-click the project’s node then select Add New Build
Library from popup menu.
The New Build Library dialog box opens.
2. In the Library Name field, enter a name for your new library.
3. Specify your library type as User or External Library. External refers to pre-compiled
libraries that are used as part of your design, for example, compiled version of the UVM
library.
4. In the Library Mapping field, specify the location of your library, for example:
$(PROJ_DIR)/libraries/xyz
5. For Verilog projects, the search path for `include files is automatically set to
$(PROJ_DIR)/<xyz>. If Verilog `include files are not located within the hierarchy of an
existing library specify the new path.
6. In the Linked Libraries field, specify the names of other design libraries linked to your
design. If these libraries exist as part of your project they are automatically detected.
7. Click OK.
The Build Libraries browser displays showing the new library.
Related Topics
New Build Library Dialog Box
Adding Content to a Build Library
Build Libraries Browser
Modifying Library Properties
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Building a SystemVerilog-VHDL Assistant Project
Adding Content to a Build Library
The Edit Build Library dialog box displays. This dialog box is similar to the New Build
Library Dialog Box, but the Library Name and Library Type controls are dimmed.
3. Change the settings you want to apply to the library, namely the Library Mapping,
Include Search Path, or Linked Libraries.
4. Click OK.
Related Topics
New Build Library Dialog Box
Creating a Build Library
Build Libraries Browser
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Building a SystemVerilog-VHDL Assistant Project
Editing Command Templates
Procedure
1. Specify the content of your build project by selecting a project node, then do one of the
following
• On the main menu bar, click Tools > Project Settings.
• Right-click it and select Project Settings from the popup menu.
The Project Settings dialog box displays.
2. Choose the Build Settings option and the page displays in the right pane.
3. Set a default tool to be used in building your project by choosing one of the Active
Build Configuration drop-down list options, for example, choose QuestaSim. You can
set the location by using a pre-defined environment variable, absolute path or relative
path.
4. In the left pane, select a <build tool name> node, for example, QuestaSim.
A page displays in the right pane of the dialog box in which you can:
• Manually set the location of the build tool.
• Set variables that can be used in defining the commands needed to run the utilities
defined for this build tool. Refer to Setting Build Variables.
Note
SystemVerilog-VHDL Assistant automatically detects the location of the build
tool and stores the value in a defined variable.
5. Browse to the Build Tools node to display the available utilities for the selected build
tool. On selecting any of the utilities, a page displays in the right pane of the dialog box
showing a template for the command used to run the utility.
6. If you are content with the default settings click OK; otherwise, configure the build tool
and its utilities according to your needs.
7. When satisfied with your command templates, click Apply.
You have now stored both the library and project build settings information that will be
used to generate a Makefile. The information is stored in XML format in a file with the
extension .bld that resides in the same location as the project <project>.svap.
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Building a SystemVerilog-VHDL Assistant Project
Setting Build Variables
The following example clarifies this using the vsim Questa command:
vsim -l xyz
vsim -l %(WorkLib)
In the template, you have replaced the actual path to the library you want to simulate with one of
the internally defined variables in SystemVerilog-VHDL Assistant that is used to point to the
current project’s work library. Refer to Internal Variables.
You can further simplify the command template by creating a user-defined variable that you
give a value equal to the command switch and the internal variable:
vsim $MY_LIBRARY
Related Topics
Build Settings
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Building a SystemVerilog-VHDL Assistant Project
Running a Project Makefile
Refer to Specifying Project Settings. The build settings information is stored in XML format in
a .bld file that resides in the same location of the project <project>.svap.
Procedure
1. Do one of the following:
• On the main menu bar, click Build > Generate Makefile.
• Right-click the project’s node in the Projects browser and choose Build >
Generate Makefile from the popup menu.
A new directory is created in the Projects browser “_Build_Files” > QuestaSim >
Makefile.
2. Double-click the generated Makefile to examine its contents in the editor. Explore the
listed targets and identify their automatically detected dependencies.
The created Makefile is stored in the following path: <project_dir>/_Build_Files/
<downstream_name>/Makefile
Note
By double-clicking the generated Makefile, a tab is opened in SystemVerilog-
VHDL Assistant text editor displaying the file and the Outline browser shows and
enables direct navigation to the code objects available in the file. You can perform all
the actions that SystemVerilog-VHDL Assistant text editor provides (deleting, copying,
pasting, cutting, autocompletion, syntax highlighting) on the Makefile.
You need to update your Makefile when any of the command templates defined for the
downstream utilities is modified.
Related Topics
Specifying Project Settings
Build Settings
Running a Project Makefile
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Building a SystemVerilog-VHDL Assistant Project
Simulating and Optimizing a Design Through the Top-Level Module
Procedure
1. In the Projects browser, right-click the project node. From the popup menu, select Build.
A cascade menu showing a list of available targets displays.
2. Select the required target.
Note
When you right-click a project in the Projects browser and select Build, a cascade
menu listing the names of all the available targets in the Makefile displays.
3. The Console tab displays the results of running the Makefile. Errors and warnings
generated by the build tool (for example, vlog/vsim errors) are displayed in red and blue,
respectively.
4. After successful compilation, QuestaSim is invoked on the compiled test bench.
Tip
Double-clicking the messages in the Console tab will cross-reference the file and
line number in SystemVerilog-VHDL Assistant Text Editor.
Related Topics
Creating a Project Makefile
Procedure
1. Right-click on any top module in any browser and select Build from the popup menu.
2. Choose one of the following sub-menus:
• Simulate to simulate this top module only
• Optimize and Simulate to run Questa optimization then simulating the top module
• Optimize to optimize this top module only
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Building a SystemVerilog-VHDL Assistant Project
Simulating and Optimizing a Design Through the Top-Level Module
Related Topics
Working With Modules
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Building a SystemVerilog-VHDL Assistant Project
Simulating and Optimizing a Design Through the Top-Level Module
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Chapter 12
Setting Preferences
SystemVerilog-VHDL Assistant allows you to set how you want it to operate on both the user
and the project level through its Preferences and Project Settings dialog boxes.
Preferences Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Editors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Project Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Build Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Class Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Project Settings Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Project Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Build Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Verilog/SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Standard Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Check Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
RTL Instancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Build Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Properties Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Properties - Resource page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Properties - Resource Filters page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Properties - Refactoring History page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
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Setting Preferences
Preferences Dialog Box
You can set the default user settings preferences by clicking on an option to display its
corresponding page in the right pane of the dialog box. You can choose one of the following
options:
Editors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Project Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Build Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Class Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
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Setting Preferences
Preferences Dialog Box
Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
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Setting Preferences
Editors
Editors
To access: Tools > Preferences > Editors
On the Editors page, you can customize the editor in terms of showing or hiding line numbers,
highlighting current line and showing the print margin.
Figure 12-2. Preferences Dialog Box - Editors Page
Objects
Table 12-1. Preferences Dialog Box - Editors Page Contents
Name Description
Show line numbers Checking/unchecking this check box will cause line numbers to
appear in/disappear from the context bar of SystemVerilog-VHDL
Assistant text editor.
Show whitespace Checking/unchecking this check box will cause whitespace
characters characters to appear in/disappear from SystemVerilog-VHDL
Assistant text editor.
Highlight current line As you work with a file in SystemVerilog-VHDL Assistant text
editor, the line you are then currently working on will be highlighted,
if you check this check box.
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Setting Preferences
Editors
Related Topics
View Customization
Setting Format Preferences
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Setting Preferences
Editors
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Setting Preferences
Editors
Objects
Table 12-2. Preferences Dialog Box - Coloring Page Contents
Name Description
Keywords, Comments, Code elements to which you can apply Color or font
Characters, Strings characteristics (Bold, Italic, Underlined)
Color Applies desired color to selected code elements (Keywords,
Comments, Characters, Strings)
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Setting Preferences
Editors
Related Topics
Setting Format Preferences
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Setting Preferences
Editors
Objects
Table 12-3. Preferences Dialog Box - VHDL Syntax Coloring Page Contents
Object Description
Token Styles Displays different VHDL code elements. Select the token to
which you want to apply specific color, background, style and
font settings.
Color Select the color you want to apply to the selected token in the text
editor.
Background Select the background color you want to use for the selected
token in the text editor.
Style Select which styles you want to apply to the selected token: Italic,
Bold, Underline and Strike through.
Font Click Change to choose the font related to the selected token.
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Setting Preferences
Editors
Objects
Table 12-4. Preferences Dialog Box - VHDL Construct Templates Page Contents
Object Description
New Clicking this button opens the New Template dialog box which
allows you to create user-defined templates. The templates you
create along with their corresponding information are displayed
in the Templates table.
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Setting Preferences
Editors
Table 12-4. Preferences Dialog Box - VHDL Construct Templates Page Contents
(cont.)
Object Description
Edit Selecting an existing template in the Templates table and
clicking this button opens the Edit Template dialog box. This
allows you to edit the definition of the template. The edits you
make are reflected in the Templates table.
Remove Selecting an existing template in the Templates table and
clicking this button removes the template from the list.
Restore Removed If you remove the entity or the architecture templates shipped
with SystemVerilog-VHDL Assistant, you can restore them
back by clicking this button.
Revert to Default If you edit the definition of the entity or the architecture
templates shipped with SystemVerilog-VHDL Assistant, you
can revert to the original definition by selecting the template in
the table and clicking this button.
Import Allows you to import .xml template files.
Export Allows you to export .xml template files.
Templates table The Templates table lists the existing entity and architecture
templates shipped with SystemVerilog-VHDL Assistant in
addition to user-defined templates (if any). The table displays
the name of the template, the context in which the template
applies, its description and whether it is automatically inserted.
Preview When a template is selected in the table, you can preview the
corresponding code template defined for the template.
Usage Notes
A template is inserted within VHDL files using the auto-complete feature. For more
information, refer to “Using Construct Templates” on page 326.
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Setting Preferences
Editors
VHDL Scalability
To access: Tools > Preferences > Editors > VHDL > Scalability
Scalability page allows you to detect any file with a number of lines more than a specific
threshold that you provide. Any file that has a number of lines more than the specified threshold
becomes in scalability mode, meaning that the tool applies scalability mode settings to it.
Scalability mode settings include different options that you can enable or disable to enhance the
editor’s performance with files in scalability mode (large files).
Note
In order for some scalability mode options to reflect properly, you must close the file and
reopen it to make sure the latest settings are applied.
Objects
Table 12-5. Preferences Dialog Box - Scalability Page Contents
Name Description
Use automatic scalability detection and Allows you to disable the user-specified
settings scalability settings and handle the files using
the default tool settings. This option is the
default selection.
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Setting Preferences
Editors
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Setting Preferences
Browsers
Browsers
To access: Tools > Preferences > Browsers > Customize View
Choosing any of the browsers’ names visible under the Customize View option in the
Preferences dialog box opens the corresponding page on the right pane. Each page enables you
to control the display and grouping of object types within a browser. That is, you can choose
which objects to show or hide within a browser and which objects to group in folders. For
example, The below figure shows the Projects browser page in the Preferences dialog box.
The available options include: The Build Libraries, the Class Diagram Outline, the Class
Hierarchy, the Design Hierarchy, the Design Objects, the Outline, the Projects browsers, and
the Static/Dynamic Structure Outline.
Figure 12-8. Preferences Dialog Box - Projects Page
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Setting Preferences
Browsers
Objects
Table 12-6. Preferences Dialog Box - Projects Page Contents
Name Description
Object Type This column lists all the objects you can display in the browser.
Show Selecting the check box will display the current object in the browser.
Otherwise, the object will be hidden.
Group Selecting the check box will lead to grouping the current object type in
folders within the browser.
Show all Displays all the available object types in the browser.
Group all Groups all the shown object types in folders.
Opens the help page from the tool’s documentation regarding this topic. A
pane opens in the right-hand side of the dialog box where the content
displays.
Note
By clicking the Customize Browser Contents button from the browser’s toolbar, the
Preferences (Filtered) Dialog Box displays where you can perform the same operations
above.
Related Topics
Preferences (Filtered) Dialog Box
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Setting Preferences
Logging
Logging
To access: Tools > Preferences > Logging
On the Logging page, you can enable/disable displaying errors and warnings in the Console tab.
Figure 12-9. Preferences Dialog Box - Logging Page
Objects
Table 12-7. Preferences Dialog Box - Logging Page Contents
Name Description
Show timestamp in log Allows you to show the time and date of the log messages in
messages the Console tab.
Display errors and warnings in Allows you to enable/disable displaying error and warning
Console messages in the Console tab.
Log Level Choose an option from the dropdown list; Error/Warning/
Note/Plain/Debug. This is used for specifying to which level
the messages will be displayed. For example, if you select
“Note”, this means that you want to display notes, plain and
debug messages.
Related Topics
Tools Menu
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Setting Preferences
Logging
Console
To access: Tools > Preferences > Logging > Console
On the Console page, you can customize the appearance (for example, color and font) of
different messages in the Console tab.
Figure 12-10. Preferences Dialog Box - Console Page
Objects
Table 12-8. Preferences Dialog Box - Console Page Contents
Name Description
Error, Warning, Note, Plain, Allows you to set different colors for each type of message
Debug, Transcript Api, Prompt that displays in the Console tab.
messages color
Max size of command history Allows you to set the size you want to allocate for the
commands’ history for future retrieval.
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Setting Preferences
Logging
Related Topics
Tools Menu
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Setting Preferences
Project Management
Project Management
To access: Tools > Preferences > Project Management
On the Project Management page you can set the project management and project paths’
preferences.
Through this page, you can also allow the design import process to ignore all the directories that
contain “.svn”, “CVS” and any other strings you add. You can also edit the default list of
Verilog extensions allowed in SystemVerilog-VHDL Assistant. By adding any file that has one
of the defined extensions to a project, SystemVerilog-VHDL Assistant will be able to parse this
file and identify its dialect accordingly.
Figure 12-11. Preferences Dialog Box - Project Management Page
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Setting Preferences
Project Management
Objects
Table 12-9. Preferences Dialog Box - Project Management Page Contents
Name Description
Default Location for New Allows you to edit the default location for creating new projects
Projects using a pre-defined environment variable, absolute path or
relative path.
Note: This option only applies when creating a new
SystemVerilog-VHDL Assistant project from within
SystemVerilog-VHDL Assistant not from HDL Designer Series.
Default Location for New Allows you to edit the default location for creating new files.
Files
Default Template Project Allows you to change the default template project or add another
Path template project using a pre-defined environment variable,
absolute path or relative path.
Load previously opened On invoking SystemVerilog-VHDL Assistant you can enable/
projects disable the loading of projects opened in the previous invocation
of SystemVerilog-VHDL Assistant.
Open previously opened On re-opening a project you can enable/ disable opening of
files previously opened project files.
Apply Save project Allows you to enable/ disable saving projects automatically
automatically after changes while closing a SystemVerilog-VHDL Assistant project.
Store paths in relative form Allows you to store all possible path entries in relative form.
(./../) where possible Refer to Ensuring SystemVerilog-VHDL Assistant Project
Portability for more information.
Store paths using matching Allows you to store all possible path entries using the most
environment variables where matching environment variable. Refer to Ensuring
possible SystemVerilog-VHDL Assistant Project Portability for more
information.
Environment Variables This option is only enabled when the option “Store paths using
matching environment variables where possible” is selected.
All: Allows you to use all the available environment variables.
Specified: Allows you to use specific environment variables.
These environment variables should be listed in the “List of
environment variables” field.
List of environment Allows you to enter a list of Environment Variables you want to
variables use when using soften paths. Its default value is
SVASSISTANT_HOME. Note that this option is only enabled
when the option “Specified” is selected.
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Setting Preferences
Project Management
Note
The Default Directories to Ignore text box supports glob expressions. All glob expressions
are allowed, except the NOT expression (for example, ~).
By hovering over different options on this page of the dialog box, tooltips are displayed with the
corresponding descriptions.
Related Topics
Tools Menu
Reloading a Project
New Project Wizard
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Setting Preferences
Build Management
Build Management
To access: Tools > Preferences > Build Management
On the Build Management page, you can set the preferences related to the generation of a
project Makefile.
Figure 12-12. Preferences Dialog Box - Build Management Page
Objects
Table 12-10. Preferences Dialog Box - Build Management Page Contents
Name Description
Default Makefile Name Allows you to edit the default name of the auto-generated
Makefile.
Default Directory in which Allows you to browse or edit the default directory location where
to generate Makefile and the Build operation will be performed.
perform Build When you change this default directory, default location changes
for all future new build libraries.
Auto update makefile Allows you to enable/ disable displaying a prompt when the
without Prompt auto-generated Makefile needs to be re-generated. In the case of
choosing not to display the prompt, the Makefile will be
automatically updated.
Prompt for build process Allows you to enable/ disable displaying warning popup
warnings messages if there were any problems encountered during the
build process.
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Setting Preferences
Build Management
Note
By hovering over different options in this page of the dialog box, tooltips are displayed with
the corresponding descriptions.
Related Topics
Tools Menu
Building a SystemVerilog-VHDL Assistant Project
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Setting Preferences
Class Diagram
Class Diagram
To access: Tools > Preferences > Class Diagram
On the Class Diagram page, you can specify what you want displayed in you visualized class
diagram.
Figure 12-13. Preferences Dialog Box - Class Diagram Page
Objects
Table 12-11. Preferences Dialog Box - Class Diagram Page Contents
Name Description
Enable Comment Extraction Allows you to enable/disable the display of comments on the
class diagram’s objects. When checked, the tooltips of the
objects will show their associated code comments. Also, the
main visualized class will have its code comments displayed in
the diagram in a yellow box.
Show UVM/OVM Contents Allows you to show or hide the details of UVM/OVM classes in
class diagrams. When checked, any UVM/OVM classes in the
class diagram will have their contents displayed, namely
declarations and methods.
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Setting Preferences
Class Diagram
Table 12-11. Preferences Dialog Box - Class Diagram Page Contents (cont.)
Name Description
Show User Class Contents Allows you to show or hide the details of the class in class
diagrams. When checked, any user class in the class diagram
will have its contents displayed, namely declarations and
functions.
Show User Class Initial Allows you to show or hide the initial value if specified by the
values user in the class declaration.
Show Enum Content Allows you to show or hide the available values of the enum in
class diagrams.
Show Generalization Allows you to show or hide the inheritance relation between two
Relationships classes in class diagrams.
Show Instance Aggregation Allows you to show or hide the Instance Aggregation
Relationships Relationship denoted by an arrow which shows instances of
other classes, it points from the parent to the instanced class.
Show Type Dependencies Allows you to show or hide the types of objects declared or
referenced. It applies to a class or an enum.
Object Box Width Limit (# of Controls the object box size for the displayed class diagram.
characters)
Note
By hovering over different options in this page of the dialog box, tooltips are displayed with
the corresponding descriptions.
For detailed information on the contents of the Class Diagram page, refer to Class Diagram
Notation.
Related Topics
Tools Menu
Class Diagram Notation
Visualizing a Class
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Setting Preferences
Keys
Keys
To access: Tools > Preferences > Keys
On the Keys page, you can edit all SystemVerilog-VHDL Assistant shortcuts by adding,
removing, or updating current shortcuts.
Figure 12-14. Preferences Dialog Box - Keys Page
Objects
Table 12-12. Preferences Dialog Box - Keys Page Contents
Name Description
Scheme Allows you to choose the default scheme.
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Setting Preferences
Keys
Related Topics
Using SystemVerilog-VHDL Assistant Text Editor
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Setting Preferences
Project Settings Dialog Box
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Setting Preferences
Project Management
Project Management
To access: Tools > Project Settings > Project Management
On the Project Management page, you can browse to a default Template Project. You can also
allow the design import process to ignore all the directories that contain “.svn”, “CVS” and any
other strings you add.
Furthermore, you can edit the default list of Verilog extensions allowed in SystemVerilog-
VHDL Assistant. By adding any file that has one of the defined extensions to a project,
SystemVerilog-VHDL Assistant will be able to parse this file and identify its dialect
accordingly.
Figure 12-15. Project Settings Dialog Box - Project Management Page
Objects
Table 12-13. Project Settings Dialog Box - Project Management Page Contents
Name Description
Location for New Files Allows you to edit the location for creating new files.
Template Projects Paths Allows you to change the template project paths or add another
template project using a pre-defined environment variable,
absolute path or relative path.
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Setting Preferences
Project Management
Table 12-13. Project Settings Dialog Box - Project Management Page Contents
Name Description
Store paths in relative form Allows you to store all possible path entries in relative form.
(./../) where possible Refer to Ensuring SystemVerilog-VHDL Assistant Project
Portability for more information.
Maximum number of Allows you to enter a limit for the relative levels in relative
allowed up levels in relative paths. This option is only enabled when the option “Store paths
paths in relative form (./../) where possible” is selected.
Store paths using matching Allows you to store all possible path entries using the most
environment variables where matching environment variable. Refer to Ensuring
possible SystemVerilog-VHDL Assistant Project Portability for more
information.
Environment Variables This option is only enabled when the option “Store paths using
matching environment variables where possible” is selected.
All: Allows you to use all the available environment variables.
Specified: Allows you to use specific environment variables.
These environment variables should be listed in the “List of
environment variables” field.
List of environment Allows you to enter a list of Environment Variables you want to
variables use when using soften paths. Its default value is
SVASSISTANT_HOME. Note that this option is only enabled
when the option “Specified” is selected.
Directories to Ignore Allows you to specify which directories should be ignored when
adding existing files. It has two default values: “.svn” and
“CVS”. Strings should be separated by spaces.
So, for example, if the dialog box contains the string “.svn” then
any folder called .svn will be shown in the Add Files to Project
Dialog Box but it will not be imported; the same applies to any
files that contain the “.svn” string in their paths.
Verilog File Extensions This field displays the default list of Verilog extensions allowed
in SystemVerilog-VHDL Assistant. You can use this field to edit
the Verilog extensions that should be identified by
SystemVerilog-VHDL Assistant separated by spaces. When any
files having those extensions are added to a project,
SystemVerilog-VHDL Assistant will parse those files and detect
their dialects. When you edit this field, you will be prompted
whether you need to reload the current project to be updated with
the modified values.
Extension for New Files Enables you to set the file extension for the new files by choosing
an option from the drop-down list.
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Setting Preferences
Project Management
Note
The Directories to Ignore dialog box supports glob expressions. All glob expressions are
allowed except the NOT expression (for example, ~).
Related Topics
Referencing a Template Project
New Project Wizard
Tools Menu
Add Files to Project Dialog Box
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Setting Preferences
Build Management
Build Management
To access: Tools > Project Settings > Build Management
On the Build Management page you can edit the name of the auto-generated Makefile and set
the Questa executable directory location.
Figure 12-16. Project Settings Dialog Box - Build Management Page
Objects
Table 12-14. Project Settings Dialog Box - Build Management Page Contents
Name Description
Generated Makefile Name Allows you to edit the name of the auto-generated Makefile. If
this field was left empty, upon clicking the OK button, an error
message will be displayed in the dialog box informing you that
the Makefile Name can’t be an empty value.
Directory in which to Allows you to browse or edit the directory location where the
generate Makefile and Build operation will be performed.
perform Build When you change this default directory, default location changes
for all future new build libraries.
Simulator executable Allows you to set the Simulator executable directory location.
directory location You can browse to a different Simulator executable directory
location by clicking on the adjacent Browse button.
Its default value is detected by SystemVerilog-VHDL Assistant.
SystemVerilog-VHDL Assistant searches in the PATH
environment variable for the Simulator installation.
Related Topics
Tools Menu
Add Files to Project Dialog Box
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Setting Preferences
Build Management
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Setting Preferences
Verilog/SystemVerilog
Verilog/SystemVerilog
To access: Tools > Project Settings > Verilog/SystemVerilog
On the Verilog/SystemVerilog page, you can specify your +defines to be taken in consideration
when parsing the project.
Figure 12-17. Project Settings Dialog Box - Verilog/SystemVerilog Page
Objects
Table 12-15. Project Settings Dialog Box - Verilog/SystemVerilog Page
Contents
Name Description
Macro Definitions This is where you specify your +defines to be taken in consideration
when parsing the project, for example, +define+SIZE=13. If you
specify an invalid +defines and press the OK button, an error message
will be displayed at the top of the page. When you edit this field, you
will be prompted whether you need to reload the currently opened
projects to be updated with the modified values.
Update project build Choosing this option updates the build settings pages with the Macro
defines definitions you specified, to be taken in consideration when building the
project.
Related Topics
Build Settings
Specifying Project Settings
Project Settings Dialog Box - Build Settings Page
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Setting Preferences
Standard Libraries
Standard Libraries
To access: Tools > Project Settings > Standard Libraries
On the Standard Libraries page you can edit the settings of the UVM/OVM libraries that were
automatically added to the project.
Figure 12-18. Project Settings Dialog Box - Standard Libraries Page
Objects
Table 12-16. Project Settings Dialog Box - Standard Libraries Page Contents
Name Description
Add the following UVM/ Selecting this option activates the following three entries in the
OVM library source files to dialog box: Version, Location, and Copy to project directory.
the project
Version Allows you to select the library version that you want to add to
your project. The default is UVM 1.1d. Selecting None does not
add a library to the project and removes any previously added
libraries
Location Allows you to specify the location of the source library to be
added to your project using a pre-defined environment variable,
absolute path or relative path.
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Setting Preferences
Standard Libraries
Table 12-16. Project Settings Dialog Box - Standard Libraries Page Contents
Name Description
Copy to project directory When this option is selected, the library source files are copied
into the project instead of referencing to their location, example:
“<hds_installation_directory>/svassistant/examples/labs”. The
default is to copy the library source files into the project.
Create a build library in Creates a user library, adds the library’s source files to it and
which to compile the UVM/ compiles these files when simulating the project.
OVM library files
Use the pre-compiled Uses the pre-compiled UVM/OVM library specified in the
version of the UVM/OVM Location text box below when simulating the project.
library
Location If you selected to use the precompiled version of the build library
above, the location of the precompiled UVM/OVM library is
specified here. The default value is the path to the precompiled
libraries in Questa, if available. If you change this path,
SystemVerilog-VHDL Assistant will create an external library to
map to the path you specified using a pre-defined environment
variable, absolute path or relative path.
Related Topics
Tools Menu
Add Files to Project Dialog Box
New Project Wizard
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Setting Preferences
Check Settings
Check Settings
To access: Tools > Project Settings > Check Settings
SystemVerilog-VHDL Assistant allows you to perform checking on your active project. Prior to
running checks, the Check Settings page of the Project Settings dialog box allows you to set
your policy, ruleset, and exclusion file locations. You can also choose your policy and enable/
disable pragma exclusions.
Figure 12-19. Project Settings Dialog Box - Check Settings Page
Objects
Table 12-17. Project Settings Dialog Box - Check Settings Page Contents
Name Description
Policy Location Specify or browse to the path location of your policy.
TB Policy Allows you to choose from the drop-down menu the policy
you want to apply to the DesignChecker analysis of your test
bench. The default policy for test benches is
Verification_UVM_Policy/Verification_OVM_Policy.
RTL Policy Allows you to choose from the drop-down menu the policy
you want to apply to the DesignChecker analysis of your RTL
design. The default policy for RTL designs is
My_Essentials_Policy.
RuleSet Location Specify or browse to the path location of your ruleset.
Exclusion File Location Specify or browse to the path location of your exclusion file.
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Setting Preferences
Check Settings
Table 12-17. Project Settings Dialog Box - Check Settings Page Contents
Name Description
Enable pragma exclusions Check/Uncheck this option to enable/disable pragma
exclusions. On checking this option, you can skip RTL code
blocks while running a DesignChecker analysis.
Manage Policies/ RuleSets Clicking this button invokes the DesignChecker tool in order
to set up policies and rules.
Restore Defaults Disregards any modifications you have made and reverts to
the default define macros.
Apply Click it to apply the new changes.
Related Topics
Project Settings Dialog Box - Check Settings Page
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Setting Preferences
RTL Instancing
RTL Instancing
To access: > Tools > Project Settings > RTL Instancing
SystemVerilog-VHDL Assistant supports RTL object instancing in Verilog/SystemVerilog and
VHDL files.
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Setting Preferences
RTL Instancing
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Setting Preferences
RTL Instancing
Tip
Hover your cursor over any Verilog/SystemVerilog Instancing option to display the
available information about this option.
Objects
Table 12-18. Project Settings Dialog Box - Verilog/SystemVerilog Instancing
Page Contents
Name Description
Instancing name rule Allows you to define the naming convention to follow when
instancing a new RTL object. A numeric suffix is
automatically added after the defined name to indicate the
instance number.
Port mapping style Select the port mapping style to use when instancing a new
RTL object. The default selection is “Named”.
Parameter mapping style Select the parameter mapping style to use when instancing a
new RTL object. The default selection is “Named”.
Create declarations for required Creates the required declarations for new signals (signal
new signals (signal stubs) stubs) before connecting them to the instance.
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Setting Preferences
RTL Instancing
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Setting Preferences
RTL Instancing
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Setting Preferences
RTL Instancing
Tip
Hover your cursor over any VHDL Instancing option to display the available information
about this option.
Objects
Table 12-19. Project Settings Dialog Box - VHDL Instancing Page Contents
Name Description
Instancing name rule Allows you to define the naming convention to follow when
instancing a new RTL object. A numeric suffix is
automatically added after the defined instancing name to
indicate the instance number.
Create declarations for required Creates the required declarations for new signals (signal
new signals (signal stubs) stubs) before connecting them to the instance.
Create unique signals Creates unique signals declaration names and connects them
decelerations names to the instance. This option is applicable only if the “Create
declarations for required new signals (signal stubs)” option is
checked.
Retain port comments in the Retains any comments associated with object’s ports
corresponding instance declarations when an instance is created from this object.
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Setting Preferences
RTL Instancing
Table 12-19. Project Settings Dialog Box - VHDL Instancing Page Contents
Name Description
Insert configuration statement Inserts the configuration statement after the instance
after component declaration declaration. This is applicable only if the instance
configuration statement is not already inserted in the same
file.
Add synthesis pragma Adds synthesis pragma to the configuration statement.
Extract Entity generics Extracts the entity generics and maps each generic declaration
to its default value.
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Setting Preferences
Build Settings
Build Settings
To access: Tools > Project Settings > Build Settings
The Build Settings Pages enable you to configure the tools that shall be used later in building
the project. The Build Settings pages are used as part of the whole building process as follows:
After having created your project’s build libraries and added design files to them, you use these
pages to configure the tools to be used in building those libraries. In the following stage of
generating the Makefile, the information supplied in these pages are added to the Makefile. The
final stage would be then building the project.
The Project Settings Dialog Box - Build Settings Page consists of several sub-pages. Use the
tree in the left pane to open the required page. The first page you encounter when you open the
dialog box is the Build Settings page.
Figure 12-22. Project Settings Dialog Box - Build Settings Page
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Setting Preferences
Build Settings
Objects
Table 12-20. Project Settings Dialog Box - Build Settings Page Contents
Name Description
Active build configuration Use the drop-down list to select the name of the downstream
family you will use to build the project (such as QuestaSim).
Also you can use a pre-defined environment variable, absolute
path or relative path.
Project build defines Instead of adding `define directives in your HDL code, you
can use this table to specify the define macros that need to be
passed during building the project.
To make an entry in the table, single-click in the cell, type
your entry, and then press Enter. You can alternatively press
the New button and type your entries.
To delete an entry, select the entry, and press Delete or the
Remove button.
Restore Defaults Disregards any modifications you have made and reverts to
the default define macros.
Apply Click it after Choosing the Active build configuration and
adding or removing an entry to apply the new changes.
OK Closes the dialog box after saving the new modifications.
Cancel Cancels the operation and closes the dialog box.
Related Topics
Project Settings Dialog Box - Build Settings Page
Tools Menu
Building a SystemVerilog-VHDL Assistant Project
Specifying Project Settings
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Setting Preferences
Properties Dialog Box
• Right-click on the projects node, a folder or a single file then select Properties.
• Press Alt+Enter
Properties - Resource page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Properties - Resource Filters page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Properties - Refactoring History page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
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Setting Preferences
Properties - Resource page
Objects
Name Description
Path Indicates the location of the selected projects’ node, folder or
the single file within the workspace.
Type Indicates the type of the selected resource. i.e. Project, Folder
or File.
Location Indicates the location of the selected projects’ node, folder or
the single file on your desk.
Last modified Indicates the last modified date and time for the selected
resource.
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Setting Preferences
Properties - Resource page
Name Description
Attributes Allows you to change the attributes of the selected resource to
Read only, Archive or Derived.
Text file encoding Sets an alternate text coding. It allows you to either inherit the
encoding of the text file from container (Cp1252) i.e. the
selected resource inherits the text encoding specified for its
container resource or choose Other if you want to work with
text files that originate from another source and select an
appropriate one from the drop down options.
Store the encoding of derived Checking this option will store the encoding of derived
resources separately resources in a separate preferences file. Note that this option is
available if a project was selected.
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Setting Preferences
Properties - Resource Filters page
Objects
Name Description
Add button Allows you to add filters to the selected project/ folder.
Add Group button Allows you to add group filters to the selected project/ folder.
Edit button Allows you to edit filters to the selected project/ folder.
Remove button Allows you to delete filters to the selected project/ folder.
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Setting Preferences
Properties - Refactoring History page
Objects
Name Description
Remove button Allows you to delete history for the selected project.
Remove All button Allows you to delete all history for the selected
project.
Persist project refactoring history in Checking this option will persist project refactoring
project folder instead of workspace history in project folder instead of workspace.
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Chapter 13
Working with External Tools
SystemVerilog-VHDL Assistant has external tools that allow you to configure and run
programs, batch files, and other configurations. You can save these external tool configurations
to run them later.
External Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Process Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
External Tools
External tools are used to configure and run programs, batch files, and other configurations.
You can save and choose to run these configurations later.
Output from external tools is displayed in the Process Console. For more information, see
“Process Console” on page 425.
The following variables are available when you configure an external tool. These variables are
automatically expanded each time the external tool runs.
Variable Name Description
${workspace_loc} The absolute path to SVA workspace directory.
The default location is %APPDATA%\SVAssistant\
ec_prefs\ec_user on Windows and $HOME/
SVAssistant/ec_prefs/ec_user on Linux.
Note: If the environment variable
SVASSISTANT_USER_HOME is set before
invoking SystemVerilog-VHDL Assistant, the
workspace location would be
${SVASSISTANT_USER_HOME}/ec_prefs/ec_user
Example:
SVASSISTANT_USER_HOME=”C:/Workspace”
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Working with External Tools
External Tools
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Working with External Tools
External Tools
Examples
Assume your workspace directory is C:\workspace\ec_prefs\ec_user and you have two projects,
MyProject1 and MyProject2.
The first project, MyProject1, is located inside the workspace directory. The second project,
MyProject2, is located outside the workspace directory at C:\projects\MyProject2. If the
resource /MyProject2/MyFolder/MyFile.txt is selected, the variable examples in External Tools
Variable Examples will be expanded when an external tool is run.
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Working with External Tools
External Tools
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Working with External Tools
Process Console
Process Console
The Process Console shows the output of a process and allows you to provide keyboard input to
a process. The Process Console shows three kinds of text:
• Standard output
• Standard error
• Standard input
Objects
Table 13-2. Process Console Icons
Icon Name Description
Clear Console Clears the currently active console.
Display Selected Console Opens a listing of current consoles and
allows you to select which to display.
Open Console Opens a new console of the selected type.
Pin Pins the current console to remain on top of
all other consoles.
Scroll Lock Determines if scroll lock should be enabled
or not in the current console.
Remove All Terminated Removes all of the terminated launches from
Launches the current console.
Remove Launch Removes the current launch from the
console.
Terminate Terminates the running launch in the current
console.
Show Console When Opens and brings a console to the front when
Standard Out Changes information is written to the System.out
stream.
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Working with External Tools
Process Console
Related Topics
External Tools
Using the Console Tab
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Appendix A
Internal Variables
This appendix lists SystemVerilog-VHDL Assistant template and build manager internal
variables.
System Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Build Manager Internal Variables (Macros). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
System Variables
System variables can be used in templates.
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Internal Variables
Build Manager Internal Variables (Macros)
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Internal Variables
Build Manager Internal Variables (Macros)
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Internal Variables
Using Internal Variables
Note that spaces are not allowed. During Makefile generation, the Build Manager replaces each
%(variablename) with the value of the corresponding project resource currently being visited
by the Build Manager. A Build variable can have a rule by which it is substituted. This rule is
defined in the tool build model file (.bld). For example, QuestaSim vlog defines a rule for the
work library variable %(WorkLib) such that it is always substituted by -work <build library
name>.
If, for any reason, the value of the variable cannot be substituted, the resultant command written
to the Makefile will have the non-substituted string %(variablename) and hence an error will
occur if the make utility invokes that command.
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Appendix B
Command Line Switches
The following command line switches can be used when you invoke SystemVerilog-VHDL
Assistant from HDL Designer Series or directly from a shell.
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Command Line Switches
Running SystemVerilog-VHDL Assistant in Batch Mode
Lets explore the example below to figure out how we can run the different SystemVerilog-
VHDL Assistant flows in batch mode. The example shows a TCL script in which
SystemVerilog-VHDL Assistant APIs have been embedded to trigger various SystemVerilog-
VHDL Assistant functions. The project name and project path are passed to the script as two
command line arguments.
The script is based on the multadd_uvm project and is invoked using the following command:
Where:
To facilitate your understanding of the script, you will divide it into six parts:
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Command Line Switches
Preparing Working Environment
::setApplicationExitCode 3
return
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Command Line Switches
Opening Intended Project and Configuring Its Top Level
Using our previously defined assert procedure, we will check for the existence of the entered
project path. If not found, SystemVerilog-VHDL Assistant exits and an error is logged to the
standard output.
::enableOutputLogging 1 $PROJ_DIR/logs/OutputLog.txt
::enableBuildLogging 1 $PROJ_DIR/logs/BuildLog.txt
::enableChecksLogging 1 $PROJ_DIR/logs/ChecksLog.txt
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Command Line Switches
Compiling and Simulating (Building) the Design
We then run the configured check policy on the “multadd_uvm” project using the API
::dcCheckProjectOp.
::dcCheckProjectOp $PROJ_NAME
::setUsePrecompiledUvmLibrary 1 $PROJ_NAME
::buildProjectOp $PROJ_NAME
We will configure our assert procedure to exit upon not locating the Makefile or the compiled
library. This will cause the application to exit and will issue an error message.
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Command Line Switches
Visualizing the Design
We will use Questa to simulate the design and therefore we will need to configure it to run in
batch mode as well.
As our build configuration has changed we will need to re-generate the project Makefile.
::generateMakefileOp $PROJ_NAME
Now we can simulate the UVM test “minmax_test” by setting the value of the environment
variable "SVASSISTANT_SIM_OPTIONS" to "+UVM_TESTNAME=minmax_test".
Finally, we will call the assert procedure to flag an error incase of a simulation failure and cause
the application to exit.
You may need to focus on only one of the project classes and therefore produce a visualization
of it only and not of the whole project. In our code, we will visualize the “rand_test” class using
the API ::visualizeClassByFilePathOp and check that the visualization file was generated.
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Command Line Switches
Creating a Coverage Component
Our assert function will throw an error message "Extend of Class Failed" incase the
“newcov.svh” file is not detected in the path specified in our API.
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Command Line Switches
Creating a Coverage Component
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Appendix C
Error and Warning Messages
The SystemVerilog-VHDL Assistant message system helps you identify and troubleshoot
problems while using the application. The messages display in the Errors and Warnings browser
and in the Output browser transcript. Accordingly, you can access the issued messages from a
saved transcript file.
Messages are categorized into errors and warnings.The severity level of the messages are
predefined and can not be changed.
Miscellaneous Messages
This section describes miscellaneous messages that may be associated with SystemVerilog-
VHDL Assistant.
Suggested Action
Analyze the reported files to detect the reason and fix it. The inability to extract information can
be due to one of these reasons:
`ifdef FILE1_SVH
`define FILE1_SVH
class theOldClass;
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Error and Warning Messages
Miscellaneous Messages
endclass
`endif
file1.svh:
`ifdef FILE1_SVH
`define FILE1_SVH
class theClass;
endclass
`endif
module top;
`ifdef TEST
`include “incl1.svh”
`else
`include “incl2.svh”
`endif
endmodule
In the above example “Include Files”, TEST is not defined and consequently incl1.svh
will not get parsed and the warning will be reported on incl1.svh file. This could be fixed
by setting the TEST define in the Project PlusArgs. Please refer to “Defining Project
Arguments” on page 187.
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Glossary
Analysis Component
The components which receive information about the current status in the test bench and then use
that information to determine the correctness or completeness of the test. Two common kinds of
analysis components are Scoreboards and Coverage Collectors.
Assertion
A statement that a certain property must be true. Assertions allow for automated checking that
the specified property is true and can generate automatic error messages if the property is not
true.
Build Manager
A system that manages the auto-generation of Makefiles for the Build Tools.
Build Tool
A utility within a downstream family that is used to build a project or a single file. For example,
the QuestaSim downstream family contains several build tools such as Questa vlog and Questa
vsim.
Checks
A process in SystemVerilog-VHDL Assistant in which the code is analyzed to perform linting
and UVM/OVM compliance checking. The code is analyzed against the rules preset in the and
the analysis results are reported in DesignChecker.
Child Class
A class which is derived (extended) from a Parent Class and inherits all its properties.
Class
A blueprint, prototype or template from which objects are created.
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Compilation Unit
A portion of the code that can be compiled individually. Examples of compilation units in
SystemVerilog would be modules, packages, interfaces and program blocks.
Component
Components are instantiable objects such as modules in SystemC or modules, interfaces,
program blocks and classes in SystemVerilog.
Coverage Collector
A type of Analysis Component which checks streams of transactions and counts the transactions
or various aspects of the transactions. The purpose is to determine the completeness of the
simulation. The particular thing that a coverage collector counts is dependent on the design and
the specifics of the test; for example, the number of transactions and the number of errors.
Coverage collectors can also perform computations as part of a completeness check; for
example, they may keep a ratio of errors to successful transactions.
Driver
A type of Transactor which converts a stream of transactions into pin level activity.
Environment Component
In Test benches, the environment is the set of components that provide all the needs for the DUT
to operate. The environment components are responsible for generating traffic for the DUT.
They are all transaction level components and have only transaction level interfaces. The most
common kind of environment component is: Stimulus Generators.
Extended Class
A subclass that inherits all the attributes and behaviors of the Parent Class.
Factory
A class that creates objects dynamically. The Factory pattern is an object oriented method used
in software development. OVM implements this pattern through the OVM Factory class.
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Integrated Development Environment- IDE
A software application that provides comprehensive facilities to programmers/engineers for
software/hardware projects development. SystemVerilog-VHDL Assistant is an example of IDE.
Interface
A means of establishing communication between the DUT (Device Under Test) and the UVM/
OVM Test bench modules.
Library
A logical container for the files that have the Compilation Units needed for building. The
dependencies between those Compilation Units are extracted when a Makefile is generated, then
this information is later passed to the Build Tools.
Makefile
A description file containing the targets and dependencies required for the Build Tools. The
information in the Makefile is extracted from the Library and from the configurations in the
Project Build Settings dialog box.
Modport
A means of grouping the signals of a module and controlling their direction. Modport derives
from the keywords “module” and “port”.
Monitor
A type of Transactor which, as the name implies, monitors a bus. It watches the pins and
converts their wiggles to a stream of transactions. Monitors are passive, meaning they do not
affect the operation of the DUT in any way.
Outline Browser
A browser in SystemVerilog-VHDL Assistant that shows the code objects available only in the
active file, which is the file currently opened in the text editor.
OVM Factory
A Factory class that dynamically creates objects of type ovm_object or ovm_component.
Parent Class
A class from which Child Classes can be derived (extended).
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Project
A means of assembling a number of relevant design files in a single entity to facilitate their
management. To be able to work on your designs in SystemVerilog-VHDL Assistant, you have
to create a project and then add design files. Creating a project leads to the creation of a project
file with the extension .svap; this file includes references to the location of any design files you
add to the project.
Projects Browser
A browser in SystemVerilog-VHDL Assistant which provides a comprehensive view of your
projects’ contents, and hence, it is considered the most significant of SystemVerilog-VHDL
Assistant’s browsers. The Projects browser is a tree view listing all the projects created in
SystemVerilog-VHDL Assistant, the source files within each project, and the code objects within
each file. In addition to showing the source files within each project, the browser shows any
available associated files such as documentation files, visualization files, Makefiles, and so on.
QuestaSim
A Mentor Graphics tool used for simulating designs. QuestaSim is the default simulator for
SystemVerilog-VHDL Assistant.
Resource
An HDL object resourced in SystemVerilog-VHDL Assistant and stored in a library to be
analyzed afterwards by Build Tools.
Responder
A type of Transactor which is similar to a driver, but it responds to activity on pins rather than
initiating activity.
Scoreboard
A type of Analysis Component which is used to determine the correctness of the DUT.
Scoreboards take information going into and out of the DUT and determines if the DUT is
responding correctly to its stimulus.
Stimulus Generator
A type of Environment Component which creates a stream of transactions for stimulating the
DUT. Stimulus generators can be random, directed, or directed random; they can be free running
or have controls; and they can be independent or synchronized. The simplest stimulus generator
randomizes the contents of a request object and sends that object to a Driver.
Super Class
Parent Class from which Child Classes can be derived (extended).
SystemVerilog
SystemVerilog is the industry's first unified hardware description and verification language
(HDVL) standard. SystemVerilog is a major extension of the established Verilog language. It
was developed originally by Accellera.
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SystemVerilog-VHDL Assistant
An EDA tool that provides an excellent environment for testing, creating, viewing, modifying
and analyzing Verilog and SystemVerilog designs. It is the first tool thatautomates the design
verification and testing process using the new UVM/OVM techniques.
SystemVerilog Class
A user-defined data type that brings in the essence of object oriented programming to the
SystemVerilog language.
SystemVerilog Include
A SystemVerilog file containing global declarations or other SystemVerilog code which can be
included by reference using the `include compiler directive.
SystemVerilog Interface
An interface encapsulates the connectivity between two or more modules. It can contain initial
and always blocks, tasks and functions and can also define the direction of a signal from a
module using a Modport.
SystemVerilog Module
Any hierarchical portion of a hardware design is described in SystemVerilog by a module.
Modules define both the interface to the block of hardware (i.e. the inputs and outputs) and its
internal structure or behavior.
SystemVerilog Package
An object used to share declarations among modules, programs, interfaces and other packages.
The set of items defined within the package can be used by any design unit that imports that
package.
SystemVerilog Parameter
A constant value declared within the module structure.
Test bench
A software program used to verify the correctness or soundness of a design or model.
Transactor
The role of a transactor in a test bench is to convert a stream of transactions to pin level activity
or vice versa, convert pin level activity into a stream of transactions. Transactors are
characterized by having at least one pin level interface and at least one transaction level
interface. Examples of transactors are: Monitors, Drivers, and Responders.
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Verification
The process of comparing the actual behavior of a design against the expected to determine their
equivalence.
Virtual Folder
A logical folder that can be optionally created in SystemVerilog-VHDL Assistant to organize the
design files inside the Projects Browser. In addition, when adding existing design files to a
project, their physical directory structure on the hard disk is automatically mimicked in the
Projects Browser using virtual folders; removing such virtual folders does not affect the
corresponding physical folders.
Visualization File
A file containing graphical representations of the test bench’s UVM/OVM Components, ports
and connections. The file has the extension .ctv and is saved within the project’s folder on the
hard disk. There is also another type of visualization files having the extension .ctcv. This type
contains graphical representations of the test bench’s classes; it illustrates code-related
information such as the inheritance of classes, their declarations, methods, and so on.
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Index
extended by, 54
Index
—L— —Q—
Library properties, 132 Questa, 103, 140, 141, 183, 415
Run -All, 355, 357, 358
—M—
Makefile
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(“U.S.”) government agencies, which prohibit export, re-export or diversion of certain products, information about the products, and
direct or indirect products thereof, to certain countries and certain persons. Customer agrees that it will not export or re-export Products
in any manner without first obtaining all necessary approval from appropriate local, E.U. and U.S. government agencies. If Customer
wishes to disclose any information to Mentor Graphics that is subject to any E.U., U.S. or other applicable export restrictions, including
without limitation the U.S. International Traffic in Arms Regulations (ITAR) or special controls under the Export Administration
Regulations (EAR), Customer will notify Mentor Graphics personnel, in advance of each instance of disclosure, that such information
is subject to such export restrictions.
13. U.S. GOVERNMENT LICENSE RIGHTS. Software was developed entirely at private expense. The parties agree that all Software is
commercial computer software within the meaning of the applicable acquisition regulations. Accordingly, pursuant to U.S. FAR 48
CFR 12.212 and DFAR 48 CFR 227.7202, use, duplication and disclosure of the Software by or for the U.S. government or a U.S.
government subcontractor is subject solely to the terms and conditions set forth in this Agreement, which shall supersede any
conflicting terms or conditions in any government order document, except for provisions which are contrary to applicable mandatory
federal laws.
14. THIRD PARTY BENEFICIARY. Mentor Graphics Corporation, Mentor Graphics (Ireland) Limited, Microsoft Corporation and
other licensors may be third party beneficiaries of this Agreement with the right to enforce the obligations set forth herein.
15. REVIEW OF LICENSE USAGE. Customer will monitor the access to and use of Software. With prior written notice and during
Customer’s normal business hours, Mentor Graphics may engage an internationally recognized accounting firm to review Customer’s
software monitoring system and records deemed relevant by the internationally recognized accounting firm to confirm Customer’s
compliance with the terms of this Agreement or U.S. or other local export laws. Such review may include FlexNet (or successor
product) report log files that Customer shall capture and provide at Mentor Graphics’ request. Customer shall make records available in
electronic format and shall fully cooperate with data gathering to support the license review. Mentor Graphics shall bear the expense of
any such review unless a material non-compliance is revealed. Mentor Graphics shall treat as confidential information all information
gained as a result of any request or review and shall only use or disclose such information as required by law or to enforce its rights
under this Agreement. The provisions of this Section 15 shall survive the termination of this Agreement.
16. CONTROLLING LAW, JURISDICTION AND DISPUTE RESOLUTION. The owners of certain Mentor Graphics intellectual
property licensed under this Agreement are located in Ireland and the U.S. To promote consistency around the world, disputes shall be
resolved as follows: excluding conflict of laws rules, this Agreement shall be governed by and construed under the laws of the State of
Oregon, U.S., if Customer is located in North or South America, and the laws of Ireland if Customer is located outside of North or
South America or Japan, and the laws of Japan if Customer is located in Japan. All disputes arising out of or in relation to this
Agreement shall be submitted to the exclusive jurisdiction of the courts of Portland, Oregon when the laws of Oregon apply, or Dublin,
Ireland when the laws of Ireland apply, or the Tokyo District Court when the laws of Japan apply. Notwithstanding the foregoing, all
disputes in Asia (excluding Japan) arising out of or in relation to this Agreement shall be resolved by arbitration in Singapore before a
single arbitrator to be appointed by the chairman of the Singapore International Arbitration Centre (“SIAC”) to be conducted in the
English language, in accordance with the Arbitration Rules of the SIAC in effect at the time of the dispute, which rules are deemed to be
incorporated by reference in this section. Nothing in this section shall restrict Mentor Graphics’ right to bring an action (including for
example a motion for injunctive relief) against Customer in the jurisdiction where Customer’s place of business is located. The United
Nations Convention on Contracts for the International Sale of Goods does not apply to this Agreement.
17. SEVERABILITY. If any provision of this Agreement is held by a court of competent jurisdiction to be void, invalid, unenforceable or
illegal, such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect.
18. MISCELLANEOUS. This Agreement contains the parties’ entire understanding relating to its subject matter and supersedes all prior
or contemporaneous agreements. Any translation of this Agreement is provided to comply with local legal requirements only. In the
event of a dispute between the English and any non-English versions, the English version of this Agreement shall govern to the extent
not prohibited by local law in the applicable jurisdiction. This Agreement may only be modified in writing, signed by an authorized
representative of each party. Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent consent, waiver
or excuse.