Ethernet Frame Transmission Using The eZ80F915050 Module: Application Note

Application Note
Ethernet Frame
Transmission Using The
eZ80F915050 Module
AN021201-1104
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applications, or technology described is intended to suggest possible uses and may be superseded.
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AN021201-1104
Application Note
Ethernet Frame Transmission Using The eZ80F915050 Module
iii
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
eZ80Acclaim!™ Flash Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Hardware Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
eZ80F91 50 MHz Module Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
eZ80F91 MCU Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
eZ80® CPU Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ethernet Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Developing an eZ80F91 MCU Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Testing/Demonstrating the Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Appendix A—References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Appendix B—Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Appendix C—Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
C Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Header Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
AN021201-1104 Table of Contents

Application Note
iv
List of Figures
Figure 1. Top-Level View of Hardware Components . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. The Role of the eZ80F915050 Module in Ethernet Connectivity . . . . . 4
Figure 3. The eZ80F915050 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Ethernet Connectivity Blocks on the eZ80F91 MCU . . . . . . . . . . . . . . 5
Figure 5. EMAC Shared Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Buffers in EMAC Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Contents of Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Block Diagram Representation of Hardware Setup . . . . . . . . . . . . . . 14
Figure 9. The Main Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
List of Tables
Table 1. Receive Descriptor Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2. Transmit Descriptor Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. List of References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AN021201-1104 List of Figures

Application Note
Abstract
This Application Note demonstrates the use of ZiLOG products to communicate
over the Ethernet by transferring a frame consisting of data from one unit to
another.
The eZ80F91 MCU features an on-chip Ethernet Media Access Controller
(EMAC) unit with a full-functional 10/100 Mbps Media-Independent Interface (MII).
The eZ80F91 50 MHz (eZ80F915050) module includes an eZ80F91 MCU as well
as a PHY from Advanced Micro Devices that forms the physical transceiver layer
for Ethernet communication. An RJ45 connector is used to plug in standard Ether-
net cables. These features make it easier to use the eZ80F91 MCU for transmit-
ting data over the Ethernet.
Two eZ80F91 development kits, each with eZ80F915050 modules, are connected
using a crossover Ethernet cable. Data is transmitted from one eZ80F91 device to
the other. On the transmission side, user-entered data is compiled into an IEEE
802.3 frame; on the reception side, data is extracted from the frame and displayed
to the user via the HyperTerminal application.
eZ80Acclaim!™ Flash Microcontrollers

eZ80Acclaim!™ on-chip Flash Microcontrollers are an exceptional value for cus-
tomers designing high-performance, 8-bit MCU-based systems. With speeds up
to 50MHz and an on-chip Ethernet MAC (eZ80F91 MCU only), designers have
the performance necessary to execute complex applications quickly and effi-
ciently. Combining Flash and SRAM, eZ80Acclaim!™ devices provide the memory
required to implement communication protocol stacks and achieve flexibility when
performing in-system updates of application firmware.
eZ80Acclaim!™ Flash MCUs can operate in full 24-bit linear mode, addressing
16MB without a Memory Management Unit. Additionally, support for the Z80-com-
patible mode allows Z80/Z180 customers to execute legacy code within multiple
64 KB memory blocks with minimum modification. With an external bus supporting
the eZ80®, Z80, Intel, and Motorola bus modes and a rich set of serial communi-
cations peripherals, designers have several options when interfacing to external
devices.
Some of the many applications suitable for eZ80Acclaim!™ devices include vend-
ing machines, point-of-sale terminals, security systems, home and building auto-
mation, communications, industrial control and facility monitoring, and remote
control.
AN021201-1104 Abstract
Application Note
Discussion
This Application Note is intended to demonstrate the capability of the EMAC unit
on the eZ80F91 MCU. Transmitting data over the Ethernet offers multiple options
that can be configured using the eZ80F91 MCU’s many registers. In addition, this
document also discusses the framing of data in accordance with IEEE 802.3 stan-
dards.
An IEEE 802.3 frame consists of a 14-byte header, 46 to 1500 bytes of data, and
an optional 4-byte cyclic redundancy check. The 14-byte header consists of a 6-
byte source address, a 6-byte destination address, and a 2-byte type/length field.
To explain data transmission requires a brief discussion of the OSI Model, which
consists of seven layers, as described below, in order from the top layer to the
bottom layer.
Application. Governs how a particular application uses a network
Presentation. Governs how data is represented
Session. Governs the establishment of communication with a remote system
Transport. Governs how data is transferred
Network. Governs how assignments and the forwarding of packets are addressed
Data Link. Governs how frames are sent over a network
Physical. Governs basic network hardware
For Ethernet data transmission, information from the upper five layers is compiled
into the Data field of an IEEE 802.3 frame. The Data Link and Physical layers
depend very closely on the hardware, and must be understood clearly to imple-
ment the top layers. This Application Note will show how the Physical and Data
Link layers are implemented using ZiLOG development kits.
Hardware Components
A top-level view of the application’s required hardware components is shown in
Figure 1.
®
eZ80
eZ80F915050
Development
Module
Platform Ethernet
cable
Figure 1. Top-Level View of Hardware Components
AN021201-1104 Discussion
Application Note
eZ80® Development Platform

The eZ80® Development Platform contains a number of peripheral devices,
including memory and connectors, to aid developers in evaluating the
eZ80Acclaim!™ family of devices for a number of applications. Two 50-pin con-
nectors, JP1 and JP2, allow the eZ80F91 MCU and other modules to be con-
nected to this board. The ZiLOG Debug Interface (ZDI), available on the board,
connects to a Target Interface Module (TIM) that provides a method of download-
ing code to the MCU. A console port on the eZ80® Development Platform can be
used to connect a serial cable to a computer to provide a user interface via the
HyperTerminal application. The eZ80® Development Platform contains 512 KB
SRAM in the address range B80000h–BFFFFFh that can be used to store pro-
gramming instructions.
eZ80F915050 Module
ZiLOG’s eZ80F915050 Module includes AMD’s NetPHY AM79C874, a RJ45 con-
nector to connect to the Ethernet via cable, and the eZ80F91 MCU, which fea-
tures an on-chip Ethernet Media Access Controller (EMAC) unit. The PHY and the
EMAC unit together implement the Physical Layer for Ethernet data transmission.
Figure 3 shows the eZ80F915050 Module with the eZ80F91 MCU, the AMD
79C874 PHY, and the RJ45 connector. In addition, the eZ80F915050 module con-
tains 512 KB SRAM that can be used to store programming instructions. The
range of module memory can be set by the user.
Ethernet Cables
The Ethernet cable that connects the eZ80® Development Platform and the
eZ80F81 Module to the Ethernet can either be a patch cable or a crossover cable,
depending on the configuration of the network, as explained below.
Patch Cable. When an Ethernet hub is used, CAT5 patch cables are used to trans-
mit data. An Ethernet hub takes care of connecting the signals to make an Ether-
net network. While transferring frames an IP address is not used. For this
application, patch cables are therefore used only in the programming interface.
Patch cables are usually blue in color and occasionally green.
Crossover Cable. Crossover cables allow connection without a hub. In a crossover
cable, the signal lines are crossed over so that the Transmit pin on one side gets
connected to the Receive pin on other side and vice versa. These cables are usu-
ally orange in color to differentiate them from patch cables.
eZ80F91 50 MHz Module Description

Figure 2 depicts the components used by eZ80F915050 Module for Ethernet
transmission from one eZ80Acclaim!™ development kit to another. These compo-
nents—the eZ80F91 MCU, the PHY, the MII Interface, and the RJ45 connector—
are described in this section.
Application Note
MII
eZ80F91 RJ45
PHY
MCU Connector
Ethernet
cable
Figure 2. The Role of the eZ80F915050 Module in Ethernet Connectivity
The eZ80F915050 Module features an on-board eZ80F91 MCU, a PHY, and an

RJ45 connector to transmit data from one location to another. Figure 3 shows a
picture of the eZ80F915050 Module.
RJ45
Connector
eZ80F91 AMD
with 79C874
On-Chip PHY
EMAC
Module
Figure 3. The eZ80F915050 Module
eZ80F91 MCU
The eZ80F91 MCU is based on the eZ80® CPU core. The eZ80F91 MCU blocks
used in this application are the EMAC unit, the EMAC Control Registers, a mem-
ory address decoder, the UART block, an interrupt controller, and on-chip mem-
ory. Further details about the eZ80® blocks are discussed in the eZ80F91 MCU
Description section on the next page.
Application Note
PHY
PHY is a Physical Layer Transceiver device. Different manufacturers produce
PHYs with different characteristics. The hardware described in this Application
note uses an eZ80F915050 Module that includes AMD’s Am79C874 PHY. The
AMD PHY can receive and transmit data reliably at over 130 meters. It also
includes input filtering and output wave shaping for unshielded twisted pair opera-
tion. In addition, if set to autonegotiation mode, it can determine network speed
and the full or half-duplex modes of operation. For more information related to the
AMD PHY, refer to AMD documentation.
MII Interface
The MII interface provides a simple standard connection between the EMAC and
the PHY. The MII is designed to make the differences more transparent between
various media, such as shielded or unshielded differential wire pairs, Ethernet
cables, and the MAC sublayer. The end result is that the CPU can act indepen-
dently of media type.
The MII consists of 15 signals, including a 4-bit-wide receive data bus, a 4-bit-
wide transmit data bus, and control signals to facilitate data transfers between the
PHY and the EMAC.
RJ45 Connector
A RJ45 connector is used to connect the Ethernet cables to the PHY for the pur-
pose of transmitting data over the Ethernet.
eZ80F91 MCU Description

Figure 4 shows the blocks on the eZ80F91 MCU, and their role in Ethernet con-
nectivity.
Internal EMAC
Memory Registers
® EMAC
External eZ80 EMAC
Shared
Memory CPU Unit
Memory MII
Figure 4. Ethernet Connectivity Blocks on the eZ80F91 MCU
Application Note
The eZ80F91 MCU consists of eZ80® CPU, on-chip memory, and an Ethernet
Media Access Controller consisting of EMAC registers, EMAC shared memory,
and an EMAC unit.
eZ80® CPU Description

The eZ80® CPU is the main functional unit that reads programming instructions
from memory and executes them. More details regarding the eZ80® CPU can be
found in the eZ80® CPU User Manual (UM0077); this document is available on
zilog.com.
Memory Description
Memory provides for the storage of instructions that, when executed by the eZ80®
CPU, set up and command the EMAC and the PHY to send and receive Ethernet
frames. Memory is included on the eZ80F91 MCU, the eZ80F915050 Module,
and on the eZ80® Development Platform. For a map of the memory available on
the chip, module, and platform, refer to the eZ80F91 Product Specification
(PS0192) and the eZ80F91 Module Product Specification (PS0193). The code
used for this application is listed in Appendix C on page 25.
On-Chip Memory. The eZ80F91 MCU features 8 KB of on-chip SRAM that, on
power-up, is mapped to the address range FFE000h–FFFFFFh. This RAM memory
can be mapped to the top of any 64 KB block, or it can be disabled.
The eZ80F91 MCU also features 256 KB of Flash memory that can be used to
store programming instructions. This memory can be mapped anywhere in the
address space.
Module Memory. The eZ80F915050 Module contains 512 KB of SRAM for storing
program instructions. The user can map this memory to a different address range,
if appropriate.
Platform Memory. The eZ80® Development Platform contains 512 KB of SRAM in
the address range B80000h–BFFFFFh that can be used to store programming
instructions.
On-Chip EMAC Unit Description

The eZ80F91 MCU contains a full-function 10/100 Mbps Ethernet Media Access
Controller (EMAC) unit that also includes a Media Independent Interface (MII).
The MII management unit of the EMAC provides a two-wire control status path to
the MII PHY. Read and Write communication to and from registers within the PHY
is accomplished through the EMAC control registers.
EMAC Control Registers Description

Before the application is programmed, it is essential that the programmer under-
stand the registers used by the EMAC. These registers are briefly described
Application Note
below. For more details, please refer to the EMAC chapter of the eZ80F91 Prod-
uct Specification (PS0192).
EMAC Test Register. The EMAC_TEST register is used to configure the test
modes for various functionalities.
EMAC Configuration Register 1. The EMAC_CFG1 register allows control of the
padding, autodetection, cyclic redundancy checking, full-duplex or half-duplex
mode, field length checking, maximum packet ignores, and proprietary header
options.
EMAC Configuration Register 2. The EMAC_CFG2 register controls the behavior
of the back pressure and late collision data from the descriptor table.
EMAC Configuration Register 3. The EMAC_CFG3 register controls preamble
length and value, excessive deferment, and the number of retransmission tries
before the packet is aborted.
EMAC Configuration Register 4. The EMAC_CFG4 register controls pause control
frame behavior, back pressure, and receive frame acceptance.
EMAC Station Address Registers. The six EMAC_STAD_0 to EMAC_STAD_5 reg-
isters are used as the source address when transmitting frames and compared to
destination address when receiving frames.
EMAC Transmit Pause Timer Value Registers. The EMAC_TPTV_H and
EMAC_TPTV_L registers are inserted into outgoing pause control frames as the
pause timer value upon asserting a Transmit Pause Control Frame (TPCF—bit 2
of EMAC Configuration Register 4).
EMAC Maximum Frame Length Registers. The EMAC_MAXF_H and
EMAC_MAXF_L registers determine the length of the maximum frame that can be
received.
EMAC Address Filter Register. The EMAC_AFR register functions as a filter to
control promiscuous mode as well as multicast and broadcast messaging.
EMAC Hash Table Registers. For the eight EMAC_HTBL_0 to EMAC_HTBL_7
registers, when a multicast message is received, the first 6 bits of the CRC are
decoded and added to a table that points to a single bit within the hash table
matrix. If the selected bit = 1, the multicast packet is accepted, if the bit = 0, the
multicast packet is rejected. This application allows reception of all multicast mes-
sages by configuring it in the EMAC Address Filter Register.
EMAC MII Management Register. The EMAC_MIIMGT register is used to control
the external PHY attached to the MII. A rising edge on bit 7 causes
[EMAC_CTLD_H, EMAC_CTLD_L] control data to be transmitted to an external
PHY if the MII is not busy. Similarly, a rising edge on bit 6 causes status to be read
from the external PHY via [EMAC_PRSD_H, EMAC_PRSD_L] if the MII is not
busy.
Application Note
EMAC PHY Configuration Data Register. The EMAC_CTLD_H and

EMAC_CTLD_L registers are loaded with data to be sent via the MDIO pin to the
PHY. The PHY is selected by setting the EMAC_FIAD. The register inside of the
PHY is selected by setting EMAC_RGAD. When bit 7 of EMAC_MIIMGT sees a
rising edge, it causes data to be transferred from EMAC_CTLD_H and
EMAC_CTLD_L to the PHY.
EMAC PHY Address Register. The EMAC_RGAD register is used to select a spe-
cific register inside the PHY.
EMAC PHY Unit Select Address Register. The EMAC_FIAD register is used to
select PHY.
EMAC Transmit Polling Timer Register. The EMAC_PTMR register is used to set
the value after which the EMAC checks the transmit descriptor table in EMAC
memory to see if it owns any of the packets in EMAC shared memory.
EMAC Reset Control Register. The EMAC_RST register is used to reset EMAC
functionality.
EMAC Buffer Size Register. The EMAC_BUFSZ register is used to control the size
of buffers in EMAC shared memory as well as the level at which a pause control
frame is to be transmitted.
EMAC Interrupt Enable Register. The EMAC_IEN register is used to enable the
interrupts related to EMAC.
EMAC Interrupt Status Register. The EMAC_ISTAT register is used to determine
the status of various interrupts. It is cleared by writing a 1 into the selected bit.
EMAC PHY Read Status Data Register. The EMAC_PRSD_H and EMAC_PRSD_L
registers are where the status read by the EMAC from the PHY is stored.
EMAC MII Status Register. The EMAC_MIIStat register is where the current state
of the PHY is stored.
In addition to the above, the following registers store the addresses of memory
locations that form EMAC shared memory and aid the Transmit DMA and Receive
DMA to write and read from the shared memory.
• EMAC Transmit Lower Boundary Pointer Register [EMAC_TLBP_L,
EMAC_TLBP_H]
• EMAC Boundary Pointer Register [EMAC_BP_L, EMAC_BP_H,
EMAC_BP_U]
• EMAC Receive High Boundary Pointer Register [EMAC_RHBP_L,
EMAC_RHBP_H]
• EMAC Receive Read Pointer Register [EMAC_RRP_L, EMAC_RRP_H]
• EMAC Receive Write Pointer Register [EMAC_RWP_L, EMAC_RWP_H]. This
register is used by the EMAC and is read only for the eZ80® CPU.
Application Note
• EMAC Transmit Read Pointer Register [EMAC_TRP_L, EMAC_TRP_H]. This

register is used by the EMAC and is read only for the eZ80® CPU.
EMAC Shared Memory

EMAC shared memory is used both by the eZ80® CPU and on-chip EMAC unit. It
may be located anywhere in the address space and is defined by the EMAC
TLBP, EMAC BP, and EMAC RHBP registers described previously. These regis-
ters can be set using the ZiLOG Development Studio (ZDS II) project settings, or
by software.
To use the EMAC unit, the eZ80® CPU passes commands to it through the EMAC
shared memory. The pointers to the transmit and receive buffer sections in EMAC
shared memory, illustrated in Figure 5, are configured according to the program.
Upper Memory Address
RHBP
Rx Buffer
BP
Tx Buffer
TLBP
Lower Memory Address
Figure 5. EMAC Shared Memory Configuration
The eZ80® CPU places packets to be transmitted into this shared memory and
reads received packets from shared memory. The EMAC reads packets to be
transmitted from shared memory and stores received packets in shared memory.
Access to shared memory is through a semaphore bit (bit 16) in the descriptor
table at the beginning of each packet. Details for the descriptor table and sema-
phore bit are explained in the following paragraphs.
EMAC shared memory is divided into transmit buffer and receive buffer areas, as
defined by the following three registers:
EMAC TLBP. This register points to the start of the transmit buffer in EMAC shared
memory.
EMAC BP. This register points to the start of the receiver buffer.
EMAC RHBP. This register points to the end of the receiver buffer + 1.
Application Note
10
In Figure 5, EMAC shared memory is divided into transmit buffer and receive
buffer areas, as defined by the following three registers:
EMAC TLBP. This register points to the start of the transmit buffer in EMAC shared
memory.
EMAC BP. This register points to the start of the receiver buffer.
EMAC RHBP. This register points to the end of the receiver buffer + 1.
The Transmit and Receive shared memory is divided into buffers of 32, 64, 128,
or 256 bytes in size, based on the contents of the EMAC_BUFSZ register. Each
buffer contains a descriptor table, and packet data as can be seen in Figure 6.
Offset
Ethernet
Packet
consisting of
one or more
buffers
0007h
Descriptor
Table
TLBP 0000h
Figure 6. Buffers in EMAC Shared Memory
The Transmit and Receive buffer areas are subdivided into packet buffers of 32,
64, 128, or 256 bytes in size. The size of the packet buffer is set in bits 7 and 8 of
the EMAC_BUFSZ register. An Ethernet packet can accommodate multiple buff-
ers. Each packet begins at the next available buffer boundary. At the start of each
packet is the packet descriptor, a 7-byte field that describes the packet. The actual
Ethernet packet follows the descriptor.
The descriptor table contains three entries: the Next pointer (np), the packet size
(pkt_size), and the packet status (stat), as illustrated in Figure 7.
Application Note
11
Offset
stat
0005h
pkt_size
0003h
np
0000h
Figure 7. Contents of Descriptor Table
• np is a 24-bit pointer to the start of the next packet. The next packet will start
at the beginning of the next available buffer, following the end of this packet.
• pkt_size contains the number of bytes of data that make up the Ethernet
packet not including the seven descriptor table bytes.
• stat contains the status of the packet. The status is different for transmit and
receive packets.
Transmit descriptor status is described in Table 1. The transmit descriptor status

is first written by software to give ownership of the EMAC shared memory to
eZ80® CPU. The value written by software is don’t care except for the TxOwner
bit, which is written to a 1 to give ownership to the EMAC, or 0 if ownership
remains with the software. When the EMAC has completed transmitting the
packet, the status word of the Tx Descriptor is updated by the hardware. The
TxOwner bit is cleared and the other status bits are written with appropriate val-
ues.
Application Note
12
Table 1. Transmit Descriptor Status Bits
Bit Name Description

15 TxOwner 0 = Host (eZ80®) owns, 1 = EMAC owns.
14 TxAbort 1 = Packet Aborted (Not transmitted).
13 TxBPA 1 = Back pressure is applied.
12 TxHUGE 1 = Packet size is greater than maximum frame length.
11 TxLOOR 1 = Type/length field out of range (larger than 1518 bytes).
10 TxLCError 1 = Type/length field is not a Type field and it does not match the actual
data byte length of the Ethernet packet.
9 TxCrcError 1 = Packet contains an invalid CRC. This flag is set when CRCEN = 0
and the last 4 bytes of the packet are not the valid CRC.
8 TxPktDeferred 1 = Packet is deferred.
7 TxXsDfr 1 = Packet is excessively deferred.
6 TxFifoUnderrun 1 = TxFIFO has underrun.
5 TxLateCol 1 = Late collision has occurred.
4 TxMaxCol 1 = Maximum collisions have occurred.
3:0 TxNumberof-Collisions This field contains the number of collisions that occurred while
transmitting the packet.
Receive descriptor status is described in Table 2. The receive descriptor fields are
written by the EMAC when the packet has been completely written into the
receive buffer.
Table 2. Receive Descriptor Status Bits

15 RxOK 1 = Packet received.
14 RxAlignError 1 = Odd number of nibbles received.
13 RxCrcError 1 = The CRC is in error.
12 RxLongEvent 1 = A long or dropped event has occurred.
11 RxPCF 1 = The packet is a pause control frame.
10 RxCF 1 = The packet is a control frame.
9 RxMcPkt 1 = The packet has a multicast address.
8 RxBcPkt 1 = The packet has a broadcast address.
7 RxVLAN 1 = The packet is a VLAN packet.
6 RxUOpCode 1 = Unsupported Op Code is indicated in the Op Code field of the Ethernet packet.
Application Note
13
Table 2. Receive Descriptor Status Bits (Continued)

5 RxLOOR 1 = The Type/length field is out of range (larger than 1518 bytes).
4 RxLCError 1 = Type/length field is not a Type field and it does not match the actual data byte
length of the Ethernet packet.
3 RxCodeV 1 = A code violation is detected.
2 RxCEvent 1 = A carrier event is previously seen.
1 RxDvEvent 1 = A rxdv event is previously seen.
0 RxOVR 1 = Receive Overrun has occurred.
For more information regarding the various bits in the transmit and receive
descriptor table status bytes, refer to the EMAC chapter in eZ80F91 MCU Product
Specification (PS0192).
Ethernet Data Transmission

Data transmission over the Ethernet medium can be segmented into three main
steps, as outlined below.
1. Initialization of the EMAC, PHY and the CPU.
a. Initialize EMAC Control Registers.
b. Initialize PHY registers.
c. Enable interrupts after setting interrupt handlers for the EMAC interrupts.
2. Transmission of frame
a. Generate fields within the frame.
b. Generate an Ethernet packet with the help of the frame.
c. Create a descriptor table for the Ethernet packet.
d. Transfer control of the buffer to EMAC for Transmission.
e. Once the packet is transmitted interrupt occurs and the program is looped
back to initial starting point.
3. Reception of frame.
a. Check the status of reception.
b. Copy data into memory location specified by the user.
c. Update the EMAC Interrupt Status Register and loop to initial starting point.
After data has been received over the Ethernet, the different fields within an
Ethernet frame, namely the source MAC address, the destination MAC address,
the type and length of data, and the data itself, are displayed to the user in the
HyperTerminal window.
Application Note
14
A flow chart representing the process of Ethernet frame transmission and reception,
as has been demonstrated in this application, is shown in Appendix B on page 24.
Developing an eZ80F91 MCU Application

The application described in this document uses the eZ80F915050 Module
mounted onto the eZ80® Development Platform. Programming is performed using
a ZPAK II debug interface tool and an Ethernet hub connected to a computer with
ZDS II for eZ80Acclaim!™ installed. For this application, communication between
the two eZ80F915050 modules is performed using a crossover Ethernet cable; a
user interface is provided with the help of serial ports connected to separate
HyperTerminal applications running on the same or different computers.
Hardware Architecture
Figure 8 shows the hardware setup required for this application.
\
User Interface
eZ80F91
PC running MCU
HyperTerminal UART RJ45 Ethernet
Connector
Platform PHY
Memory eZ80F915050
PC running Module
ZDS II for
eZ80Acclaim! ZPAK II TIM
v4.8.0 ®
eZ80 Development Platform Crossover
Cable
Ethernet hub
eZ80F91
Programming ZPAK II TIM MCU
Interface
Platform PHY
Memory eZ80F915050 RJ45 Ethernet
PC running Module Connector
UART
HyperTerminal
®
eZ80 Development Platform
User Interface
Application Hardware
Figure 8. Block Diagram Representation of Hardware Setup
AN021201-1104 Developing an eZ80F91 MCU Application

Application Note
15
As shown in Figure 8, the hardware setup can be segmented into three main
parts:
Programming Interface. These blocks, used to program the microcontroller,
include the ZDI port on the eZ80® Development Platform connected to a target
interface module. The target interface module is connected to a ZPAK II unit via a
ribbon cable. The ZPAK II unit is connected to an Ethernet hub via an Ethernet
patch cable. Programming of the microcontrollers is controlled via a computer run-
ning ZDS II for eZ80Acclaim!™ connected to the Ethernet hub using an Ethernet
patch cable. ZDS II can be installed from the CD that is contained in the
eZ80Acclaim!™ Development Kit. The hardware components for this section are
all included in the eZ80Acclaim!™ Development Kit. Details regarding setting up
the programming interface are described in the eZ80Acclaim!™ Development Kits
Quick Start Guide (QS0020) and are beyond the scope of this Application Note.
Application Hardware. These blocks, used to implement Ethernet transmission
and reception, include the eZ80® Development Platform and the eZ80F915050
Module. The module includes an eZ80F91 MCU, a PHY to implement the Physi-
cal Layer for transmission and reception, and an RJ45 connector to connect
Ethernet cables that can transmit signals over long distances.
User Interface. Data can be exchanged with the user by running the HyperTermi-
nal application on a PC and connecting a serial port on the PC to the console port
on the eZ80® Development Platform using a RS-232 serial cable. The user inter-
face is provided through the UART0 block of the eZ80F91 MCU; this interface is
configured for 57600 bits per second, 8 data bits, no parity, 1 stop bit, and no flow
control. Details regarding setting up a user interface via the UART block and the
HyperTerminal application are provided in the sample program on the
eZ80Acclaim!™Development Kit CD.
EMAC shared memory can be enabled within the ZDS II Integrated Development
Environment using the Enable EMAC Shared Memory checkbox. This checkbox
can be found in the Configuration Settings dialog box, which the user can navi-
gate to via the following ZDS II menu path: Project → Settings → Debugger →
Target → Configure. The upper byte of the EMAC shared memory registers must
also be entered in the project settings. EMAC shared memory can also be initial-
ized by setting the EMAC RHBP, EMAC BP, and EMAC TLBP registers using soft-
ware.
Software Implementation
As discussed in the Ethernet Data Transmission section on page 13, the entire
application can be segmented into three main phases:
• Initialization of the EMAC, the PHY, and the CPU
• Frame transmission

Application Note
16
• Frame reception
Each of the above phases is explained in detail below, along with a discussion of
the software functions used for this application. A code listing of the software func-
tion, including comments, is presented in Appendix C on page 25.
After initialization, the user is asked to enter a letter to indicate usage either as a
transmitter or as a receiver. If the Transmit option is selected, functions related to
transmission are executed. If the Receive option is selected, functions related to
the reception of Ethernet frame are executed.
Initialization of the EMAC, PHY, and CPU

Initialization of the EMAC, PHY, and CPU using the EMAC control registers is per-
formed by the EthInitFunc function with the aid of the PhyInit function and
other supporting functions. EthInitFunc contains two arguments: a pointer to the
location in which a Station Address is stored, and a pointer to the function to be
executed when an EMAC Rx interrupt occurs.
The application described in this Application Note accepts all Ethernet frames,
including broadcast and multicast frames, regardless of the destination address.
The user should change the hash table entries by configuring the EMAC_HTBL_0
to EMAC_HTBL_7 registers before calling EthInitFunc, if appropriate.
Ethinitfunc performs the following three operations:
1. Copies the IEEE MAC address (6 bytes) from the ieeeaddr location passed
to it as an argument into the EMAC_STAD registers.
The following registers are initialized:
– EMAC_STAD_0
– EMAC_STAD_1
– EMAC_STAD_2
– EMAC_STAD_3
– EMAC_STAD_4
– EMAC_STAD_5
2. Initializes the EMAC configuration registers, as follows:

a. Initialize the EMAC_BUFSZ register to determine the size of buffers in
EMAC shared memory. The buffer size has been set to the minimum
possible value of 32 bytes to make maximum use of EMAC shared
memory.

Application Note
17
b. Initialize the EMAC_TPTV registers. For the purposes of this application,

the pause timer value must be set to 1400h. EMAC_TPTV_L and
EMAC_TPTV_H are the initialized registers.
c. Initialize the following registers to create pointers to EMAC shared memory:
EMAC_TLBP_L
EMAC_TLBP_H
EMAC_BP_L
EMAC_BP_H
EMAC_BP_U
EMAC_RHBP_L
EMAC_RHBP_H
EMAC_RRP_L
EMAC_RRP_H
While the user can set these registers directly, the following paragraph
describes how they are set using the program listed in Appendix C on
page 25 and using the project settings in ZDS II.
The application described in this document sets TLBP to C7C000h and
RHBP to C7E000h. C7 is selected in the project settings by entering C7 as
the upper byte when enabling EMAC shared memory in the following
ZDS II menu path: Project → Settings → Debugger → Target → Config-
ure. The RAM Address offset, currently set to C000h in the F91_emac.h
file, is added to the C70000h address value to obtain a value for TLBP. As
a result, TLBP is configured to a value of C7C000h.
RHBP is obtained by adding the EMAC RAM size, which is currently set to
2000h in the F91_emac.h file. As a result, the value of RHBP is set to
C7E000h. BP is determined using equations so as to allow at least one
packet and an additional buffer.
d. Initialize the EMAC_PTMR register, which is currently set to 1 to reflect a
minimum time between successive polls of EMAC shared memory.
e. Initialize the EMAC_TEST register. which is configured in the application
to disable the EMAC test modes by writing a 0 to this register.
f. Initialize the following EMAC_CFG registers to specify the mode of opera-
tion:
EMAC_CFG1. Set to 02h to allow reception of frames and disable padding
and CRC, half-duplex mode, CSMA/CD enabled.
EMAC_CFG2. Set to 56h to allow late collisions until 56 bytes are success-
fully transmitted.
EMAC_CFG3. Set to 15h to specify 15 retransmission attempts.

Application Note
18
EMAC_CFG4. Set to 11h to receive all frames.
g. Initialize the EMAC_AFR register to 0Fh to allow broadcast and multicast

addresses.
h. Initialize the EMAC_MAXF_L and EMAC_MAXF_H registers to specify the
maximum frame length for frames to be received. The application sets the
frame length to a maximum of 1536 bytes by initializing them to 0600h.
i. Initialize the EMAC_RST register, which is reset to 00h to prevent reset-
ting of the on-chip EMAC block.
j. Set the MII management clock by initializing the EMAC_MIIMGT register.
The MII clock is set to the system clock divided by 20.
3. PHY is initialized using the PhyInit function. The following steps are pro-
grammed into the PhyInit function:
a. Initialize EMAC_FIAD register with the PHY address to access the PHY.
b. Check the values in the PHY_ID1_REG and PHY_ID2_REG registers.
c. Reset the PHY by writing to the PHY_CREG register.
d. Read the PHY_SREG and PHY status registers to check if autonegotia-
tion is enabled.
e. Establish a link/connection according to user-defined options if autonegoti-
ation mode is not enabled.
f. Check whether a link is established, and indicate the result to the user via
HyperTerminal.
4. Clear the EMAC_ISTAT register by reading it to make sure that no interrupts

are waiting to be executed.
5. Call the init_default_vectors boot module function to initialize the I regis-
ter by specifying the upper byte of the interrupt vector address. Set vectors for
the EMAC Tx and EMAC Rx interrupt service vectors to the user-defined
ethisr_tx and ethisr_rx functions.
6. Enable the transmission and reception of interrupts by setting the correspond-
ing bits (bits 0 and 3) in the EMAC_IEN register.
The Receive interrupt handler has already been specified. Therefore, if data is
received, an EMAC Rx interrupt will occur and transfer program execution to
the ethisr_rx interrupt service routine written by the user. To transmit data,
the user is asked to press a key indicating the data to be sent.
Frame Transmission
The Transmit process consists of the following main operations.

Application Note
19
1. Generate a frame for transmission.

For this application, an Ethernet packet is defined as:
– Order/Type 2 bytes
– Length of packet 2 bytes
– Destination Address 6 bytes
– Source Address 6 bytes
– Type/length of data 2 bytes
– Data 1500 bytes maximum
The minimum length of data field in an Ethernet frame is specified as 46 bytes.

Therefore, the length of a packet can be construed to be:
46 bytes of data + 2 bytes of length field + 6 bytes of destination address +
6 bytes of source address = 60 bytes
a. Initialize the length of the packet field to 40h = 60d bytes1.
The destination address is considered to be FFFFFFFFFFFFh for broad-
cast.
b. Initialize the length of data field to 2Eh = 46d bytes.
All 46 bytes of data are initialized to the ASCII code for the user-entered
character.
2. Check for the availability of the buffers in the EMAC shared memory transmit
buffer section (see Figure 5).
3. Generate entries for the Tx buffer descriptor table.
4. Copy the data, including the descriptor table, into EMAC shared memory.
5. Enable interrupts.
6. Transfer control to the EMAC by setting bit 8 of the first byte in the descriptor
table.
7. The frame is transmitted by the hardware, and an EMAC Tx interrupt is gener-
ated. At this time, the status in the descriptor table and the EMAC_ISTAT reg-
ister can be verified to ensure transmission of the frame.
8. After completing transmission, the program accompanying this Application
Note transfers control back to the main program where the user can transmit
data or wait for the system to receive data. If the user chooses to exit the pro-
gram, he/she is prompted to enter X.
1.d = decimal, or Base 10 value.

Application Note
20
Frame Reception
The Receive process consists of the following main operations.
1. The PHY and the EMAC are already initialized. Therefore, the link is estab-
lished, and the EMAC unit on the eZ80F91 MCU receives a frame over the
Ethernet MII and generates an EMAC Rx interrupt. When the EMAC Rx inter-
rupt occurs, control is transferred to the user-defined ethisr_rx interrupt ser-
vice routine.
2. Read the EMAC_ISTAT register to clear the status register.
3. Control is transferred to the RxNotify function, the location of which is speci-
fied when EthInitfunc is called by the main program.
4. RxNotify creates a buffer in memory and calls the ReceivePkt function.
5. The amount of data received is found by reading the number of packet size
bytes in the descriptor table. The flags in the Ethernet packet (order/type field)
are initialized to status bytes from the descriptor table. Data is copied from
EMAC shared memory to the buffer specified by RxNotify when calling
ReceivePkt.
6. Data is recovered from the received frame and the first byte is displayed in the
HyperTerminal window.
7. The displayed fields are the destination address, the source address, the
length of data, and the character that is intended to be transmitted by the user.
8. Upon returning from the RxNotify function, the ethisr_rx interrupt service
routine updates rrp to point to the next packet specified in the descriptor
table.
9. Control is then transferred to the main.c file. The user is prompted to either
wait for the system to receive data, enter X to exit the program, or enter a key
to transmit data.
Testing/Demonstrating the Application

1. If the same computer and/or hub are used to program both eZ80F915050
modules, change the IP address settings on one of the ZPAK II units to
192.168.1.60. Also change the computer IP address to 192.168.1.20. To
determine how to change the IP address of the ZPAK II and the computer,
please refer to eZ80Acclaim!™ Development Kits Quick Start Guide
(QS0020).
2. Open the emactxrx.pro project in ZDS II. Navigate via the Project → Set-
tings → Debugger → ZPAK II Driver Configuration menus to change the IP
address to 192.168.1.50. Build and run the project.
AN021201-1104 Testing/Demonstrating the Application

Application Note
21
3. In the HyperTerminal window, you should see a prompt asking you to enter T
for transmit or R for Receive. Enter R to configure the eZ80F91 MCU as a
receiver.
4. Open another copy of ZDS II and navigate via the Project → Settings →
Debugger → ZPAK II Driver Configuration menus to modify the IP address
to 192.168.1.60. Build and run the project.
5. The HyperTerminal application prompts the user to enter T for transmitter or R
for receiver. Entering T to begin a transmit operation prompts the user to enter
a character to be transmitted via the Ethernet. Entering this character in
HyperTerminal will show RxData, as well as the character (in the HyperTermi-
nal program) on the receiving PC.
Conclusion
This Application Note demonstrates how to use ZiLOG’s eZ80F91 MCU to send
and receive information across the Ethernet medium at the hardware level. A low-
level driver function can be written to accept a single byte of data from the user
(via HyperTerminal), generate a frame, and transmit it over the Ethernet. Recep-
tion of an Ethernet frame is also incorporated into the application, and the recov-
ery of data is demonstrated.
Summary
The eZ80F91 MCU includes an on-chip Ethernet MAC, which greatly enhances
the possibility of sending and receiving data over the Ethernet. While a user can
send data using a number of TCP/IP protocols that are demonstrated in the ZTP
software package (such as UDP, PPP, etc.), all data transmission is essentially
performed at the hardware level by encoding the information into the data field of
the Ethernet frame. By using data in the form of an Ethernet frame, the user can
eliminate the additional complexity required to encode and decode data according
to the protocol used. This application can also aid in debugging and toward devel-
oping an understanding of how the protocol actually works by adding that func-
tionality during frame generation and reception.
AN021201-1104 Conclusion
Application Note
22
Notes
AN021201-1104 Notes
Application Note
23
Appendix A—References
Further details about the eZ80F91 MCU, EMAC operation, and the eZ80Acclaim!™
development system can be found in the references listed in Table 3.
Table 3. List of References
Topic Document Name

Ethernet Driver ZiLOG TCP/IP Software Suite v1.3 Programmer’s Guide
Reference Manual (RM0008): How to Create a Custom
Driver.
Write your own EMAC Driver for Metro IPWorks Technical
Article (TA0003).
EMAC Unit eZ80F91 MCU Product Specification (PS0192): Ethernet
Media Access Controlller.
IEEE 802.3 Standard IEEE 802.3u Standard (IEEE standards).
eZ80F915050 Module eZ80F91 Module Product Specification (PS0193).
AMD Am79C874 PHY AMD 79C874 PHY Datasheet (AMD documentation).
eZ80F91 Development Kit eZ80F91 Development Kit User Manual (UM0142).
ZDS II User Manual ZDS II–eZ80Acclaim!™ User Manual (UM0144).
Interrupt processing Setting Interrupts in ADL Mode on the eZ80F91 MCU
Technical Note (TN0020).
AN021201-1104 Appendix A—References

Application Note
24
Appendix B—Flowcharts
The main battery-charging routine is illustrated in Figure 9.
Start
EthinitFunc: Initialize EMAC Registers,

initialize PHY via PhyInit function,
Set interrupt vectors
Tx Tx/Rx? Rx
Wait for EMAC

Generate frame
Rx interrupt
Generate descriptor table, Udate status register

copy data into shared and pointers, copy data
memory, transfer ownership from RxDMA to EMAC
of packet to EMAC shared memory
Wait for EMAC

Tx interrupt
Figure 9. The Main Routine
AN021201-1104 Appendix B—Flowcharts

Application Note
25
Appendix C—Source Code

This appendix provides a listing of the C and Header Files associated with the
application described in this document.
Note: The code files in this section are listed merely to assist the reader, and are
intended only for the purpose of review. Copying these code listings from
this document for actual use can result in compilation errors, and is
therefore strongly discouraged. To use properly-formatted code for your
development work, please refer to the source code file that is a companion
to this document.
C Files
The following C files are listed in this section:
• main.c
• bothfns.c
• F91_phy.c
• macfns.c
• uart_main.c
main.c
/*
* Copyright 2004, ZiLOG Inc.
* All Rights Reserved
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of ZiLOG Inc., and might
* contain proprietary, confidential and trade secret information of
* ZiLOG, our partners and parties from which this code has been licensed.
*
* The contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of ZiLOG Inc.
*/
#include <stdio.h>
#include "new_uart.h"
#include "_eZ80.h"
#include "F91_emac.h"
#include "AMD79C874_phy.h"
#include "new_ether.h"
void txpacket(void);
AN021201-1104 Appendix C—Source Code

Application Note
26
void txrx(void);
extern SYSCALL ETHINITFUNC(char * ieeeaddr, void (*rxnotify)(void));

extern SYSCALL TransmitPkt(struct ep *pep);
extern void rxnotify(void);
extern void abort(void);
void main(void)
{
SYSCALL EMACinit;
char * ieeeaddr;
char func;
uart_init();
printf ("\n\n\n\n
************************************************************");
printf ("\n Zilog development board eZ80F91 EMAC Module demonstration\n");
ieeeaddr = (char *) 0xC40000;
//call ethinitfunc
EMACinit = ETHINITFUNC(ieeeaddr, rxnotify);
if (EMACinit != PEMAC_INIT_DONE)
{
printf ("\n Error in EMAC initialization, Exiting program");
abort();
txrx();
}
void txrx(void)
{
printf ("\n\n TO EXIT : Press X");
printf ("\n RECEIVER : Wait for data to be received");
printf ("\n TRANSMITTER : Enter key representing data for transmission \n ");
txpacket();
}
void txpacket(void)
{
BYTE message;
struct ep txframe;
struct ep * ptxframe;
BYTE i;
SYSCALL txpktstatus;

Application Note
27
message = getchar();
if (message == 'x' || message == 'X')
{
asm("di");
printf( "\n ************************************************************"
);
abort();
}
// prepare frame for transmission

txframe.ep_len = 0x003A;
txframe.ep_eh.eh_dst[0] = 0xFF;
//enter code for your Ethernet MAC Address here

txframe.ep_eh.eh_src[0] = 0x00;
txframe.ep_eh.eh_src[3] = 0xAB;
txframe.ep_eh.eh_src[4] = 0xCD;
txframe.ep_eh.eh_src[5] = 0xEF;
txframe.ep_eh.eh_type = 0x002E;
for(i=1;i<=46;i++)
{
txframe.ep_data[i-1] = message;
}
ptxframe = &(txframe);
//call transmitpkt
txpktstatus = TransmitPkt (ptxframe);
if (txpktstatus == PKTTOOBIG)
printf("\n packet too big\n");
}
bothfns.c
/*

Application Note
28

*
*
*/
#include <stdio.h>
#include "_ez80f91.h"
extern void emac_reset(void);

extern SYSCALL PhyInit(void);
extern void init_default_vectors(void);
extern void set_vector( unsigned short vector, void( *handler )( void ) );
extern void ethisr_tx(void);
extern void ethisr_rx(void);
extern void ReceivePkt(struct ep * databuff);
extern void emac_enable_irq(void);
SYSCALL ETHINITFUNC(char * ieeeaddr, void (*rxnotifyaddr)(void));

void rxnotify(void);
void F91IntTask( void );
BYTE * p_internal_sram_base;// 24-bit address of internal MAC SRAM

WORD buf_size;
WORD buf_size_shift;
WORD buf_mask;
struct desctbl * twp;

struct desctbl * trp;
struct desctbl * rwp;
struct desctbl * rrp;
struct desctbl * tlbp;
struct desctbl * bp;
struct desctbl * rhbp;
struct ep rxdfrm;
SYSCALL ETHINITFUNC(char * ieeeaddr, void (*rxnotifyaddr)(void))

{
//

Application Note
29
// ieeeaddr is pointer to a char array containing 6 bytes of

// EMAC Station Address
//
char i;
WORD phy_data;
WORD temp;
/*
* Save the interrupt callback addresses
*/
if( rxnotifyaddr == 0 )
{
printf("\n illegal callbacks\n");
return (ILLEGAL_CALLBACKS);
}
/*
* Ensure internal EMAC Ram is enabled. Calculate memory base address and
clear it.
*/
p_internal_sram_base = (BYTE *)((((DWORD)RAM_ADDR_U) << 16) +
(BYTE*)EMAC_RAM_OFFSET);
RAM_CTL |= ERAM_EN;
emac_reset();
// setup the emac station address

for (i = 0; i < 6; i++)
{
EmacStad(i) = (BYTE)*(ieeeaddr+i);
}
// check by reading back station address

for (i = 0; i < 6; i++)
{
if (EmacStad(i) != (BYTE)*(ieeeaddr+i))
{
printf("\n ieeeaddr = %#x \n",ieeeaddr);
printf("\n i = %d, Emacstad(i) = %#x, *(ieeeaddr+i) = %#x\n", i,
(EmacStad(i)), *(ieeeaddr+i));
printf("\n pemac not found\n");
return(PEMAC_NOT_FOUND);
}
}
// disable EMAC interrupts

EMAC_IEN = 0;

Application Note
30
// clear interrupt status flags

EMAC_ISTAT = 0xff;
// setup buffer size

if( F91_emac_config.buf_size > BUF32 )
{
buf_size = BUF32;
}
else
{
buf_size = F91_emac_config.buf_size;
}
buf_size_shift = 8 - buf_size;
EMAC_BUFSZ = buf_size << 6;
buf_mask = 0xFFFF << buf_size_shift;
buf_size = 1 << buf_size_shift;
// set pause frame control timeout value

EMAC_TPTV_L = 0x14;
EMAC_TPTV_H = 0x00;
/*
* Ensure there is enough room in the Tx buffer for at least 1
* full sized ethernet frame + one extra emac packet buffer.
*/
temp = (MAXDATASIZE + HEADERSIZE + sizeof(struct desctbl) + (buf_size<<1) -1)
& buf_mask;
if( ((F91_emac_config.tx_buf_size & buf_mask) >= temp)
&& ((F91_emac_config.tx_buf_size & buf_mask) <= EMAC_RAM_SIZE) )
{
temp = F91_emac_config.tx_buf_size & buf_mask;
}
if( F91_emac_config.tx_buf_size != temp )
{
printf( "Adjusted F91 Tx buffer size to %u\n", temp );
}
// init descriptor tables boundry pointers

tlbp = (struct desctbl*)(p_internal_sram_base);
bp = (struct desctbl*)(p_internal_sram_base + temp);
rhbp = (struct desctbl*)(p_internal_sram_base + EMAC_RAM_SIZE);
// load Emac i/o regs from pointers

EMAC_TLBP_L = ((DWORD) tlbp);
EMAC_TLBP_H = ((DWORD) tlbp) >> 8;
EMAC_BP_L = ((DWORD) bp);
EMAC_BP_H = ((DWORD) bp) >> 8;

Application Note
31
EMAC_BP_U = ((DWORD) bp) >> 16;

EMAC_RHBP_L = ((DWORD) rhbp);
EMAC_RHBP_H = ((DWORD) rhbp) >> 8;
// setup s/w pointers to ring buffers

twp = trp = tlbp;
rwp = rrp = bp;
// write rrp into i/o reg rrp

EMAC_RRP_L = ((DWORD) rrp);
EMAC_RRP_H = ((DWORD) rrp) >> 8;
// host owns first buffer

twp->stat = 0x0000;
// set polling timer for minimum timeout period

EMAC_PTMR = 1;
// disable EMAC test modes

EMAC_TEST = 0;
//enable frame length checking to be performed

EMAC_CFG1 = 0x02;
// set the late collision byte at byte 56

EMAC_CFG2 = 56;
// set max # collisions = 15

EMAC_CFG3 = 15;
// Enable the EMAC receiver

EMAC_CFG4 = RXEN;
EMAC_CFG4 |= PARF;
// Init the Address Filter

EMAC_AFR = 0x0F;
// set the max # bytes per packet to 1536

EMAC_MAXF_L = 0x00;
EMAC_MAXF_H = 0x06;
// take EMAC out of reset

EMAC_RST = 0;
// Initialize the PHY AMD 79C874

// set mmiimgt mdc clock rate

Application Note
32
EMAC_MIIMGT = CLKDIV20;
if( PhyInit() != OK )
{
printf( "Phy initialization error\n" );
return( SYSERR );
}
//clear interrupt status register

EMAC_ISTAT = 0xff;
// Check access to EMAC shared ram

// don't overwrite tx status descriptor
for (i=10; i<18; i++)
p_internal_sram_base[i] = i;
for (i=10; i<18; i++)

{
if( p_internal_sram_base[i] != i )
{
printf("\n pemac_smem_fail\n");
return (PEMAC_SMEM_FAIL);
}
}
// setup EMAC interrupts

init_default_vectors();
set_vector(0x40, ethisr_rx );
set_vector(0x44, ethisr_tx );
// enable the tx and rx interrupts

EMAC_IEN = RXDONEIEN | TXDONEIEN;
emac_enable_irq();
return (PEMAC_INIT_DONE);
}
void rxnotify(void)
{
struct ep * databuff;
databuff = &rxdfrm;
//call receivepkt
ReceivePkt(databuff);
}

Application Note
33
F91_phy.c
/*
*
*
*/
#include <stdio.h>
#include "_eZ80F91.h"
void sleep100(WORD ticks);

void delay_ms(unsigned int time);
SYSCALL PhyInit( void )

{
WORD phy_data;
WORD i;
BOOL Auto;
/*
* Configure Phy address on the F91
*/
EMAC_FIAD = PHY_ADDRESS;
// check if phy detected

if (read_phy_reg(PHY_ID1_REG, &phy_data) != OK )
return(PEMAC_PHYREAD_ERROR);
else {
if (phy_data != PHY_ID1)
return(PEMAC_PHY_NOT_FOUND);
}
if (read_phy_reg(PHY_ID2_REG, &phy_data) != OK )
return(PEMAC_PHYREAD_ERROR);
else {
if (phy_data != PHY_ID2)
return(PEMAC_PHY_NOT_FOUND);
}

Application Note
34
/*
* Re-initialize the Phy controller
*/
write_phy_reg(PHY_CREG, PHY_RST);
sleep100(10);
read_phy_reg( PHY_SREG, &phy_data );

if( phy_data & PHY_CAN_AUTO_NEG )
{
phy_data = PHY_RESTART_AUTO_NEG | PHY_AUTO_NEG_ENABLE;
Auto = TRUE;
}
else
{
phy_data = 0;
Auto = FALSE;
EMAC_CFG1 = PADEN | CRCEN;
}
/*
* Set desired link capabilities
*/
switch( F91_emac_config.mode )
{
case( F91_AUTO ):
{
if( Auto )
{
write_phy_reg(PHY_ANEG_ADV_REG,
PHY_ANEG_100_FD
| PHY_ANEG_100_HD
| PHY_ANEG_10_FD
| PHY_ANEG_10_HD
| PHY_ANEG_802_3 );
}
else
{
printf( "\nHW modifications required to enable Auto-Negotiation\n" );
}
break;
}
case( F91_100_FD ):
{
phy_data |= PHY_100BT | PHY_FULLD;
PHY_ANEG_100_FD
| PHY_ANEG_100_HD

Application Note
35
| PHY_ANEG_10_FD
| PHY_ANEG_10_HD
| PHY_ANEG_802_3 );
break;
}
case( F91_100_HD ):
{
phy_data |= PHY_100BT | PHY_HALFD;
PHY_ANEG_100_HD
| PHY_ANEG_10_FD
| PHY_ANEG_10_HD
| PHY_ANEG_802_3 );
break;
}
case( F91_10_FD ):
{
phy_data |= PHY_10BT | PHY_FULLD;
PHY_ANEG_10_FD
| PHY_ANEG_10_HD
| PHY_ANEG_802_3 );
break;
}
case( F91_10_HD ):
default:
{
phy_data |= PHY_10BT | PHY_HALFD;
PHY_ANEG_10_HD
| PHY_ANEG_802_3 );
break;
}
}
write_phy_reg(PHY_CREG, phy_data);
/*
* Wait for a link to be established
*/
i = 50;
while( !(phy_data & (PHY_AUTO_NEG_COMPLETE | PHY_LINK_ESTABLISHED)) )
{
sleep100(10);
if( i==0 )
{
printf( "\nUnable to establish Ethernet Connection\n" );

Application Note
36
break;
}
i--;
if( i%10 == 0 )
printf( "." );
}
if( phy_data & PHY_LINK_ESTABLISHED )

{
// Read the AMD diagnostics register to determine link settings
read_phy_reg( PHY_DIAG_REG, &phy_data );
if( phy_data & PHY_100_MBPS )
{
printf( "\n 100 Mbps " );
}
else
{
printf( "\n 10 Mbps " );
}
if( phy_data & PHY_FULL_DUPLEX )

{
printf( "Full-Duplex " );
EMAC_CFG1 = PADEN | CRCEN | FULLD;
}
else
{
printf( "Half-Duplex " );
EMAC_CFG1 = PADEN | CRCEN;
}
printf( "\n Link established" );

return( OK );
}
}
void sleep100(WORD ticks)

{
int i;
i = 50*ticks;
delay_ms(i);
}
void delay_ms(unsigned int time)

{
unsigned int timer = 0;
unsigned char uclear;

Application Note
37
TMR2_CTL = 0x00;
TMR2_RR_H = 0x0C;
TMR2_RR_L = 0x35;
uclear = TMR2_IIR;
TMR2_CTL = 0x0F;
do {
if (TMR2_IIR & 0x01)
timer++;
} while (timer != time);
}
//writing into the AMD 79C874 PHY registers.

WORD write_phy_reg(WORD phy_reg, WORD data)
{
// write the phy reg
EmacCtld= data;
EMAC_RGAD = phy_reg;
EMAC_MIIMGT |= LCTLD;
// wait for mii done
while(EMAC_MIISTAT & MGTBUSY);
return(OK);
}
//reading from the AMD 79C874 PHY registers.

WORD read_phy_reg(WORD phy_reg, WORD* data)
{
// read the creg
EMAC_RGAD = phy_reg;
EMAC_MIIMGT |= RSTAT;
// wait for mii done
while(EMAC_MIISTAT & MGTBUSY);
*data = (EMAC_PRSD_L + ((WORD)EMAC_PRSD_H<<8));
return(OK);
}
macfns.c
/*
* Copyright 2003-04, ZiLOG Inc.
*
*

Application Note
38
*/
#include <stdio.h>
#include "_ez80f91.h"
/*
* Function Prototypes
*/
extern SYSCALL PhyInit( void );

extern void *memcpy(void *s1, void *s2, size_t n);
extern void txrx (void);
extern void abort(void);
void emac_enable_irq(void);
void SendNow(struct ep * databuff);
/*
* Global Variables
*/
extern BYTE* p_internal_sram_base;// 24-bit address of internal MAC

SRAM
const F91_EMAC_CONF_SF91_emac_config =
{
1568, // Size of Mac transmit buffer
F91_10_HD,// Default to 10 Mbps Half Duplex
BUF32 // Each packet buffer in EMAC_RAM will be 32 bytes long
};
/*
* Pointers into EMAC shared memory for buffer management.
* Currently these are unprotected.
*/
extern struct desctbl * twp;
extern struct desctbl * trp;
extern struct desctbl * rwp;
extern struct desctbl * rrp;
extern struct desctbl * tlbp;
extern struct desctbl * bp;
extern struct desctbl *rhbp;

Application Note
39
extern WORD buf_mask;

extern WORD buf_size;
extern WORD buf_size_shift;
extern voidrxnotify(void);
struct ep * pep;
// ---------------------------------------------------------------------------
--
void SendNow(struct ep * databuff)

{
struct desctbl * NextPkt;
WORD Len = databuff->ep_len;
WORD WrapLen;
BYTE * pSrc;
BYTE * pDst;
/*
* Calculate the address of the emac packet buffer that will immediately
* follow the one about to transmitted. Before giving the current
* packet to the emac HW, set the ownership of the next packet buffer to
* Host Owns so the emac HW does not try to transmit the frame.
*
* Note: this implementation only sends 1 packet at a time and the the
* init routine has already verified that a max sized frame can fit in the
* emac Tx buffer. Therefore there is no need to track how many ehternet
* buffers remain.
*/
NextPkt = (struct desctbl*) ((BYTE*)twp + ((Len+buf_size-1+DATA_OS) &
(buf_mask)));
if( NextPkt >= bp )
{
NextPkt = (struct desctbl*)((BYTE*)tlbp + ((BYTE*)NextPkt - (BYTE*)bp));
}
NextPkt->stat = HOST_OWNS;
twp->np = NextPkt;
twp->pktsz = Len;
/*
* Copy packet data into the emac Tx buffer. Check to see if the data will
* wrap around the end of the transmit buffer.
*/
pSrc = (BYTE*)&databuff->ep_eh;

Application Note
40
pDst = (BYTE*)twp+DATA_OS;
WrapLen = (BYTE*)bp - pDst;

if( WrapLen >= Len )
{ // No wrap
memcpy( pDst, pSrc, Len );
}
else
{ // Wrap
memcpy( pDst, pSrc, WrapLen );
memcpy( tlbp, &pSrc[WrapLen], (Len-WrapLen) );
}
emac_enable_irq();
/*
* Set the status to Emac owns so the HW will begin trnamitting the frame.
*/
twp->stat = EMAC_OWNS;
twp = NextPkt;
}
SYSCALL TransmitPkt(struct ep *pep)

{
INT16 status;
BYTE CritFlag;
WORD lengthcompare;
BYTE prnstat;
lengthcompare = pep->ep_len;
if( pep->ep_len <= (MAXDATASIZE + HEADERSIZE) )

{
status = TX_WAITING;
SendNow( (struct ep *) &pep->ep_order );
}
else status = PKTTOOBIG;
return( status );
}
void ethisr_tx(void)
{
BYTE CritFlag;
struct desctbl * HW_TRP;
BYTE temp;
temp = EMAC_ISTAT;

Application Note
41
EMAC_ISTAT = TX_DONE;
/* Determine the location of HW Transmit Read Pointer */

HW_TRP = (struct desctbl*)(p_internal_sram_base + EMAC_TRP_L +
((WORD)EMAC_TRP_H<<8));
temp = EMAC_ISTAT;
asm("ei");
/* Verify the current tx frame was sent */

if( trp->stat & TxAbort )
{
printf("\n Packet Aborted, Check connections");
asm("di");
abort();
}
txrx();
}
//Receive Interrupt Processing

void ethisr_rx(void)
{
WORD temp;
BYTE temp1;
if( rrp->np == ((struct desctbl*)(p_internal_sram_base + EMAC_RWP_L +

((WORD)EMAC_RWP_H<<8))) )
{
EMAC_ISTAT = RXDONE;//rx_stat;
}
temp = rrp->stat;
rxnotify();
// update rrp to next pkt

rrp = rrp->np;
// update rrp i/o reg - for h/w rx buffer counting

// must do this or we'll run outofbufs.
EmacRrp = (DWORD)rrp;
asm("ei");
txrx();
}
//Receive Packet Processing

Application Note
42
void ReceivePkt(struct ep * databuff)

{
WORD temp;
BYTE* psrc;
BYTE* pdst;
WORD txferSz;
BYTE*ptr;
WORD i;
WORD datalen;
BYTE temp1;
BYTE datalen_l, datalen_h;
uart_init();
temp1 = EMAC_ISTAT;
asm("di");
txferSz = rrp->pktsz;
// set databuff->Flags from rx descriptor status

databuff->ep_order = rrp->stat;
databuff->ep_len = rrp->pktsz;
// move the data from the rx ring buffers into system buffer
pdst = (BYTE*)&databuff->ep_eh;
psrc = (BYTE*)rrp+DATA_OS;
if (psrc+txferSz > (BYTE*)rhbp)

{
temp = (BYTE*)rhbp - psrc;
memcpy(pdst, psrc, temp);
memcpy(&pdst[temp], bp, txferSz-temp);
}
else
{
memcpy(pdst, psrc, txferSz);
}
ptr = (BYTE *) &databuff->ep_eh;

printf( "Rx Data : ");
printf(" Destination Address (Hex)\t");
for(i=0; i<6;i++)
printf("%02x",*(ptr+i));
ptr += 6;
printf("\n\t\t Source Address (Hex)\t\t");
for(i=0; i<6;i++)
printf("%02x",*(ptr+i));
ptr += 6;
printf("\n\t\t Datafield length \t\t");
datalen_l = *ptr;

Application Note
43
ptr++;
datalen_h = *ptr;
datalen = 0x0000;
datalen = (datalen_h*16)+datalen_l;
printf("%04d", datalen);
ptr++;
printf("\n\t\t Received data\t\t\t");
for (i=0; i<datalen;i++)
{
if (datalen == 0x002E)
printf("%c ", *ptr);
else printf("%#x ", *ptr);
}
void emac_reset( void )

{
EMAC_IEN = 0;
// Reset all pemac blocks

EMAC_RST = SRST | HRTFN | HRRFN | HRTMC | HRRMC | HRMGT;
}
void emac_enable_irq( void )

{
// enable the tx and rx interrupts
EMAC_IEN = 0xFF;
}
void emac_disable_irq( void )

{
// Disable the tx and rx interrupts
EMAC_IEN = 0;
}
uart_main.c
/*****************************************************************************
* This program will exercise the eZ80Acclaim! UART. The UART will be used
* to print a few messages and echo any character it receives from the
* Console port.
*
****************************************************************************/
#include <eZ80F91.h>

Application Note
44
extern long SysClkFreq;
void uart_init(void)
{
#if (SIMULATE==0)
unsigned short int i;
unsigned short brg;
brg = SysClkFreq/(16 * UART_BPS);
PD_ALT2 = 0x03;
PD_ALT1 = 0x00;
PD_DDR = 0xEB;
PD_DR = 0x00;
PB_DR = 0x40;
PB_ALT2 = 0x00;
PB_ALT1 = 0x00;
PB_DDR = 0xBF;
UART0_LCTL |= LCTL_DLAB;
UART0_BRG_L = (brg & (unsigned short)0x00FF);
UART0_BRG_H = (brg & (unsigned short)0xFF00) >> (unsigned short)8;
UART0_LCTL &= ~LCTL_DLAB;
SetLCTL(UART_DATA_BITS, UART_PARITY, UART_STOP_BITS);

#endif
}
int putch(int ch)

{
while ((UART0_LSR & LSR_THRE) == (unsigned char)0);
UART0_THR = ch;
if (ch == LF)
{
while ((UART0_LSR & LSR_THRE) == (unsigned char)0);
UART0_THR = CR;
}
return (ch);
}

Application Note
45
int getch(void)
{
while ((UART0_LSR & LSR_DR) == (unsigned char)0);
return (UART0_RBR);
}
Header Files
The following header files are listed in this section:
• AMD79C874_phy.h
• basetypes.h
• F91_emac.h
• generic_phy.h
• new_ether.h
• new_uart.h
• uart_main.h
• _ez80.h
• _eZ80F91.h
AMD79C874_phy.h
/*
*
*
*/
/*
* Copyright 2001-04, Metro Link, Inc.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Metro Link, Inc. and may
* Metro Link, Inc. and/or its partners.

Application Note
46
*
* permission of Metro Link, Inc.
*
*/
/
******************************************************************************
**src: AMD79C874_phy.h
**
**DPC7/19/01Initial
**
** Description: header file for ethernet phy (AMD 79c874)
**
*****************************************************************************
*/
#ifndef _AMD79C874_PHY_H_
#define _AMD79C874_PHY_H_
#include "generic_phy.h"
/*
* Default Phy address
*/
#define PHY_ADDRESS 0x001F
/*
* Phy registers unique to the AMD79C874.
*/
#define PHY_DIAG_REG 18
#define PHY_MODE_CTRL_REG21
/*
* ID register values to identify the Phy.
* PHY_ID1 is the expected value from PHY_ID1_REG.
* PHY_ID2 is the expected value from PHY_ID2_REG.
*/
#define PHY_ID1 0x0022
#define PHY_ID2 0x561B
/*
* Diagnostic Register (Register 18) bit definitions
*/
#define PHY_FULL_DUPLEX 0x0800
#define PHY_100_MBPS 0x0400
#define PHY_RX_PASS 0x0200

Application Note
47
#define PHY_RX_LOCK 0x0100
/*
* Mode Control Register (Register 21) bit definitions
*/
#define PHY_GPSI_EN 0x0800
#define SYSERR -1
#endif
basetypes.h
/*
*
*
*/
#ifndef _BASETYPES_H_
#define _BASETYPES_H_
/*
* Macro Definitions
*/
#define NULLPTR (void *) 0
#define TRUE 1
#define FALSE 0
#define SYSCALLINT16
#define PROCESSINT16
#define COMMANDINT16
#define LOCALstatic
/*
* Structures and Type Definitions
*/
typedef void * HANDLE;

Application Note
48
// Unsigned Base Types

typedef unsigned char BOOL;
typedef unsigned char BYTE;
typedef unsigned short int WORD;
typedef unsigned long intDWORD;
typedef unsigned char UINT8;

typedef unsigned short UINT16;
typedef unsigned long UINT32;
// Signed Base Types

typedef signed char INT8;
typedef signed short INT16;
typedef signed long INT32;
#endif
F91_emac.h
/*
*
*
*/
/*
**src: F91_emac.h
**
**DPC2/20/01Initial
**
** ez80s191 header file for ethernet mac
**Packet descriptor struct with corresponding bit definitions
** Timer/Timeout bit values
*/
#ifndef _F91_EMAC_H_
#define _F91_EMAC_H_
#include "basetypes.h"
#define EMAC_RAM_SIZE 0x2000

Application Note
49
#define EMAC_RAM_OFFSET 0xC000
// descriptor buffer sizes

#define BUF256 0x00
#define BUF128 0x01
#define BUF64 0x02
#define BUF32 0x03
// buffer mask
#define BUFMSK256 0xFF00
#define BUFMSK128 0xFF80
#define BUFMSK64 0xFFC0
#define BUFMSK32 0xFFE0
#define ABITS 13
#define TBL_INIT 0x010b00
#define DATA_OS (sizeof(struct desctbl))

#define CRCLEN 4
#define MINPKTSZ 64
#define MAXDATASIZE 1500

#define HEADERSIZE 14
#define CRCSIZE 4
#define MAXFRAMESIZE (MAXDATASIZE + HEADERSIZE + CRCSIZE)
#define MINFRAMESIZE 64
#define MIN_NUM_RX_BUFS 2
// tx statusH bit definition

#define EMAC_OWNS 0x8000// 1=mac owns
#define HOST_OWNS 0x0000// 0=host owns
#define TxOK 0x0000// pkt transmitted ok
#define TxAbort 0x4000// pkt aborted
#define TxBPA 0x2000// back pressure applied
#define TxHuge 0x1000// pktsize > maxf
#define TxLOOR 0x0800// length out of range
#define TxLCError 0x0400// length check error
#define TxCrcError 0x0200// crc error
#define TxPktDeferred 0x0100// pkt was deferred
// tx statusL bit definition

#define TxXsdfr 0x0080// excessive defer
#define TxFifoUnderRun 0x0040// fifo under run error
#define TxLateCol 0x0020// late collision
#define TxMaxCol 0x0010// max # collisions
#define TxNumColMask 0x000f// # collisions

Application Note
50
// rx statusH bit definition

#define RxOK 0x8000// pkt received ok
#define RxAlignError 0x4000// checks for an even # of nibbles
#define RxCrcError 0x2000 // checks for CRC# == FCS#
#define RxLongEvent 0x1000// long event or dropped event
#define RxPCF 0x0800// pause control frame
#define RxCF 0x0400// control frame
#define RxMCPkt 0x0200// multicast pkt
#define RxBCPkt 0x0100// broadcast pkt
// rx statusL bit definition

#define RxVLAN 0x0080// vlan frame type
#define RxUOpCode 0x0040// unsupported opcode
#define RxLOOR 0x0020// length out of range
#define RxLCError 0x0010// length check error
#define RxCodeV 0x0008// receive code violation
#define RxCEvent 0x0004// carrier event previously seen
#define RxDvEvent 0x0002// RXDV event previously seen
#define RxOVR 0x0001// rx fifo overrun
#define PEMAC_NOT_FOUND -1
#define PEMAC_PHY_NOT_FOUND -2
#define PEMAC_PHYREAD_ERROR -3
#define PEMAC_PHYINIT_FAILED -4
#define PEMAC_SMEM_FAIL -5
#define ILLEGAL_CALLBACKS -6
#define PEMAC_INIT_DONE 0
#define OUT_OF_BUFS 4
#define TX_FULLBUF 3
#define TX_WAITING 2
#define TX_DONE 1
#define PKTTOOBIG -2
/*
* Macros for Mode member of F91_EMAC_CONF_S
*/
#define F91_10_HD 0
#define F91_10_FD 1
#define F91_100_HD 2
#define F91_100_FD 3
#define F91_AUTO 4
typedef struct F91_EMAC_CONF_S

{
WORDtx_buf_size;// total tx buffer size in EMAC RAM

Application Note
51
BYTEmode; // Physical connection type

WORDbuf_size;// EMAC_Ram packet buffer size
} F91_EMAC_CONF_S;
typedef struct desctbl

{
struct desctbl*np;
WORD pktsz;
WORD stat;
}DescTbl;
#endif
generic_phy.h
/*
*
*
*/
#ifndef _GENERIC_PHY_H_
#define _GENERIC_PHY_H_
/*
* Common Phy registers.
*/
#define PHY_CREG 0
#define PHY_SREG 1
#define PHY_ID1_REG 2
#define PHY_ID2_REG 3
#define PHY_ANEG_ADV_REG4
/*
* MII Management Control Register (Register 0) bit definitions
*/

Application Note
52
#define PHY_RST 0x8000

#define PHY_LOOPBACK 0x4000
#define PHY_100BT 0x2000
#define PHY_AUTO_NEG_ENABLE0x1000
#define PHY_POWER_DOWN 0x0800
#define PHY_ISOLATE 0x0400
#define PHY_RESTART_AUTO_NEG0x0200
#define PHY_FULLD 0x0100
#define PHY_COLLISION_TEST0x0080
#define PHY_10BT 0
#define PHY_HALFD 0
/*
* MII Management Status Register (Register 1) bit definitions
*/
#define PHY_AUTO_NEG_COMPLETE0x0020
#define PHY_CAN_AUTO_NEG 0x0008
#define PHY_LINK_ESTABLISHED0x0004
/*
* Aut-Negotiation Advertisement Register (Register 4) bit definitions
*/
#define PHY_ANEG_100_FD 0x0100
#define PHY_ANEG_100_HD 0x0080
#define PHY_ANEG_10_FD 0x0040
#define PHY_ANEG_10_HD 0x0020
#define PHY_ANEG_802_3 0x0001
/*
* Function prototypes
*/
extern WORD write_phy_reg(WORD phy_reg, WORD data);
extern WORD read_phy_reg(WORD phy_reg, WORD* data);
/*
* Global Variables
*/
extern const F91_EMAC_CONF_SF91_emac_config;
#endif
new_ether.h

Application Note
53
#defineIP_ALEN4/* IP address length in bytes (octets)*/

#defineEP_ALEN6 /* number of octets in physical address*/
#defineEP_DLEN1500/* length of data field ep*/
typedefBYTE Eaddr[EP_ALEN]; /* a physical Ethernet address*/
structeh {/* ethernet header*/

Eaddreh_dst;/* destination host address*/
Eaddreh_src;/* source host address*/
WORDeh_type; /* Ethernet packet type (see below)*/
};
structep{/* complete structure of Ethernet packet*/

WORD ep_order; /* byte order mask (for debugging)*/
WORD ep_len;/* length of the packet*/
struct eh ep_eh;/* the ethernet header*/
BYTE ep_data[EP_DLEN]; /* data in the packet*/
};
new_uart.h
// new_uart.h
#define UART 0
#define UART_BPS 57600
#define UART_DATA_BITS 8
#define UART_PARITY 0
#define UART_STOP_BITS 1
#define LCTL_DLAB (unsigned char)0x80

#define LSR_THRE (unsigned char)0x20
#define LSR_DR (unsigned char)0x01
#define LF '\n'
#define CR '\r'
#define SetLCTL(d, p, s) UART0_LCTL = ((d-5)&3) | (((s-1)&1)<<2) | (p&3)
void uart_init(void);
uart_main.h
#include <eZ80F91.h>
#include <stdio.h>
/* Define SIMULATE as:

Application Note
54
* 1 when using the simulator

* 0 when using a hardware target
*/
#define SIMULATE 0
#define UART 0
#define UART_BPS 57600
#define UART_DATA_BITS 8
#define UART_PARITY 0
#define UART_STOP_BITS 1
void uart_init(void);
int putch(int ch);
int getch(void);
void test(void);
int printf(char * format, ...);

int scanf(char * format, ...);
int sprintf(char * s,char * format, ...);
int sscanf(char * s,char * format, ...);
int vprintf(char * format,char * arg);
int vsprintf(char * s,char * format,char * arg);
char *gets(char * s);
int puts(char * s);
int getchar(void);
int putchar(int c);
#if (UART==1)&&(SIMULATE==0)
#define UART_RBR UART1_RBR

#define UART_THR UART1_THR
#define UART_BRG_L UART1_BRG_L
#define UART_BRG_H UART1_BRG_H
#define UART_LCTL UART1_LCTL
#define UART_LSR UART1_LSR
#else
#define UART_RBR UART0_RBR
#define UART_THR UART0_THR
#define UART_BRG_L UART0_BRG_L
#define UART_BRG_H UART0_BRG_H
#define UART_LCTL UART0_LCTL
#define UART_LSR UART0_LSR
#endif
#define LCTL_DLAB (unsigned char)0x80

#define LSR_THRE (unsigned char)0x20
#define LSR_DR (unsigned char)0x01

Application Note
55
#define SetLCTL(d, p, s) UART_LCTL = ((d-5)&3) | (((s-1)&1)<<2) | (p&3)
#define LF '\n'
#define CR '\r'
//extern long SysClkFreq;
_ez80.h
/*
*
*
*/
/*
* Copyright 2001-2004, Metro Link, Inc.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Metro Link, Inc. and may
* Metro Link, Inc. and/or its partners.
*
* permission of Metro Link, Inc.
*
*/
#ifndef __EZ80_H_
#define __EZ80_H_
#include <basetypes.h>
/*
* Pointer type definitions for the eZ80 Compiler to access I/O.
* Note that all on-chip IO devices are internal. However, some IO macros
* use the __EXTIO keyword. These macros are intended to be used with a
* variable that holds the base address of the peripheral. This allows the
* same code fragment to operate on identical peripherals located at different
* places in the IO map. For example, if your code neede to write the value

Application Note
56
* 0x11 to either UART_THR0 or UART_THR1 depending on the value of a variable,

* and that variable contained the base address of which UART to use, you could
* either write:
*
* if( uart_base == UART0 )
* {
* UART_THR0 = 0x11;
* }
* else
* {
* UART_THR1 = 0x11;
* }
*
* Or you could use the base-indexed macro like this:
* UART_THR(uart_base) = 0x11;
*
* However you must not use a constant with the base-index macros. For
example,
* UART_THR( UART0 ) = 0x11;
* will produce unpredictable results.
*/
typedef volatile BYTE __INTIO *IORegInt8;
typedef volatile BYTE __EXTIO *IORegExt8;
typedef volatile WORD __INTIO *IORegInt16;
typedef volatile WORD __EXTIO *IORegExt16;
/* eZ80 Common Peripheral devices */

#define UART0 0xC0
#define UART1 0xD0
/* UART_IER bits */
#define IER_MIIE0x08
#define IER_LSIE0x04
#define IER_TIE 0x02
#define IER_RIE 0x01
/* UART_IIR bits */
#define IIR_FIFOEN0xC0
#define IIR_ISCMASK0x0E
#define IIR_RLS0x06
#define IIR_RDR0x04
#define IIR_CTO0x0C
#define IIR_TBE0x02
#define IIR_MS0x00
#define IIR_INTBIT0x01
/* UART_FCTL bits */
#define FCTL_TRIGMASK0x00

Application Note
57
#define FCTL_TRIG_10x00
#define FCTL_TRIG_140xC0
#define FCTL_CLRTXF0x04
#define FCTL_CLRRXF0x02
#define FCTL_FIFOEN0x01
/* UART_LCTL bits */
//#define LCTL_DLAB0x80
#define LCTL_SB 0x40 /* Send Break */
#define LCTL_FPE0x20 /* Force Parity Error */
#define LCTL_EPS0x10 /* Even Parity */
#define LCTL_PEN0x08 /* Parity Enable */
#define LCTL_2STOPBITS0x04
#define LCTL_5DATABITS0x00
/* UART_MCTL bits */
#define MCTL_LOOP0x10
#define MCTL_OUT20x08
#define MCTL_OUT10x04
#define MCTL_RTS0x02
#define MCTL_DTR0x01
/* UART_LSR bits */
#define LSR_ERR 0x80
#define LSR_TEMT0x40
//#define LSR_THRE0x20
#define LSR_BI 0x10
#define LSR_FE 0x08
#define LSR_PE 0x04
#define LSR_OE 0x02
//#define LSR_DR0x01
/* UART_MSR bits */
#define MSR_DCD 0x80
#define MSR_RI 0x40
#define MSR_DSR 0x20
#define MSR_CTS 0x10
#define MSR_DDCD0x08
#define MSR_TERI0x04
#define MSR_DDSR0x02
#define MSR_DCTS0x01
/* WDT_CTL bits */

Application Note
58
#define WDTCTL_EN0x80
#define WDTCTL_NMI0x40
#define WDCTL_RST_FLAG0x20
#define WDTCTL_TWO180x03
/* WDT_RR bits */
#define WDTRR_RESET10xA5
#define WDTRR_RESET20x5A
/*
* Chip select Control Register bit definitions
*/
#define CSCTL_WAIT_STATE_MASK0xE0
#define CSCTL_7_WAIT_STATES0xE0
#define CSCTL_6_WAIT_STATES0xC0
#define CSCTL_5_WAIT_STATES0xA0
#define CSCTL_4_WAIT_STATES0x80
#define CSCTL_MEMORY_ACCESS0x00
#define CSCTL_IO_ACCESS0x10
#define CSCTL_ENABLE_CS0x08
#define CSCTL_DISABLE_CS0x00
#endif
_eZ80F91.h
/*
*
*
*/
/*

Application Note
59
**src: ez80s191.h
**
**DPC2/20/01Initial
**
** ez80s191 header file for internal I/O registers
**
*/
#ifndef __EZ80F91_H_
#define __EZ80F91_H_
#include <ez80f91.h>
#include "_eZ80.h"
#define OK1
/* EMAC */
#define EmacStad(q)*((IORegExt8)(0x25+q))
#define EmacHtbl(q)*((IORegExt8)(0x33+q))
#define EmacCtld*((IORegInt16)((BYTE)0x3c))
#define EmacRrp*((IORegInt16)((BYTE)0x49))
// test reg
#define TESTFIFO0x40 // enable fifo test
#define TXSEL0x20 // select fifo for test_fifo
#define RXSEL0x00 // select fifo for test_fifo
#define SSTCT0x10 // shorcut slot timer counter when 1
#define SIMR0x08 // simulation reset - reset random number generator in
PETFUN
#define FRC_OVR_ERR 0x04// force rx overrun error
#define FRC_UND_ERR 0x02// force tx underrun error
#define LPBK0x01 // internal loop back enable
// cfg1 reg
#define PADEN0x80 // 1=pad short packets
#define ADPAD0x40 // Auto detect pad enable
#define VLPAD0x20 // VLAN pad enable
#define CRCEN0x10 // crc enable
#define FULLD0x08 // Full Duplex - mac ignores crs and col when 1
#define FLCHK0x04 // Frame length check
#define HUGEN0x02 // huge packet enable
#define DCRCC0x01 // Delayed crc check
// cfg2 reg
#define BPNB0x80 // backpreswsure no back off - if set, mac will
automatically retry
// if a collision occurs
#define NOBO0x40 // no back off
#define LCOL_MASK0x3f // late collision window

Application Note
60
// cfg3 reg
#define LONGP0x80 // Long preamble enforcement
#define PUREP0x40 // Pure preamble enforcement
#define XSDFR0x20 // Excess Defer
#define BITMD0x10 // Bit mode 10 mb/s ENDEC mode
#define RETRY_MASK0x0f // Retry count mask
// cfg4 reg
#define TPCF0x40 // tx pause control frame
#define THDF0x20 // tx half duplex (jams incoming packets)
#define PARF0x10 // Pass all Receive frames
#define RXFC0x08 // rx flow control
#define TXFC0x04 // tx flow control (allow pause frames)
#define TPAUSE0x02 // Test pause - mac control is paused
#define RXEN0x01 // allows mac to output srxen
// reset reg
#define SRST0x20 // s/w reset
#define HRTFN0x10 // host reset tx function
#define HRRFN0x08 // host reset rx function
#define HRTMC0x04 // host reset tx MCS
#define HRRMC0x02 // host reset rx MCS
#define HRMGT0x01 // host reet MII MGT
// mii reg
#define LCTLD0x80 // load control data
#define RSTAT0x40 // read status
#define SCINC0x20 // Scan Increment across multiple PHY's
#define SCAN0x10 // 1=scan mgmt cycles continuously
#define SPRE0x08 //suppress preamble
#define CLK_MASK0x07 // clock select
#define CLKDIV280x07
#define CLKDIV80x03
#define CLKDIV60x02
#define CLKDIV40x01
// interrupt enable reg

#define TXFSMERRIEN0x80
#define MGTDONEIEN0x40
#define RXCFIEN0x20
#define RXPCFIEN0x10
#define RXDONEIEN0x08
#define RXOVRRUNIEN0x04
#define TXPCFIEN0x02

Application Note
61
#define TXDONEIEN0x01
// define istat reg

#define TXFSMERR0x80
#define MGTDONE0x40
#define RXCF0x20
#define RXPCF0x10
#define RXDONE0x08
#define RXOVRRUN0x04
#define TXPCF0x02
#define TXDONE0x01
// bufsz reg
#define BUFSZMASK0xc0
#define TPCF_LEVEL0x3f
// SAL Address Selection Reg

#define PROMISCUOUS0x08
#define AMULTICAST0x04
#define QMULTICAST0x02
#define BROADCAST0x01
#define STAD0x00
// mii mgt status

#define MGTBUSY0x80
#define MIILF0x40
#define RDNVALID0x20
#define RDADDRMASK0x1f
// mii mgt phy registers

#define MII_CREG0x00
#define MII_SREG0x01
// fifo flags bit definitions

#define TXFF0x80
#define TXFAE0x20
#define TXFE0x10
#define RXFF0x08
#define RXFAF0x04
#define RXFAE0x02
#define RXFE0x01
/* TIMER */
#define TMR00x60
#define TMR10x65
#define TMR20x6F
#define TMR30x74
#define TMR_CTL(base)(*((IORegExt8)(base+0)))

Application Note
62
#define TMR_IER(base)(*((IORegExt8)(base+1)))
#define TMR_IIR(base)(*((IORegExt8)(base+2)))
#define TMR_DRL(base)(*((IORegExt8)(base+3)))
#define TMR_DRH(base)(*((IORegExt8)(base+4)))
#define TMR_RRL(base)(*((IORegExt8)(base+3)))
#define TMR_RRH(base)(*((IORegExt8)(base+4)))
/* Timer Control Register bit definitions */

#define TCR_BRK_STP0x80
#define CLKSELSYS0x00
#define TCR_CLKDIV_MASK 0x18
#define TCR_CONT_EN0x04
#define TCR_RLD_EN0x02
#define TCR_PRT_EN0x01
#define TMRCLKDIV40x00
/* Timer Interrupt enable register bit definitions */

#define TIER_IRQ_EOC_EN0x01
#define TIER_IRQ_ICA_EN0x02
#define TIER_IRQ_ICB_EN0x04
#define TIER_IRQ_0C0_EN0x08
#define TIER_IRQ_OC1_EN0x10
#define TIER_IRQ_OC2_EN 0x20
#define TIER_IRQ_OC3_EN0x40
/* Timer Interrupt Identification register bit definitions */

#define TIIR_EOC0x01
#define TIIR_ICA0x02
#define TIIR_ICB0x04
#define TIIR_0C00x08
#define TIIR_OC10x10
#define TIIR_OC2 0x20
#define TIIR_OC30x40
/* Ram Control */
#define GPRM_EN0x80
#define ERAM_EN0x40
/* Flash Control */
#define FLASH_CTRL_7_WS0xE0
#define FLASH_CTRL_6_WS0xC0
#define FLASH_CTRL_5_WS0xA0
#define FLASH_CTRL_4_WS0x80

Application Note
63
#define FLASH_ENABLE0x08
#define FLASH_DISABLE0x00
/* UART */
#define UART_RBR(base)(*((IORegExt8)(base+0)))
#define UART_THR(base)(*((IORegExt8)(base+0)))
#define BRG_DLRL(base)(*((IORegExt8)(base+0)))
#define BRG_DLRH(base)(*((IORegExt8)(base+1)))
#define UART_IER(base)(*((IORegExt8)(base+1)))
#define UART_IIR(base)(*((IORegExt8)(base+2)))
#define UART_FCTL(base)(*((IORegExt8)(base+2)))
#define UART_LCTL(base)(*((IORegExt8)(base+3)))
#define UART_MCTL(base)(*((IORegExt8)(base+4)))
#define UART_LSR(base)(*((IORegExt8)(base+5)))
#define UART_MSR(base)(*((IORegExt8)(base+6)))
#define UART_SPR(base)(*((IORegExt8)(base+7)))
/* CS Bus Mode Control bits */

#define CSBM_CTL_MASK0xC0
#define CSBM_CTL_EZ80_MODE0x00
#define CSBM_CTL_Z80_MODE0x40
#define CSBM_CTL_INTEL_MODE0x80
#define CSBM_CTL_MOTOROLA_MODE0xC0
#define CSBM_CTL_AD_MUX0x20
#define CSBM_CTL_EZ80_CLOCKS_MASK0x0F
#define CSBM_CTL_1_EZ80_CLOCKS0x01
#define CSBM_CTL_10_EZ80_CLOCKS0x0A
#define CSBM_CTL_11_EZ80_CLOCKS0x0B
#define CSBM_CTL_12_EZ80_CLOCKS0x0C
#define CSBM_CTL_13_EZ80_CLOCKS0x0D
#define CSBM_CTL_14_EZ80_CLOCKS0x0E
#define CSBM_CTL_15_EZ80_CLOCKS0x0F
/* PLL Control 0 */
#define PLL_CHARGE_PUMP_MASK0xC0
#define PLL_100uA 0x00
#define PLL_500uA 0x40
#define PLL_1mA 0x80

Application Note
64
#define PLL_1_5mA 0xC0
#define PLL_LOCK_MASK 0x0C

#define PLL_LOCK_8_CYCLES_OF_20ns0x00
#define PLL_LOCL_16_CYCLES_OF_400ns0x0C
#define PLL_CLK_MUX_MASK0x03
#define PLL_CLK_IS_EXT 0x00
#define PLL_CLK_IS_PLL 0x01
#define PLL_CLK_IS_RTC 0x02
/* PLL Control 1 */
#define PLL_LOCKED_STATUS0x20
#define PLL_LOCKED_INT 0x10
#define PLL_UNLOCKED_INT0x08
#define PLL_LOCKED_IE 0x04
#define PLL_UNLOCKED_IE 0x02
#define PLL_ENABLE_PLL 0x01
#define PLL_DISABLE_PLL 0x00
/* Interrupt vector table offsets */

#define IV_ERX0x40
#define IV_ETX0x44
#define IV_ESYS0x48
#define IV_PLL0x4C
#define IV_FLSH0x50
#define IV_TMR00x54
#define IV_TMR10x58
#define IV_TMR20x5C
#define IV_TMR30x60
#define IV_RSVD10x64
#define IV_RSVD20x68
#define IV_RTC0x6C
#define IV_UART00x70
#define IV_UART10x74
#define IV_I2C0x78
#define IV_SPI0x7C
#define IV_PA00x80
#define IV_PA10x84
#define IV_PA20x88
#define IV_PA30x8C
#define IV_PA40x90
#define IV_PA50x94
#define IV_PA60x98
#define IV_PA70x9C
#define IV_PB00xA0

Application Note
65
#define IV_PB10xA4
#define IV_PB20xA8
#define IV_PB30xAC
#define IV_PB40xB0
#define IV_PB50xB4
#define IV_PB60xB8
#define IV_PB70xBC
#define IV_PC00xC0
#define IV_PC10xC4
#define IV_PC20xC8
#define IV_PC30xCC
#define IV_PC40xD0
#define IV_PC50xD4
#define IV_PC60xD8
#define IV_PC70xDC
#define IV_PD00xE0
#define IV_PD10xE4
#define IV_PD20xE8
#define IV_PD30xEC
#define IV_PD40xF0
#define IV_PD50xF4
#define IV_PD60xF8
#define IV_PD70xFC
#endif

Ethernet Frame Transmission Using The eZ80F915050 Module: Application Note

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Application Note

ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126

ZiLOG Worldwide Headquarters

AN021201-1104 Table of Contents

AN021201-1104 List of Figures

eZ80Acclaim!™ Flash Microcontrollers

Figure 1. Top-Level View of Hardware Components

eZ80® Development Platform

eZ80F91 50 MHz Module Description

Figure 2. The Role of the eZ80F915050 Module in Ethernet Connectivity

The eZ80F915050 Module features an on-board eZ80F91 MCU, a PHY, and an

Figure 3. The eZ80F915050 Module

eZ80F91 MCU Description

Figure 4. Ethernet Connectivity Blocks on the eZ80F91 MCU

eZ80® CPU Description

On-Chip EMAC Unit Description

EMAC Control Registers Description

EMAC PHY Configuration Data Register. The EMAC_CTLD_H and

• EMAC Transmit Read Pointer Register [EMAC_TRP_L, EMAC_TRP_H]. This

EMAC Shared Memory

Upper Memory Address

Figure 5. EMAC Shared Memory Configuration

Figure 6. Buffers in EMAC Shared Memory

Figure 7. Contents of Descriptor Table

Transmit descriptor status is described in Table 1. The transmit descriptor status

Table 1. Transmit Descriptor Status Bits

Bit Name Description

Table 2. Receive Descriptor Status Bits

Bit Name Description

Table 2. Receive Descriptor Status Bits (Continued)

Bit Name Description

Ethernet Data Transmission

Developing an eZ80F91 MCU Application

Figure 8. Block Diagram Representation of Hardware Setup

AN021201-1104 Developing an eZ80F91 MCU Application

AN021201-1104 Developing an eZ80F91 MCU Application

Initialization of the EMAC, PHY, and CPU

2. Initializes the EMAC configuration registers, as follows:

AN021201-1104 Developing an eZ80F91 MCU Application

b. Initialize the EMAC_TPTV registers. For the purposes of this application,

AN021201-1104 Developing an eZ80F91 MCU Application

EMAC_CFG4. Set to 11h to receive all frames.

g. Initialize the EMAC_AFR register to 0Fh to allow broadcast and multicast

4. Clear the EMAC_ISTAT register by reading it to make sure that no interrupts

AN021201-1104 Developing an eZ80F91 MCU Application

1. Generate a frame for transmission.

The minimum length of data field in an Ethernet frame is specified as 46 bytes.

1.d = decimal, or Base 10 value.

AN021201-1104 Developing an eZ80F91 MCU Application

Testing/Demonstrating the Application

AN021201-1104 Testing/Demonstrating the Application

Table 3. List of References

Topic Document Name

AN021201-1104 Appendix A—References

EthinitFunc: Initialize EMAC Registers,

Wait for EMAC

Generate descriptor table, Udate status register

Wait for EMAC

Figure 9. The Main Routine

AN021201-1104 Appendix B—Flowcharts

Appendix C—Source Code

AN021201-1104 Appendix C—Source Code

extern SYSCALL ETHINITFUNC(char * ieeeaddr, void (*rxnotify)(void));