Implementation of OFDM modulator and

demodulator subsystems using 16 point FFT/IFFT

pipeline arhitecture in FPGA
Jayanta Bhattacharya1 ,Supratik De , Soumyadeep Bose ,Indrajit Banerjee ,Tridib Bhuniya, Rahit Karmakar,Kaustav Mandal,Richa
Sinha,Anubhav Roy,Anusha Chaudhuri
Department Of Electronics & Communication
Institute Of Engineering & Management
West Bengal,India
1.jayanta.bhattacharya@iemcal.com

ABSTRACT- A multi-carrier modulation technique is
Orthogonal Frequency Division Multiplexing (OFDM) which
divides the available spectrum into many carriers. The spectrum
efficiently uses in OFDM compared to FDMA by spacing the
channels much closer together. All carriers in OFDM orthogonal
to one another to prevent interference between the closely spaced
carriers. The objective of this work is to study and design a basic
OFDM modulator and demodulator which contain FFT (Fast
Fourier Transform) and IFFT (Inverse Fast Fourier Transform),
mapping block (QAM), De- mapping block, serial to parallel and
parallel to serial converter using hardware programming language
(VHDL). In OFDM system IFFT/FFT processor is designed
based on pipelined architecture. The pipeline architecture hold so
good so as to reduce the huge structure of FFT/IFFT processor. In
this work radix-22 algorithm and radix-22 architecture is used to
design FFT processor.
The design has been written in VHDL language and then
simulated in the Xilinx ISE simulator 14.2 software and finally
implement the designed in FPGA board (SPARTAN 3E starter
kit).
Keywords— OFDM,FFT, radix-22 algorithm
I. INTRODUCTION
OFDM is multi-carrier modulation system, unlike
conventional single – carrier modulation system (AM/FM).
For demanding high bandwidth and high data rate, OFDM has
been adopted in several wireless standards, such as Digital
audio broadcasting (DAB), Digital video broadcasting (DVB-
T), IEEE 802.11a local area network (WLAN), and IEEE
802.16a metropolitan area network. OFDM is also being
pursued for dedicated short range communication (DSRC) for
road side to vehicle communication. OFDM converts a
broadband frequency-selective channel into a parallel
collection of narrowband flat sub channels. The sub-carriers
have the minimum frequency separation required to maintain
orthogonality among them, though the signal spectra
corresponding to the different subcarriers overlap in
frequency. Hence, the available bandwidth is used very
efficiently. If knowledge of the channel is available at the
transmitter, then the OFDM transmitter can adapt its signaling
strategy to match the channel. Due to the fact that OFDM uses
a large collection of narrowly spaced sub channels, these
adaptive strategies can approach the ideal water pouring
capacity of a frequency-selective channel. In practice this is
achieved by using adaptive bit loading techniques, where
different sized signal constellations are transmitted on the
subcarriers. OFDM is a block modulation scheme where a
block of N information symbols is transmitted in parallel on
sub- carriers. The time duration of an OFDM symbol is N
times larger than that of a single-carrier system. An OFDM
modulator can be implemented as an inverse discrete Fourier
trans- form (IDFT) on a block of information symbols
followed by an analog-to-digital converter (ADC) and at the
demodulator part FFT block may be used. So IFFT/FFT block
is an important part of the OFDM system. Here IFFT/FFT
block in OFDM system will be implemented by a new
approach. Basically the approach is to design an FFT/IFFT
processor by pipeline architecture which is a real time system
that means it generate the result in a specified time. Moreover
FPGA could be the idle platform considering re-
configurability. In this work an OFDM modulator and
demodulator are designed and implemented in FPGA.
II. METHODOLOGY.
Fig. 1 Basic transmitter and receiver system
This is the basic block diagram of OFDM transmitter and
receiver system. In the transmitter system forward error
control/ correction coder is used to obtain the protection against
burst errors. Serial to parallel conversion block require for
converting serial data to the parallel data. The number of bits in
parallel data should be dependent on the modulation technique.
At the receiver side we need the parallel to serial converter
which convert parallel data to serial data which are to be
received. Interleaver [5] is done to protect the transmitting
data from the burst error during the transmitting time

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.Conceptually, the in-coming bit stream is re-arranged so that ROM is used to store each constellation point. Each I (real)and
adjacent bits are no more adjacent to each other at the time of Q(imaginary) represent by the 16 bit binary number and MSB
the operation. The constellation mapper basically maps the of each 16 bits are representing sin bit next 9 bit represent
incoming bits onto complex symbol. Different modulation integer part of the number and last 6 bit are represented
technique can be used such as QPSK, BPSK, and QAM etc. fractional part of the number
For the mapping of incoming bits to the constellation point at
first we need to make the bit stream in group and then map B. -QAM block:
them corresponding I-Q value. The number of bits in the group Output of the serial to parallel converter is applied to the
depend on the modulation technique used. For example, 1bit QAM module. In this project 64 - QAM is used. So it provides
for BPSK, 2 bit for QPSK, 4bit for 4-QAM and 6bit for 64- 64 constellation point and each symbol maps to their
QAM etc. The reverse operation is done on the de-mapper in corresponding constellation point. Each point provides real
the receiver side, where incoming constellation point is and imaginary value according to the I-Q diagram. To create
reconverted into the group of bits according to their I-Q value. 64 constellation points each symbol must contain 6 bits. ROM
The most important block in the OFDM is FFT/IFFT block
is used to store each constellation point. Each I (real)and
.IFFT basically gives the OFDM orthogonality. The IFFT
transforms a spectrum into time domain signal. It converts a Q(imaginary) represent by the 16 bit binary number and MSB
number of complex data points into the same number of data of each 16 bits are representing sin bit next 9 bit represent
points in the time domain. Similarly, FFT at the receiver side integer part of the number and last 6 bit are represented
performs the reverse operation i.e. it converts the time domain fractional part of the number
signal to the frequency domain signal. RF modulator and RF
demodulator block is used to modulate I-Q output of the Table .2: represent of constellation of 64- QAM
processed IFFT block on the RF carrier of the transmitter. First Real (I) Last 3bits
Similarly on the receiver side RF demodulator down converts 3bits of value of input imaginary
I-Q signal which to be fed to FFT block. input data(Din) (Q) value
data(Din) b3b4b5
III. DESIGN OF EACH BLOCK
b0b1b2 000 -7
A. Serial to parallel converter 000 -7 001 -5
The first stage is serial to parallel converter. Any input serial 001 -5 011 -3
data is converted into parallel bits. In this work it gives 6 bits 011 -3 010 -1
parallel output at a time. In this case 6 bits parallel data makes 010 -1 110 1
a symbol which is applied to the 64-qam mapper circuit. The
register is the basic component to make a serial to parallel
110 1 111 3
converter. It needs 6 clock pulses to give 6 bit output from 111 3 101 5
serial input. The procedure of data shifting in the shift register 101 5
is given in the following table: 1 100 7
100 7
Table:1 The procedure of data shifting in the shift register
Resister contain Raising edge C. IFFT block:
Clock The main part of OFDM modulator is IFFT which provide the
orthogonal sub carrier for modulation. IFFT block is designed
by the help of the FFT block with little modification. To make
X X X X X D0 1st clock the IFFT block at first an input data applied to the complex
conjugate block then applied to the FFT block and then output
of the FFT block also applied to the complex conjugate block.
The complex conjugate block converts complex data in
X X X X D1 D1 2ND clock complex conjugate from by only inverting MSB of the
imaginary data in. the output of the complex conjugate block
applied to the divided by N block whose output is gives IFFT
value
X X X D0 D1 D2 3rd clock

X X D0 D1 D2 D3 4th clock
Fig. 2 IFFT block
X D0 D1 D2 D3 D4 5th clock
D. FFT block:
D0 D1 D2 D3 D4 D5 th
6 clock The FFT module is most vital block in the OFDM system. 16-
point FFT is design using R2SDF architecture. It has seen, this

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architecture can be designed using two butterfly circuits. Two
butterfly circuits are identical to each other. Each butterfly
circuit contains adder- Subtractor block, and switching
block. The butterfly circuit has four 16 bit input lines and four ………… (3)
16 bit output lines. Two input ports are directly connected The butterfly structure has form of
with real and imaginary data with of the previous stage and
other two are connected with the output of the FIFO block
which feeds back previous sample of real and imaginary data
for pipelined processing. Two output ports feed real and
imaginary sample to the FIFO input and other two output ports
pass real and imaginary data to the next stage. The control If the expression within the braces of the equation (3) is
signal is generated by the simple binary counter. further decomposing we will get normal radix-2 FFT [1]
results. The key idea of the new algorithm to process the
Radix-22 DIF FFT algorithms: [1] second step decomposition to remaining DFT coefficients,
In this work radix-22 algorithm and radix-22 architecture is
used to design FFT processor. The reason to select this including the “twiddle factor” , [1]to exploit
algorithm is radix-2 is a good algorithm. It has low
quantization noise and it is also easily parameterizable to the the exceptional values in multiplication before the next
different FFT lengths. Due to high quantization noise and butterfly is contacted. The twiddle factor decomposition is[1]
difficult to parameterizable for different FFT length radix-r
does not seem too good a chose as the radix -2 one. The noise
is very bad for the OFDM communication.
Since minimizing the number of multiplier is an important ……(4)
matter for design, form this side split radix algorithm is good Substituting eqn. (4) in eqn. (3) and derive the summation
choice because it lower number of multiplier compare to other with index n2 the DFT will be in four time shorter DFT length.
algorithm. But this algorithm is very complex to design and it
is not easily parameterizable for different FFT length. The
control of this type of processor is more complex. …..(5)
The radix -22 algorithm is most attractive algorithm because it Where H (k1, k2, n3)[1] express as the equation
is very simple to design, low number of multiplier and simple
control structure
The radix-22 algorithm can be thought of as a radix-4
algorithm by the radix-2 building block. That is the notion of
radix-22 DIF algorithm is used to clearly reflect the structural ..(6)
relation with radix-2 algorithm and identical computational
requirement with radix-4 algorithm. The equation (5) represents two stage of butterfly’s structure
The DFT of size N defined by with only trivial multiplication. AS BF I and BF II .after two
stages, full multipliers are required to compute the product of
X (K) = 0≤K<N ………… (1)
the decomposed twiddle factor [1] in the
equation (5).The butterfly-I is the one represented by the
Where WN detonates the nth primitive root of unite, with
formula in the brackets into the last part of equation (6) and
exponent calculated modulo N. to make the derivation of new
butterfly –II is same equation with a multiply by the (-j)(k1+2k2)
algorithm clearer, consider first two steps of decomposition in
.the complete radix-22 algorithm is derive by applying this
the -2 DIF FFT together. Appling 3 - dimensional linear index
procedure recursively.[1]
map[1]
R22SDF FFT processor architecture are shown in the fig

N = < n1 + n2+n3>N ………………(2)

K = <k1+2k2+4k3>N

The common factor algorithm (CFA) will be by the putting the

value of N and K
Fig. 3 R22SDF FFT processor architecture
X(K1+2K2+4k3)=
( n1+ n2+n3)

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Butterfly structure for R22SDF FFT multiplied in still next N/2 cycle When the first half of the
next frame of the time sequence is loaded in.
1Butterfly –I architecture:
The diagram shown below is of the butterfly-I architecture[1]. Butterfly-II architecture:
The main component is add-subtractor block and switch-I
block. Second butterfly circuit is same as the first butterfly circuit,
but has only difference in trivial multiplication, included to
implement twiddle factor multiplication by (-j) (k1+ k2) [1]. The
trivial multiplication is real and imaginary value swapping.
This happens when the input sequence just N/4 .The basic
diagram of Butterfly- II is shown below

Fig 4: Butterfly –I architecture[1]

Adder- Subtractor Block

The adder block is designed by 16 bit parallel adder circuit. Fig 5: Butterfly –II architecture[1]
And by using the adder block one can also subtract operation
Switching- II Block
using XOR gate. The parallel adder circuit is designed by full
adder circuit and XOR gate. The main function of this block is
Switching –II block is connected to the input of the butterfly
to add and subtract depending on the mode of input line. If the
circuit. This provides the trivial multiplication by changing
mode input is zero, it operates as the adder circuit and mode is
real number to imaginary number. The trivial multiplication
one, it operates as the subtraction. The output of the Adder-
happens at the (N/4) sequence of the input frame. The control
Subtractor circuits is in 2’s compliment format so it needs to
signal (en) is provided by the binary counter. This switch has
be converted in the normal bit format; that is MSB should be
two 16 bit input line which are directly connected to the two
sine bit and next 9 bits represent integer and 6 bits represent
output lines (16 bit) when the control signal (en) is low and
fractional part [1,M,N]..
two input lines are connected to the output line by inter
changing position when the control signal is “1”. The
Switching-I block
switching diagram is shown here.
If one takes a close look on the butterfly-I structure [1], one
Table 3: Input and output of
can see two paths in the output side. In One path incoming
switching Block
input data is directly connected to the output. In the second
path output of the addition and subtraction is connected to the
output. This selection of two paths is done by the bank of 16, A B EN D E
Fig. 6 Switching Block
2-to-1 multiplexer. The bank of mux selects the output either 0 0 0 0 0
coming directly from the input from output of the add-sub 0 0 1 0 0
block. The control input of the multiplexer is general which is
0 1 0 0 1
provided by the output of the binary counter.
0 1 1 1 0
On first N/2 cycles, the 2-to-1 multiplexors in butterfly-I 1 0 0 1 0
module switch to the “0” and the butterfly is idle; the input 1 0 1 0 1
data from left is directed to the shift register (FIFO) until they 1 1 0 1 1
are filled. On the next N/2 cycles, the multiplexor turns to the
position “1”, the butterfly compute a 2 point DFT with 1 1 1 1 1
incoming data and data stored in the shift register (FIFO) [1].
The table shows, the input values interchange only when the
Z1 (n) = x (n) + x (n + N/2) “en” signals is one. Only when N/4 sequence data is inputted,
Z1 (n + N/2) = x (n) + x (n + N/2) the “en” signal becomes “1”. This is done according to the
fig.6.
The butterfly output Z1 (n) is to be applied to the twiddle En = (not T) and S
factor, and Z1 (n + N/2) is sent back to the shift registers to be S and T are output bit of the binary counter

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E. Design of the twiddle- factor generator:
The twiddle factor generator contains ROM block to store the
value of the twiddle factor. The value is represented by fixed
point representation, in the format [1:1:14], that means that
MSB one bit represents sign of the value and next one bit
represent integer value and last 14 bit represent fractional
value. Here only one bit is required to represent integer value
because twiddle factor value always stay between [-1, +1] and
thus the large number of bits represent fraction field to provide
very accurate precision. The twiddle factor values are fed to
the complex multiplier along with the output of the butterfly-
II. After multiplication, bit format will not change
In the FFT architecture after two stage, full multipliers are
required to compute the product of decomposed twiddle factor
WNn3(k1+ k2) [1] as shown in the equation (5.12).
The twiddle factor is generated according to the serial number
of the table, one by one. This sequence is maintained with the
help of the binary counter output
Complex multiplier:
Complex multiplier is an important component for the OFDM
System. Complex number multiplication needs four real
number multiplication and two additions. In real number
processing, carry bit is needed to be propagated from least
significant bit (LSB) to the most significant bit (MSB), when
binary partial products are added. Therefore, the addition and
subtraction after binary multiplications, limit the overall
speed, although many techniques have proposed to overcome
this problem.
In this work a parallel array multiplier is used for the real
multiplication. The complex number multiplication system can
be divided into two main components known as real part(R)
and imaginary part (I).
R + jI = (A + jB) (C + jD) ………… (7)
Based on the equation (6.1), the real part is the output for (AC
- BD) and the imaginary part is the output for (BC + AD). To
generate those two main components require sub-components
called partial product generator and adder/subtractor
Fig.7 Complex multiplier
The partial product generator is done by real multiplication.
The most vital issue to design real multiplier is to keep the bit
length fixed throughout the architecture. The output of the real
multiplication bit length will be double. So it needs to truncate
least significant bits after multiplier operation. In this project
format, MSB represents the sign bit and next 9 bits represent
the integer and next 6 bits represent fraction part. For the
twiddle factor value MSB represents the sign bit and next bit
is integer bit and last 14 bits represent fractional part. The
output of the multiplier MSB represents the sign bit and next 9
bits represent the integer and next 6 bits represent fraction part
and last 16 bits are simply truncated. Due to truncation, it
provides little bit truncation error which is over come by dding
error correction technique at the output of the multiplier.
F. Control block:
Control signal in radix -22 algorithm of the FFT may be
generated simply using only binary counter. The length of the
binary counter must be log2N. So for 16 point FTT design, the
control signal generated by the binary counter is of 4 bit
length.
G. QAM De Mapper block:
De Mapper block operation is opposite operation of QAM
mapper block. De Mapper block gives symbol output
according to the input of the real and imaginary value which is
the output of the FFT block.
H. Parallel to serial block:
The output of the de QAM circuit is applied to the parallel to
serial block which convert 6 bit parallel data to serial data that
is same as original serial data. It is made by simple parallel to
serial shift register
IV. SIMULATION RESULT
Simulation result of the serial to parallel converter.
Fig. 8 simulation result of the serial to parallel converter
Simulation result of the QAM-mapping
QAM block provide I-Q value for each symbol according to
the constellation points which are previously describe.
Symbols and their corresponding I-Q value are shown in
below table. These symbols are generated from serial to
parallel converter
Fig. 9 Simulation result of the QAM-mapping
Simulation results of the IFFT
Output of QAM mapper block is applied to the IFFT block.
Input and output bits of IFFT Block are shown in below
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table. The output of the IFFT block is applied to the
demodulator block
Fig. 10 Simulation results of the IFFT
simulation results OFDM modulator and demodulator
Fig. 11 simulation results OFDM modulator and demodulator
RTL Diagram of OFDM modulator and demodulator
Fig.12 RTL Diagram of OFDM modulator and demodulator
V.
VI. CONCLUSION AND FUTURE SCOPE
In this paper basic OFDM modulator and demodulator has
been successfully designed using mixed style VHDL program
and it has also been implemented in the FPGA kit.
The OFDM modulator and demodulator consists of serial to
parallel converter , QAM-mapper ,IFFT , FFT ,De-QAM, and
parallel to serial converter. Each of those blocks has been
tested by Xilinx simulator during design process. The
IIFT/FFT processor has been successfully designed based on
the pipeline architecture using radix 22 algorithm which
reduces the complexity of FFT. In this design, the output of
the OFDM demodulator using FFT has insignificant error,
because of truncation of bits, at the output of parallel
multiplier. This error is removed by the round-off of the
output of FFT.
.
This OFDM modulator demodulator implementation on
FPGA proves the validity and success of the design procedure.
To point out some direction where the future work is possible,
this portion suggests to the improvement of the project work
and interesting continuation which remain incomplete due to
limited time. For the future work it is suggested to develop
other modules such inter-leaver, error correction, cyclic prefix
and RF part. Those will make a complete set of OFDM system
for transmitter and receiver for wireless non line of sight
communication applications.
VII. REFERENCES
1. Shousheng He and Mats Torkelson “A New
Approach to Pipeline FFT Processor“ Department of
Applied Electronics, Lund University,2003
2. 26th NATIONAL RADIO SCIENCE
CONFERENCE (NRSC2009) “Implementation of an
OFDM System Using FPGA” March 17-19,2009,
Faculty of Engineering, Future Univ., Egypt
3. “Design and implementation of OFDM transmitter
and receiver on FPGA hardware” kamaru adzha bin
kadiran,”Master of Electrical Engineering
(Electronics and Telecommunication) Faculty of
Electrical Engineering Universiti Teknologi
Malaysia NOVEMBER, 2005
4. Aifeng Ren*, Ming Luo*, Fangming Hu* “FPGA
Implementation of an OFDM Modem” School of
Electronic and Engineering, XiDian University,
Xi’an 710071, P. R.
5. Wiedong Li ,” study on implementation of low power
FFT processor” Thesis No 1030, DEPARTMENT OF
Electrical Engineering, Linkoping university Sweden,
june 2003.
6. International Standard ISO/IEC 8802-11:1999/Amd
1:2000(E) IEEE Std 802.11a-1999 Information
technology—Telecommunications and information
exchange between systems—Local and metropolitan
area networks—Specific requirements Part 11:
Wireless LAN Medium Access Control (MAC) and
Physical Layer (PHY) Specifications Amendment 1:
High-speed Physical Layer in the 5 GHz band
7. “OFDM Baseband Receiver Design for Wireless
Communications” Tzi-Dar Chiueh and Pei-Yun Tsai
© 2007 John Wiley & Sons (Asia) Pte Ltd. ISBN:
978-0-470-82234-0
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