Sensorless

Contents
Contents i
Abstract iv
List of Figures vi
List of Tables ix
Abbreviations x
Symbols xi
1 Introduction 1
1.1 Motivation for Grid Connected Inverter . . . . . . . . . . . . . . . . 1
1.2 Specification, Demands and Standards . . . . . . . . . . . . . . . . 2
1.3 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Research Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 Outline of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Grid Connected Inverter 10

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Voltage Source Inverter . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Fundamental Components . . . . . . . . . . . . . . . . . . . 11
2.3 Operation Of Grid Connected Inverter . . . . . . . . . . . . . . . . 12
2.3.1 Unity Power Factor (Rectifier) . . . . . . . . . . . . . . . . . 12
2.3.2 Unity Power Factor (Inverter) . . . . . . . . . . . . . . . . . 13
2.3.3 Leading Power factor . . . . . . . . . . . . . . . . . . . . . . 13
2.3.4 Lagging Power factor . . . . . . . . . . . . . . . . . . . . . . 14
2.4 Controls of VSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.1 Hysteresis Control . . . . . . . . . . . . . . . . . . . . . . . 15
i
Contents ii
2.4.2 Predictive Current Control . . . . . . . . . . . . . . . . . . . 15

2.4.3 Proportional Integral Control . . . . . . . . . . . . . . . . . 15
2.4.4 Proportional Resonant Control . . . . . . . . . . . . . . . . 16
2.5 Comparison of Different Filters Used for grid Connection . . . . . . 20
2.5.1 L-filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5.2 LC-filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5.3 LCL-filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Modeling and analysis 23

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Modeling of LCL Filter . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Modeling of PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.1 Analog PWM . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 Digital PWM . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 DC Voltage Loop Modeling . . . . . . . . . . . . . . . . . . . . . . 30
4 Design of Grid Connected Inverter 32

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2 LCL Filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.1 Selection of LCL Parameters . . . . . . . . . . . . . . . . . . 33
4.2.2 Passive Damping . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3 Current Controller Design . . . . . . . . . . . . . . . . . . . . . . . 37
4.3.1 PR Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3.2 Selective Harmonic Compensation . . . . . . . . . . . . . . . 39
4.3.3 Proportional Resonant Integral Controller . . . . . . . . . . 41
4.4 DC Voltage Controller Design . . . . . . . . . . . . . . . . . . . . . 42
5 Performance Analysis Through Simulation 44

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2 Simulation of Grid Connected Inverter . . . . . . . . . . . . . . . . 45
5.3 PR Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.4 Harmonic Compensator . . . . . . . . . . . . . . . . . . . . . . . . 46
5.5 Proportional Resonant Integral Controller . . . . . . . . . . . . . . 48
6 Development of Laboratory Prototype 54

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.2 Inverter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3 Control and Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.2 Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.3 Optical-isolator . . . . . . . . . . . . . . . . . . . . . . . . . 57
Contents iii
6.3.4 Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.3.4.1 Bootstrap Component Selection . . . . . . . . . . . 59
6.3.5 Voltage Sensor Peripheral Selection . . . . . . . . . . . . . . 60
6.3.6 Current Sensor . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.7 Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.8 Synchronizing Circuit . . . . . . . . . . . . . . . . . . . . . . 63
6.4 Sampling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.5 Major Design Issues and Recommendation . . . . . . . . . . . . . . 64
6.5.1 EMI Noise Problem . . . . . . . . . . . . . . . . . . . . . . . 64
6.5.2 Shielding Control Signals from EMI . . . . . . . . . . . . . . 66
6.5.3 PCB layout considerations . . . . . . . . . . . . . . . . . . . 67
6.5.3.1 Power bus Decoupling . . . . . . . . . . . . . . . . 67
6.5.4 Problem with Buffer . . . . . . . . . . . . . . . . . . . . . . 68
6.5.5 Driver Circuit Peripheral Consideration . . . . . . . . . . . . 68
6.5.5.1 Minimize the effect of parasitic components . . . . 68
6.5.5.2 Reduce control IC exposure . . . . . . . . . . . . . 69
6.5.5.3 Improve local decoupling . . . . . . . . . . . . . . . 69
6.6 Performance Analysis of Laboratory prototype . . . . . . . . . . . . 71
6.6.1 Steady State Operation . . . . . . . . . . . . . . . . . . . . . 71
6.6.2 Transient Operation . . . . . . . . . . . . . . . . . . . . . . 72
7 Conclusion and Future Scope 77

7.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.2 Future Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
A Simulation Subsystem 82
B Hardware Circuit Diagrams 84
C DSP Program 89
Abstract
The depletion of fossil fuel resources on a worldwide basis has necessitated
an urgent search for alternative energy source which is sustainable and viable to
meet up the present day demands.There are compelling reasons to believe that the
traditional system of large, central power stations connected to their customers by
hundreds or thousands of miles of transmission lines will likely be supplemented
and eventually replaced with cleaner, smaller plants located closer to their loads.
Such distributed generation systems reduce transmission line losses and costs,
increases their overall efficiency and economic advantages.
The available sources for distributed power generation provide power in dc

form eg. Solar PV cell, fuel cell etc. Hence a power electronic converter is required
to connect these energy sources to the grid. Certain constraints are imposed by
the international standards to maintain the power quality of these power elec-
tronic converters. These standards are taken as base for the design of the power
electronic converters. DC-DC converters can be used for the special application
like maximum power point tracking and voltage boosting. Main emphasis of this
project is given on the design of the power electronic converter for grid interface.
A prototype of generic grid connected inverter is designed and developed

for the power rating of 100W. The grid connected inverter is operated in current
control mode to inject sinusoidal current with the help of DSP TMS320F28027.
The filters are used for attenuating switching frequency components in the current.
An isolation transformer is used to interface the inverter with the grid which also
acts as step up transformer.
For current control application traditionally Proportional Integral (PI) con-

trollers were used, but now the focus of research is shifting towards Proportional
Resonant (PR) controllers. PR controllers have inherent advantages like low
Contents v
steady state error when tracking sinusoidal reference and also better disturbance
rejection capability as compared with PI controllers. In this project three differ-
ent topologies of PR controller are studied and analysed. It was found that PRI
controller gives better THD over the other two topologies.
List of Figures
2.1 Basic Circuit for Grid connected Inverter . . . . . . . . . . . . . . . 11

2.2 Operation in Unity Power Factor Mode (rectifier) . . . . . . . . . . 12
2.3 Operation in Unity Power Factor Mode (inverter) . . . . . . . . . . 13
2.4 Operation in Leading Power Factor Mode . . . . . . . . . . . . . . . 14
2.5 Operation in Lagging Power Factor Mode . . . . . . . . . . . . . . . 14
2.6 Block Diagram of Plant Along with Controller[1] . . . . . . . . . . . 16
2.7 Frequency Response of Ideal PR controller . . . . . . . . . . . . . . 17
2.8 Frequency Response of Practical PR Controller . . . . . . . . . . . 18
2.9 Frequency Response of PR Controller for variation in Ki . . . . . . 19
2.10 Frequency Response of PR Controller for variation in ξ . . . . . . . 19
2.11 Frequency Response of PR Controller for variation in Kp . . . . . . 20
2.12 Different Topologies for Filters . . . . . . . . . . . . . . . . . . . . . 21
3.1 Grid Connected Inverter Through LCL Filter . . . . . . . . . . . . 24

3.2 Block Diagram of LCL Filter . . . . . . . . . . . . . . . . . . . . . 24
3.3 Analog PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4 Digital PWM in (a)Single Update Mode, (b)Double Update Mode . 28
3.5 Equivalent model of digital PWM . . . . . . . . . . . . . . . . . . . 29
3.6 Voltage Control Loop . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1 Frequency Response of LCL Filter Under Un-damped and Damped

condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2 Characteristics of passive damping method . . . . . . . . . . . . . . 37
4.3 Current Control Loop . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.4 Frequency Response of Current Control Loop with Iref as input . . 39
4.5 Frequency Response of Current Control Loop with Vg as input . . . 39
4.6 Topology for PR + Harmonic Compensator . . . . . . . . . . . . . 40
4.7 Frequency Response of Current Control Loop for harmonic com-
pensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.8 Topology of PRI controller[2] . . . . . . . . . . . . . . . . . . . . . 41
4.9 Frequency Response of Current Control Loop for PRI controller . . 42
4.10 Voltage loop block diagram . . . . . . . . . . . . . . . . . . . . . . 42
vi
List of Figures vii
4.11 Frequency Response of Voltage Loop with PI controller . . . . . . . 43
5.1 Simulink Model of grid Connected Inverter . . . . . . . . . . . . . . 45

5.2 Inverter Voltage (Vinv ) and Inverter Current (Ii ) . . . . . . . . . . . 47
5.3 Grid Voltage (Vg ) and Grid Current (Ig ) . . . . . . . . . . . . . . . 47
5.4 Inverter Voltage (Vinv ) and Grid Voltage (Vg ) . . . . . . . . . . . . 48
5.5 FFT Analysis of Inverter Current (Ii ) . . . . . . . . . . . . . . . . . 48
5.6 FFT Analysis of Grid Current (Ig ) . . . . . . . . . . . . . . . . . . 49
5.7 DC Bus Voltage (Vi ) . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.8 Inverter Voltage (Vinv ) and Inverter Current (Ii ) . . . . . . . . . . . 50
5.10 FFT Analysis of Inverter Current (Ii ) . . . . . . . . . . . . . . . . . 50
5.12 Inverter Voltage (Vg ) and Inverter Current (Ii ) . . . . . . . . . . . . 51
5.15 Performance Comparison of Various PR Controller Topologies . . . 53
6.1 Block Diagram of Laboratory Setup . . . . . . . . . . . . . . . . . . 55

6.2 Power Supply Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3 Top view of IC HD74LS04 . . . . . . . . . . . . . . . . . . . . . . . 57
6.4 Top view of TLP250 . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.5 Circuit diagram of driver circuit . . . . . . . . . . . . . . . . . . . . 58
6.6 Circuit for Voltage Sensor . . . . . . . . . . . . . . . . . . . . . . . 61
6.7 Hall Effect Current Sensor . . . . . . . . . . . . . . . . . . . . . . . 62
6.8 Attenuator, Level Shifter and Precision rectifier . . . . . . . . . . . 63
6.9 Synchronizing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.10 (a)Counter Value Variation, (b)Inverter Output Voltage, (c)Load
Current Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.11 Gate signals from DSP [Ch1: 2V/div],Driver Output Voltage [CH2:
5V/div] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.12 Various Shielding Options . . . . . . . . . . . . . . . . . . . . . . . 66
6.13 Power Bus Decoupling Capacitor Placement . . . . . . . . . . . . . 67
6.14 Recommendation for Minimization of Parasites . . . . . . . . . . . 69
6.15 Placement of Decoupling Capacitor (a)Recommended (b)Not Rec-
ommended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.16 Placement of Bootstrap components (a)Recommended, (b)Not rec-
ommended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.17 Experimental Setup Photograph . . . . . . . . . . . . . . . . . . . . 71
6.18 Inverter Output Voltage(Vinv ) [CH1: 50V/div] and Current (Ii )
[CH2:5A/div] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
List of Figures viii
6.19 Current at the output of filter [CH2:5A/div] . . . . . . . . . . . . . 73

6.20 Grid Current(Ig ) [CH2: 940mA/div] . . . . . . . . . . . . . . . . . 73
6.21 Grid Voltage (Vg ) [CH1: 250V/div] and Grid Current (Ig ) [CH2:
940 mA/div] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.22 FFT Analysis of Grid Current Ig . . . . . . . . . . . . . . . . . . . 74
6.23 DC bus voltage(Vi ) [CH1: 25V/div] and current(Idc ) [CH2: 1A/div] 74
6.24 Transient Response: Inverter Voltage [CH1:50V/div] and Inverter
Current [CH2: 10A/div] . . . . . . . . . . . . . . . . . . . . . . . . 75
6.25 Transient response: Grid Voltage [CH1: 250V/div] and Grid Cur-
rent [CH2: 940mA/div] . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.26 Comparison of Simulation and Experimental Results . . . . . . . . 76
A.1 Inverter sub system . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

A.2 Filter sub system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A.3 Controller sub system . . . . . . . . . . . . . . . . . . . . . . . . . . 83
B.1 Circuit for DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

B.2 Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
B.3 One Leg for Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . 85
B.4 DC voltage Sensor Circuit . . . . . . . . . . . . . . . . . . . . . . . 86
B.5 current Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
B.6 Precision Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
B.7 Synchronizing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 88
B.8 Circuit for LM337 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
List of Tables
1.1 Summary of Grid Standards . . . . . . . . . . . . . . . . . . . . . . 3
4.1 Selected values for LCL filter . . . . . . . . . . . . . . . . . . . . . . 36
5.1 Selected values for Simulation . . . . . . . . . . . . . . . . . . . . . 44

5.2 Comparison of THD for Various topologies of PR controller . . . . . 49
ix
Abbreviations
ADC Analog to Digital Converter

DSP Digital Signal Processor
EMI Electro Magnetic Induction
ESR Equivalent Series Resistance
GM gain Margin
HC Harmonic Compensator
IC Integrated Circuit
PCB Printed Circuit Board
PCC Point of Common Coupling
PI Proportional Integral
PR Proportional Resonant
PRI Proportional Resonant Integral
PM Phase Margin
PV Photovoltaic
PWM Pulse Width Modulation
DPWM Digital Pulse Width Modulation
THD Total Harmonic Distortion
VSI Voltage Source Inverter
x
Symbols
δ angle degree
C output filter capacitance F
Cdc DC bus capacitance F
f Grid Frequency Hz
fs Switching Frequency Hz
Idc DC bus current A
Ig Grid Current A
Ii Inverter Current A
Ki Gain for Resonant Controller
Kiv Gain for Integral Controller
Kp Gain for Proportional Controller of current controller
Kpv Gain for Proportional controller for Voltage controller
L1 Inverter Side Inductor H
L2 Grid Side Inductor H
rc Damping Resistance Ω
r1 Internal Resistance of Inverter side Inductance Ω
r2 Internal Resistance of Grid side Inductance Ω
Td Delay Time sec
Ts Switching Period sec
Vi DC bus Voltage V
Vinv Inverter Output Voltage V
xi
Symbols xii
Vg Grid Voltage V
ω0 Angular Frequency of Grid rads−1
Dedicated to my parents.
xiii
Chapter 1
Introduction
1.1 Motivation for Grid Connected Inverter
The global energy consumption is rising and increasing attention is paid

to alternative methods of electricity generation. The low environmental impact
of renewable energies makes them a very attractive solution for growing energy
demand. In this trend towards the diversification of energy markets, Photovoltaic
(PV) power supplied to the utility grid is gaining more and more popularity. There
is an uncertainty in the Power generated by the PV cells. While it is clear that
the renewable energy is not an immediate answer to the problem, it can certainly
play a role in the solution to global energy needs in conjunction with traditional
sources of energy.
In addition to the large scale solar power plants, the market of residential
PV power generation has grown rapidly in recent years. Unlike solar power farms
residential PV modules require the grid connected inverter to be small, low power
and single phase units. In Maharashtra, India a single phase electricity distribution
system is preferred for single family or light commercial application. Voltage level
1
Chapter 1. Introduction 2
in the single phase distribution system is 230 V, and frequency is 50 Hz. Therefore
single phase 50Hz, 230V point of common coupling (PCC) can be used as basic
guideline when designing the grid connected inverter.
The price of PV modules was in past a major contribution of these systems.

A downward tendency is now seen in the price of the PV modules due to massive
increase in the production capacity of PV modules. The cost of grid connected
inverter, is, therefore, becoming more visible in the total system price. A cost
reduction per inverter watt is, therefore, important to make the system more
attractive. Focus has therefore been placed on new, cheap, and innovative inverter
solutions, which has resulted in a high diversity.
General off-grid solar PV system requires energy storage system, as solar

energy is not available during all the hours of day. Energy storage systems like
batteries are not efficient ways of storing energy. By the use of grid connected
PV based inverters the requirement of energy storage system is eliminated. When
solar PV systems used in conjunction with conventional energy sources, can help
make power grid more efficient and cost effective.
1.2 Specification, Demands and Standards
Inverter interfacing DC source with the grid involves one major task. It is to
insure that the current injected into the grid is sinusoidal in nature. It is further
analyzed as below.
Since the inverter is connected to the grid, the standards given by the util-
ity companies must be obeyed. In particular the future international standard
IEC61727 and the present standard EN61000-3-2, IEEE1547 are worth consider-
ing. Summaries are listed in Table 1.The inverter must also be able to detect the
islanding situation and take appropriate measures in order to protect persons and
Table 1.1: Summary of Grid Standards
Issue IEC61727 IEEE1547

Nominal Power 10kW 30kW
Harmonic Currents (3-9)4% (2-12)4%
(Order-h) Limits
(11-15)2% (11-16)2.0%
(17-21)1.5% (17-22)1.5%
(22-23)0.6% (22-24)0.6%
(>35)0.3%
Maximum Current THD 5% 5%
Power factor at 50% 0.9
of rated power
DC Current injection <1.0% <0.5%
Voltage range for
normal operation 85%-110% 88%-110%
Frequency range for
normal operation 50± 1Hz 59.3 Hz to 60.5 Hz
equipments. Islanding is the continued operation of the inverter when the grid is
removed on purpose, by accident, or by damage. In other words grid has been
removed from the inverter, which then only supplies local loads. The available
detection schemes are normally divided into two groups: active and passive. The
passive methods do not have any influence on power quality, since they just mon-
itor grid parameters. The active schemes introduce disturbance into the grid and
monitor the effect. This may affect the power quality, and problems may occur
with the multiple inverters working in parallel with the grid.
The IEEE and IEC standard put limitation on the maximum allowable
amount of injected dc current into the grid. The purpose of limiting the injec-
tion is to avoid saturation of the distribution transformer. However the limits are
rather small (0.5 % and 1.0 % of the rated output current), and such small values
can be difficult to measure precisely with the exciting circuits inside the inverters.
This can be mitigated by with improved measuring circuits or by including a line
frequency transformer between the inverter and the grid.
1.3 Literature Review
Traditionally PI controller was used for controlling the current in the grid
connected inverter. Problems with PI controller are less disturbance rejection ca-
pability and the tracking ability of the PI controller is not good when the reference
is sinusoidal in nature. Thus the literature survey is oriented in search of the con-
troller which has better disturbance rejection capability and low steady state error
when tracking the sinusoidal reference for single phase grid connected inverter.
In this paper [3] “A review of single phase grid connected inverters for pho-
tovoltaic modules” by S. B. Kjaer, J. K. Pedersen, F. Blaabjerg, review on the
grid connected inverters is given which focuses on the comparison of the inerter
topologies for demands, lifetime, component ratings, and cost. Finally some of
the topologies are pointed out for the single PV module or multiple PV module
application.
[4] “Design and control of LCL filter based 3 phase active rectifier”, M.
Liserre, F. Blaabjerg, and S. Hansen, proposes step by step procedure for designing
the LCL filter of a front end three phase active rectifier. A design procedure and
simulation model provides a powerful tool to design to design LCL filter based
active rectifier.
[5] “Linear current control scheme with series resonant harmonic compen-
sator for single phase grid connected photovoltaic inverters,” M. Castilla, J. Miret,
J. Matas, L. G. de Vicuna, J. M. Guerrero, this paper details with an important
aspect in the operation of single phase grid connected PV inverters. Series con-
nection of harmonic compensator provides efficient attenuation of grid voltage
distortion and accurate synchronization with grid.
[6] “Control design guidelines for single phase grid connected photovoltaic
inverters with damped resonant harmonic compensators,” M. Castilla, J. Miret,
J. Matas, L. G. de Vicuna, J. M. Guerrero, this paper gives a systematic design

procedure for selecting the gains and parameters of harmonic compensators. The
design procedure is formulated according to the standard requirements of the grid
interconnection.
[7] “Selective harmonic compensation control for a single phase active power
filter with high harmonic rejection,” J. Miret, M. Castilla, J. Matas, J. M. Guer-
rero, J. C. Vasquez, Application of PR controller in active filter domain is discussed
in this paper. The approach is based on an outer voltage control loop, inner current
control loop.
[8] “Small signal modeling of digitally controlled grid connected inverters

with LCL filters,” X. Zang, J. W. Spencer, J. M. Guerrero, In this paper new
small signal z-domain models are deduced for digitally controlled grid connected
inverters. The proposed method model the inverter including various delay effects
under most possible circumstances, which allow direct design for controller in z-
domain.
[2] “Mitigation of lower order harmonics in a grid connected single phase PV

inverter,” A. Kulkarni, V. John, A novel design of inverter current control that
mitigates lower order harmonics is presented in this paper. An adaptive harmonic
compensation technique and its design are presented in this paper. In addition a
Proportional-Resonant-Integral (PRI) controller and its design is proposed. this
controller eliminated dc component in the control system.
[9] “A new control structure for grid connected PV inverters with zero steady
state error and selective harmonic compensation,” R. Teodorescu, F, Blaabjerg, U.
Borup, M. Liserre, In this paper stationary frame generalized integrators are used
to control fundamental current and to compensate the grid harmonics providing
disturbance rejection capability without need of feed forward grid compensation.
Moreover the use of grid LCL filter is investigated with the proposed controller.
[1] “Design and control of proportional resonant controller based photovoltaic

power conditioning system,” H. Cha, T. Vu, J. Kim, In this paper a proportional-
resonant controller is used for replacing the PI controller. A theoretical analysis
of PR controller is presented and verified experimentally.
[10] “Limitations of voltage oriented PI control of grid connected PWM rec-

tifiers with LCL filter,” J. Dannehl, C. Wessels, and F. W. Fushs, System stability
is analyzed with respect to different ratios of LCL filter resonance and control
frequencies. PIc onreoller has already been shown to be suitable solution also for
LCL filters, but there are limitations. These are investigated in this paper.
[11] “Small signal z- domain analysis of digitally controlled converters,” D.

M. Van de Sype, K. De Gusseme, F. M. L. L. De Belie, A. P. Vanden Bossche,
and J. A. Melkebeek, paper presents a new exact small signal z-domain model
is derived. In accordance with the zero-order-hold equivalent commonly used for
regular digital control system, this z domain model gives rise to the development
of uniformly sampled PWM equivalent of the converter.
[12] “A sampling algorithm for digitally controlled Boost PFC converters,”

D. M. Van de Sype, K. De Gusseme, A. P. Vanden Bossche, J. A. Melkebeek, to
avoid aliasing without employing a very high sampling frequency, the sampling
is synchronized with pulse width modulation. A new sampling algorithm, called
alternating edge sampling and intended for symmetric PWM, is deduced switch-
ing noise immunity, straightforwardness, accurate measurement of average input
current and the need of only few processor cycles is presented in this paper.
[13] “Digital Control In Power Electronics,” S. Buso, P. Mattavelli, Thiss

book presents some typical converter control problems and their basic digital so-
lutions based on the most widespread digital control techniques.
[14] “Filter optimization for grid interactive voltage source inverters,” P.

Channegowda, V. John, The focus of this paper is to analyze the LCL filter design
procedure from the point of view of power loss and efficiency. Total LCL filter loss
per phase is plotted. There cureves are used to find the most efficient LCL filter
design.
[15] “A design method for the passive damped LCL and LLCL filter based
single phase grid tied inverter,” W. Wu, Y. He, T. Tang, F. Blaabjerg this paper
introduces a new passive damping scheme with low power loss for the LCL filter.
A simple engineering design criterion is proposed to find the optimized damping
resistor value for LCL and LLCL filter.
In single phase systems, grid synchronization can be carried out by filtering

grid voltage or by use of PLL which is most widely accepted solution for grid
synchronization[5]. Implementation of PLL increases the computational load on
the digital controller. This motivates the research for elimination PLL in synchro-
nization process. Literature review reveals the use of PR controller for current
control in single phase grid connected inverters. Different topologies of the PR
controller are discussed in[2][5]. Literature survey motivated for comparison of
the different PR controller topologies, and analysing their performance for single
phase grid connected inverter. A modified digital PWM (double update mode) is
proposed to reduce the delay effect generated in digital PWM. A novel sampling
algorithm is discussed in[12] for boost converter, which eliminates the switching
frequency ripple in the sampled signal. Research is carried out for development of
similar sampling algorithm for grid connected inverters.
1.4 Research Objective
This project aims to a design and implementation of grid connected single

phase inverter with ensuring following points:
• Ensure that the voltage on the DC side of the VSI and the output current are
well regulated by choosing appropriate inverter topology, the output filter
configuration and proper control methods.
• The output current should meet the standard associated with the PV in-
verters as laid out in [16][17]. This will help in complying with the grid code
specified in the international standards.
• Introduce new method of grid synchronization other than Phase lock loop,
so that the computational load on the controller is reduced.
• Exploit new generation low cost micro-controller units to reduce the cost of
the overall system.
1.5 Outline of Thesis
In Chapter 1 the motivation for grid connected system and specification,

demands and standards which are required to be maintained for grid synchro-
nization are discussed. The literature survey related to grid connected inverter
is outlined in Chapter 2. Operation of grid connected inverter and its various
modes of operation are presented. Various control strategies for the current control
are discussed. Comparison of different filters used for interfacing for inverter with
grid is presented. In Chapter 3 modeling and analysis of the grid connected in-
verter is discussed. Chapter 4 Presents the designing of grid connected inverter.
Complete close loop design of the inverter is discussed. Chapter 5 This chapter
presents the performance analysis of the inverter through simulation. Chapter

6 This chapter gives information about laboratory prototype design and develop-
ment.Important points to be kept in mind for designing of the hardware prototype
are discussed. Also the performance of the prototype is analysed with results. In
Chapter 7 Concluding remarks are given in this chapter.
Chapter 2
Grid Connected Inverter
2.1 Introduction
Aim of this chapter is to introduce a test case we will be dealing with in the
following sections. In this chapter basic working of the grid connected inverter
is explained. Various modes of operations of the grid connected inverter is also
discussed in this chapter. These modes are described with the help of vector
diagrams which are helpful for understanding the concept of bidirectional power
flow.
2.2 Voltage Source Inverter
Considered inverter circuit for the grid connection is described in Fig. 2.1.
The power converter has a conventional topological structure, which is known
as single phase full bridge inverter. We will now analyze the power converter’s
organization in some detail.
10
Chapter 2. Grid Connected Inverter 11
A B
Ls Ig
+
+ C1
Vdc Vinv
- -
A’ B’ Vg
Figure 2.1: Basic Circuit for Grid connected Inverter
2.2.1 Fundamental Components
The ideal dc voltage source Vi at the input, in practice are approximately

implemented by a suitably sized capacitor, fed by primary energy source like bat-
tery, dc-dc converter, PV module or fuel cell. The capacitor is normally large
enough to store large amount of energy, and their purpose is to remove the high
frequency ripple in the dc bus caused due to the switching of the inverter switches.
The power switches are represented by conventional IGBT symbol. The

switches used are two quadrant switches. Two quadrants implies to the capability
of switches to conduct both positive and negative current. For this purpose each
switch is paralleled with freewheeling diode. This makes the switch bidirectional
as far as the current flow is considered.
In this chapter the load is considered as the series connection of a resistor

Rs, inductor Ls, and grid with voltage Vs. of the which which characterizes a dc
source on one side and an ac source on another. Inverter under consideration is a
single phase full bridge inverter. A coupling inductor is used between the grid and
the inverter. Coupling inductor also acts as a filter for attenuating the switching
frequency components in the output.
2.3 Operation Of Grid Connected Inverter
Fig.2.1 shows the basic circuit of the grid connected inverter. Before un-
derstanding the operation of grid connected inverter assumption is made that the
current Ig is maintained sinusoidal. Operation of the grid connected inverter can
be explained in four different modes. Various modes of operation of are given
below depending upon the nature of the current drawn from the grid or supplied
to the grid.
2.3.1 Unity Power Factor (Rectifier)
In this mode of operation the active power is drawn from the grid at unity
power factor. Fig.2.2 shows the vector diagram and the waveforms of the grid
voltage and the grid current. Current Ig is in phase with the grid voltage Vg . from
the reference direction of the current Ig shown in the Fig.2.2, it is clear that the
power is flowing from grid to inverter. In other words, the converter is operating
as a rectifier and drawing current from the grid which is in phase with the grid
voltage. Power flow from the grid to converter is also justified from the vector
diagram shown in Fig.2.2 , grid voltage Vg is leading the inverter voltage Vinv by
angle δ.
Vg
Ig Vg Ig
t
j LsIg
Vinv
Figure 2.2: Operation in Unity Power Factor Mode (rectifier)

2.3.2 Unity Power Factor (Inverter)
In this mode active power is drawn from the converter and injected into the
grid. Fig.2.3 shows vector diagrams and waveform showing Vg and Ig when the
converter is operating in this mode. From the fig it is clear that the current Ig
is 1800 out of phase with Vg . From the reference direction of current shown in
Fig.2.3 it is clear that the active power flow is from converter to the grid. If grid
in considered as a load from the point of view of converter then load is supplied
at unity power factor. Power flow from inverter to grid is justified, grid voltage Vg
is lagging the inverter voltage Vinv by angle δ.
Vinv
Vg
Ig
j LsIg
Ig
Vg
Figure 2.3: Operation in Unity Power Factor Mode (inverter)
2.3.3 Leading Power factor
In this mode converter acts as capacitive load for the grid. Current drawn
from the grid Ig is leading. Waveforms for the currentIg and voltage Vg is given in
Fig2.4. From the Fig 2.4 we can see that the current Ig is leading voltage Vg by
900 .From the vector diagram2.4 it is clear, inverter voltage Vinv is in phase with
the grid voltage Vg , magnitude of Vinv is greater than the Vg hence the reactive
power flows from inverter to grid. Thus it can be said that the inverter is acting
as a source of reactive power.
Ig Vg
Ig
Vinv
Vg j LsIg
Figure 2.4: Operation in Leading Power Factor Mode
2.3.4 Lagging Power factor
Fig.2.5 shows the vector diagram and waveforms for the grid voltage Vg and
current Ig , when the inverter is operating in lagging power factor mode. In this
mode the converter acts as a sink for reactive power. From fig 2.5 it is clear that
the grid voltage Vg and inverter voltage Vinv are in phase. Thus only reactive
power exchange will exist between the grid and the converter. As the magnitude
of Vg is more than that of the Vinv the reactive power flow will be from grid to
converter. This can be proven from the vector diagram2.5.
Vg
Ig
Vg
Vinv j LsIg
Ig
Figure 2.5: Operation in Lagging Power Factor Mode
2.4 Controls of VSI
There are three major output current control techniques for the single phase
VSI: hysteresis band, predictive, and sinusoidal pulse width modulation (SPWM)
with Proportional Integral (PI) controller control.
2.4.1 Hysteresis Control
Traditional hysteresis controllers normally have an error band within a fixed

range. In such controllers, if the measured output current is lower than the lower
limit of the hysteresis band of the reference current, the bridge increases its output
voltage, increasing the current. On the contrary, when the output current is
higher than the upper limit of the hysteresis band of the reference current, the
bridge reduces its output voltage, decreasing the current. This type of controller
has the advantage of simplicity and robustness, but the fixed error band would
cause constant varying switching frequency, which may increase the complexity of
designing the output filters and the heat sinks of the switches.[13]
2.4.2 Predictive Current Control
Predictive controllers calculate the required bridge output voltage to force

the measured output current to follow the reference value. This type of control
offers a potential to achieve precise current control with minimum distortions.
However, the controller needs complicated calculations and requires a very accu-
rate knowledge of the system parameters.[13]
2.4.3 Proportional Integral Control
The traditional method of SPWM control uses a proportional-integral (PI)

compensator in the feedback loop to regulate the output current. The traditional
method of PI controller has some drawbacks which are discussed in[2].
Current
Plant Vg(S)
controller
Vt(S)
Ig*(S) Gc(S) Gi(S) Gf(S) Ig(S)
Figure 2.6: Block Diagram of Plant Along with Controller[1]
2.4.4 Proportional Resonant Control
Over past few years researchers are exploring use of proportional resonant
(PR) controller for current control in single phase grid connected inverter.[1][5][6]
PR controller has the ability to eliminate the steady state error when tracking
sinusoidal wave.
Referring the Fig.2.6, system is a two input single output system. In the
Fig.2.6 Gc (s) is the current controller transfer function, Gi (s) is the transfer func-
tion of the inverter and Gf (s) is the transfer function of filter. In this system
Ig∗ (s) is the reference signal and Vg (s) is the disturbance signal. Eq. 2.1 can be
derived by following the superposition theorem. Eq. 2.2 shows the variation in
grid current with respect to the reference current. Eq.2.3 shows the effect of the
grid voltage on the grid current.
Ig (s) = Ha (s)Ig∗ + Hb (s)Vg (2.1)
Ig Gc (s)Gi (s)Gf (s)

Ha (s) = ∗
= (2.2)
Ig 1 + Gc (s)Gi (s)Gf (s)
Ig Gf (s)
Hb(s) = = (2.3)
Vg 1 + Gc (s)Gi (s)Gf (s)
From the equations it is clear that in order to eliminate the effect of distur-
bance (Vg), value of Eq.2.3 must be zero. From Eq. 2.3 it is clear that its value
Magnitude (dB) 300
200
100
0
90
45
Phase (deg)
-45
-90
0 1 2 3
10 10 10 10
Frequency (Hz)
Figure 2.7: Frequency Response of Ideal PR controller
can be made zero only if the value of denominator is infinite. Variable that can
be controlled in the denominator is Gc (s). If the value of Gc (s) is infinite at the
fundamental frequency then the effect of Vg in the current can be eliminated.
In order to achieve this Proportional Resonant (PR) Controller is introduced.

Eq.2.4 gives the equation of the ideal PR controller. PR controller is a generalized
integrator which is tuned to resonate at the fundamental grid frequency. Fig.2.7
shows the frequency and phase response of the ideal PR controller. As can be seen
in the frequency response the magnitude of the PR controller output is infinite
at the resonant frequency and the phase of the PR controller is zero at the same
frequency. At the same time, infinite gain cannot be achieved in the analog as well
as the digital system. Hence practical PR controller is introduced. Eq 2.5 shows
the practical PR controller.
Y (s) s
Gc (s) = = Kp + Ki 2 (2.4)
U (s) s + ω02
Y (s) 2ξωs
Gc (s) = = Kp + Ki 2 (2.5)
U (s) s + 2ξωs + ω02
Fig.2.8 shows the bode magnitude and phase plot of the practical PR con-
50
40
Magnitude (dB)
30
20
10
0
90
Phase (deg)
-90
1 2
10 10
Frequency (Hz)
Figure 2.8: Frequency Response of Practical PR Controller
troller which is represented in Eq. 2.5. As we can see from the frequency response
the gain of the PR controller is high at the fundamental frequency which is suffi-
cient to eliminate the grid voltage tracking error.
Fig2.9-2.11 shows the variation in the response of the PR controller with the
variation of the parameters.
Assuming Kp = 0 and ξ = 0.001, the value of Ki is changed. It can be noted that

the variation of Ki has no change on the bandwidth. The magnitude of the gain
is added as the value of Ki is added.
Assuming Kp = 0, Ki = 1, the value of ξ is changed. It can be noted that

the variation of ξ has an effect on the bandwidth. As the value of ξ increases the
bandwidth also increases. As the gain of the controller should be high only at the
fundamental frequency hence the value of ξ is maintained low. With the increase
in the ξ there is no effect on the phase of the controller.
When the value of Kp is added the magnitude of the PR increases but the
peak value still remains at the resonant frequency. The phase magnitude decreases
Magnitude (dB) 100
50
-50
-100
90
Ki=10
Ki=100
Phase (deg)
Ki=1000
0
-90
1 2 3
10 10 10
Frequency (Hz)
Figure 2.9: Frequency Response of PR Controller for variation in Ki
Bode Diagram
0
-20
Magnitude (dB)
-40
-60
-80
-100
90
=0.01
=0.001
45
Phase (deg)
=0.0001
-45
-90
1 2 3
10 10 10
Frequency (Hz)
Figure 2.10: Frequency Response of PR Controller for variation in ξ
as the Kp increases. Fig 2.11 shows the frequency response of the PR controller
with variation in Kp with Ki=100 and ξ = 0.001 which are maintained constant.
Magnitude (dB) 50
-50
90
Kp=0.1
Kp=1
Phase (deg)
Kp=5
0
-90
0 1 2 3 4
10 10 10 10 10
Frequency (Hz)
Figure 2.11: Frequency Response of PR Controller for variation in Kp
2.5 Comparison of Different Filters Used for grid

Connection
VSI that is supplying to the grid is controlled by the sophisticated control

algorithms like SPWM which ensures nearly sinusoidal currents. The output filter
reduces the harmonics in generated current caused by semiconductor switching.
There are several types of filters. The simplest variant is filter inductor
connected to the inverter’s output. But also combinations with capacitors like LC
or LCL can be used. These possible topologies are shown in Fig.2.12
2.5.1 L-filter
The L-filter (Fig. 2.12(a)) is the first order filter with attenuation 20 dB/decade
over the whole frequency range. Therefore the application of this filter type is
suitable for converters with high switching frequency, where the attenuation is
Ls Ls Ls1 Ls2
VSI VSI C VSI C
a. b. c.
Figure 2.12: Different Topologies for Filters
sufficient. On the other side inductance greatly decreases dynamics of the whole
system.
2.5.2 LC-filter
The LC-filter is depicted in Fig. 2.12(b). It is second order filter and it has
better damping behaviors than L-filter. This simple configuration is easy to design
and it works mostly without problems. The second order filter provides 40 dB per
decade attenuation after the cut-off frequency f0 , it has no gain before f0 , but it
presents a peaking at the resonant frequency f0 .
2.5.3 LCL-filter
LCL filter is shown in the Fig. 2.12(c). The attenuation of the LCL-filter is 60
dB per decade for frequencies above resonant frequency, therefore lower switching
frequency for the converter can be used. It also provides better decoupling between
the filter and the grid impedance and lower current ripple across the grid inductor.
Therefore LCL-filter fits to our application. Transfer function of LCL filter is
discussed in chapter 3. The LCL filter has good current ripple attenuation even
with small inductance values. However it can bring also resonances and unstable
states into the system. Therefore the filter must be designed precisely according
to the parameters of the specific converter and damping arrangement should also
be considered. Designing of the LCL filter is discussed in chapter 4.
Chapter 3
Modeling and analysis
3.1 Introduction
This chapter presents the modeling and analysis of the complete system.
For close loop control of the system the modeling of the system which is to be
controlled should be done perfectly. In the subsections of this chapter modeling
of various components of the system is discussed one by one.
3.2 Modeling of LCL Filter
A third order LCL filter, Figure 3.1, was used to meet the aforementioned
harmonic reduction target. Signal flow graph approach is used to model the sys-
tem. Fig. 3.1 shows the grid connected inverter through the LCL filter. Parasitic
resistance of the filter components is also considered while modeling so that the
model is more nearer to the realistic model. By doing s domain analysis of the sys-
tem and using the Kirchhoff’s current and voltage laws we get following equations.
23
Chapter 3. Modeling and Analysis 24
Applying kirchhoff’s current law at node Vc , we get
1
Ig (s) = [Vc (s) − Vg (s)] (3.1)
L2 s + r2
1 + rc Cs
Vc (s) = [Ii (s) − Ig (s)] (3.2)
Cs
1
Ii (s) = [Vinv (s) − Vg (s)] (3.3)
L2 s + r2
Ii L1 r1 Vc L2 r2 Ig
C
Vinv Vgrid
rc
Figure 3.1: Grid Connected Inverter Through LCL Filter
vg
1
ii 1+rcCs
1 ig
Vinv L1s+r1 Cs vc L2s+r2
Figure 3.2: Block Diagram of LCL Filter
Ii (s) L2 Cs2 + (r2 + rc )Cs + 1

G1 (s) = = (3.4)
Vinv (s) d3 s3 + d2 s2 + d1 s + d0
Ig (s) rc Cs + 1
G2 (s) = = (3.5)
Vinv (s) d3 s3 + d2 s2 + d1 s + d0
Ii (s) rc Cs + 1
G3 (s) = =− 3 (3.6)
Vg (s) d3 s + d2 s2 + d1 s + d0
Ig (s) L2 Cs2 + (r2 + rc)Cs
G4 (s) = = (3.7)
Vg (s) d3 s3 + d2 s2 + d1 s + d0
d3 = L1 L2 C (3.8)
d2 = [(rc + r2 )L1 + (rc + r1 )L2 ]C (3.9)
d1 = L1 + L2 + [r1 rc + r2 rc + r1 r2 ] (3.10)
d0 = r1 + r2 (3.11)
Using eq.3.1-3.3 block diagram of the inverter can be obtained. This block
diagram is depicted in fig.3.2. As can be seen from the block diagram of the
LCL filter, system is 2 input and 1 output system. By applying the Mason’s Gain
formula we can find out transfer functions of the system for different inputs. These
transfer functions are represented by eq.3.4-3.7.
3.3 Modeling of PWM
3.3.1 Analog PWM
Considering the basic circuit given in Fig.2.1, it can be said that, as a result
of the analog comparator and driving circuitry operation, a square-wave voltage
VOC will be applied to the load, with constant frequencyfs , where fS = 1/TS and
TS being the period of the carrier signal c(t), and variable duty-cycle d. This is
implicitly defined, again from Fig.3.3 Finally, from Fig.3.3 the relation between
duty-cycle and the average value (in the modulation period) of the load voltage can
be calculated. Simple calculations show that, in each modulation period, where
m is assumed as constant, the eq3.12 holds
V*GE1(t)
m(t)
+
VMO(t)
-
C(t) V*GE2(t)
Comparator
Driver
CPK C(t) m(t)
Ts
V*GE1(t)
*
V GE2 (t)
DTs
VOC(t) +VDC
-VDC
Figure 3.3: Analog PWM
m Cpk
= (3.12)
DTs Ts
m
d= (3.13)
Cpk
If we now assume that the modulating signal changes slowly along time, with
respect to the carrier signal, i.e., the upper limit of the m(t) bandwidth is well
below 1/TS , we can still consider the result 3.13 correct. The duty-cycle, in turn,
is transferred to the load voltage waveform by the power converter. The slow
variations of the load voltage average value will therefore copy those of the signal
m(t).
3.3.2 Digital PWM
Detail modeling of the analog pulse width modulation (PWM) is discussed

in previous section. In this section modeling of Digital PWM is considered. The
basic principal of the analog PWM also applies to the digital implementation of the
PWM modulator. In more direct sense also known as, “uniformly sampled PWM.”
The analog carrier is replaced by digital counter and the analog comparator is
replaced by the digital one.
The principle of operation is straightforward: the counter is incremented at

every clock pulse; any time the binary counter value is equal to the programmed
duty-cycle (match condition), the binary comparator triggers an interrupt to the
microprocessor and, at the same time, sets the gate signal low. The gate signal is
set high at the beginning of each counting (i.e., modulation) period, where another
interrupt is typically generated for synchronization purposes. The counter and the
compare register have certain number of bits, n, which are often 8 or 16. Depending
on the ratio between the durations of the modulation period and the counter clock
period, a lower number of bits, Ne , are available to represent the duty-cycle. The
counter and comparator have a given number of bits, n, which is often 16, but can
be as low as 8, in case a very simple micro-controller is used. Actually, depending
on the ratio between the durations of the modulation period and the counter clock
period, a lower number of bits, Ne, could be available to represent the duty-cycle.
The number Ne of bits needed to represent the duty-cycle is given by the Eq.3.14
where f-clock is the modulator clock frequency, fs =1/Ts is the desired modulation
frequency, and the floor function calculates the integer part of its argument.
log( fclock
fs
)
Ne = f loor[ ]+1 (3.14)
log 2
Consider single update mode specified in Fig. 3.4 (a), it is immediate to

see that the modulating signal update is performed only at the beginning of each
Cpk Ts m(t) Cpk Ts m(t)

ms(t) ms(t)
VMo(t)
t
VMo(t) VMo(t)
(a) (b) t
Figure 3.4: Digital PWM in (a)Single Update Mode, (b)Double Update Mode
modulation period. Hence digital PWM can be modeled this with a sample and
hold effect. We can observe that, if we neglect the digital counter and binary
comparator operation assuming infinite resolution, the digital modulator works
exactly as an analog one, where the modulating signal m(t) is sampled at the
beginning of each modulation period and the sampled value kept constant for the
whole period.
It is now evident that, because of the sample and hold effect, the response
of the modulator to any disturbance, e.g., to one requiring a step change in the
programmed duty cycle value, can take place only during the modulation period
following the one where the disturbance actually takes place. Note that this delay
effect amounts to a dramatic difference with respect to the analog modulator
implementation, where the response could take place already during the current
modulation period, i.e., with negligible delay. This simple fact implies a significant
reduction of the system’s phase margin with respect to the analog case, which often
compels the designer to adopt a more conservative regulator design and to accept
a lower closed loop system bandwidth. Therefore implementation of digital PWM
calls for the delay, which equals the modulation period.
Double update mode of digital PWM is depicted in Fig.3.4(b), update in-

stants are: at the starting of modulation period and in the middle of modulation
Cpk Ts
m(t)
ms(t)
m(t) ms(t)
ZOH VMo(t)
t
C(t)
VMo(t)
t
Figure 3.5: Equivalent model of digital PWM
period counter equal to Cpk and counter equal to zero. In double update mode
compare register is updated twice per modulation period. Therefore response to
the disturbance comes into effect in half of the modulation period. The delay
caused by the digital PWM is reduced to half of the modulation period. Double
update mode is preferred over the single update mode as delay effect is reduced
to half as that of later one. Reduction of delay effect will improve the close loop
performance. An equivalent model of the uniformly sampled digital PWM with
double update mode is shown in the Fig3.5. PWM can be modeled by eq.3.15, for
double update mode, where Td = Ts /2.
1 −sTd
P W M (s) = e (3.15)
Cpk
When working in the close loop system the feedback signals are sampled
twice per modulation period. Then sampled signals are processed, which leads to
extra addition of processing and computational delay. If samples are taken once
per modulation period then the processing delay will be equal to one modulation
period. Hence to reduce processing delay samples are taken twice per modulation
period. Thus the computational and processing delay is equal to Ts /2, in other
words computational delay is reduced to half of modulation period if sampling
frequency is double the modulation frequency. This computational and processing
delay can be added with the delay caused by digital PWM. Thus the total delay
of PWM (Td ) becomes Ts . The delay effect is replaced by Pade approximation
given as eq.3.16.
1 − sTd
e−sTd = (3.16)
1 + sTd
3.4 DC Voltage Loop Modeling
DC bus voltage control loop modeling is presented in [5]. Using Tellegnance

theorem the differential equation on dc side is given by eq3.17. id c(t) consist of
two components a dc component and a double line frequency ac component. Both
of those components can be obtained from the power balance equation, eq.3.19.
dVdc (t)
Cdc = idc (t) (3.17)
dt
Vdc (t)idc (t) = Vg cos(ωt)Ig cos(ωg t − φ) (3.18)

V gIg V gIg
Vdc (t)Idc (t) + Vdc (t)Idcripple (t) = cos(φ) + cos(2ωg t − φ) (3.19)
2 2
Vg
Idc (t) = √ rms Ig cos(φ) (3.20)
2Vdc
Vg Ig
Idcripple (t) = cos(2ωg t − φ) (3.21)
2Vdc (t)
Since aim is to maintain the grid current in phase with the grid voltage, eq.3.20
can be rewritten as 3.22.
Vg Ig
Idc = √ rms (3.22)
2Vdc Vg
Using these equations dc voltage control loop is modeled. Fig3.6 shows the block
diagram of the outer voltage control loop.
*
Vdc PI Vg(pu) Gc(s) Ii
Vdc
1 Vgrms
1/Vg(pu)
sCdc 2Vdc
Figure 3.6: Voltage Control Loop

Chapter 4
Design of Grid Connected

Inverter
4.1 Introduction
In this chapter design of Power stage and control stage is presented. Power
stage design includes design of the output filter and selection of dc link capacitor.
In control stage, close loop design and stability analysis of the current control loop
and voltage control loop is discussed.
4.2 LCL Filter design
A third order LCL filter, is used to connect the inverter to the grid, to reduce
the size of the filter components. A switching frequency of 7 kHz was selected based
on the filter size and the practical implementation of digital controller. Laplace
domain analysis of the filter is represented in the Chapter3.
32
Chapter 4. Design of Grid Connected Inverter 33
The terminal voltage Vinv contains a fundamental component and high fre-
quency components which could result in higher frequency distortions on grid
current. As LCL filter can cause the system to become unstable and it can also
trigger resonance, selection of the resonance frequency depends on the close loop
system bandwidth. Bandwidth of the system depends on the filter parameters
and the control parameters. For selection of the filter parameters an estimate of
the system bandwidth is required. Bandwidth is assumed to be 1/15th of the
switching frequency. Resonance frequency of the LCL filter is given by the eq.4.1
s
1 L1 + L2
fres = (4.1)
2π L1 L2 Cf
4.2.1 Selection of LCL Parameters
The procedure for choosing the LCL filter parameters uses the power rating
of the converter, line frequency and switching frequency as the inputs. The process
to calculate the switching ripple includes frequency domain approach rather than
the time domain approach. Detailed design of LCL filter is discussed in[4]
(En )2
Zb = (4.2)
Pn
1
Cb = (4.3)
ωb Zb
Where En is the base rms voltage, ωn is the grid frequency, and Pn is the
power rating of the converter. The resonant frequency is referred to the switching
frequency value by eq.4.4. Where the k factor represents how far the switching
frequency is from the resonance frequency ωres .
ωres = kωsw (4.4)

The ripple attenuation, passing from the converter side to the grid side, can be
calculated with the eq.4.5-4.7.
2
ig (hsw ) ZLC
= 2 − ω2 |
(4.5)
v(hsw ) ωsw L|ωres sw
ii (hsw ) 1
= (4.6)
v(hsw ) ωsw L
ig (hsw ) Z2
= 2 LC 2 (4.7)
ii (hsw ) |ωres − ωsw |
The LCL filter can be designed using the following step by step procedure.
• Select the required current ripple on the converter side. Design the inner
inductor L1 . The outer inductor can be determined as a function of L1 ,
using the index γ for the relation between the two inductances.
L1 = γL2 (4.8)
• Select the reactive power absorbed at rated conditions and determine the
capacitor value. Take x as percentage of the reactive power absorbed under
rated conditions.
Cf = xCb (4.9)
• Select the desired current ripple reduction. The ripple at attenuation, cal-
culated neglecting losses and the damping of the filter, is defined by eq.4.7
and can be rewritten considering eq.4.8 and eq.4.9 as
ig (hsw ) 1
= (4.10)
ii (hsw ) |1 + γ(1 − ax)|
2
where a = LCb ωsw
Having established the design of filter, some limits on the parameter values should
be introduced[4].
• The capacitor value is limited by the decrease of the power factor at rated
power (generally less than 5%). The power factor decrease can also be a
function of the ac sensor position.
• The total value of inductance should be less than 0.1 pu to limit the ac
voltage drop during operation. Otherwise a higher dc-link voltage will be re-
quired to guarantee current controllability, which will result in higher switch-
ing losses.
• The total value of inductance should be less than 0.1 pu to limit the ac
voltage drop during operation. Otherwise a higher dc-link voltage will be re-
quired to guarantee current controllability, which will result in higher switch-
ing losses.
• The resonant frequency should be in a range between ten times the line fre-
quency and one-half of the switching frequency, to avoid resonance problems
in the lower and upper parts of the harmonic spectrum.
If the resonance frequency is within the bandwidth of the controller then

active damping must be used but if the resonance frequency is not within the
bandwidth of the controller then choice will be passive damping [15]. Passive
damping must be sufficient to avoid oscillation, but losses cannot be so high as to
reduce efficiency. Also [14] presents the optimization of the selection of the filter
parameters.
200
Damped
Magnitude (dB)
100 Undamped
-100
-200
90
Phase (deg)
-90
2 3 4 5
10 10 10 10
Frequency (Hz)
Figure 4.1: Frequency Response of LCL Filter Under Un-damped and

Damped condition
Table 4.1: Selected values for LCL filter
Parameter Value
L1 3.2 mH
L2 1.8 mH
C 1.47 µF
rc 47Ω
4.2.2 Passive Damping
The aim of the passive damping scheme is to reduce the Q factor at the
characteristic resonance frequency eq.4.4. In this case damping is achieved by
adding a resistor in series with the capacitor. To obtain proper damping effect the
value of ωres has to be limited in the resistive region[15], as shown in the fig.4.2.
Also care must be taken that the power loss in the damping resistor should also be
limited to a small value. Fig3.1 shows the circuit for passive damped LCL filter.
[15] Discusses about the detail design of the different types of the passive damped
LCL filter. Selected values of the filter components based on the theory discussed
above are given in table4.1
Capacitive Resistive
Region Region
-20dB/decade
1/(rcC)
ωres
Figure 4.2: Characteristics of passive damping method
4.3 Current Controller Design
4.3.1 PR Controller
DPWM model
Static gain Delay effect
Inverter gain Load admiance

Iref PR Controller
T
+ m 1-s S d Gf(s) Ii
H1(S) Cpk 2 VDC
- TS
1+s
2
Figure 4.3: Current Control Loop
Fig4.3 shows the block diagram of the current control loop. Where Gf (s) is
the transfer function of the filter given by eq.3.4 Transfer function of the PWM
inverter is given by eq.3.15, which considers the effect of delay caused by digital
PWM and also the sampling algorithm. Current regulator implemented in this
paper is Proportional Resonant controller. PR controller is represented by eq.4.11.
Close loop transfer function of the current control lop is calculated by the Mason’s
gain formula.
2ξω0 s
H1(s) = Kp + Ki (4.11)
s2 + 2ξω0 s + ω02
Design of PR compensator is similar to that of PI compensator. While de-

signing it is to be considered that the current control loop is inner loop and the
response of the inner loop should be faster as compared to the outer dc voltage
control loop. In order to satisfy certain dynamic response standards such as mini-
mum peak overshoot and minimum settling time, the phase margin is maintained
in the range of 300 to 600 and the system bandwidth is maintained to about 1/15th
of switching frequency. Value of Kp is found out by the restriction maintained by
the system bandwidth. System open loop gain is equated to 0 db at the crossover
frequency of 1/15t h of switching frequency. After the value of Kp is set then the
value of Ki is adjusted in order to get the phase margin in the range of 300 to 600 .
Fig.4.4 show the bode magnitude and phase plot of the current control loop
for Iref as the input to the system. From Fig.4.4 it can be seen that for Iref as the
input the gain of the system at fundamental frequency is very high which satisfies
the requirement for low steady state error at the fundamental frequency. Fig.4.5
show the bode magnitude and phase plot of the current control loop for the grid
voltage (Vg ) as the input. It is noticeable form the fig.4.5 that the gain of the
current control loop is negligible for grid voltage as the input. If grid voltage is
considered as an external disturbance then it can be said that the disturbance
rejection is better by the use of PR controller. From Fig.4.4 it can be noticed
that the bandwidth of the current control loop is around 1/15th of the switching
frequency. Phase margin is 530 . Gain margin is 26 dB. These values satisfy the
stability criteria and also the design criteria discussed in the beginning of this
section.Selected values for stability analysis are Kp = 0.15, Ki = 600, ξ = 0.0005.
Magnitude (dB) 100
50
-40
180
Phase (deg)
-180
-360
0 1 2 3 4 5
10 10 10 10 10 10
Frequency (Hz)
Figure 4.4: Frequency Response of Current Control Loop with Iref as input
0
Magnitude (dB)
-50
-100
-150
90
Phase (deg)
-90
0 1 2 3 4 5
10 10 10 10 10 10
Frequency (Hz)
Figure 4.5: Frequency Response of Current Control Loop with Vg as input
4.3.2 Selective Harmonic Compensation
The harmonic compensator, which is connected in parallel with the tracking

regulator, is formed by several band pass filters used to resonate at the desired
harmonic frequency. Transfer function for the harmonic compensator is given by
eq.4.12
h
X 2ξ(nω0 s)
H2 (s) = Kn (4.12)
n=3
s2 + 2ξ(nω0 )s + (nω0 )2
Iref + + d
+ H1(S) + PWM
- +
Ii
H2(S)
Figure 4.6: Topology for PR + Harmonic Compensator
100
Magnitude (dB)
50
-40
90
0
Phase (deg)
-90
-180
-270
0 1 2 3 4 5
10 10 10 10 10 10
Frequency (Hz)
Figure 4.7: Frequency Response of Current Control Loop for harmonic com-
pensation
h
2ξω0 s X 2ξ(nω0 s)
GR(s) = Kp + Ki 2 2
+ Kn 2 (4.13)
s + 2ξω0 s + ω0 n=3 s + 2ξ(nω0 )s + (nω0 )2
Where n can take values 3,5,. . . h (with h being highest current harmonic
component to be attenuated). Using eq.4.11 and eq.4.12 current controller can
be represented by eq.4.13. In this project the harmonic compensator for 3rd
harmonic is implemented. Fig4.7 shows bode magnitude and phase plot of the
current control loop with the implementation of the 3rd harmonic compensator.
From the fig4.7 it is clear that the gain and phase margin both are positive and
the phase margin in the range of the 300 to 600 . Thus the transient stability of
the current control loop can be ensured.
4.3.3 Proportional Resonant Integral Controller
Conventional stationary reference frame control consist of a PR controller

to generate the inverter voltage reference. A modification to the PR controller is
done by adding an integral block as shown in fig4.8. This modification is presented
in [2]. The topology under consideration is very sensitive to the presence of the
dc offset in the inverter terminal voltage. The dc offset can be added because of
various factors such as the offsets in the A/D converter, and the sensors.
PRI
* Contoller
i dc = 0 + GI
-
+
+ +
Iref GR(s)
-
Ii
Figure 4.8: Topology of PRI controller[2]
Fig4.9 shows the bode magnitude and phase plot for the Proportional Reso-
nant Integral(PRI) controller. From the Fig4.9 it clear that the gain of the current
control loop for the frequencies below fundamental frequencies is very small. Hence
the disturbance rejection is achieved for the dc components present in the feed-
back signals. Moreover fig4.9 also depicts that the gain and phase margin of the
current control lop for PRI controller is positive 25dB and the phase margin is
54.20 , hence transient stability is also achieved. Parameters selected for stability
analysis are Kp =0.15, Ki = 600, Ki3 =600, ξ = 0.0001, Kif = 10.
Magnitude (dB) 100
50
-40
180
90
Phase (deg)
-90
-180
-270
0 1 2 3 4 5
10 10 10 10 10 10
Frequency (Hz)
Figure 4.9: Frequency Response of Current Control Loop for PRI controller
*
Vdc PI Vg(pu) Gc(s) Ii
Vdc
1 Vgrms
1/Vg(pu)
sCdc 2Vdc
Figure 4.10: Voltage loop block diagram
4.4 DC Voltage Controller Design
Outer loop is the DC voltage control loop. Response of the outer control loop
should be slower as compared with the inner control loop. To get slow response
of the outer control loop the bandwidth of the outer loop is maintained around
1/10th of the inner control loop bandwidth. Thus outer control loop will be having
slower response as compared to that of the inner control loop. Fig4.10 shows the
block diagram of the outer voltage control loop. Transfer function of the blocks
shown is derived in the previous chapter. Eq 4.14 represents the voltage controller
transfer function.
Kiv
P I(s) = Kpv + (4.14)
s
Magnitude (dB) 100
-100
-180
0
Phase (deg)
-180
-360
-1 0 1 2
Frequency 3 4 5
10 10 10 10 (Hz) 10 10 10
Figure 4.11: Frequency Response of Voltage Loop with PI controller
Proportional Integral (PI) compensator is used for the control if the outer
voltage control loop. Gain Kpv of the PI compensator is selected to get required
bandwidth. Fig4.11 shows the bode magnitude and phase plot of the voltage con-
trol loop. From the magnitude plot it can be noted that the 0dB cutoff frequency
of the outer voltage control loop is maintained around 15 Hz. Gain Kiv of the PI
compensator is selected in such a way that the phase margin of the voltage control
loop is maintained in the range of 300 to 600 . From frequency response4.11 it
can be noted that the phase margin of the voltage control loop is around 470 and
gain margin is around 38.2 dB. Both gain margin and phase margin are positive,
thus the voltage control loop is stable. Values selected for stability analysis are
Kpv =0.5, Kiv =40.
Chapter 5
Performance Analysis Through

Simulation
5.1 Introduction
The MATLAB/Simulink is used to simulate the grid connected inverter[18].

The MATLAB/Simulink blocks are used to create the system model. Mostly
simulink toolbox is used for the control blocks and sim-power system toolbox is
used for the power circuit components. Matlab coding is used for the stability
analysis and retrieving the results from the simulink models.
Table 5.1: Selected values for Simulation
Parameter Symbol Value

DC link Voltage Vi 56V
Dc link Capacitor Cdc 2200µF
Inverter side inductor L1 3.2mH
Grid side inductor L2 1.8mH
Output filter capacitor C 1.47µF
Damping resistor rc 47Ω
Grid Voltage Vg 25V
44
Chapter 5. Performance Analysis Through Simulation 45
Vdc [Vdc]
Discrete, [P] P1
Ts = 5e-005 s.
V_i [V_i]
powergui
[N] N1
[Ig]
Idc [Idc]
+
Ig
P P1
P2
- Vg + v -K- [Vg]
N g -
g1
DC Source Inverter Filter

[Vdc] Vdc
P [P]
[Vg] Vg
N [N]
[Ig] Ig
Controller
Figure 5.1: Simulink Model of grid Connected Inverter
The simulation is run in variable step mode with ode23tb (stiff/TR-BDF2)

solver having maximum step size of 0.0002 and relative tolerance of 1e−4 . Each
signal which is analyzed is saved to workspace in the format of structure with
time.
5.2 Simulation of Grid Connected Inverter
The simulation model grid connected inverter is shown in Fig 5.1. The DC
source supplies the power for to the inverter. Feedbacks are taken from the DC
bus voltage (Vi ), inverter current (Ii ) and the per unit grid voltage (Vg(pu) ). The
control block receives these feedbacks from the sensors. These feedback values are
compared with the reference signals to generate the actuation signal. Actuation
signal is then compared with the carrier wave (triangular in nature) to generate
the gate signals for the switches of the inverter. In next section the nature of the
waveforms are shown in the form of figures and are analyzed.
5.3 PR Controller
PR controller discussed in the chapter4 is implemented and various wave-

forms are plotted using Matlab. Fig5.2 represents the Inverter output voltage
(Vinv ) and inverter output current (Ii ). Fig5.2 shows that the current is sinusoidal
in nature with presence of higher order frequencies. Fig.5.5 shows the FFT anal-
ysis of the Inverter current (Ii ). From the FFT analysis it can be seen that the
current Ii consist of higher order components i.e. switching frequency components
and its side bands. Since unipolar modulation is selected, and the switching fre-
quency is 7 kHz, the component present in the current is of 14 kHz. Fig.5.3 grid
voltage (Vg ) and grid current (Ig ) and fig5.6 shows the FFT analysis of the grid
current(Ig ). Fig5.6 shows that the higher order harmonics are filtered out by the
LCL filter. Fig.5.7 shows the dc bus voltage variation. DC bus voltage has a
100Hz harmonic component, which is because of the current drawn from the dc
bus which is having dominant 100Hz component.
5.4 Harmonic Compensator
It can be seen from the fig5.6 that current Ig consist of a 3rd harmonic com-
ponent with magnitude of around 5% of the fundamental component. According
to the grid norms magnitude of the 3rd harmonic should be less than 4%. Hence
to achieve this harmonic compensators (HC) are used along with PR controller,
transfer function of tracking regulator is given by eq.4.13. The gain Ki3 Simu-
lation is performed for PR controller along with HC. Fig5.8 shows the inverter
Inverter_Voltage
100
Vinv(V)
-100
0.44 0.45 0.46 0.47 0.48 0.49 0.5
Inverter Current
5
Ii(A)
-5
0.44 0.45 0.46 0.47 0.48 0.49 0.5
Time(sec)
Figure 5.2: Inverter Voltage (Vinv ) and Inverter Current (Ii )
50
Vg(V)
-50
0.44 0.45 0.46 0.47 0.48 0.49 0.5
5
Ig(A)
-5
0.44 0.45 0.46 0.47 0.48 0.49 0.5
Time(sec)
Figure 5.3: Grid Voltage (Vg ) and Grid Current (Ig )
output current (Ii ), fig5.9 shows the grid current (Ig ). Fig5.10-5.11 shows the
FFT analysis of (Ii ) and (Ig ) respectively. From the FFT analysis it is clear that
the magnitude of the 3rd harmonic is reduced as compared to the PR controller
only.
Inverter_Voltage
100
50
Vinv(V)
-50
-100
0.44 0.45 0.46 0.47 0.48 0.49 0.5
Inverter Current
4
2
Vg(V)
-2
-4
0.44 0.45 0.46 0.47 0.48 0.49 0.5
Time(sec)
Figure 5.4: Inverter Voltage (Vinv ) and Grid Voltage (Vg )
Switching frequency
component
Figure 5.5: FFT Analysis of Inverter Current (Ii )
5.5 Proportional Resonant Integral Controller
As discussed in last chapter PRI controller is designed and the simulation is

performed for the designed values. Fig5.12 shows the inverter voltage (Vinv ) and
inverter current (Ii ) for PRI controller. Fig5.13 represents the grid voltage (Vg )
and grid current(Ig ). As can be seen from fig.5.14 the FFT analysis of the grid
current the THD is reduced as compared with the PR and HC controller, also the
Fundamental (50Hz) = 3.726 , THD= 4.50%

Mag (% of Fundamental)
100
80 5
60
40
20
0
0 500
0
0 1000 2000 3000 4000 5000 6000 7000 8000
Frequency (Hz)
Figure 5.6: FFT Analysis of Grid Current (Ig )
60
55
Vi(V)
50
45
40
0.44 0.45 0.46 0.47 0.48 0.49 0.5
Time
Figure 5.7: DC Bus Voltage (Vi )
Table 5.2: Comparison of THD for Various topologies of PR controller
Type THD
PR 4.5%
PR+HC 3.49%
PRI 2.5%
even order components are removed from the currents. Thus PRI controller gives
better performance than the normal PR and PR+HC controller.
Performance analysis of the different PR controller topologies was carried out

using simulation tool. Fig5.15 presents the results of the comparison. Simulation
100
Vinv(V)
-100
0.44 0.45 0.46 0.47 0.48 0.49 0.5
5
Ii(A)
-5
0.44 0.45 0.46 0.47 0.48 0.49 0.5
Time(sec)
Figure 5.8: Inverter Voltage (Vinv ) and Inverter Current (Ii )
Inverter_Voltage
50
Vg(V)
-50
0.44 0.45 0.46 0.47 0.48 0.49 0.5
5
Ig(A)
-5
0.44 0.45 0.46 0.47 0.48 0.49 0.5
Time(sec)
100
80
60
10
40 5
20 0
0 200 400
0
0 500 1000 1500
Frequency (Hz)
Figure 5.10: FFT Analysis of Inverter Current (Ii )


110
100
90
80
10
70
60
5
50
40
30 0
0 100 200 300 400 500
20
10
0
0 500 1000 1500
Frequency (Hz)
100
Vinv(V)
-100
0.44 0.45 0.46 0.47 0.48 0.49 0.5
Inverter Current
5
Ii(A)
-5
0.44 0.45 0.46 0.47 0.48 0.49 0.5
Time(sec)
Figure 5.12: Inverter Voltage (Vg ) and Inverter Current (Ii )
was carried out for different power levels ranging from 65W to 135W and the THD
of grid current was recorded. From the results it can be seen that the THD of
current using PR controller is in the range of 4-5%, for PR and HC together it
is in the range of 3-4%. Whereas in case of PRI controller the THD is least in
the range of 2-3%. Hence it can be inferred that the PRI controller gives better
performance as compared with the PR or PR+HC controllers.
Inverter_Voltage
50
Vg(V)
-50
0.44 0.45 0.46 0.47 0.48 0.49 0.5
5
Ig(s)
-5
0.44 0.45 0.46 0.47 0.48 0.49 0.5
Time(sec)

110
100
90
80
5
70
4
60 3
50 2
40 1
30 0
0 100 200 300 400 500
20
10
0
0 500 1000 1500
Frequency (Hz)

4.5
3.5
3
THD (%)
2.5
1.5
1 PR
PR+HC
0.5
PRI
0
60 70 80 90 100 110 120 130 140
Power(W)
Figure 5.15: Performance Comparison of Various PR Controller Topologies

Chapter 6
Development of Laboratory
Prototype
6.1 Introduction
In this chapter, the implementation of a single phase dc-ac converter with

inductor current and voltage control will be discussed. The parameters of design
are presented with the selection of components required for a converter. The
design algorithm on MATLAB platform is developed to reduce the reworking time
of prototype development. The close loop controller algorithm is implemented in
discrete system on low cost digital controller (TMS320F28027)[19].
6.2 Inverter Design
IGBT with body diode selected as power semiconductor switch for inverter,
since inverter operate at lower switching frequency than that of DC-DC converter
and also conduction loss are less. For safety purpose the forward block voltage
54
Development of Laboratory Prototype 55
Figure 6.1: Block Diagram of Laboratory Setup
of switch is chosen double the times of DC bus voltage. Hence forward block in
voltage required is around 200V, but 200V switches are not standard value. The
standard value available is 600V. The peak current through the switch will be the
peak AC line current of single-phase inverter which is around 10A but practically
available lowest current rating of the switch is 600V/24A, hence HGTG30N60C3D
IGBT is used in prototype.
6.3 Control and Driver Circuit
The driver circuit part is depicted in the fig.6.1. It consists of PWM gen-
eration block, buffer, optical isolator and driver. The control circuit consist of
sensors, signal conditioning circuit and digital controller. To provide power to all
these circuits regulated power supplies are required.
Voltage
Regulator
230V IC
AC
C1 C2 C3 DC
1100uF 0.01uF 0.01uF
50V cer cer
Figure 6.2: Power Supply Circuit
6.3.1 Power Supply
The main purpose of power supply is to supply DC Power to the various ICs
used in control circuit and gate driver circuit. The Toroidal transformer is used
to step-down the 230V to 18V and converted into DC by diode bridge rectifier.
The power supply required by the buffer IC is +5V, optical-isolator IC and

driver IC is +15V., Op-amp is ±15 V, current sensor +3.3V. Voltage regulator
IC is chosen according to the required voltage level. Buffer requires +5V hence
regulator IC 7805 is used and 7815 is used to provide +15V which is required
for both optical-isolator IC and driver IC. For -15V which is required by op-amp,
regulator IC 7915 is used. To get a proper output from the ICs, ripple free rated
voltage (Vcc ) should be provided. To ensure this EMI filter capacitors should be
connected at the output of the each power supply. 3.3V supply for current sensor
is derived from +15v bus by using adjustable regulator IC LM337. The basic
power supply circuit is shown in fig.6.2
6.3.2 Buffer
The output of DSP should be converted to TTL compatible logic to drive the
optical coupler hence we need a level shifter or buffer to convert the 3.3V to TTL
compatible. A buffer is also has more fan-outs compared to DSP. A buffer is a
single input-output device having gain1. Buffer IC HD74LS04 is used for isolation
purpose. A +5V dc supply is required for the buffer. The top view of the buffer
IC is shown in fig.6.3
Figure 6.3: Top view of IC HD74LS04
6.3.3 Optical-isolator
The optical-isolator is used to isolate the control signal from the power signal.
IC TLP-250 has been used for the purpose of isolation. TLP250 has a capability
to drive MOSFET/IGBT. But in this prototype it acts only as a optical isolator.
It consists of a light emitting diode and an integrated photo-detector which is used
for isolation. Its maximum frequency of operation is 25 kHz. Also a 0.1µF bypass
capacitor is required to be connected between pins 8 and 5 i.e. Vcc and ground.
The top view of an opt-isolator IC is shown in fig.6.4
6.3.4 Gate driver
The gate driver circuit is the interface between the control and power circuit.
The driver circuit amplifies the control signals to the levels required to drive the
power switch. The driver circuit has significant power capabilities compared to
Figure 6.4: Top view of TLP250
+5
From
DSP
1 14 +15
+15 Dbs
2 13
1k 1 8
3 12
2 TLP Cf
4 7 Cbs
11 250 5k
7404 3 6 1 +
5 10 8
4 2 IR 7 -
9 5
6 Cf 2111
3 6
7 8 LO
4 5
Cf=0.01uF GND
HO
VS
Figure 6.5: Circuit diagram of driver circuit
control circuit. For proper turning ON and OFF the switch the driver circuit
components should be properly designed. The gate driver used in the project is
IR2111. It is used to provide HO and LO pulses for upper and lower switch of
single leg of inverter.
It also generates built in dead band of 700ns. Hence no additional circuitry

is required for generating dead band. The features of driver IC IR2111 are:
• Floating channel designed for bootstrap operation

• Fully operational to +600V
• Tolerant to negative transient voltage
• dV/dt immune
• Gate drive supply range from 10 to 20V
• CMOS Schmitt-triggered inputs with pull down
• Internally set dead-time
• Under voltage lockout for both channels
• Matched propagation delay for both channels
• High side output in phase with input
• Also available LEAD-FREE
6.3.4.1 Bootstrap Component Selection
The bootstrap capacitor is done based on the following calculation. The val-
ues are taken from the data sheet of IR2111, HGTG30N60C3D. Also the equations
and values are arrived based on QG = 180nC.
f = 7 kHz
IQBS(M AX) = 100 µA
ICBS(LEAK) = 0 (as Tantalum capacitor is used.)
QL G = 5nC (600V IC’s)
Vcc = 15V
VF = 1.5 V
VLS = 1.7V
VM IN = 10 V
IQBS(M AX) ICBS(LEAK)
2[2QG + f
+ QLS + f
]
C≥ (6.1)
Vcc − Vs − VLS − VM IN
C ≥ 0.75871µF
C = 0.75871µF × 15
C = 6.3214 µF Selecting higher value of capacitor hence 47µF, 35V is used.
The Bootstrap diode is selected based on the following calculations. The

bootstrap diode (DBS ) needs to be able to block the full power rail voltage, which
is seen when the high side device is switched on. It must be a fast recovery device
to minimize the amount of charge fed back from the bootstrap capacitor into the
Vcc supply.
VRRM = Power rail voltage

QBS = 0.545µC
max trr = 100ns
IF = QBS × f
Boot strap diode
QBS = 0.545 µC.
IF = 2.18 mA.
Therefore selecting an ultra fast diode UF4007,with VRRM = 1000 V, IF = 1 A
and max trr = 75 nsec.
6.3.5 Voltage Sensor Peripheral Selection
The circuit diagram for the Hall Effect voltage sensor is shown in the fig.6.6.
In the present experimental setup peripheral to measure 100V. The transducer’s
optimum accuracy is obtained at the nominal primary current. As far as possible
Ri should be calculated so that the nominal voltage to be measured corresponds
to a primary current of 10mA. Thus input resistance is calculated by eq.6.2 Max-
imum output voltage corresponding to 100V is considered as therefore the output
resistance is calculated by eq.6.4
-15 V +15 V +HT
Rvi
ii
+ + DC voltage
io
- LV 25-V Vi
M -
Output Rvo
Voltage
GND - HT
Figure 6.6: Circuit for Voltage Sensor
100V
Rvi = = 10kΩ (6.2)
10mA
2500
CTratio = = 2.5 (6.3)
1000
3V
Rvo = = 120Ω (6.4)
25mA
6.3.6 Current Sensor
The current sense circuit feeds its measurement to the DSP. The current
sensor WCS2720 is used in the feedback process. This sensor has maximum pass
current of 30A dc and having a sensitivity of 64 mV/A. The WCS2720 provides
economical and precise solution for both DC and AC current sensing in industrial,
(a) (b)
Figure 6.7: Hall Effect Current Sensor
commercial and communication systems. The WCS2720 consists of a precise,

low-temperature drift linear hall sensor IC with temperature compensation cir-
cuit and a current transformer with 0.4mΩ typical internal conductor resistance.
This extremely low resistance can effectively reduce power loss, operating tem-
perature and increase the reliability greatly. Applied current flowing through this
conduction path generates a magnetic field which is sensed by the integral hall
IC and converted into a proportional voltage. The terminals of the conductive
path are electrically isolated from the sensor leads. This allows the WCS2720
current sensor to be used in applications requiring electrical isolation without the
use of opt-isolators or other costly isolation techniques and makes system more
competitive in cost.
6.3.7 Signal Conditioning
[20]The low level bipolar voltage signals available on the output of the voltage
transducer cannot be give to the analog to digital converter (ADC) channel of the
Aenuator Level Shier Precision Recﬁer

3.2kΩ
10kΩ
- 10kΩ - Output
TL064 - TL064
+ TL064 + D
+ ZD
-1.5V 10kΩ
Figure 6.8: Attenuator, Level Shifter and Precision rectifier
DSP directly because the ADC is unable to read negative voltages. And the
maximum voltage that can be read by the ADC is 3.3V. Thus the signal is to be
made compatible with the ADC circuitry. First the signal is scaled using the op-
amp based attenuators to the voltage range of ±1.65 V, then using a level shifter
a dc offset voltage of 1.65V is added to the circuit. To get a constant dc voltage of
-1.65 V adjustable voltage regulator LM337 is used. The precision rectifier avoids
the negative excursion of the voltage. A zener diode with cut in voltage of 3.3 V
is used to avoid the any over voltage above 3.3V. In this way the ADC channel
of the DSP is protected against the over voltage and the negative excursion. This
circuit is given in the fig.6.8.
6.3.8 Synchronizing Circuit
The point of common coupling (PCC) voltages may be distorted and may also
cause distortions in the output current as grid voltage is used for the generation of
the reference signal of the inverter current. Thus to get a distortion free waveform
a op-amp based 2nd order filter is designed. For a cutoff frequency of 59 Hz. The
phase shift added by the low pass filter is corrected by using a all pass filter. Signal
Low Pass Filter Phase Corrector

1.5k
2.2k
1.5k
- 1.5k
Input 274k 274k TL064 - Output
+ 100n TL064
+
100n 100n
47k
Figure 6.9: Synchronizing Circuit
obtained from the all pass filter is passed through the signal conditioning circuit.
So as to make it compatible with the ADC channels.
6.4 Sampling Algorithm
Synchronization of sampling with the switching is should always be maintained[13][12][21].

From the fig6.10 we can understand the requirement of synchronization. If the
sampling is done when the value of counter is equal to Cpk or equal to zero, then
the value sensed will be the average value. As we can see from the fig. the prob-
ability of switching is very less when the counter is equal to zero or Cpk . Thus
this algorithm eliminates the requirement of filters between sensor and controller.
User guides for TMS320F28027 were used for the actual implementation of this
sampling algorithm in the programming.[19]
6.5 Major Design Issues and Recommendation
6.5.1 EMI Noise Problem
With ref to the block diagram6.1 of the hardware prototype. DSP (digital
signal processor) generates gate signals which are transferred to the buffer IC.
Cpk
m(t)
0
(a)
Vdc
-Vdc
(b)
I_load
(c)
Ts
Figure 6.10: (a)Counter Value Variation, (b)Inverter Output Voltage, (c)Load

Current Variation
Figure 6.11: Gate signals from DSP [Ch1: 2V/div],Driver Output Voltage
[CH2: 5V/div]
Electromagnetic induction was experienced in the DSP signals. Circuit was ana-
lyzed and the reasons for the EMI were found out. Source for the EMI was from
the power circuit. High frequency current flow in the power circuit because of
the PWM. There was no shielding provided to the wires carrying controls signals.
Hence noise was getting induced in the control signals. This is visible from the
Fig.6.11 (experimental result)[22]. Also there were some flows in the printed cir-
cuit board (PCB) design. In the next sub section solutions to these problems are
discussed.
ATTENUATION (DB)
a. 100 100 0
b. 100 1 M
0
c. 100 1 M 27
100 1 M
d. 13
e. 100 1 M 13
`
f. 100 1 M 28
80
g. 100 1 M
Figure 6.12: Various Shielding Options
6.5.2 Shielding Control Signals from EMI
Presents different ways of shielding the control signals. The magnetic field
shielding properties of various cable configurations are measured and compares in
[17]. Test results are shown in fig6.12. Since in our system ground is required at
both the ends hence configuration (f) is suitable which has attenuation of 28 dB
for the magnetic field induction.
Capacitor Capacitor
Power Bus
Ground Bus
C1 IC
IC
C2
Pwr Gnd
IC
Not
recommended Recommended
(a) (b)
Figure 6.13: Power Bus Decoupling Capacitor Placement
6.5.3 PCB layout considerations
Also improper PCB design is responsible for induction of noise into the sys-
tem. Hence some good and bad practices for PCB design are discussed in this
section.
6.5.3.1 Power bus Decoupling
Fig6.13(a) shows two different ways of placing the power bus decoupling
capacitor. Decoupling capacitor should be placed in such a way that the electrical
distance of the capacitor should be least from the terminals of the IC. Mechanical
distance of the capacitor C2 is less as compared to that of capacitor C1 but as
depicted in fig6.13(a) the electrical distance of the C1 is lesser as compared to that
of C2 . Hence position of C1 is recommended over C2 . Fig6.13(b) presents another
issue in placing of the decoupling capacitor. In the non recommended circuit the
length of the path from capacitor terminals to the IC pin is longer as compared
with the one in recommended circuit. As the length is more parasitic inductance
of the path increases, which defeats the purpose of the decoupling capacitor.
6.5.4 Problem with Buffer
Buffer IC 74HCT04 is used to convert the DSP output 3.3V to TTL com-
patible logic to drive TLP 250. The five volt power supply IC heats up lot. HCT
family is not compatible with DSP and TLP250. It draws a huge current. Al-
though the purpose of IC and its number is same it creates problem. The problem
is solved by using 74LS04 which Transistor based. The 7404 is same IC but it has
many logic families like LS (Low-power Schottky), HCT (High speed, compatible
logic levels to bipolar parts), HC (High-speed CMOS) and etc. In these family only
74LS family is to be used as buffer or level shifter. Moreover instead of 74LS04
we can use 74LS07 or purpose made level shifters like 74LVC4245 which specially
designed for 3.3V to 5V conversion.
6.5.5 Driver Circuit Peripheral Consideration
Following guidelines represent good practice in control IC circuits and war-

rant attention regardless of the observed latch-up safety margin[23][21].
6.5.5.1 Minimize the effect of parasitic components
Use thick direct tracks between switches with no loops or deviations. Avoid
interconnect links this can add significant inductance. Reduce the lead inductance
by reducing the package height above PCB. Consider co-locating power switches
to reduce track length.
Vs
Lo
COM
LOAD RETURN
Figure 6.14: Recommendation for Minimization of Parasites
6.5.5.2 Reduce control IC exposure
Connect Vs and com as shown in the fig.6.14 minimize the practices in the
driver circuit by using short and direct tracks. Locate the control IC as close as
possible to the power switch.
6.5.5.3 Improve local decoupling
Improve bootstrap capacitor (Cb ) by using at least one low ESR capacitor in
parallel with the Cb , if not then the capacitors like tantalum capacitor should be
used as a bootstrap capacitor. Connect decoupling capacitors directly across the
recommended pins.
Vb
Vb
Vs
Vs
Vcc Vcc
co co
m m
(a) (b)
Figure 6.15: Placement of Decoupling Capacitor (a)Recommended (b)Not
Recommended
Dbs Dbs
Cbs
Vcc Vb Vcc Vb
R R
Ho Ho
IR2111
IR Cbs IR2111
IR
21 21
11 11
Vs Vs
(a) (b)
Figure 6.16: Placement of Bootstrap components (a)Recommended, (b)Not

recommended
MCB
DC bus
capacitor
Current
Sensor
L1
Inverter
Driver
rc C
Signal L2
conditioning
Voltage
sensor
Controller
Power
MCB
Supply
Torroidal Interfacing
transformer Transformer
Figure 6.17: Experimental Setup Photograph
6.6 Performance Analysis of Laboratory proto-

type
6.6.1 Steady State Operation
Performance of the grid connected single phase inverter prototype is dis-

cussed in this section. Fig6.18 shows the Inverter output voltage (Vinv ) and in-
verter output current (Ii ), from the figure it is clear that the current has higher
order harmonic components. These components are filtered out by the LCL filter.
Fig6.19 shows the current at output of the LCL filter. Higher order harmonic com-
ponents are absent in the LCL filter output. Fig6.22 presents the FFT analysis of
the Grid current (Ig ), it can be observed from the FFT analysis that the amount
of the lower order harmonics are less and overall THD obtained is around 11%.
Position of the current sensor is responsible for the power factor of the current
that is being injected into the grid. In the present case the current sensor is placed
on the input of filter. Hence the current at the input of filter is maintained in
phase with the grid current as per unit grid voltage is taken as the reference for
generation of Iref . The reactive power required for the inductive components like
filter inductors and the isolation transformer is to be supplied by the grid. Thus
the unity power power factor could not be maintained at the PCC. Fig6.21 shows
the grid voltage (Vg ) and grid current(Ig ), which makes it clear that the current
is lagging the grid voltage with some small angle.
Fig 6.23 shows the DC bus voltage and the current supplied by the DC bus
to the inverter. It is clear that the voltage control loop operation is stable and it
is following the reference voltage set point of 56V. The DC bus current has the
dominant component of 100 Hz. This component is because of the output current
of the inverter which is tried to be maintained at 50 Hz by the PR controller of
the current control loop.
6.6.2 Transient Operation
Fig6.24 shows the transient response of the inverter. At the ↓ instant, inverter
is connected to the grid. It is clear from the figures that the settling time of the
system is very small. Response reaches steady state in around 2 cycles. This
response validates the frequency domain analysis done during the designing of
current controller voltage controller gains. Digital PWM in double update mode
Figure 6.18: Inverter Output Voltage(Vinv ) [CH1: 50V/div] and Current (Ii )
[CH2:5A/div]
Figure 6.19: Current at the output of filter [CH2:5A/div]
Figure 6.20: Grid Current(Ig ) [CH2: 940mA/div]

Figure 6.21: Grid Voltage (Vg ) [CH1: 250V/div] and Grid Current (Ig ) [CH2:
940 mA/div]

110
100
90 10
80 8
70 6
60
4
50
2
40
0
30 0 5 10 15
20
10
0
0 5 10 15 20 25
Harmonic order
Figure 6.22: FFT Analysis of Grid Current Ig
Figure 6.23: DC bus voltage(Vi ) [CH1: 25V/div] and current(Idc ) [CH2: 1A/-
div]
Figure 6.24: Transient Response: Inverter Voltage [CH1:50V/div] and In-

verter Current [CH2: 10A/div]
Figure 6.25: Transient response: Grid Voltage [CH1: 250V/div] and Grid
Current [CH2: 940mA/div]
is implemented in the laboratory prototype. Thus the advantage of double update

mode for good transient response is validated.
Fig6.26 compares the THD of the grid current obtained from simulation and
experimental results. In case of simulation the gird current THD is almost constant
and is around 2-3%. Whereas the experimental results show that the THD values
are more when the power transferred is less, when the power transferred increases
the THD values stabilise to around 11%. There is a variation in the THD values
of the grid current with variation in power transferred to the grid. Reasons for
variation in THD for experimental results could not be found out, this problem
can be investigated in future, it is also reported in the future scope.
18
Simulation
16 Practical
14
12
THD(%)
10
2
20 25 30 35 40 45 50 55 60 65 70
Power(W)
Figure 6.26: Comparison of Simulation and Experimental Results

Chapter 7
Conclusion and Future Scope
7.1 Conclusion
This project presented the design, analysis and realization of single phase grid
connected inverter. Operation of grid connected inverter is explained. Modelling
of different components of grid connected inverter is discussed.
It is concluded that in double update mode od digital PWM the modulator

phase lag is reduced by one half of the modulation period. This property can give
significant benefit in terms of the achievable speed of response, for any controller
built on top of the digital modulator.
As discussed the damping scheme used is resistive damping which calls for
the power loss. It was observed that the system efficiency is around 74%. Main
cause for the reduction in the efficiency is the power loss in the damping circuit.
To reduce the losses in the damping circuit active damping is to be implemented.
A comparative performance analysis between different PR controller topolo-

gies is presented. It was concluded that out of the three discussed PR controller
77
Bibliography 78
topologies, PRI controller gives best performance. It was verified by simulation

that the PRI controller eliminates the dc components in the grid current and gives
THD values in the range of 2-3% which are better than the THD values of PR con-
troller (3-4%) and PR+HC controller (4-5%). Experimental results do not show
the same performance as that of the simulation. Variation in THD of the grid cur-
rent was noted with increase in power transferred. In case of experimental results
grid current has THD of 11.84% when power transferred is 65W. Reasons for the
variation in THD could not be found out, this phenomenon can be investigated in
future.
7.2 Future Scope
In this project LCL filter with passive damping is used which results to
power loss in the damping resistor. Future research can be carried out in the field
of actively damping the resonance caused due to LCL filter. Thus improving the
system efficiency.
Variation in THD of grid current with respect to the power transferred was
found out in the experimental results, reasons for this variation to be investigated
in future.
Transformer is used for interfacing the inverter with grid. It was observed
during laboratory prototype development that the transformer parameters are
changing the close loop response of the system. Hence systematic design of the
transformer to be done and mathematical model of the same to be included in the
design process of close loop controllers.
Other topologies of the PR controller can be searched and investigated for

getting better THD of the current that is being injected into the grid.
Bibliography
[1] J. Kim H. Cha, T. Vu. Design and control of proportional resonant controller
based photovoltaic power conditioning system. Energy conservation congress
and exposition, pages 2198–2205, 2009.
[2] V. John A. Kulkarni. Mitigation of lower order harmonics in a grid-connected

single-phase pv inverter. IEEE Transcations on Power Electronics, 28(11):
5024–5037, November 2013.
[3] F. Blaabjerg S. B. Kjaer, J. K. Pedersen. A review of single phase grid

connected inverters for photovoltaic modules. IEEE Transaction in Power
Electronics, 72(12):4477–4479, December 2001.
[4] S. Hansen M. Liserre, F. Blaabjerg. Design and control of an lcl filter based
three phase active rectifier. IEEE Transactions on Industry Applications,, 41
(5):4477–4479, September/October 2005.
[5] J. Matas L. G. de Vicuna J. M. Guerrero M. Castilla, J. Miret. Linear

current control scheme with series resonant harmonic compensator for single
phase grid connected photovoltaic inverters. IEEE Transactions on Industrial
Electronics,, 55(7):2724–2733, July 2008.
[6] J. Matas L. G. de Vicuna J. M. Guerrero M. Castilla, J. Miret. Control

design guidelines for single phase grid connected photovoltaic inverters with
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Electronics, 56(11):4492–4501, November 2009.
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monic compensation control for a single phase active power filter with high
harmonic rejection. IEEE Transactions on Industrial Electronics, 56(8):3117–
3127, August 2009.
[8] J. M. Guerrero X. Zang, J. W. Spencer. Small signal modeling of digitally

controlled grid connected inverters with lcl filters. IEEE Transactions on
Industrial Electronics,, 60(9):3117–3127, September 2013.
[9] Blaabjerg U. Borup M. Liserre R. Teodorescu, F. A new control structure

for grid connected pv inverters with zero steady state error and selective
harmonic compensation. Applied power electronics conference and exposition,
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[10] C. Wessels J. Dannehl and F. W. Fushs. Limitations of voltage oriented pi

control of grid connected pwm rectifiers with lcl filter. IEEE Transactions on
Industrial Electronics, 56(2):380–388, Feb. 2009.
[11] F. M. L. L. De Belie A. P. VandenBossche D. M. Van de Sype, K. De Gusseme

and J. A. Melkebeek. Small signal z- domain analysis of digitally controlled
converters. IEEETransaction on Power Electronics, 21(2):470–478, March
2006.
[12] A. P.VandenBossche J. A. Melkebeek D. M. Van de Sype, K. De Gusseme.

A sampling algorithm for digitally controlled boost pfc converters. IEEE
Transaction on Power Electronics, 19(3):649–657, May 2004.
[13] P. Mattavelli S. Buso. Digital control in power electronics. Morganand Clay-

pool Publishers, 2007.
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[14] V. John P. Channegowda. Filter optimization for grid interactive voltage

source inverters. IEEE Transactions on Industrial Electronics, 57(12):4106–
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[15] T. Tang F. Blaabjerg W. Wu, Y. He. A design method for the passive damped
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Industrial Electronics,, 60(10):4339–4350, October 2013.
[16] Ieee standards for interconnecting distributed resources with electric power
systems. IEEE Std 1547, 2013.
[17] Characteristics of the utility interface for photovoltaic systems. IEC 61727
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[23] International rectifier, design tip 98-2a. .

Appendix A
Simulation Subsystem
Figure A.1: Inverter sub system
82
Appendix A. Appendix Title Here 83
Figure A.2: Filter sub system
num(z)
56 num(z)
z-1 -K-
z2 -1.999z+1 >= 1
PI
PR P
-1 2142
1 Vdc 1
2 -1
Vg
>= 2
N
3 Ig
Figure A.3: Controller sub system

Appendix B
Hardware Circuit Diagrams
Port:J1
Port:J6
ADCIN1 ePWM1A
Vdc J1.6 J6.1 A
ADCIN4 ePWM1B
Vg J1.8 J6.2 B
ADCIN2 Port:J5
Ii
J5.5
J3.1 Port:J3 J3.2
DSP
GND
Figure B.1: Circuit for DSP
84
Appendix B. Hardware Circuit Diagrams 85
+5
From
DSP
ePwm1 A/B 1 14 +15
+15 Dbs
DSP gnd
2 13
1k 1 8
3 12
2 TLP Cf
4 7 Cbs
11 250 5k
7404 3 6 1 +
5 10 8
4 2 IR 7 -
9 5 Cf
6 2111
3 6
7 8 LO
4 5
Cf=0.01uF GND
HO
VS
Figure B.2: Driver Circuit
+HT
10 Ω
HO
1 kΩ
Vs
A’
10 Ω
LO
1 kΩ
Gnd
-HT
Figure B.3: One Leg for Inverter
-15 V +15 V +HT
Rvi
ii
+ + DC bus
io
- LV 25-V voltage
Vdc -
M
Output R vo
Voltage
GND - HT
Figure B.4: DC voltage Sensor Circuit
Figure B.5: current Sensor
Precision Recer 1 Precision Recer 2
- -
TL064 TL064
ADCINA4 From Current
Vdc1 + D + D ADCINA1
ZD Sensor ZD
Figure B.6: Precision Rectifier

Low Pass Filter Phase Corrector

1.5k
2.2k
1.5k
- 1.5k
274k 274k TL064 -
+ 100n TL064
Vg2
+
Grid 100n 100n
47k
230/9V
Aenuator Level Shier Precision Recer

3.2 K
10 K
10 K
Vg2 - 10 K - 1N4148
TL064 - TL064 ADCINA2
+ TL064 + D
- 1.5 V ZD
10 K +
Figure B.7: Synchronizing Circuit
100Ω
Figure B.8: Circuit for LM337

Appendix C
DSP Program
89

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Contents

2 Grid Connected Inverter 10

2.4.2 Predictive Current Control . . . . . . . . . . . . . . . . . . . 15

3 Modeling and analysis 23

4 Design of Grid Connected Inverter 32

5 Performance Analysis Through Simulation 44

6 Development of Laboratory Prototype 54

6.3.4 Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7 Conclusion and Future Scope 77

B Hardware Circuit Diagrams 84

The available sources for distributed power generation provide power in dc

A prototype of generic grid connected inverter is designed and developed

For current control application traditionally Proportional Integral (PI) con-

2.1 Basic Circuit for Grid connected Inverter . . . . . . . . . . . . . . . 11

3.1 Grid Connected Inverter Through LCL Filter . . . . . . . . . . . . 24

4.1 Frequency Response of LCL Filter Under Un-damped and Damped

4.11 Frequency Response of Voltage Loop with PI controller . . . . . . . 43

5.1 Simulink Model of grid Connected Inverter . . . . . . . . . . . . . . 45

6.1 Block Diagram of Laboratory Setup . . . . . . . . . . . . . . . . . . 55

6.19 Current at the output of filter [CH2:5A/div] . . . . . . . . . . . . . 73

A.1 Inverter sub system . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

B.1 Circuit for DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

1.1 Summary of Grid Standards . . . . . . . . . . . . . . . . . . . . . . 3

4.1 Selected values for LCL filter . . . . . . . . . . . . . . . . . . . . . . 36

5.1 Selected values for Simulation . . . . . . . . . . . . . . . . . . . . . 44

ADC Analog to Digital Converter

1.1 Motivation for Grid Connected Inverter

The global energy consumption is rising and increasing attention is paid

The price of PV modules was in past a major contribution of these systems.

General off-grid solar PV system requires energy storage system, as solar

1.2 Specification, Demands and Standards

Table 1.1: Summary of Grid Standards

Issue IEC61727 IEEE1547

1.3 Literature Review

J. Matas, L. G. de Vicuna, J. M. Guerrero, this paper gives a systematic design

[8] “Small signal modeling of digitally controlled grid connected inverters

[2] “Mitigation of lower order harmonics in a grid connected single phase PV

[1] “Design and control of proportional resonant controller based photovoltaic

[10] “Limitations of voltage oriented PI control of grid connected PWM rec-

[11] “Small signal z- domain analysis of digitally controlled converters,” D.

[12] “A sampling algorithm for digitally controlled Boost PFC converters,”

[13] “Digital Control In Power Electronics,” S. Buso, P. Mattavelli, Thiss

[14] “Filter optimization for grid interactive voltage source inverters,” P.

In single phase systems, grid synchronization can be carried out by filtering

1.4 Research Objective

This project aims to a design and implementation of grid connected single

1.5 Outline of Thesis

In Chapter 1 the motivation for grid connected system and specification,

presents the performance analysis of the inverter through simulation. Chapter

Grid Connected Inverter

2.2 Voltage Source Inverter

Figure 2.1: Basic Circuit for Grid connected Inverter

2.2.1 Fundamental Components

The ideal dc voltage source Vi at the input, in practice are approximately

The power switches are represented by conventional IGBT symbol. The

In this chapter the load is considered as the series connection of a resistor

2.3 Operation Of Grid Connected Inverter

2.3.1 Unity Power Factor (Rectifier)

Figure 2.2: Operation in Unity Power Factor Mode (rectifier)

2.3.2 Unity Power Factor (Inverter)

Figure 2.3: Operation in Unity Power Factor Mode (inverter)

2.3.3 Leading Power factor

Figure 2.4: Operation in Leading Power Factor Mode

2.3.4 Lagging Power factor