6468
8, AUGUST 2017
Iterative Learning Controller With Multiple
Phase-Lead Compensation for Dual-Mode
Flyback Inverter
Hyosin Kim, Student Member, IEEE, Jin S. Lee, Member, IEEE, Jih-Sheng Lai, Fellow, IEEE,
and Minsung Kim, Member, IEEE
Abstract—This paper proposes an iterative learning control
(ILC) scheme for a dual-mode flyback inverter operating in both
discontinuous conduction mode (DCM) and continuous conduc-
tion mode (CCM). In dealing with more than 200-W power ap-
plications, the dual-mode flyback inverter takes advantage of both
DCM and CCM operations. However, it is difficult to control the
output current because the system gain is quite low in DCM and
the system transfer function has a right-half plane zero in CCM. To
overcome the problems occurring in DCM and CCM operations,
we propose an ILC scheme with multiple phase-lead compensa-
tion. The ILC is proposed to achieve accurate reference tracking
and to reject periodic disturbances. The multiple phase-lead com-
pensation technique is then employed to compensate for the effect
of different system dynamics. As a theoretical result, we derive the
asymptotic stability of the closed-loop system. We also performed
the numerical simulations and experimental tests to validate the
proposed control approach.
Index Terms—Continuous conduction mode (CCM), discontin-
uous conduction mode (DCM), nominal duty, single-stage inverter,
switching linear systems.
I. INTRODUCTION
HE distributed renewable energy systems are recently in-
T troduced and widely accommodated to reduce greenhouse
gas emissions and to overcome the inherent limitations of cen-
tralized power plants [1]. Among the distributed energy systems,
there are small/medium energy systems such as photovoltaic
panels [2], [3] or thermoelectric power modules [4] that generate
electrical energy from primary energy sources. These systems
Manuscript received June 21, 2016; accepted September 22, 2016. Date
of publication September 29, 2016; date of current version March 24, 2017.
This work was supported in part by the Ministry of Science, ICT, and Fu-
ture Planning, Korea, under the “ICT Consilience Creative Program” IITP-
R0346-16-1007 supervised by the Institute for Information and Communica-
tions Technology Promotion and in part by the POSTECH Basic Science Re-
search Institute Grant. Recommended for publication by Associate Editor L.
Corradini.
H. Kim is with the Department of Electrical Engineering, Pohang University
of Science and Technology (POSTECH), Pohang 37673, South Korea (e-mail:
foruever@postech.ac.kr).
J. S. Lee and M. S. Kim are with the Department of Creative IT Engineering,
Pohang University of Science and Technology (POSTECH), Pohang 37673,
South Korea (e-mail: jsoo@postech.ac.kr; redtoss@postech.ac.kr).
J.-S. Lai is with the Future Energy Electronics Center, Virginia Polytechnic
Institute and State University (Virginia Tech), Blacksburg, VA 24061 USA
(e-mail: laijs@vt.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2016.2614602
0885-8993 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO.
are combined with the grid-connected inverters to deliver the
generated electrical energy to the utility grid. Recently, using
the module integrated converter (MIC) [5]–[16] in the inverter
stage becomes popular because it enables individual operation
of each module such as photovoltaic panel and reduces power
losses caused by the mismatch between modules. In addition,
it allows ease of maintenance because it prevents the system
malfunction due to a single point of failure and provides “plug
and play” features.
Among the single-phase MICs, the single-stage flyback in-
verter with unfolding circuitry is considered to be the most
attractive due to its low cost, small size, and high conversion
efficiency. Its operation can be classified into two modes: dis-
continuous conduction mode (DCM) and continuous conduc-
tion mode (CCM). Flyback inverter that operates in DCM has
been widely used because its output current is easy to control
[13]–[19]. However, it suffers from high switching loss and high
voltage stress as the rated power becomes higher. At the high
rated power level, flyback inverter operating in CCM is better
in efficiency, less in voltage stress, and easier to design a filter
than that operating in DCM [8], [12], [20]. But it requires high
magnetizing inductance and large-size transformer. To manage
high power capacity with small-size transformer, we need to use
a flyback inverter operating in both DCM and CCM operations,
but it becomes difficult to control the output current. In DCM,
the system suffers from low system gain because the magnitude
of the system transfer function is small and nearly constant.
In contrast, in CCM, the system gain is relatively high but the
transfer function has a right-half plane (RHP) zero that can cause
the system to be unstable when the inverter is combined with a
high-gain feedback controller.
To overcome the aforementioned problems, we propose the
use of iterative learning control (ILC) scheme with multiple
phase-lead compensation in this paper. The ILC algorithm has
been widely used as an effective solution to track a periodic
signal and eliminate the periodic disturbances in the dynamic
systems [21]–[25]. It iteratively adjusts the current control in-
puts using the information obtained from the previous trial, and
consequently generates a series of control inputs such that the
tracking errors converge to zero. However, if the ILC is applied
by itself, different system dynamics may severely degrade the
ILC system performance. Thus, the multiple phase-lead com-
pensation technique is mainly used to compensate for the effect
KIM et al.: ITERATIVE LEARNING CONTROLLER WITH MULTIPLE PHASE-LEAD COMPENSATION FOR DUAL-MODE FLYBACK INVERTER 6469

Fig. 1. Circuit diagram of single-stage flyback inverter.

of different system dynamics. We model the dual-mode fly-

back inverter as a discrete-time linear switching system, and
derive asymptotic stability of the closed-loop system with the
proposed control scheme. We performed simulation and exper-
imental tests to validate the proposed control scheme.
This paper is organized as follows. In Section II, we introduce
the modeling of the dual-mode flyback inverter. In Section III,
we present the proposed control scheme and derive the asymp-
totic error convergence of the closed-loop system. In Section IV,
we present the simulation and experimental results. Finally, we
make conclusions in Section V.

II. PRELIMINARIES AND PROBLEM FORMULATION

A. Operation of Dual-Mode Flyback Inverter
Fig. 1 shows the circuit diagram of the single-stage flyback
inverter. It consists of input capacitor Cin , primary switch S1 ,
diode D, transformer T with turns ratio n = Ns /Np , an unfold-
ing bridge (S2 –S5 ), and a capacitor–inductor (Cf , Lf ) output
filter. It is operated as follows: the dc energy source first gen-
erates the source current; the flyback converter operating at
appropriate switching frequency converts this source current to
rectified sinusoidal current; the unfolding H-bridge circuit op-
erating at the grid frequency unfolds the rectified sinusoidal Fig. 2. Waveforms of iL m , ip ri , and ise c corresponding to S1 and D states.
current; the output LC filter attenuates the ripples; the filtered T s is the switching period. (a) In DCM. (b) In CCM.
sinusoidal current is then supplied to the grid.
The flyback inverter is designed to operate in both DCM and
tizing inductance is chosen to provide a balance between high
CCM in a grid period. Fig. 2 shows the waveforms of iL m ,
efficiency and appropriate transformer size.
ipri , and isec with different states of S1 and D when the flyback
As shown in Fig. 3, the DCM and CCM intervals appear
inverter differs according to whether the converter operates in
alternatively in a grid period. To control the output current in
DCM or CCM. Ts is the switching period of the switch S1 , and
each mode, we can use the nominal duty as a feedforward input
the magnetizing current iL m is the sum of ipri and isec . In DCM,
to reduce the burden of a feedback controller [8], [20]. The
the magnetizing current increases when the switch is turned ON
nominal duty DDCM for DCM is given as
and decreases when the switch is turned OFF. Once the current
reaches zero, it stays there until the switch is turned ON again. 2 
DDCM (t) = Po Lm fs sin(2πfg t) (1)
But in CCM, the magnetizing current iL m never decreases to Vdc
zero. As shown in Fig. 2, in generating the same amount of
averaged magnetizing current, the flyback inverter operating in and the nominal duty DCCM for CCM is given as
CCM requires less peak current than in DCM; thus, the cur- |vg (t)|
rent stress is reduced and a higher efficiency is achieved. The DCCM (t) = . (2)
nVdc + |vg (t)|
CCM interval can be increased by increasing the magnetizing
inductance, but this strategy requires increase in transformer The flyback inverter operates in DCM when DDCM <
size. Efficiency trades off with transformer size, so the magne- DCCM , and it operates in CCM when DDCM > DCCM . The
6470 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 8, AUGUST 2017

⎡ ⎤
iL m (t)
⎢ ⎥
⎢ ⎥

⎢ in ⎥
⎢ v C (t)
⎥
y(t) = 0 0 1 0 ⎢ ⎥. (4)
⎢ i (t) ⎥
⎢ Lf ⎥
⎣ ⎦
vc f (t)
Phase 2 (S1 OFF, D ON):
⎡ ⎤ ⎡ ⎤
diL m (t) RC f RC f 1
⎢ −
⎥ ⎢ n2 L 0 −
⎢ dt ⎥ nLm nLm ⎥
⎢ dvC (t) ⎥ ⎢ ⎥
m
⎢ ⎥ ⎢ ⎢ 1 ⎥
⎢
in
⎥ 0 − 0 0 ⎥
⎢ dt ⎥ ⎢ ⎢ Rdc Cin ⎥
⎢ ⎥=⎢ R ⎥
Fig. 3. Waveforms of the nominal duty D n o and the grid voltage v g during a ⎢ diL f (t) ⎥ ⎢ Cf RC f + Rf 1 ⎥ ⎥
⎢ ⎥ ⎢ 0 − ⎥
grid period. The dotted black line indicates D D C M and the dash-dot black line ⎢ dt ⎥ ⎢ nLf L L ⎥
indicates D C C M . The red line indicates D n o . T g is the grid period. ⎢ ⎥ ⎣ f f
⎦
⎣ ⎦ 1 1
dvC f (t) 0 − 0
nCf Cf
dt
⎡ ⎤
⎡ ⎤ 0 0
iL m (t)
⎢ ⎥ 
⎢ ⎥ ⎢ 1 ⎥
⎢ vC i n (t) ⎥ ⎢ 0 ⎥ Vdc
×⎢ ⎥ ⎢R C
⎢ i (t) ⎥ + ⎢ dc in
⎥
⎣ Lf ⎦ ⎢ 1 ⎥
⎥ |vg (t)|
⎣ 0 −
Lf ⎦
vC f (t)
0 0
(5)
Fig. 4. Equivalent circuit of dual-mode flyback inverter.
⎡ ⎤
iL m (t)
resulting operating regions of the flyback inverter and the shape ⎢ ⎥

⎢ vC i n (t) ⎥
of the nominal duty Dno are shown in Fig. 3. y(t) = 0 0 1 0 ⎢ ⎢ ⎥. (6)
⎥
⎣ iL f (t) ⎦
B. Dynamic Model of Dual-Mode Flyback Inverter vc f (t)
Fig. 4 shows the flyback inverter circuit that incorporates par- Phase 3 (S1 OFF, D OFF):
asitic components and magnetizing inductance. Three operating ⎡ ⎤ ⎡ ⎤
diL m (t) 0 0 0 0
phases can be identified with this circuit:
⎢ dt ⎥ ⎢ ⎥⎡ i (t) ⎤
1) switch turned ON and diode turned OFF; ⎢ ⎥ ⎢ ⎥ Lm
⎢ dvC (t) ⎥ ⎢ 1 ⎥⎢
2) switch turned OFF and diode turned ON; ⎢ in ⎥ ⎢0 − 0 0 ⎥⎢ ⎥
⎢ ⎥ ⎢ R Cin ⎥⎢ vC i n (t) ⎥
3) switch turned OFF and diode turned OFF. ⎢ dt ⎥ ⎢ dc
⎥⎢ ⎥
⎢ ⎥= ⎥
⎢ diL f (t) ⎥ ⎢ RC + Rf 1 ⎥⎢
⎥⎣ iL f (t) ⎥
⎥ ⎢
The state equations in each state are represented as follows: − f
⎢ ⎢ 0 0 ⎥ ⎦
Phase 1 (S1 ON, D OFF): ⎢ dt ⎥ ⎢ Lf Lf ⎥
⎢ ⎥ ⎣ ⎦ vC f (t)
⎡ ⎤ ⎡ ⎤ ⎣ ⎦ 1
diL m (t) 1 dvC f (t) 0 0 − 0
0 0 0 Cf
⎢ dt ⎥ ⎢ Lm ⎥ dt
⎢ ⎥ ⎢ ⎥ ⎡ ⎤
⎢ dvC (t) ⎥ ⎢ 1 1 ⎥
⎢ in ⎥ ⎢− − 0 0 ⎥ 0 0
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢ dt ⎥ ⎢ Cin Rdc Cin ⎥ ⎢ 1 ⎥ 
⎢ ⎥=⎢ ⎥ ⎢ 0 ⎥ Vdc
⎢ diL f (t) ⎥ ⎢ RC f + Rf 1 ⎥
⎢ ⎥ ⎢ 0 0 − ⎥ +⎢ R C
⎢ dc in
⎥ (7)
⎢ dt ⎥ ⎢ Lf Lf ⎥ ⎢ 1 ⎥⎥ |vg (t)|
⎢ ⎥ ⎢ ⎥ ⎣ 0 −
⎣
dvC f (t)
⎦ ⎣ 1 ⎦ Lf ⎦
0 0 − 0 0 0
dt Cf
⎡ ⎤ ⎡ ⎤
⎡ ⎤ 0 0 iL m (t)
iL m (t) ⎢ ⎥
⎢ ⎥ ⎢ ⎥
⎢ vC i n (t) ⎥
⎢ ⎥ ⎢ ⎢ 1 ⎥⎡ ⎤ y(t) = 0 0 1 0 ⎢ ⎥
0 ⎥ ⎢ i (t) ⎥.
⎢ vC i n (t) ⎥ ⎢ (8)
⎥ Vdc ⎣ Lf ⎦
⎢ ⎥ ⎢ Rdc Cin ⎥⎣ ⎦
×⎢ ⎥+
⎢ i (t) ⎥ ⎢ ⎢ 1
⎥
⎥ |v vc f (t)
⎢ Lf ⎥ ⎢ 0 − ⎥ g (t)|
⎣ ⎦ ⎣ Lf ⎦ As shown in Fig. 2, the flyback inverter experiences phases
vC f (t) 0 0 1, 2, and 3 in DCM and phases 1 and 2 in CCM. Using the
(3) averaged state-space modeling technique for DCM and CCM
KIM et al.: ITERATIVE LEARNING CONTROLLER WITH MULTIPLE PHASE-LEAD COMPENSATION FOR DUAL-MODE FLYBACK INVERTER 6471

[8], [26], we can derive the average model as (9) and (10) be formulated as the switched linear system
⎡ ⎤
diL m (t) ẋ(t) = An x(t) + Bn d(t) (15)
⎢ dt ⎥
⎢ ⎥ y(t) = Cn x(t) (16)
⎢ dvC i n (t) ⎥
⎢ ⎥
⎢ dt ⎥
⎢ ⎥ with the switching sequence
⎢ diL (t) ⎥ = ⎧
⎢ ⎥
t ∈ [0, t1 )
f
⎢ ⎥ ⎪
⎪ 1,
⎢ dt ⎥ ⎪
⎪
⎣ ⎦ ⎪
⎪ 2, t ∈ [t1 , t2 )
dvC f (t) ⎪
⎨
dt n = 3, t ∈ [t2 , t3 ) (17)
⎡ ⎤ ⎪
⎪
RC f d2 (t) d1 (t) RC f d2 (t) d2 (t) ⎪
⎪ t ∈ [t3 , t4 )
⎪ 4,
⎢ − n2 Lm (d1 (t) + d2 (t)) Lm nLm
−
nLm ⎥
⎪
⎪
⎩
⎢ ⎥ t ∈ [t4 , Tg ]
⎢ ⎥ 5,
⎢ d (t) 1 ⎥
⎢ − 1
− 0 0 ⎥
⎢ Cin (d1 (t) + d2 (t)) Rdc Cin ⎥ as shown in Fig. 3. Note here that the switching indices 1, 3, 5
⎢ ⎥
⎢ ⎥ correspond to DCM and 2, 4 correspond to CCM.
⎢ RC f d2 (t) RC f + Rf 1 ⎥
⎢ 0 − ⎥ Since the dual-mode flyback inverter performs the same tasks
⎢ nL (d (t) + d (t)) Lf ⎥
⎢ f 1 2 Lf ⎥ repetitively with a grid period Tg , it can be described as a series
⎢ ⎥
⎣ d2 (t) 1 ⎦ of switched iterative linear systems
0 − 0
nCf (d1 (t) + d2 (t)) Cf ẋi (t) = An xi (t) + Bn di (t) (18)
⎡ ⎤ ⎡ ⎤
iL m (t) 0 0 yi (t) = Cn xi (t) (19)
⎢ ⎥ ⎢ ⎥
⎢ v (t) ⎥ ⎢ ⎢
1
0 ⎥
⎥ 
where i indicates the number of iterations, xi (t), yi (t), di (t)
⎢ Cin ⎥ ⎢ ⎥ Vdc
×⎢ ⎢ ⎥ R C
⎥+⎢ ⎥ (9)
dc in are, respectively, the states, outputs, inputs at the ith iteration.
⎢ iL f (t) ⎥ ⎢ ⎢ 1 ⎥⎥ |v (t)|
⎣ ⎦ ⎣ 0 − g To develop a control system in the discrete-time domain,
Lf ⎦ we need to develop a small signal model in the discrete-time
vC f (t) 0 0 domain. Discretizing (18) and (19) and formulating them for
⎡ ⎤
iL m (t) a generalized switching sequence gives a series of switched
⎢ ⎥ iterative linear systems as
⎢ ⎥

⎢ vC i n (t) ⎥
y(t) = 0 0 1 0 ⎢ ⎢
⎥,
⎥ (10) xi (k + 1) = Fn xi (k) + Gn uc (k) (20)
⎢ iL f (t) ⎥
⎣ ⎦ yi (k) = Hn xi (k) (21)
vC f (t)
with the switching sequence
where d1 (t) is the duty ratio when the switch is turned ON, ⎧
⎪
⎪ 1, k ∈ [k0 , k1 ]
d2 (t) = d 12L m i L m (t)
(t)v C i n (t)T s − d1 (t) in DCM and d2 (t) = 1 − d1 (t) ⎪
⎨ 2, k ∈ [k1 + 1, k2 ]
in CCM. n= . .. (22)
By linearizing (9) and (10), we can derive the small signal ⎪
⎪ .. .
⎪
⎩
models for DCM and CCM as follows: N, k ∈ [kN −1 + 1, kN ]
DCM
where k is the discrete time index starting from k = k0 = 0 to
ẋ(t) = ADCM x(t) + BDCM d(t) (11) k = kN , xi (k) ∈ Rm ×1 , yi (k) ∈ R, and uc (k) ∈ R are, respec-
tively, the state vector, output, and control input for i = 1, 2, ...,
y(t) = CDCM x(t) (12)
and Fn ∈ Rm ×m , Gn ∈ Rm ×1 , and Hn ∈ R1×m are discrete-
CCM time system matrices.
The proposed controller is then developed based on the fol-
ẋ(t) = ACCM x(t) + BCCM d(t) (13) lowing assumptions.
y(t) = CCCM x(t) (14) Assumption 1: The desired system is invertible, that is, there
exists a unique bounded input ud (k) such that
where x(t) = [īL m (t), v̄C i n (t), īL f (t), v̄C f (t)]T , d(t) = d¯1 (t),
y(t) = īL f (t) are the state, control input, and output. īL m (t), xd (k + 1) = Fn xd (k) + Gn ud (k) (23)
v̄C i n (t), īL f (t), v̄C f (t), and d¯1 (t) are the incremental variations yd (k) = Hn xd (k), for all k ∈ [0, kN ] (24)
of iL m (t), vC i n (t), iL f (t), vC f (t), and d1 (t). The parameters
ADCM , ACCM , BDCM , BCCM , CDCM , and CCCM are derived with the switching sequence n as given in (22). xd (k) ∈ Rm ×1
in Appendix A. is the desired state vector and yd (k) ∈ R is the desired output.
In a grid period, the flyback inverter operates in DCM and Assumption 2: The initial resetting condition holds for all
CCM alternatively as shown in Fig. 3. Therefore, its model can iterations, i.e., xi (0) = xd (0) and yi (0) = yd (0), i = 1, 2, ....
6472 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 8, AUGUST 2017

Theorem 1: Consider the discrete-time switched linear system

(20) and (21) with switching sequence (22). Assume that the
assumptions 1 and 2 are satisfied and that the inequality

ρ(In − Pn Mn Ln ) < 1 (29)

holds for all subsystems, where ρ(·) denotes the spectral radius,
In is the (kn − kn −1 ) × (kn − kn −1 ) identity matrix, Pn ∈
R(k n −k n −1 ) × m (k n −k n −1 ) , Mn ∈ Rm (k n −k n −1 ) × (k n −k n −1 ) , and
Ln ∈ R(k n −k n −1 ) × (k n −k n −1 ) and are represented as
⎡ ⎤
Hn 0 ··· 0
⎢ 0 ··· 0 ⎥
⎢ Hn ⎥
Fig. 5. Schematic diagram of the proposed control scheme for the dual-mode
flyback inverter.
Pn = ⎢
⎢ .. ..
⎥
. . .. ⎥ (30)
⎣ . . . . ⎦

III. CONTROLLER DESIGN 0 0 · · · Hn

⎡ ⎤
The control objective of the grid-connected flyback inverter Gn 0 ··· 0
is to make the output current of the flyback inverter track the ⎢ ··· 0 ⎥
⎢ F̄n Gn Gn ⎥
desired sinusoidal signal as closely as possible. Since the sys- Mn = ⎢
⎢ .. ..
⎥
. . .. ⎥ (31)
tem gain of the dual-mode flyback inverter in the DCM region is ⎣ . . . . ⎦
low, we need to use the high-gain feedback controller to achieve F̄nk n −k n −1−1 Gn F̄nk n −k n −1−2 Gn · · · Gn
accurate reference tracking and disturbance rejection. However, ⎡ ⎤
the possible amount of increase in the control gain in the feed- l1,1 l1,2 ··· l1,k n −k n −1
⎢ ··· ⎥
back controller is limited by the RHP zero in CCM. In fact, if ⎢ l2,1 l2,2 l2,k n −k n −1 ⎥
the control gain is too high, the control system may result in Ln = ⎢
⎢ .. .. .. ..
⎥
⎥ (32)
unacceptable power quality and total harmonic distortion due to ⎣ . . . . ⎦
this RHP zero. Using the nominal duty in the feedforward loop lk n −k n −1 ,1 lk n −k n −1 ,2 · · · lk n −k n −1 ,k n −k n −1
can reduce the burden from the high-gain controller and achieve 
kl , if p+λn −1 = q
equivalent control accuracy with less control gain, but the use lp,q = p, q = 1, ..., kn − kn −1 (33)
0, else
of a feedback controller plus nominal duty generally does not
achieve satisfactory control accuracy. To improve tracking ac-
curacy and disturbance rejection, we propose to use an iterative where F̄n = Fn − kp Gn Hn . Then, the proposed controller (25)
learning controller as shown in Fig. 5. guarantees that the output tracking error of the closed-loop sys-
The proposed control input can be represented as tem converges to zero.
Proof. Applying the controller (25) to the discrete-time
uc (k) = uf b (k) + uf f (k) + ui (k) (25) switched linear system (20), (21) and subtracting the obtained
equations from those of the desired system (23), (24), we have
where uf b (k) ∈ R is the state-feedback controller, uf f (k) ∈ R
is the nominal duty, and ui (k) ∈ R is the proposed iterative
δxi (k + 1) = Fn δxi (k) + Gn (ud (k) − uc (k)) (34)
learning controller. As for uf b (k), uf f (k), ui (k), we propose
to use ei (k) = Hn δxi (k) (35)

uf b (k) = kp e(k) (26) where δxi (k) = xi (k) − xd (k).

uf f (k) = Dno (k) Substituting proportional control law (26) into uc (k) in (34),
 we have
DDCM (k), if DDCM (k) ≤ DCCM (k)
= (27)
DCCM (k), if DDCM (k) > DCCM (k) δxi (k + 1) = F̄n δxi (k) + Gn ūi (k) (36)

ui+1 (k) = ui (k) + kl ei (k + λn ) (28) ei (k) = Hn δxi (k), for all k ∈ [kn −1 , kn ] (37)

where kp is the proportional gain; λn ≥ 1 is the phase-lead step; where ūi (k) = ud (k) − uf f (k) − ui (k). Substituting time in-
ei (k) = yi (k) − yd (k) is the output error; kl is the learning dex k = kn −1 , ..., kn in (36) and (37) and rearranging the ob-
controller gain; i = 0, 1, ... is the iteration index; k = 0, ..., kN tained equations of the subsystem, we have
is the time index; and n = 1, ..., N is the switching index. Using
the simple proportional controller such as uf b (k) = kp e(k) is ΔXn ,i = Mn Ūn ,i + Dn δxi (kn −1 ) (38)
acceptable because the control accuracy depends heavily on the
nominal duty uf f (k) and the iterative learning rule ui (k). En ,i = Pn ΔXn ,i (39)
KIM et al.: ITERATIVE LEARNING CONTROLLER WITH MULTIPLE PHASE-LEAD COMPENSATION FOR DUAL-MODE FLYBACK INVERTER 6473

where the sequence of δxi (k), ei (k), and ūi (k) are combined and
into the vector forms as
⎡ ⎤ ⎡ ⎤⎡ ⎤
ΔXn ,i = [δxi (kn −1 + 1)T , δxi (kn −1 + 2)T , ΔX1,i M1 0 · · · 0 Ū1,i
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢ ΔX2,i ⎥ ⎢ 0 M2 · · · ⎥ ⎢ Ū2,i ⎥
0
..., δxi (kn )T ]T ∈ Rm (k n −k n −1 ) (40) ⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢ . ⎥=⎢ .. .. . . ⎥⎢ . ⎥
..
⎢ .. ⎥ ⎢ ⎥ ⎢ .. ⎥
En ,i = [ei (kn −1 +1), ei (kn −1 +2), ..., ei (kn )]T ∈ Rk n −k n −1 ⎣ ⎦ ⎣ . . . ⎦⎣ . ⎦
(41) ΔXN ,i 0 0 · · · MN ŪN ,i
k n −k n −1 ⎡ ⎤⎡ ⎤
Ūn ,i = [ūi (kn −1 ), ūi (kn −1 +1), ..., ūi (kn −1)] ∈ R
T
0 0 ··· 0 0
(42) ⎢ ⎥⎢ ⎥
⎢0 D2 S1 · · · 0 ⎥ ⎢ ΔX1,i ⎥
⎢ ⎥⎢ ⎥
T T (k −k T
and Dn = [F¯n , F¯n2 , ..., F̄n n n −1 ]T ∈ Rm (k n −k n −1 )×m ,
) +⎢. .. . . .. ⎥⎢ .. ⎥.
⎢ .. . ⎥ ⎢ ⎥
where F̄n = Fn − kp Gn Hn . Applying the same steps for all ⎣ . . ⎦⎣ . ⎦
subsystems under Assumption 2, we have 0 0 · · · DN SN −1 ΔXN −1,i
⎡ ⎤ ⎡ ⎤⎡ ⎤ (47)
ΔX1,i M1 0 · · · 0 Ū1,i
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢ ΔX2,i ⎥ ⎢ 0 M2 · · · 0 ⎥ ⎢ Ū2,i ⎥
⎢ ⎥ ⎢ ⎥⎢ ⎥ Moving the second term on the right-hand side of (47) to the
⎢ . ⎥=⎢ . . . ⎥⎢ ⎥
⎢ .. ⎥ ⎢ .. .. . . ... ⎥ ⎢ ... ⎥ left-hand side of (47), we obtain
⎣ ⎦ ⎣ ⎦⎣ ⎦
ΔXN ,i 0 0 · · · MN ŪN ,i
⎡ ⎤⎡ ⎤
⎡ ⎤⎡ ⎤ I1 0 ··· 0 ΔX1,i
D1 0 · · · 0 0 ⎢ ⎥⎢ ⎥
⎢ ⎥⎢ ⎥ ⎢ −D2 S1 I2 ··· 0 ⎥ ⎢ ΔX2,i ⎥
⎢ 0 D2 · · · 0 ⎥ ⎢ δxi (k1 ) ⎥ ⎢ ⎥⎢ ⎥
⎢ ⎥⎢ ⎥ ⎢ .. .. ⎥⎢ . ⎥
+⎢ . . . ⎥⎢ ⎥ (43) ⎢ 0 ⎦⎣ . ⎥
⎥ ⎢
.. .
⎢ .. .. . . ... ⎥ ⎢ .. ⎥ ⎣ . . . ⎦
⎣ ⎦⎣ . ⎦
0 0 −DN SN −1 IN ΔXN ,i
0 0 · · · DN δxi (kN −1 )
⎡ ⎤⎡ ⎤
⎡ ⎤ ⎡ ⎤⎡ ⎤ M1 0 · · · 0 Ū1,i
E1,i P1 0 · · · 0 ΔX1,i ⎢ ⎥⎢ ⎥
⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ 0 M2 · · · 0 ⎥ ⎢ Ū2,i ⎥
⎢ E2,i ⎥ ⎢ 0 P2 · · · 0 ⎥ ⎢ ΔX2,i ⎥ ⎢ ⎥⎢ ⎥
⎢ ⎥ ⎢ ⎥⎢ ⎥ =⎢ . . . ⎥⎢ ⎥ (48)
⎢ . ⎥=⎢ . . . ⎥⎢ ⎥. (44) ⎢ .. .. . . ... ⎥ ⎢ ... ⎥
⎢ .. ⎥ ⎢ .. .. . . ... ⎥ ⎢ ... ⎥ ⎣ ⎦⎣ ⎦
⎣ ⎦ ⎣ ⎦⎣ ⎦
0 0 · · · MN ŪN ,i
EN ,i 0 0 · · · PN ΔXN ,i
Then, the state-error vector δxi (kn ) can be described as
and multiplying the inverse of first matrix on the left-hand side
δxi (kn ) = Sn ΔXn ,i (45) of (48) gives
.
where Sn = [ 0m ×m (k n −k n −1 −1) .. Im ×m ]. ⎡ ⎤ ⎡ ⎤−1
Substituting (45) into (43) results in ΔX1,i I1 0 ··· 0
⎡ ⎤ ⎡ ⎤⎡ ⎤ ⎢ ⎥ ⎢ ⎥
M1 0 · · · 0 ⎢ ΔX2,i ⎥ ⎢ −D2 S1 I2 ··· 0 ⎥
ΔX1,i Ū1,i ⎢ ⎥ ⎢ ⎥
⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ . ⎥=⎢ .. .. ⎥
⎢ ΔX2,i ⎥ ⎢ 0 M2 · · · 0 ⎥ ⎢ Ū2,i ⎥ ⎢ .. ⎥ ⎢ ..
. 0 ⎥
⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎣ ⎦ ⎣ . . ⎦
⎢ . ⎥=⎢ . . . ⎥⎢ ⎥
⎢ .. ⎥ ⎢ .. .. . . ... ⎥ ⎢ ... ⎥ ΔXN ,i 0 0 −DN SN −1 IN
⎣ ⎦ ⎣ ⎦⎣ ⎦
⎡ ⎤⎡ ⎤
ΔXN ,i 0 0 · · · MN ŪN ,i M1 0 · · · 0 Ū1,i
⎡ ⎤⎡ ⎤ ⎢ ⎥⎢ ⎥
D1 0 · · · 0 0 0 ··· 0 ⎢ 0 M2 · · · 0 ⎥ ⎢ Ū2,i ⎥
⎢ ⎥⎢ ⎥
⎢ ⎥⎢ ⎥ ×⎢ . . . ⎥⎢ ⎥. (49)
⎢ 0 D2 · · · 0 ⎥ ⎢ 0 S1 · · · 0 ⎥ ⎢ .. .. . . ... ⎥ ⎢ ... ⎥
⎢ ⎥⎢ ⎥ ⎣ ⎦⎣ ⎦
+⎢ . . . ⎥⎢ .. ⎥
⎢ .. .. . . ... ⎥ ⎢ ... ... . . . . ⎥ 0 0 · · · MN ŪN ,i
⎣ ⎦⎣ ⎦
0 0 · · · DN 0 0 · · · SN −1
⎡ ⎤ Then, we simply rewrite the generalized state equation (49)
0 and the output-error equation (44) as
⎢ ⎥
⎢ ΔX1,i ⎥
⎢ ⎥
×⎢ .. ⎥ (46)
⎢ ⎥ ΔXi = S −1 M Ūi (50)
⎣ . ⎦
ΔXN −1,i Ei = P ΔXi = P S −1 M Ūi (51)
6474 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 8, AUGUST 2017

where M = diag(M1 , ..., MN ), P = diag(P1 , ..., PN ), and modifying the learning rule (28) as follows:
⎡ ⎤
I1 0 ··· 0 
kn
⎢ ⎥ ui+1 (k) = (1−γ)ui (k) + ak ,j ei (j), k = kn −1 , ..., kn −1
⎢ −D2 S1 I2 ··· 0 ⎥
⎢ ⎥
S=⎢ .. .. ⎥ j =k n −1 +1
⎢ ..
. 0 ⎥ (55)
⎣ . . ⎦
where γ is the forgetting factor. The phase-lead compensation
0 0 −DN SN −1 IN and the low-pass filtering algorithm can be implemented in the
⎡ ⎤ ⎡ ⎤ ⎡ ⎤ ILC by designing the learning gain as
ΔX1,i Ū1,i E1,i
⎢ ⎥ ⎢ ⎥ ⎢ ⎥ k
⎢ ΔX2,i ⎥ ⎢ Ū2,i ⎥ ⎢ E2,i ⎥ , if k+λn − α −1 α −1
2 ≤ j ≤ k+λn + 2
l
⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ak ,j = α (56)
ΔXi = ⎢ . ⎥ , Ūi = ⎢ . ⎥ , Ei = ⎢ . ⎥ . 0, else
⎢ .. ⎥ ⎢ .. ⎥ ⎢ .. ⎥
⎣ ⎦ ⎣ ⎦ ⎣ ⎦
ΔXN ,i ŪN ,i EN ,i where kl is the conventional learning gain, α is the number of
samples to calculate the zero phase moving average, and λn
From (28) and (33), we obtain the ILC law as is the number of the phase-lead step. If we choose γ = 0.1,
kl = 0.1, α = 3, and λn = 2, then the learning rule becomes
Un ,i+1 = Un ,i + Ln En ,i (52)
0.1
where ui+1 (k) = 0.9ui (k)+ (ei (k + 1)+ei (k + 2)+ei (k + 3)).
3
Un ,i = [ui (kn −1 ), ui (kn −1 +1), ..., ui (kn −1)]T ∈ Rk n −k n −1 . (57)
The learning gain matrix Ln can then be represented as
Denoting
Ln = {lpq }, lpq = ak ,j (58)
Un ,d =[ud (kn−1 ), ud (kn−1 +1), ..., ud (kn −1)]T ∈ Rk n −k n −1
k = kn−1 −1+p, j = kn−1 +q, p, q = 1, ..., kn −kn−1 . (59)
Un ,f f =[uf f (kn−1 ), uf f (kn−1 +1), ..., uf f (kn −1)]T ∈ Rk n −k n −1
⎡ ⎤ ⎡ ⎤ ⎡ ⎤ By changing the stability condition to (1−γ)I −
U1,d U1,f f Ū1,i+1 P S −1 M L < 1, we can make the output tracking error of
⎢ U2,d ⎥ ⎢ U2,f f ⎥ ⎢ Ū2,i+1 ⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
Ud = ⎢ . ⎥ , Uf f = ⎢ . ⎥ , Ūi+1 = ⎢ . ⎥ the closed-loop system ultimately bounded. The proof of
⎣ .. ⎦ ⎣ .. ⎦ ⎣ .. ⎦ the modified learning rule is essentially the same as that of
UN ,d UN ,f f ŪN ,i+1 Theorem 1.

and with the learning control law (52), we obtain the input error
IV. SIMULATION AND EXPERIMENTAL RESULT
equation as
The proposed control scheme is tested with simulation and ex-
Ūi+1 = Ud − Uf f − Ui+1 perimental examples. The simulation is performed using PSIM
= Ud − Uf f − Ui − LEi 9.0 and the experiment is performed using the prototype of the
dual-mode flyback inverter with circuit parameters and oper-
= Ūi − LEi (53) ating conditions listed in Table I. The control algorithms are
where L = diag(L1 , ..., Ln ). Substituting (53) into (51), we implemented with the TMS320F28377 microcontroller. Fig. 6
have shows the block diagram of the complete control system con-
figuration.
Ei+1 = P S −1 M Ūi+1 The dual-mode flyback inverter system is modeled as
= P S −1 M (Ūi − LEi ) xi (k + 1) = Fn xi (k) + Gn uc (k) (60)
−1
= Ei − P S M LEi yi (k) = Hn xi (k) (61)
−1
= (I − P S M L)Ei . (54) with the switching sequence given by
Since P , M , and L are block diagonal matrices and S is a ⎧
⎪
⎪ 1, k ∈ [0, k1 ]
lower triangular matrix in which block diagonal terms are iden- ⎪
⎪
tity matrices, I − P S −1 M L is also a block lower triangular ma- ⎨ 2, k ∈ [k1 + 1, k2 ]
n = 3, k ∈ [k2 + 1, k3 ] (62)
trix and its block diagonal terms are {I1 − P1 M1 L1 , ..., IN − ⎪
⎪
⎪
⎪ 4, k ∈ [k3 + 1, k4 ]
PN MN LN }. Therefore, if the condition (29) is satisfied, then ⎩
5, k ∈ [k4 + 1, k5 ].
all the eigenvalues of I − P S −1 M L exist within the unit circle,
and consequently the error converges to zero.  As shown in Fig. 3, the switching indices 1, 3, 5 correspond
In practice, a low-pass filter is frequently used to disable to DCM and 2, 4 correspond to CCM. The control input uc (k)
learning at high frequency and a forgetting factor is used to is represented as
enhance the stability of learning against unknown uncertainties.
The low-pass filter can be implemented in the proposed ILC by uc (k) = uf b (k) + uf f (k) + ui (k) (63)
KIM et al.: ITERATIVE LEARNING CONTROLLER WITH MULTIPLE PHASE-LEAD COMPENSATION FOR DUAL-MODE FLYBACK INVERTER 6475

TABLE I
PARAMETERS AND OPERATING CONDITIONS OF THE DUAL-MODE FLYBACK
INVERTER

Parameters Symbols Value

Transformer turn ratio n 3.5

Magnetizing inductance Lm 51 uH
Leakage inductance L lk 0.6 uH
Filter inductance Lf 393 uH
Input capacitance Cin 3.6 mF
Filter capacitance Cf 0.68 uF
Resistance in energy source Rd c 1Ω
Resistance in filter Rc f 0.1 Ω
Resistance in filter inductor Rf 0.24 Ω
Operating conditions Symbols Value
Nominal voltage of energy source Vd c 60 V
Grid voltage vg 220 V r m s
Grid frequency fg 60 Hz
Switching frequency fs 50 kHz
Rated power of energy source Po 200 W
Sampling frequency fc 50 kHz
Components Symbols Part number
MOSFET S1 IPP200N25N3G
Unfolding Switch S2 –S5 SPP11N60C3
Transformer core T PQ3535
Diode D C3D08065A

Fig. 7. (a) Impulse response of the dual-mode flyback inverter in DCM and
CCM. (b) Maximum impulse response time during the first quarter of the grid
period. Blue line indicates DCM and orange line indicates CCM. tp k . dcm and
tp k . ccm are the maximum impulse response times corresponding to DCM and
CCM, respectively.

Next, we need to determine the phase-lead steps. One of

the practical methods for estimating the optimum phase-lead
values is the use of maximum impulse response time [27]. We
examine the impulse response of the dual-mode flyback inverter
and determine the maximum impulse response time as shown
Fig. 6. Configuration of the proposed control system. PWM, LPF, ADC,
and PLL stand for pulse-width modulation, low-pass filter, analog-to-digital in Fig. 7.
conversion, and phase locked loop. Fig. 7(a) shows the impulse response of the flyback inverter
control system for DCM and CCM. As shown in Fig. 7(a), the
where maximum impulse response times, tpk .dcm and tpk .ccm , turn out
to be different. They depend mainly on the location of the RHP
uf b (k) = kp e(k) (64) zero, which, in turn, varies as the operating point changes. Thus,
⎧ 2 √P L f we determine the maximum impulse response times in the first
⎨ o m s
sin(2πfg k/fc ), n = 1, 3, 5
Vd c quarter of the grid period, and these are shown in Fig. 7(b).
uf f (k) = (65)
⎩ |v g (k /f c )| , n = 2, 4 Note here that the maximum impulse response time tpk .dcm
n V d c +|v g (k /f c )|
is relatively shorter than tpk .ccm . Taking the 50-kHz sampling

ui (k) + kl e(k + λd ), n = 1, 3, 5 frequency into account, we select the phase-lead step λd = 3 in
ui+1 (k) = (66) DCM and λc = 4 in CCM.
ui (k) + kl e(k + λc ), n = 2, 4
A. Simulation Results
for iteration index i, time index k, and switching index n. In this
simulation, we use kp = 0.05 and kl = 0.001. The parameters To evaluate the control accuracy of the multiple phase-lead
for nominal duty are shown in Table I. compensator, we first simulated the ILC with several phase-lead
6476
Fig. 8. (a) RMS errors of the output current when the ILC with phase-
lead compensation is used. (b) Magnified rms errors of the output current.
(c) Waveforms of the output current at the 240th iteration when the ILC with
the phase-lead step λd = λc = 3 is applied. The black dotted line shows the
rms error of the output current when the ILC is not used.
steps but with the same value for the dual-mode flyback inverter.
Fig. 8(a) and (b) shows the rms errors of the output current when
the same step value is used for DCM and CCM. At the early
stage of iterations, the rms error decreases, but begins to in-
crease as the iteration increases. Fig. 8(c) shows the waveform
of the output current at the 240th iteration when the three-step
phase-lead is applied. Although its rms error is the smallest
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 8, AUGUST 2017
Fig. 9. (a) RMS errors of the output current when the ILC with multiple
phase-lead steps is applied. (b) Magnified rms errors of the output current.
(c) Waveforms of the output current at the 540th iteration when the ILC with
multiple phase-lead steps λd = 3, λc = 4 is applied. The black dotted line
shows the rms error of the output current when the ILC is not applied.
compared with those of other several same phase-lead compen-
sators, the performance of the output current is still poor.
Fig. 9(a) and (b) shows the rms errors of the output current
with the proposed multiple phase-lead control scheme for DCM
and CCM. Without proper phase-lead, the output error increases
as the iteration increases, even if we use the multiple phase-
lead steps. However, when the three-step phase-lead is used in
KIM et al.: ITERATIVE LEARNING CONTROLLER WITH MULTIPLE PHASE-LEAD COMPENSATION FOR DUAL-MODE FLYBACK INVERTER 6477

Fig. 10. Waveforms of the output current and output current error when the
proposed controller is applied and the output power is varied.

DCM and the four-step phase-lead is used in CCM, the output

tracking error becomes nearly zero and maintains its value as the
iteration increases. Fig. 9(c) illustrates the output current of the
dual-mode flyback inverter control system with the three-step
phase-lead in DCM and the four-step phase-lead in CCM. The
output current tracks the reference very closely. Fig. 11. Time when pulse signal is added (green) and pulse response (blue) of
Fig. 10 shows the waveforms of the output current and output the dual-mode flyback inverter. (a) In DCM. (b) In CCM. tp k . dcm and tp k . ccm
are the maximum pulse response times corresponding to DCM and CCM,
current error when the output power is varied. Since the output respectively.
power is changed from 120 to 200 W, the output current is
slightly distorted. But, the actual output current well tracks the
reference output current in a few iterations.

B. Experimental Results
Fig. 11(a) and (b) shows the time when pulse signal is added
and the impulse response of the flyback inverter control system
for DCM and CCM. As shown in Fig. 11(a) and (b), the maxi-
mum impulse response time tpk .dcm and tpk .ccm are different. We
also determine the maximum impulse response times in the first
quarter of the grid period (see Fig. 12). A similar tendency was
observed in the maximum pulse response times of simulation
and those of experiment. Taking the 50-kHz sampling frequency
into account, we select the phase-lead step λd = 5 in DCM and
λc = 7 in CCM. Fig. 12. Maximum impulse response time during the first quarter of a grid
Fig. 13 shows the experimental result of the prototype dual- period. Blue line indicates DCM and orange line indicates CCM.
mode flyback inverter when the proposed control scheme is ap-
plied. An exponential filter and a forgetting factor are adopted fluctuate due to the inappropriate learning. Fig. 13(c) shows the
to disable learning at high frequency and to enhance the stability waveforms of the grid voltage and the output current when the
of learning. For the experimental setup, we used output power ILC with five-step phase-lead in DCM and seven-step phase-
Po = 140 W, forgetting factor γ = 0.0005, and phase-lead step lead in CCM is used. The output current tracks the reference
λd = 5, λc = 7. The forgetting factor was obtained heuristi- without any visible fluctuations.
cally. Fig. 13(a) shows the waveforms of the grid voltage and We also tested the conventional and proposed controller when
the output current when the PI control scheme is applied. The the output power is set to Po = 200 W. Fig. 14 (a) shows the
output current is highly distorted so that it cannot be used in waveforms of the grid voltage and the output current when the PI
practical applications. Fig. 13(b) shows the waveforms of the control scheme is applied. Similar to Fig. 13(a), the output cur-
grid voltage and the output current when the ILC with five-step rent is highly distorted. Fig. 14(b) shows the waveforms of the
phase-lead is applied. The output current in CCM region starts to grid voltage and the output current when the proposed scheme
6478
Fig. 13. Waveforms of the grid voltage (red) and the output current (blue)
when the output power is 140 W. (a) PI controller. (b) ILC with single phase-
lead step λd = λc = 5. (c) ILC with multiple phase-lead step λd = 5, λc = 7.
is applied. The proposed control scheme performs well and the
output current tracks the reference without notable performance
degradation.
Fig. 15 shows the waveforms of the output current when the
output power is changed from 120 to 200 W. A similar tendency
was observed in output current of simulation and that of experi-
ment. Even though the output current is slightly distorted at the
early stage of power variation, the output current well tracks the
reference output current in a few iterations.
V. CONCLUSION
In this paper, we propose an ILC scheme with multiple
phase-lead compensation for the dual-mode flyback inverter.
The dual-mode flyback inverter takes the advantage of DCM
and CCM operations to achieve low cost, small size, and high
conversion efficiency. To generate output current with low har-
monic components, we propose to use the ILC coupled with the
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 8, AUGUST 2017
Fig. 14. Waveforms of the grid voltage (red) and the output current (blue)
when the output power is 200 W. (a) PI controller. (b) ILC with multiple phase-
lead step λd = 5, λc = 7.
Fig. 15. Waveforms of the grid voltage (red) and the output current (blue)
when the proposed controller is applied and the output power is varied.
conventional control scheme consisting of the feedback con-
troller and the dual-mode nominal duty. In the proposed ILC
scheme, we also use a multiple phase-lead compensation al-
gorithm to compensate for the effect of different system dy-
namics. We also proved that the error of the closed-loop sys-
tem converges to zero. The simulation and experimental results
demonstrate the validity of the proposed control scheme.
APPENDIX A
PARAMETERS IN SMALL SIGNAL MODEL
The small signal model parameters in (11)–(14) are described
as shown at the top of the next page, where IL m , VC i n , IL f , VC f ,
and D are the operating points of iL m (t), vC i n (t), iL f (t), vC f (t),
and d1 (t).
KIM et al.: ITERATIVE LEARNING CONTROLLER WITH MULTIPLE PHASE-LEAD COMPENSATION FOR DUAL-MODE FLYBACK INVERTER 6479

ADCM =
⎡ ⎤
Rc f 2(Rc f IL f − VC f ) Rc f Ts D2 D 2IL m (Rc f IL f − VC f ) 2Rc f IL m Rc D 2IL m D
−
⎢ n2 Lm + 2 2
+ − 2 − f − + ⎥
⎢ nTs DVC i n 2n Lm Lm nTs DVC i n nTs DVC i n nLm nTs DVC i n nLm ⎥
⎢ ⎥
⎢ Ts D 2 1 ⎥
⎢ 0 − − 0 0 ⎥
⎢ 2Lm Cin Rdc Cin ⎥
⎢ ⎥
⎢ R c Ts D 2 ⎥
⎢ Rc f Rc + Rf 1 ⎥
⎢ − f − f ⎥
⎢ nLf 2nLm Lf Lf Lf ⎥
⎢ ⎥
⎣ 1 Ts D 2 1 Ts V C i n D ⎦
− − −
nCf 2nLm Lf Cf nLm Cf
⎡ ⎤
Rc f (1 − D) D Rc f (1 − D) 1 − D
⎢ −
⎢ 2
n Lm 2 Lm nLm nLm ⎥ ⎥
⎢ ⎥
⎢ D 1 ⎥
⎢ − − 0 0 ⎥
⎢ C R C ⎥
ACCM = ⎢ ⎢ in dc in ⎥
R (1 − D) R + R ⎥
⎢ cf −
cf f 1 ⎥
⎢ 0 ⎥
⎢ nLf Lf Lf ⎥
⎢ ⎥
⎣ 1−D 1 ⎦
0 − 0
nCf Cf
⎡R T V D 2(Rc f IL m IL f − IL m VC f ) Rc f IL f − VC f ⎤
cf s C in VC in
+ − −
⎢ n2 L2m Lm nTs VC i n D2 nLm ⎥
⎢ ⎥
⎢ ⎥
⎢ Ts V C i n D ⎥
⎢ − ⎥
⎢ Lm Cdc ⎥
BDCM = ⎢ ⎢ ⎥
⎥
⎢ R c f Ts VC i n D ⎥
⎢ − ⎥
⎢ nLm Lf ⎥
⎢ ⎥
⎣ Ts V C i n D ⎦
−
nLm Cf
⎡R I VC i n Rc f IL f − VC f ⎤
cf L m
+ −
⎢ n2 Lm Lm nLm ⎥
⎢ ⎥
⎢ IL m ⎥
⎢ − ⎥
⎢ ⎥
⎢ Cdc ⎥
BCCM = ⎢ ⎥
⎢ Rc f IL m ⎥
⎢ − ⎥
⎢ nL ⎥
⎢ f ⎥
⎣ IL m ⎦
−
nCf

CDCM = CCCM = 0 0 1 0

REFERENCES
[1] J. M. Carrasco, “Power-electronic systems for the grid integration of re-
newable energy sources: A survey,” IEEE Trans. Ind. Electron., vol. 53,
no. 4, pp. 1002–1016, Jun. 2006.
[2] W. Qi, J. Liu, and P. D. Christofides, “Distributed supervisory predictive
control of distributed wind and solar energy systems,” IEEE Trans. Control
Syst. Technol., vol. 21, no. 2, pp. 504–512, Mar. 2013.
[3] A. Ghaffari, M. Krstic, and S. Seshagiri, “Power optimization for
photovoltaic microconverters using multivariable Newton-based ex-
tremum seeking,” IEEE Trans. Control Syst. Technol., vol. 22, no. 6,
pp. 2141–2149, Nov. 2014.
[4] A. Date, A. Date, C. Dixon, and A. Akbarzadeh, “Progress of thermoelec-
tric power generation systems: Prospect for small to medium scale power
generation,” Renewable Sustain. Energy Rev., vol. 33, pp. 371–381, May
2014.
[5] D. Meneses, F. Blaabjerg, O. Garcia, and J. A. Cobos, “Review and com-
parison of step-up transformerless topologies for photovoltaic ac-module
application,” IEEE Trans. Power Electron., vol. 28, no. 6, pp. 2649–2663,
Jun. 2013.
[6] H.-J. Chiu, “A module-integrated isolated solar microinverter,” IEEE
Trans. Ind. Electron., vol. 60, no. 2, pp. 781–788, Feb. 2013.
[7] B. York, W. Yu, and J.-S. Lai, “An integrated boost resonant converter for
photovoltaic applications,” IEEE Trans. Power Electron., vol. 28, no. 3,
pp. 1199–1207, Mar. 2013.
[8] F. F. Edwin, W. Xiao, and V. Khadkikar, “Dynamic modeling and control
of interleaved flyback module-integrated converter for PV power appli-
cations,” IEEE Trans. Ind. Electron., vol. 61, no. 3, pp. 1377–1388, Mar.
2014.
[9] T. LaBella and J.-S. Lai, “A hybrid resonant converter utilizing a bidirec-
tional gan AC switch for high-efficiency PV applications,” IEEE Trans.
Ind. Appl., vol. 50, no. 5, pp. 3468–3475, Mar. 2014.
6480
[10] D. Meneses, O. Garcia, P. Alou, J. A. Oliver, and J. A. Cobos, “Grid-
connected forward microinverter with primary-parallel secondary-series
transformer,” IEEE Trans. Power Electron., vol. 30, no. 9, pp. 4819–4830,
Sep. 2015.
[11] A. Abramovitz, B. Zhao, and K. M. Smedley, “High-gain single-stage
boosting inverter for photovoltaic applications,” IEEE Trans. Power Elec-
tron., vol. 31, no. 5, pp. 3550–3558, May 2016.
[12] S.-H. Lee, W. J. Cha, B.-H. Kwon, and M. Kim, “Discrete-time repetitive
control of flyback CCM inverter for PV power applications,” IEEE Trans.
Ind. Electron., vol. 63, no. 2, pp. 976–984, Feb. 2016.
[13] J.-H. Lee, J.-S. Lee, and K.-B. Lee, “Current sensorless mppt control
method for dual-mode PV module-type interleaved flyback inverters,”
J. Power Electron., vol. 15, no. 1, pp. 54–64, Jan. 2015.
[14] A. C. Nanakos, G. C. Christidis, and E. C. Tatakis, “Weighted efficiency
optimization of flyback microinverter under improved boundary con-
duction mode (i-bcm),” IEEE Trans. Power Electron., vol. 30, no. 10,
pp. 5548–5564, Oct. 2015.
[15] M. A. Rezaei, K.-J. Lee, and A. Q. Huang, “A high-efficiency flyback
micro-inverter with a new adaptive snubber for photovoltaic applications,”
IEEE Trans. Power Electron., vol. 31, no. 1, pp. 318–327, Jan. 2016.
[16] G. Christidis, A. Nanakos, and E. Tatakis, “Hybrid discontinuous/
boundary conduction mode of flyback micro-inverter for AC-PV mod-
ules,” IEEE Trans. Power Electron., vol. 31, no. 6, pp. 4195–4205,
Jun. 2016.
[17] Y.-H. Ji, D.-Y. Jung, J.-H. Kim, T.-W. Lee, and C.-Y. Won, “A current
shaping method for PV-AC module DCM-flyback inverter under ccm
operation,” in Proc. IEEE Int. Conf. Power Electron. ECCE Asia, 2011,
pp. 2598–2605.
[18] Z. Zhang, X.-F. He, and Y.-F. Liu, “An optimal control method for pho-
tovoltaic grid-tied-interleaved flyback microinverters to achieve high effi-
ciency in wide load range,” IEEE Trans. Power Electron., vol. 28, no. 11,
pp. 5074–5087, Nov. 2013.
[19] B. Tamyurek and B. Kirimer, “An interleaved high-power flyback inverter
for photovoltaic applications,” IEEE Trans. Power Electron., vol. 30, no. 6,
pp. 3228–3241, Jun. 2015.
[20] Y. Li and R. Oruganti, “A low cost flyback CCM inverter for AC module
application,” IEEE Trans. Power Electron., vol. 27, no. 3, pp. 1295–1303,
Mar. 2012.
[21] C. Mi, H. Lin, and Y. Zhang, “Iterative learning control of antilock braking
of electric and hybrid vehicles,” IEEE Trans. Veh. Technol., vol. 54, no. 2,
pp. 486–494, Mar. 2005.
[22] A. Luo, X. Xu, L. Fang, H. Fang, J. Wu, and C. Wu, “Feedback-
feedforward pi-type iterative learning control strategy for hybrid active
power filter with injection circuit,” IEEE Trans. Ind. Electron., vol. 57,
no. 11, pp. 3767–3779, Feb. 2010.
[23] B. You, M. Kim, D. Lee, J. Lee, and J. Lee, “Iterative learning control of
molten steel level in a continuous casting process,” Control Eng. Pract.,
vol. 19, no. 3, pp. 234–242, Mar. 2011.
[24] J. Liu, P. Zanchetta, M. Degano, and E. Lavopa, “Control design and
implementation for high performance shunt active filters in aircraft
power grids,” IEEE Trans. Ind. Electron., vol. 59, no. 9, pp. 3604–3613,
Aug. 2012.
[25] P. Zanchetta, M. Degano, J. Liu, and P. Mattavelli, “Iterative learning con-
trol with variable sampling frequency for current control of grid-connected
converters in aircraft power systems,” IEE Trans. Ind. Appl., vol. 49,
no. 4, pp. 1548–1555, Apr. 2013.
[26] J. Sun, D. M. Mitchell, M. F. Greuel, P. T. Krein, and R. M. Bass, “Av-
eraged modeling of PWM converters operating in discontinuous conduc-
tion mode,” IEEE Trans. Power Electron., vol. 16, no. 4, pp. 482–492,
Jul. 2001.
[27] C. Freeman, P. Lewin, and E. Rogers, “Experimental evaluation of it-
erative learning control algorithms for non-minimum phase plants,” Int.
J. Control, vol. 78, no. 11, pp. 826–846, 2005.
Hyosin Kim (S’16) received the B.S. degree in elec-
trical engineering, in 2008, from Pohang University
of Science and Technology, Pohang, South Korea,
where he is currently working toward the Ph.D. de-
gree in electrical engineering.
His research interests include nonlinear system
analysis, intelligent control theory, and controller
design of power system.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 8, AUGUST 2017
Jin S. Lee (M’85) received the B.S. degree in elec-
tronics engineering from Seoul National University,
Seoul, South Korea, in 1975, the M.S. degree in elec-
trical engineering and computer science from the Uni-
versity of California, Berkeley, CA, USA, in 1980,
and the Ph.D. degree in system science from the Uni-
versity of California, Los Angeles, CA, in 1984.
From 1984 to 1985, he worked as a Member of the
Technical Staff at AT&T Bell Laboratories, Holmdel,
NJ, USA, and, from 1985 to 1989, as a Senior Mem-
ber of the Engineering Staff at GE Advanced Tech-
nology Laboratories, Mt. Laurel, NJ. Since 1989, he has been a Professor at
Pohang University of Science and Technology (POSTECH), Pohang, South
Korea. From 2000 to 2003, he has served as the Dean of Research Affairs
at POSTECH. From 2007 to 2012, he also served as the Dean of Academic
Affairs at POSTECH. He is currently the Head of Creative IT Engineering De-
partment and the Director of Future IT Innovation Laboratory at POSTECH.
His research interests include nonlinear systems and control, robotics, and
intelligent control.
Jih-Sheng (Jason) Lai (S’85–M’89–SM’93–F’07)
received M.S. and Ph.D. degrees in electrical engi-
neering from the University of Tennessee, Knoxville,
TN, USA, in 1985 and 1989, respectively.
In 1989, he joined the Electric Power Research
Institute (EPRI) Power Electronics Applications Cen-
ter, where he managed EPRI-sponsored power elec-
tronics research projects. In 1993, he joined the Oak
Ridge National Laboratory as the Power Electronics
Lead Scientist, where he initiated a high power elec-
tronics program and developed several novel high
power converters, including multilevel converters and soft-switching inverters.
In 1996, he joined the Virginia Polytechnic Institute and State University. He
is currently the James S. Tucker Professor in the Electrical and Computer En-
gineering Department and the Director of Future Energy Electronics Center.
He also holds the Honorary International Chair Professorship at the National
Taipei University of Technology, Taiwan and serves as a Visiting Professor
at Nanyang Technological University, Singapore. He published more than 360
refereed technical papers and 2 books and received 25 U.S. patents. His main
research interests include high efficiency power electronics conversions for high
power and energy applications.
Dr. Lai is the founding Chair of the 2001 IEEE Future Energy Challenge
and the 2016 IEEE Asian Conference on Energy, Power, and Transportation
Electrification; the General Chairs of IEEE Workshop on Computers in Power
Electronics (COMPEL 2000) and the IEEE Applied Power Electronics Con-
ference and Exposition (APEC 2005). He received the Technical Achievement
Award in Lockheed Martin Award Night, 2 Journal Paper Awards, 11 Best Paper
Awards from IEEE sponsored conferences, and Virginia Tech Deans Award on
Research Excellence. He led the student teams to win Top Three Finalist in the
Google Little Box Challenge in 2016, the Grand Prize Award from International
Future Energy Challenge in 2011, and the Grand Prize Award in Texas Instru-
ments Engibous Analog Design Competition in 2009. He also received the 2016
IEEE IAS Gerald Kliman Innovator Award.
Minsung Kim (M’14) was born in Ulsan, South
Korea, in 1986. He received the B.S. degree in elec-
trical engineering from Pohang University of Sci-
ence and Technology (POSTECH), Pohang, Korea,
in 2004, and the Ph.D. degree in electrical engineer-
ing from POSTECH, in 2013.
Since 2013, he has been in the Department of Cre-
ative IT Engineering and Future IT Research Labo-
ratory, POSTECH, where he is currently a Research
Assistant Professor. Since 2016, he has been working
as a Research Scholar at Virginia Tech’s Future En-
ergy Electronics Center, Blacksburg, VA, USA. His current research interests
include renewable energy system, power conversion circuit design, nonlinear
system analysis, and controller design for industrial process.