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Electronics Projects
Vol. 22
EFY Books & Publications
EFY is a reputed information house, specialising in electronics and information technology
magazines. It also publishes directories and books on several topics. Its current publications are:
1. Electronics Projects, Vol. 1: A compilation of selected construction projects and circuit ideas Rs 120
published in Electronics For You magazines during 1979 and 1980.
2. Electronics Projects, Vol. 2 to 19 (English version): Yearly compilations (1981 to 1998) of Rs 120 (each)
interesting and useful construction projects and circuit ideas published in Electronics For You.
3. Electronics Projects, Vol. 20, 21 and 22 (with CD): Yearly compilations (1999 to 2001). Rs 150 (each)
4. Electronics Projects, Vol. 16 (fgUnh laLdj.k): Yearly compilations (1995) of interesting and Rs 95
useful construction projects and circuit ideas published in Electronics For You.
1. Learn to Use Microprocessors (with floppy): By K. Padmanabhan and S. Ananthi (fourth enlarged edition). Rs 180
An EFY publication with floppy disk. Extremely useful for the study of 8-bit processors at minimum expense.
2. ABC of Amateur Radio and Citizen Band: Authored by Rajesh Verma, VU2RVM, it deals Rs 75
exhaustively with the subject—giving a lot of practical information, besides theory.
3. Batteries: By D.Venkatasubbiah. Describes the ins and outs of almost all types of batteries used Rs 60
in electronic appliances.

1. EFY Annual Guide: Includes Directory of Indian manufacturing and distributing units, Buyers’ Guide and Rs 300 (with CD)
Index of Brand Names, plus lots of other useful information.
2. ‘i.t.’ Directory: First comprehensive directory on IT industry covering hardware, software, telecom, Rs 250 (with CD)
dotcom and training institues.
3. Technical Educational Directory: Includes course-wise and state/city-wise listings of technical educational Rs 100
institutes in India, besides the alphabetical main directory offering all the relevant information about them.
1. Electronics For You (EFY): In regular publication since 1969, EFY is the natural choice for the entire Rs 60 (with CD)
electronics fraternity, be it the businessmen, industry professionals or hobbyists. From microcontrollers to Rs 35 (without CD)
DVD players, from PCB designing software to UPS systems, all are covered every month in EFY.
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two things in common—a background related to IT and the thirst to know more. Topics covered boast technical
depth and aim to assist in better usage of IT in organisations.
4. Facts For You: A monthly magazine on business and economic affairs. It aims to update the top decision makers Rs 50
on key industry trends through its regular assortment of Market Surveys and other important information.
5. ePower: Published every alternate month for the electronic-power industry, primarily consists of all electronic Rs 50
power-supply equipment, and their related components and services. A must read for those in this industry and
those catering to it.
6. BenefIT: A technology magazine for businessmen explaining how they can benefit from IT. Rs 20

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VOL. 22

EFY Enterprises Pvt Ltd

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New Delhi 110020
© EFY Enterprises Pvt Ltd.
First Published in this Edition, December 2006

All rights reserved. No part of this book may be reproduced in any
form without the written permission of the publishers.

ISBN 81-88152-17-X

Published by Ramesh Chopra for EFY Enterprises Pvt Ltd,

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Typeset at EFY Enterprises Pvt Ltd and
Printed at Nutech Photolithographers, B-38, Okhla Industrial Area,
Phase-1, New Delhi 110020
This volume of Electronics Projects is the twenty second in the
series published by EFY Enterprises Pvt Ltd. It is a compilation
of 21 construction projects and 66 circuit ideas published in
‘Electronics For You’ magazine during 2001.

We are also including a CD with this volume, which not only con-
tains the datasheets of major components used in construction proj-
ects but also the software source code and related files pertaining
to various projects. This will enable a reader to copy these files
directly to his PC and compile/run the program as necessary, without
having to prepare them again using the keyboard. In addition, the CD
carries useful software, tutorials and other goodies (refer ‘contents’
in CD).

In keeping with the past trend, all relevant modifications, corrections

and additions sent by the readers and authors have been incorporated in
the articles. Queries from readers along with the replies from authors/
EFY have also been published towards the end of relevant articles. It
is a sincere endeavour on our part to make each project as error-free
and comprehensive as possible. However, EFY cannot resume any
responsibility if readers are unable to make a circuit successfully, for
whatever reason.

This collection of a large number of tested circuit ideas and

construction projects in a handy volume would provide all classes
of electronics enthusiasts—be they students, teachers, hobbyists or
professionals—with a valuable source of electronic circuits, which
can be fabricated using readily-available and reasonably-priced
components. These circuits could either be used independently or in
combination with other circuits, described in this and other volumes.
We are sure that this volume, like its predecessors, will generate tre-
mendous interest among its readers.

Section A: Construction Projects

1. Build Your Own Pentium III PC.................................................................................. 3

2. Automatic Room Light Controller............................................................................... 17
3. Intelligent Water Level Controller............................................................................... 21
4. A Unique Liquid Level Indicator................................................................................. 25
5. Interface Your Printer with 8085 Microprocessor....................................................... 28
6. Morse Processor........................................................................................................... 33

7. Access-Control System................................................................................................ 42
8. Telephone Line-Interfaced Generic Switching System............................................... 46
9. Programmable Melody Generator............................................................................... 55
10. Auto Control for 3-Phase Motors................................................................................ 66
11. Telephone Remote Control.......................................................................................... 72
12. Microcontroller-Based School Timer.......................................................................... 75
13. Digital Capacitance-cum-Frequency Meter................................................................. 80
14. Fluid-Level Controller with Indicator......................................................................... 84
15. MGMA—A Mighty Gadget with Multiple Applications............................................ 87
16. Traffic and Street Light Controller.............................................................................. 91
17. Lead-Acid Battery Charger with Active Power Control.............................................. 98
18. Amplitude Measurement of Sub-Microsecond Pulses................................................ 101
19. Automatic Submersible Pump Controller.................................................................... 104
20. Transistor Curve Tracer............................................................................................... 107
21. Tripping Sequence Recorder-cum-Indicator................................................................ 113

Section B: Circuit Ideas

1. Electronic Starter for Single-Phase Motors................................................................. 119

2. Modem ‘On/Off’ Indicator.......................................................................................... 120
3. Touch-Select Audio Source......................................................................................... 121
4. Precision Attenuator with Digital Control................................................................... 121
5. Precision Amplifier with Digital Control..................................................................... 122
6. Random Number Generator Based Game................................................................... 123
7. 9-Line Telephone Sharer.............................................................................................. 124
8. Electronic Card Lock System...................................................................................... 126
9. Pulsed Operation of a CW Laser Diode....................................................................... 127
10. Generation of 1-Sec. Pulses Spaced 5-Sec. Apart....................................................... 128
11. High-/Low-Voltage Cutout with Timer........................................................................ 129
12. Automatic Heat Detector............................................................................................. 130
13. Musical ‘Touch’ Bell.................................................................................................... 131
14. Non-Contact Liquid-Level Controller......................................................................... 131
15. High-Power Bicycle Horn........................................................................................... 133
16. AC Mains Phase-Sequence Indicator.......................................................................... 133
17. Luxurious Toilet/Bathroom Facility............................................................................ 135
18. EEPROM W27C512 (Winbond) Eraser...................................................................... 136
19. Intelligent Electronic Lock.......................................................................................... 137
20. Stable 455KHz BFO for SSB Reception..................................................................... 139
21. Auto Shut-off for Cassette Players and Amplifiers...................................................... 139
22. House Security System................................................................................................ 141
23. Simple Water-Level Indicator-cum-Alarm.................................................................. 142
24. Precision Inductance and Capacitance Meter.............................................................. 142
25. Under-/Over-Voltage Beep for Manual Stabiliser....................................................... 144
26. Ultra-Sensitive Solidstate Clap Switch........................................................................ 145
27. 15-Step Digital Power Supply..................................................................................... 145
28. Microphone for Computer........................................................................................... 147
29. Versatile Zener Diode Tester........................................................................................ 147
30. DTMF Proximity Detector.......................................................................................... 149
31. Stepper Motor Control................................................................................................. 149
32. Low-Cost Intercom...................................................................................................... 150
33. High-Power Car Battery Eliminator............................................................................ 151
34. Automatic Plant Irrigator............................................................................................. 152
35. Simple Telephone Ring Tone Generator...................................................................... 152
36. Dual-Input High-Fidelity Audio Mixer....................................................................... 153
37. Unipolar/Bipolar Triangular and Bipolar Square Wave Generator.............................. 154
38. Anti-Theft Security for Car Audios............................................................................. 155
39. PC-Based Dial Clock-cum-Electronic Roulette.......................................................... 156
40. Long-Range Cordless Burglar Alarm.......................................................................... 157
41. Water-Level Controller................................................................................................ 158
42. Invisible Broken Wire Detector................................................................................... 160
43. PC-Based Multi-Mode Light Chaser........................................................................... 161
44. Fuse Status Indicators for Power-Supplies.................................................................. 163
45. A Hierarchical Priority Encoder.................................................................................. 164
46. Digital Mains Voltage Indicator................................................................................... 165
47. Electronic Dice............................................................................................................ 166
48. Light-Operated Organ.................................................................................................. 168
49. Stereo Tape Head Preamplifier for PC Sound Card..................................................... 168
50. Heart Beat Monitor...................................................................................................... 169
51. Digital Fan Regulator.................................................................................................. 170

52. Running Lights and Running Holes............................................................................ 171
53. A Simple Transistor Tester........................................................................................... 172
54. 12V, 3A Power Supply................................................................................................. 172
55. Speller Effect Sign Display.......................................................................................... 173
56. Darkroom Timer.......................................................................................................... 174
57. Active Shortwave Antenna.......................................................................................... 174
58. Long-Range Target Shooter......................................................................................... 175
59. Power Supply for Walkie-Talkies................................................................................ 176
60. High-Performance Interruption Detector..................................................................... 177
61. Digital Relay Tester for RAX and MAX..................................................................... 178
62. Fastest Finger First Indicator....................................................................................... 179
63. Decorative Signboard.................................................................................................. 180
64. Condenser Mic Audio Amplifier.................................................................................. 181
65. Smoke Alarm............................................................................................................... 182
66. Overload Protector with Reset Button......................................................................... 183
Page = 1
Build Your Own
Pentium III PC
K.c. Bhasin and neeraj Kundra

he procedure presented here there must be some slack after these ence between them.
would enable you to assemble are installed and connected.) This will • The motherboard contains sensitive
your own multimedia personal improve the cooling and reduce the components, which can be easily dam-
computer. It is assumed that you have a chances of electromagnetic interfer- aged by static electricity. Therefore the
fundamental knowledge of how a PC func- motherboard should remain

tions and some basics of electronics. By in its original antistatic
way of tools you only need Philips-head envelope until it is required
and flat-blade screwdrivers. A simple mul- for installation. When it is
timeter is the only test equipment that taken out from the enve-
you would ever require during assembly, lope, it should be immedi-
for AC and DC voltage measurement. ately placed on a suitable
All the parts needed to assemble grounded conductive sur-
this multimedia PC with processor face. The motherboard itself
speed of 700 MHz are listed under Parts should be held from edges
List. The cost of parts may vary from and the person taking it
dealer to dealer and also with time.
It is suggested to source these items
from authorised dealers who would meet
their warranty obligations. We have also
mentioned the brand names of the parts
that we used during assembly of the basic
unit. It is, however, not necessary to use
identical makes, except, of course, the
main processor and the motherboard,
based on identical chipset mentioned later
in this article.

Before starting the actual assembly of
the PC system, the following precautions
would help you to avoid any mishap dur-
ing the assembly process:
• While the motherboard has to
be fitted at a fixed place inside the
PC cabinet, the locations of add-on
cards (as and when used) and the
drives (hard disk drive, floppy disk
drive, and CD-ROM drive) within
the drives’ bay of the cabinet can be
changed within certain limits. But it
is better to place them far away from
each other. (Of course, the length of
the cable provided for interconnec-
tions to the motherboard or add-on
cards has to be taken into account, as Fig. 1: Block diagram of motherboard employing 810E chipset


would be some differences between any two
Key Features of Motherboard Using Intel 810/810E Chipset makes of the motherboard.
Processor • Start the assembly only after going
• Full support for the Intel Pentium III and Celeron processors using PGA370 socket.
• Supports 66MHz and 100MHz bus speed including all PGA370. through this article at least once. Only
• Supports 133MHz bus speed (810E chipset version only). when you feel at ease, start the assembly
VRM 8.2 (Voltage Regulator Modules) On-board of your machine as per the guidelines
• Flexible motherboard design with on-board VRM 8.2, easy to upgrade with future proces- included in this article and the applicable
sors. user’s manuals.
System Memory • Never try to insert a card in PC slots
• A total of two 168-pin DIMM sockets (3.3V SDRAM types). or try to plug/unplug a connector with
• Memory size up to 512MB.
• Supports SDRAM at 66/100 (PC100) MHz. power supply to the PC ‘on’.
• Supports symmetrical and asymmetrical DRAM addressing. • Ensure that the mains 3-pin socket
• Banks of different DRAM types and depths can be mixed. or the socket on your stabiliser/UPS that
System BIOS you would be using for connection to the
• 4-Mbit Intel Firmware hub (with security feature). SMPS of the computer and/or the monitor
• PnP, APM, ATAPI, and Windows 95/98.
is correctly wired with ‘live’ line on your
• Full support of ACPI & DMI.
• Auto-detects and supports LBA hard disks with capacities over 8.4 GB. right hand side. To find out which line is
• Easily upgradable by end-user. live (phase) and which one is neutral, use
On-board I/O your multimeter in 250V AC or higher
• Supports two PCI-enhanced IDEs PIO mode 3, mode 4, and ultra DMA 33/66 channels (optional range. The live line will show full voltage
ultra DMA 66 cable). Twin headers for four IDE devices including IDE HDDs and CDROMs. w.r.t. neutral pin and nearly the same
• One ECP/EPP parallel port (via a header).
• Two 16550A UART parallel port (via a header). voltage w.r.t. the ground pin, while the
• One floppy port. Supports two FDDs of 360KB, 720KB, 1.2MB, 1.44MB, or 2.88MB (via a neutral pin (w.r.t. ground pin) would/
header). should show very little voltage (less than
• Four USB ports (via a header, optional). 10V AC). Else, the mains wiring has a
• PS/2 mouse port (via a header, optional).
• AT keyboard port (factory option for PS/2 type).
problem that needs to be set right.
• Infrared (IrDA) support. • Don’t drop any screw or other
Plug-and-play conducting material on your PC’s moth-
• Supports plug-and-play specification 1.1. erboard as that might cause shorting of
• Plug-and-play for DOS, Windows 3.X, Windows 95, as well as Windows 98. pins/tracks and consequent damage when
• Fully steerable PCI interrupts. you switch it ‘on’.
On-board VGA • Make sure that you have a large, flat
• Hardware motion compensation for S/W MPEG2 decode (DVD).
• 3-D hyper pipelined architecture.
surface area to work on. That will reduce
• Full 2-D hardware acceleration. the chances of small screws etc falling and
• 3-D graphics visual enhancements. getting lost.
• Dynamic display memory (DDM) or optional 4MB display cache (810DC100 or 810E chipset • While screwing components on to
version only).
the chassis, do not use excessive force
• Resolution up to 1,600x1,200.
• Win 95 vxd, Win 98/NT5 mini-port drivers support. as that may damage the screws or their
• VGA port (via a header). grooves/holes.
On-board AC97 Sound
• Integrated AC97 controller with standard AC97 CODEC.
• Direct Sound and Sound Blaster compatible. Pentium III technology
• Full-duplex 16-bit record and playback.
• PnP and APM 1.2 support. Some points to be noted about the Pen-
• Win 95, 98, and NT drivers ready. tium III processor being used here are:
• Line-in, line-out, mic-in and MIDI/game port. • Intel’s Pentium III processors sup-
Power Management port various clock speeds from 450MHz
• Supports SMM, APM and ACPI. to 933 MHz. The one meant for desktop
• Break switch for instant suspend/resume on system operations. version goes up to 1.13 GHz. (We are us-
• Energy star ‘Green PC’-compliant.
• WAKE-ON-LAN (WOL) header support. ing here a 700MHz version.)
• External modem ring-in wake-up support. • Integrates P6 dynamic execution
Expansion Slots architecture and a dual independent bus
• One audio modem riser (AMR). (DIB) architecture.
• Four PCI bus master slots (ver 2.1 compliant). • Has a multi transaction system
out should wear an antistatic wrist for DIMMS and cards. • Incorporates Intel’s MMX media
strap that is properly grounded. In • If you are using a motherboard dif- enhancement technology.
the absence of a proper wrist strap, ferent from the one mentioned in the parts • Supports Internet streaming
you may make one on your own using list, modify the guidelines mentioned here single-instruction multiple data (SIMD)
a peeled off multi-strand copper cable as per the directions given in the user’s extensions.
and ground it properly. Similar han- manual (which is supplied with the moth- • Compared to Pentium II, it has 70
dling precautions are also required erboard you may be using), since there new instructions, enabling advanced 3-D


imaging, streaming audio and video, and
speech recognition.
• Has a 32k (16k for instructions and
another 16k for data) as primary (level 1)
non-blocking cache for rapid access to most
heavily used data. In addition, it has 512k
unified, non-blocking (level 2) cache or
256k advanced transfer cache integrated
on die, which runs at the core frequency
of the processor with very low memory
access time.

The motherboard
While the processor is the most important
part of the motherboard, the motherboard
itself is the most important part of the com-
puter system. Together with the chipset, it
forms the brain of your computer.
The modern motherboards do away

with the large number of controller chips
and cards that were used in the older XT
and AT versions, such as clock generator,
bus controller, timer/counter, monitor/
printer adopter, FDD and HDD control-
lers, multi-I/O or super IDE controller
card, and DMA controller. All the func-
tions performed by these controllers/cards
(and others) are now performed by just
two or three chips and that too at much
higher speed.
The motherboard based on Intel’s
810/810E chipset (being used in the
Fig. 2: PC Partner motherboard layout diagram
present system) combines the advan-
tage of a multimedia (full-screen, full-
Table I motion video with realistic graphics)
and enhanced Internet performance at
JP1, JP2—System Bus Frequency
a budget price. With this motherboard,
JP1 JP2 CPU Clock Speed
one does not need separate sound,
1 Open 1 Open 133MHz (100MHz CPU run at 133MHz Front Side Bus) video, or graphics enhancement cards.
1 Open 1 1-2 100MHz (66MHz CPU run at 100MHz Front Side Bus) A block diagram of a motherboard
1 Close* 1 1-2* Auto* employing 810E chipset is shown in
Fig. 1.
JP15 - BIOS (Firm Ware Hub) Key features. The main features
Boot Block Protect JP4 - CMOS Clear of the PC Partner motherboard used
JP15 Function JP4 Function in this project are shown in the accom-
panying box. A layout diagram showing
1 Close* Unlocked* 1 1-2* Normal
the relative position of the jumpers,
1 Open Locked 1 2-3 CMOS Clear
connectors, major components, PCI
slots, and DIMM and CPU sockets is
JP34 - On Board Crystal PCI Sound (Optional) JP29 - Keyboard Power On Select shown in Fig. 2.
JP34 Function JP29 Function Jumper settings. Positions of vari-
1 1-2* Powered by +5V* ous jumpers within the motherboard are
1 1-2* PCI Sound Enable*
1 2-3 Powered by +5V Standby shown in Fig. 3. The jumper settings for
1 2-3 PCI Sound Disable (Allows Keyboard Power On) enabling various functions are shown in
Table I. Default settings are shown with
* Default settings
JP35, JP36 - On Board AC97 Codec Sound an asterisk mark. (Note. Leave all these
# P= jumpers in their default setting posi-
JP35 JP36 Function
Primary AMR, tions for the present project. The proces-
1 1-2* 1 2-3* (S)# AC97 Sound Enable*
S = Secondary AMR sor speed setting is to be done through
1 2-3 1 1-2 (P)# AC97 Sound Disable
CMOS setup as indicated later.)


manual with 3-year lim- exposed, and two 89mm (3.5-inch) inter-
ited warranty. Similarly, en- nal bays.
sure that the 64MB SDRAM It has 200W SMPS of VESTA make
DIMM bears the label (such pre-installed (+5V @16A, +12V @6A, -5V
as PC100) to indicate that it @0.5A, and –12V @0.5A). LEDs with 2-pin
is compatible with 100MHz SIP connectors are provided for power ‘on’
system bus speed. (green and white twisted wires), HDD
Checking cabinet and (orange and white twisted wires) activity
its accessories. The AT indication, and to reset push switch (blue
Fig. 3: Jumper positions within motherboard mini tower PC cabinet and white twisted wires), which are re-
measures approx.180mm (width) x quired to be connected to the appropriate
330mm (height) x 360mm (depth). The pin pairs (Berg type) on the motherboard.
drive bays comprise two 133.35mm (Please refer Fig. 2 to spot the correspond-
(5.25-inch) exposed, one 89mm (3.5-inch) ing connectors near JP34/JP4, but for the

Fig. 4: Power on/off switch wiring

Hardware installation
and checkout
Verifying components. First, carry out
a physical check of all the items as per
the parts list to ensure that there are no
apparent deficiencies and no signs of any
physical damage, and the parts are correct
as indicated by the labels on the items/pack-
ages. For example, the Pentium processor
pack should comprise Pentium III proces-
sor labeled 700MHz/100MHz system bus,
fan/heat-sink assembly, and installation Fig. 6: DIMM installation
time being, leave them alone.) An 8-ohm,
0.5W speaker (with black and red twisted
A wires and 4-pin connector), to go into
corresponding 4-pin speaker connector
on motherboard, also forms part of the
Checking SMPS. The control con-
sole on the cabinet also has a DPDT
(a) push-button switch to switch on the
mains (230V AC) to SMPS of the compu-
ter and a parallel-wired 3-pin AC socket
(c) on SMPS for connecting AC power to the
(b) A monitor used with the PC. At this stage,
slide the shielded connectors of the four
power supply wires of the SMPS into the
corresponding connectors on the DPDT
(d) switch as per the diagram provided on
the SMPS case (top side). The same is
reproduced in Fig. 4. The white and
black wires have a return path via blue
and brown wires, respectively, when the
power supply switch is flipped ‘on’. Con-
nect the 3-pin power cord provided with
the cabinet to the socket at the back
Fig. 5: Installation of Pentium III processor in PGA 370 socket of SMPS and plug 3-pin plug into the


Parts List female power Table IV
connectors with
Item Description Make Parallel-Port Connector CN6
projection in the
AT cabinet with SMPS, power cord, Pin Signal Name Pin Signal Name
power switch, reset switch, speaker, middle. If these
LEDs, complete with connectors and are held such 1 Strobe- 14 AFD
installation hardware packet. IMIL, Chen- that all black 2 Data bit 0 15 Error
nai wires are adja- 3 Data bit 1 16 INIT
Motherboard with Intel’s 810 4 Data bit 2 17 SLCTIN
cent to each oth-
chipset PC Partner, USA along with 5 Data bit 3 18 GND
er, this forms a 6 Data bit 4 19 GND
user’s manual, CD (containing
drivers for onboard devices) and 12-pin AT power 7 Data bit 5 20 GND
headers for motherboard connectors. supply connec- 8 Data bit 6 21 GND
* (refer check-list) PC Partner tor with orange 9 Data bit 7 22 GND
Pentium PIII-700 Processor Intel wire (carrying 10 ACK 23 GND
64MB (PC 100)SDRAM (168-pin DIMM) Alpha 11 Busy 24 GND
HDD (hard disk drive) Seagate
power good sig-
12 PE 25 GND
FDD (floppy disk drive) 3.5” Sony nal) emanating 13 SLCT 26 GND
CD-ROM drive 52X with audio cable Samsung from pin 1.
Keyboard Logitech The volt-
Mouse(3-button) Logitech ages on various Table V
Colour Monitor 14” LG COM1/COM2–Serial Connectors CN4*, CN5*
USB connector bracket with 2 headers - pins of this joint
12-pin connector Pin Signal Name Pin Signal Name
*list of connectors/brackets forming part of motherboard.

with their colour 1 DCD 6 DSR
Header (connectors with cables) for HDD (40-pin twin) - one 2 SIN 7 RTS
Header for FDD (34-pin twin) - one codes are shown
Header for PS/2 mouse - one in Table II. 4 DTR 9 RI
Port bracket set with headers for: Check the cor- 5 GND 10 NC
(a) VGA (15-pin ‘D’ connector ending into 16-pin FRC and rectness of these *These connectors are for the serial port
parallel port (25-pin ‘D’ ending into 26-pin FRC) - one
(b) Com1 and Com2 (two 9-pin ‘D’ ending into 10-pin FRC) - two
voltages within bracket. Both connectors have the same pin-
the range as outs.
(c) Onboard AC97 sound codec (line-in, line-out, mic-in and
MIDI/game port ending into 26-pin FRC) - one given in Table
(red wire)] meant for various drives are
II. Then switch
also correct.
socket of the mains supply or the UPS, off the power
Motherboard fitment. The chassis
as appropriate. supply and take out the 3-pin plug
on which motherboard is to be mounted
Switch on the SMPS. The fan blower from the mains socket. If the AT power
can be easily removed from the PC
inside the SMPS should start running, connector voltages are correct, you
cabinet. Unscrew it and gently slide it
indicating availability of +12V supply to can safely assume that voltages in all
out from the main casing. Lay it flatly
the fan. Now verify all DC outputs of the other power connectors [4-pin Molex,
on the antistatic workbench (properly
SMPS as follows. carrying +12V (yellow wire) followed
grounded conductive surface). Mark the
There are two distinct 6-pin Molex by two black wires (ground) and +5V
side facing the keyboard connecter cutout
Table II on the chassis.
At Power Connector Pin Voltages All motherboards have standard
Pin Voltage Range Wire Pin Voltage Range Wire mounting holes. The hardware supplied
Colour Colour comprises plastic and metallic mother-
1 *P. G. 4.5V (min) Orange 7 Ground - Black board retaining fasteners/screw-holders.
2 +5V +5%/-4% Red 8 Ground - Black Metal-type screw-holders are better as
3 +12V +5%/-4% Yellow 9 -5V +10%/-8% White these have better strength and also these
4 -12V +10%/-9% Blue 10 +5V +5%/-4% Red ground the motherboard to the chassis.
5 Ground - Black 11 +5V +5%/-4% Red
6 Ground - Black 12 +5V +5%/-4% Red You may use four metallic screw-holders
*P. G. = Power good signal which is +5V (delayed, 100ms – 500ms).
for the four corner holes in the mother-
board, while the plastic fasteners may be
used for the middle
Table III
holes of the mother-
VGA–VGA Out Connector CN34*
Pin Signal Name Pin Signal Name
Before attempting
1 Red signal 9 NC fitment of the mother-
2 Green signal 10 GND
3 Blue signal 11 NC board, align it on the
4 NC 12 Display data channel data chassis such that the
5 GND 13 Horizontal sync keyboard connector
6 GND 14 Vertical sync on the motherboard
7 GND 15 Display data channel clock
is towards the side
*This connector is for the VGA display port. Connect a marked earlier for
VGA or higher resolution display monitor to it. this purpose. Now


Table VI Table IX
Audio & Game Port Pin Header CN341* Floppy Connector Pin Definitions (JP26)
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pin Function Pin Function

1 VCC 8 GND 15 NC 22 MIC-in 1 GND 2 FDHDIN

2 VCC 9 XTD 16 VCC 23 NC 3 GND 4 Reserved
3 SWC 10 GND 17 Line-out 24 GND 5 Key 6 FDEDIN
4 SWA 11 SWB 18 Line-out 25 Line-in 7 GND 8 Index-
5 XTC 12 XTB 19 GND 26 Line-in 9 GND 10 Morot enable
6 XTA 13 MSIN 20 GND 11 GND 12 Drive select B-
7 MSOUT 14 SWD 21 MIC-in 13 GND 14 Drive select A-
15 GND 16 Motor enable
*This header is for the audio port bracket. It connects audio ports-stereo line-out, stereo line-in 17 GND 18 DIR-
and microphone—and a game port (for a joystick or MIDI device) to your system. 19 GND 20 STEP-
21 GND 22 Write data-
fit all the screw- Table VIII 23 GND 24 Write gate-
Table VII 25 GND 26 Track 00-
CN7: USB Port IDE Connector Pin Definitions (J18, J19) 27 GND 28 Write protect-
as discussed above,
Pin Assignment Pin Function Pin Function 29 GND 30 Read data-
on the chassis, oppo-
1 VCC 1 Reset IDE 2 GND 31 GND 32 Side 1 select-
site the holes on the 33 GND 34 Diskette
2 GND 3 Host data 7 4 Host data 8
motherboard, using
3 USBP1- 5 Host data 6 6 Host data 9
4 USBP0+ Philips screws pro- 7 Host data 5 8 Host data 10 Table X
5 USBP1+ vided in the hard- 9 Host data 4 10 Host data 11 PS/2 Mouse Connector*
6 USBP0- ware packet. Align 11 Host data 3 12 Host data 12
7 GND Pin Description Pin Description
the motherboard 13 Host data 2 14 Host data 13
8 VCC 15 Host data 1 16 Host data 14 1 Mouse data 2 NC
above the fasteners
17 Host data 0 18 Host data 15 3 Ground 4 +5V
and push it down, 5 Mouse clock 6 NC
19 GND 20 Key
so that the self-retaining heads of plastic 21 DRQ3 22 GND *This connector is for the optional PS/2 mouse
fasteners pop out from the respective 23 I/O Write- 24 GND port bracket.
holes. For the metallic screw-holders, use 25 I/O Read- 26 GND
Philips screws to secure the motherboard 27 IOCHRDY 28 BALE notches at the bottom edge of DIMM with
to the chassis firmly without using exces- 29 DACK3- 30 GND the corresponding keys in the socket.
sive force. 31 IRQ14 32 IOCS16- 3. Push the DIMM vertically down,
33 Addr 1 34 GND inserting its bottom edge into the socket.
Pentium processor mounting (re-
35 Addr 0 36 Addr 2
fer Fig. 5). The processor is to be fitted 4. Once seated properly, push DIMM
37 Chip select 0 38 Chip select 1-
into the PGA370 (pin grid array with 39 Activity 40 GND down from the top edge until the retainer
370-pin recesses) socket, which is a ZIF clips snap into place and the DIMM is
(zero insertion force) socket. Take out screwdriver tip to do this, but be careful firmly held into its position.
the processor and its heat sink fitted with that screwdriver does not slip and dam- Cable set installation. While the
cooling fan and heat sink retainer clip ‘D’. age the tracks on the motherboard [refer motherboard chassis is still not replaced
Now proceed as follows: Fig. 5(d)]. into the case, you could install one of the
1. Lift handle ‘A’ to its vertical posi- 6. Connect the 3-pin fan connector to ends of all the cables originating from the
tion [refer Fig. 5(a)]. the corresponding connector CN17 marked motherboard. The installation of cables,
2. Align the processor pins with the ‘CPU Fan’ on the motherboard. which originated from SMPS and the con-
socket holes and insert the processor into DIMM installation (Fig. 6). There trol panel of the case (LEDs, reset switch,
its socket [refer Fig. 5(b)]. are two 168-pin SDRAM DIMM sockets and the speaker), would be completed
3. With the processor in its socket, on the motherboard with socket 1 marked after the motherboard chassis is screwed
lower handle ‘A’ and bring it to its closed ‘1’ and socket 2 left unmarked. The back into the PC case.
(horizontal) position [refer Fig. 5(c)]. two sockets can together accept 512MB The cables to be connected to the
4. Orient the heat sink (with fan on SDRAM (i.e. up to 256 MB each). We FRC-type male connectors/headers on the
top) such that the depression on one side propose to install a single 64MB DIMM, motherboard are listed below, and the pin
of the heat sink matches the correspond- which is quite adequate for current type assignments are shown in the referred
ing projection on PGA370 socket, and of applications. It can be inserted into any tables. On the motherboard, normally,
place it (along with fan) over the proces- of the two sockets and the same will be only start pin 1 is indicated. In an FRC
sor [refer Fig. 5(c)]. automatically suitably configured during connector, all odd number pins are in one
5. On the PGA370 socket, there are setup. Remove the DIMM from its anti- row while even number pins are in the
two small projections on opposite sides, static envelope, holding it by its edges. opposite row; pin 2 is opposite pin 1, pin 4
in which the heat sink clip has to be Proceed as follows: is opposite pin 3, and so on.
inserted. While it is fairly easy to insert 1. Using fingertips, push the retainer Pin 1 on the mating FRC female con-
one side, it is rather tricky to insert the clips on either side of the DIMM socket nector can be identified by an arrow mark
left-out side as it needs to be pulled down slightly away from the socket. over it. Ribbon cable wire going into pin
with considerable force to engage it into 2. Position the DIMM to be installed 1 is of red (sometimes blue) colour. Some
the projection. You may use the flat above the socket, aligning the two small of the FRC connector pairs have a notch


to floppy drive (DS1 in The HDD can now be installed at the
Fig.7). lowest closed (without any cutout in front)
Let us configure the position in the drive bay. Secure it like the
HDD as primary master other drives using four Philips screws.
and CD-ROM drive as • Completing the hardware in-
primary slave using a sin- stallation. After having completed the
gle cable emanating from installation of drives and the cable set
CN1 (IDE-1 header) on the of the motherboard, install back the as-
Fig. 7: Floppy drive cable for connecting up to two FDDs motherboard (refer Fig. 8). sembled motherboard chassis (complete
(We could alternatively configure CD- with its cable/connector set) into the PC
ROM drive as secondary master and cabinet and then complete the cabling
connect it directly to CN2 (IDE-2 con- as follows.
nector) in motherboard, using another You may start with AT power supply
40-pin cable/connector.) connectors. By now you are familiar with
The jumper on HDD should be used two 6-pin Molex connectors from SMPS
to short pins 7 and 8 on the jumper block used for powering the motherboard (re-
at the rear of HDD (refer Fig. 9). Simi- fer paragraph under heading ‘Checking
larly, there is a jumper block at the rear SMPS’ in Part I). Take connecter with
of CD-ROM drive with the pairs of pins orange wire (PG signal) first and align it
marked as CS (cable select), SL (slave), over pin 1 of PW1 connector on mother-

and MA (master). Ensure that jumper board. Projections on Molex connector of
is used in the middle to select the slave SMPS would engage into corresponding
mode for CD-ROM. The cable connection holes in PW1 connector. Once you have
Fig. 8: Connection of HDD and CD-ROM drive arrangement for HDD and CD-ROM is engaged the connector in this fashion,
using IDE-1 header shown in Fig. 8. make it vertical and then simply slide it
Before installation of drives, note down. It will snap into its position. (Be
and the corresponding projection, which down pin-1 orientation/position of the careful not to bend the pins and ensure
serves as a key so that they can go only 34-/40-pin interface cable connectors on that you have not engaged the wrong
the correct way. The cables used for the the drives. pins.) Similarly, insert the other 6-pin
drives have an additional connector in The CD-ROM drive may be installed Molex connector in the adjacent pins of
the middle (for slave in case of HDD and in the topmost position for 13.33cm AT power connector. On installation, all
drive B in case of FDD, which will be ex- (5.25-inch) drive, after pushing out the black coloured wires will be adjacent to
plained later). Using the tips given here, plastic piece (used for protection) cover- each other.
you can install the motherboard end of ing the cutout in this drive’s bay. Align Some of the connectors originating
the following cables: it from the front side of the case to en- from the motherboard (e.g. COM1, COM2,
• 16-pin VGA connector CN34 (refer sure that it is flush with the cabinet’s and VGA connectors) can be secured into
Table III). external surface. Using four Philips the cutouts provided on the case below the
• 26-pin parallel-port connector CN6 screws (6-32 UNC) secure it in proper SMPS. Thus secure the ‘D’ connectors for
(refer Table IV). horizontal position. The screws should COM1, COM2, and VGA into the respec-
• 10-pin serial/com ports 1 and 2, CN4 not be allowed to go more than 3.5 mm tive cutouts using Philips screws. This
and CN5 (refer Table V). into the threaded holes. saves the precious space inside the PC
• 26-pin sound cable connector CN31 Suitable cutout also exists in the drive case and gives it an ethical look.
(refer Table VI). bay for installing the 8.9cm (3.5-inch) For accommodating the panel/bracket
• 8-pin USB connector CN7 (refer floppy drive. Before fitting, ensure that for 25-pin ‘D’ connector of parallel port and
Table VII). drive door in the front opens downward PS/2 mouse as well as audio panel/bracket,
• 40-pin IDE-1 connector for HDD/CD- (hinged towards top). For installing floppy remove two of the cutouts from the rear
ROM drive CN1 (refer Table VIII). drive follow the same procedure as used of the case by just forcing them out with
• 34-pin FDD connector CN3 (refer for fixing CD-ROM drive. hands, and secure these brackets in the
Table IX). vacant positions using Philips
• 6-pin PS/2 mouse connector CN8 screws.
(refer Table X). Now you may terminate
• Installation of drives in drive’s the connectors originating from
bay. Before proceeding with the physical control panel on the cabinet at
installation of CD-ROM drive, hard disk the motherboard. Connect the
drive, and floppy drive in the drive’s bay, loudspeaker connector to CN14,
you have to plan their configuration. We power-on LED connector to
propose to use only one floppy drive. This CN12, HDD LED connector to
drive will be configured as floppy drive CN13, and reset switch connector
‘A’. The 34-pin floppy drive cable end with to CN11. (Correct orientation
twisted wires, emanating from CN3 on can be ensured by matching
the motherboard, needs to be connected the pin connected to coloured


(not white) wire to go into pin 1 of the from CN1 in the motherboard to CD-ROM Table XI
connectors in motherboard.) drive and its end connector to HDD, ensur-
Pin Assignment Internal Audio
Now connect the 40-pin middle con- ing that pin 1 of connector pairs correctly Connector Internal Audio Connector
nector (in the ribbon cable) originating match. (Projection/slot in the middle of CN25 : AUX-IN
connectors will help you in proper orien- Pin Assignment
tation of the connectors, unless you try 1 AUX-L
to force it in with wrong orientation.) 2 GND
Follow it up by connecting the 34-pin 3 GND
floppy drive end-connector (at the end of
CN24 : CD-IN
twisted cable) to the interface connector Pin Assignment
of floppy drive. This header originates 1 CD-L
from CN3 on the motherboard. 2 GND
The 4-pin Molex-type power supply 3 GND
connectors now remain to be connected 4 CD-R
to the drives. Ensure that rounded CN33 : CD-IN
Pin Assignment
shoulder on the female connectors mate
Fig. 9: Back-panel connector details of HDD 1 CD-R
and CD-ROM drives correctly with the corresponding male 2 GND
power connectors on CD-ROM drive and 3 CD-L
HDD. In all cases you will observe 4 GND
that yellow wire (+12V) pin faces CN32 : CD-IN
the PC case cover. Pin Assignment
For FDD, use the 4-pin mini 1 GND
2 CD-L
power supply connector. This con-
nector, if inserted properly, will 4 CD-R
lock itself into position. To take
out this connector, you should after correctly matching the ground pin ‘G’
press the retaining lever with marked over the analogue audio connec-
your fingertip. Connect one of the tor on CD-ROM drive (refer Fig. 10) and
4-pin connectors—CN24 or CN33 those of CN24 or CN33 or CN32 as given
or CN32—to analogue audio out- in Table XI.
put connector on CD-ROM drive, If you have followed all the tips reli-
giously, your hardware assembly is com-
Screenshots CMOS setup menus
plete on closing the cover of the cabinet
using four to six Philips screws. But before
you do that, have a look again to ensure
that no loose wires are hanging around.
After closing the cover, you may connect
the keyboard cable to the keyboard con-
 nector, mouse cable to COM1 connector,
and amplified speakers’ banana-type
stereo jack into the line-out plug on the
audio bracket.
Now that hardware assembly part of
the basic unit is over, installation of other
cards, such as LAN card (for networking),
internal modem card (for Internet access),
and TV tuner card, into the PCI slots,
using the software drivers supplied with
them, can be attempted subsequently.

Creating a startup disk

Eventually you will be using Windows
operating system (say, Windows 98), and
 for that you should be having Microsoft
Windows 98 installation CD. Use some
other PC having Windows 98 operating
system to create a ‘startup disk’. The idea
is to have all important files, including
system files, Fdisk.exe, and Format.com
files, in hand, so that you may proceed


with hardware partitioning and format-
ting of hard disk once you switch on your
newly assembled PC for the first time.
To make a startup disk, get a new
formatted 8.9cm (3.5-inch) floppy. On the
working computer, click ‘start button’,
select settings, double click on icon ‘add/
remove programs’, select ‘startup disk’,

insert formatted floppy in floppy drive, and
click over the ‘create disk’ button seen on
monitor’s screen.
The program would prompt you for
insertion of original Windows 98 CD in
CD-ROM drive. Insert the same and click
on ‘OK’ button. Even if you do not have
the original CD, but have all programs
in Win98 directory in ‘C:’ drive, you can
give the proper path and the appropriate
programs will be copied to the startup
floppy disk.

CMOS setup
Switch on the newly assembled PC. It
performs power-on-self-test (POST). Dur-
ing POST you will find ‘Num Lock’, ‘Caps
Lock’, and ‘Scroll Lock’ LEDs flashing. A
single short beep during POST indicates
that motherboard is ‘OK’.
Certain messages will keep appearing
on the screen of your monitor, including
“Press Del to enter CMOS setup”. When
this message appears, press ‘Del’ key to
enter setup. The CMOS Setup Utility
screen appears on monitor screen (refer
screenshot 1). There are seven items on 
the left, which can be selected using ar-
row keys on your keyboard. On the right,
it shows certain options that are quite
obvious and can be interactively executed
when required.
Select the first item on the left,
“Standard CMOS Features”, and press
enter to see its screen (refer screenshot 2). You would notice from screenshot second, and third boot devices to read
Use arrow keys to move between the items 2 that during power up, the BIOS has CD-ROM, HDD-0, and floppy, respec-
and ‘Page Up’ or ‘Page Down’ key to edit identified the primary master (Seagate’s tively. This will enable you to boot/run
or select the options. You may correct the 10GB hard disk ST310211A), 52X Sam- the computer from CD-ROM (if you have
date, including year and century, and the sung’s CD-ROM Drive SC-15, floppy a Windows installation), CD, HDD (after
time to their current values. drives, video, and RAM address range formatting and transferring the system
(including its breakdown). This files), or floppy drive (using the startup
latest Award BIOS 1984-2000 does floppy created earlier), in that priority.
not contain ‘Auto Detect Hard Disk’ Press ‘Esc’ to come back to the open-
as a separate utility in the CMOS ing screen. For the time being, skip
setup options. utilities/screens 4 through 7 with their
To select any other screen/setup default values. Select the last “Fre-
utility option, press ‘Esc’, select quency/Voltage Control” menu item. Edit
the next item from setup utility ‘CPU clock/spread spectrum’ item to read
menu, and press ‘Enter’. The next ‘100MHz/On’. Thereafter press ‘Esc’ and
screenshot (screen shot 3) pertains select ‘Save and Exit Setup’ or F10 key,
to ‘Advanced BIOS Features’. Here and then ‘Y’ and ‘Enter’ for saving the
you may edit and change the first, edited BIOS selections.


HDD partitioning and
Assuming that you have Windows 98
installation CD in CD-ROM drive, the
PC will boot from the CD and start the
Windows 98 setup program. Press function
key ‘F3’ to come out of the setup program 
and come to the prompt ‘D:\Win98>’. Type
‘Fdisk’ and press ‘Enter’ for starting with
the partitioning of HDD. (Note. We could
have used the ‘start up’ floppy in Drive
‘A’ instead of inserting Windows CD in
CD-ROM drive and come to ‘A:\>’ prompt
for running the ‘Fdisk’ program from ‘A’
drive, if desired.)
On pressing ‘Enter’ key, the following
FDISK main menu appears:
Current fixed disk drive: 1
Choose one of the following:
1. Create DOS partition or logical DOS drive
2. Set active partition 
3. Delete partition or logical DOS
4. Display partition information
Enter choice: [ ]
Press Esc to exit FDISK
Enter choice 1 above and press ‘Enter’
key. The next menu on page 2 appears as
1. Create primary DOS partition?
2. Create extended DOS partition?
3. Create logical DOS partition?
Type ‘1’ and press ‘Enter’ key. The
program verifies integrity of the disk and
then displays.

Do you wish to use max. size for a
primary DOS partition and make it ac-
tive. Y/N?
Type ‘N’ and press ‘Enter’. (Because,
we propose to create two DOS partitions
of equal size.) Once again the program
verifies integrity of the disk and prompts will again verify the integrity of the disk F3. Now your drives are designated as
you to enter/specify partition in megabytes and show availability of 50% of the disk under:
or percentage of disk space. Type 50% space for extended DOS partition. Type C: First partition on hard disk
and press ‘Enter’. The program complies. 50% for extended DOS partition and press D: Extended partition on hard disk
Now press ‘Esc’ key to return to the main ‘Enter’. E: CD-ROM drive
FDISK menu. Again press ‘Esc’ (only once). The pro- Now you will be able to access CD-
Now enter choice 2. (The primary DOS gram will ask you to specify the disk space ROM drive by typing ‘E:’. After the prompt
partition created earlier becomes active.) for logical drive. Simply press ‘Enter’ and ‘E:\>’, type ‘Format C:/S/U/V’ and press
The program will ask you to enter the then press ‘Esc’ to come back to the main ‘Enter’. (Here ‘C:’ refers to drive to be for-
number of partitions. As it is currently ‘1’ FDISK menu. Choose option 4 to display matted, ‘S’ to system (transfer of system
on ‘C’ drive, therefore type ‘1’ and press the information. After looking at the parti- files to ‘C’ drive during formatting), ‘U’ to
‘Enter’. tion information that it has been correctly unconditional, and ‘V’ to verification.) Af-
Again press ‘Esc’. (Do not press ‘Esc’ done, press ‘Esc’ to come out. Press keys ter formatting ‘C’ drive, you will come back
key more than once, else it will come out CTRL+ALT+DEL or RESET button for to the prompt ‘E:\Win98>’. Type ‘setup’
of FDISK.) Again you are led to main settings to take effect. The PC will boot and press ‘Enter’ to install Windows 98
FDISK menu. from CD-ROM drive as per settings done on ‘C’ drive.
Enter choice 1. You will come to menu in the CMOS setup. On booting you will As the program is interactive, keep
on page 2. Now enter choice 2 to create again come to the setup part of Windows answering the questions logically. Choose
extended DOS partition. The program 98 program. Hence to come out of it, press ‘typical’ while selecting the Windows ver-


sion. Various messages like ‘enter compu- order, and run ‘Setup’.
ter name’, workgroup, etc keep appearing, During the setup, when the
which you may reply suitably. Against program prompts you for selec-
‘date/time zone’ selection, choose India. tion of device, choose ‘Crystal
Computer will show the Agreement Audio Codec’ and click ‘OK’.
format that you are bound to accept. Again during the course of driver
Hence click on the appropriate button. installation for Crystal Audio
Before proceeding with the Windows Codec, the program will prompt
installation, the program prompts you for you for location of Windows 98
entering the key number of Windows 98 files, which you may browse
product, which accompanies each original and point towards C:\Win98
copy. You must type the key number ac- directory or towards Windows
curately. It will then copy the Windows CD as E:\Win98 and click ‘OK’
98 files to ‘C’ drive in Win98 directory. button. After finishing, you may
This will obviate use of Windows CD verify, via ‘Device Manager’ (refer
for creating a startup file, whenever preceding para) by clicking on
required. ‘Sound, Video and Game control-
To format drive ‘D’, double click on ler’ icon, that ‘Crystal Audio Co-
My Computer icon, click the right button dec’ as also ‘Crystal Audio Codec
on drive D:, choose ‘Format’, and in ‘For- with Game Device’ appear under

mat D:’ menu box, choose full and click it. (A sound icon will concurrently
on ‘Start’ button. After completion of the appear on the bottom line of your
formatting of ‘D’ drive, it is accessible for desktop.)
read/write operations. This completes par- • Intel Firmware Hub
titioning and formatting of the hard disk. configuration. In ‘Device Man-
ager’ under ‘Other Devices’, an below.
‘Unknown Device’ would still appear. This • APM. APM caters to the PC to enter
Loading concerns ‘Intel’s Firmware Hub’. To correct an energy-saving standby mode. BIOS
enables APM by default. It can be initiated
this problem, again go to 810 subdirectory
motherboard drivers on the CD, double click on ‘INF_install’, in the following ways:
• On-board VGA display driver. When and then on ‘Setup.exe’ within that sub- 1. By specifying time-out period in
the PC is running, insert the motherboard directory. A message “Found New Device BIOS setup program.
driver CD that came with the motherboard – Intel Firmware Hub” appears on the 2. By connecting a hardware suspend/
(PCPartner driver’s CD, in our case) into screen. This device will be automatically resume switch to CN10 on the mother-
CD-ROM drive. Select drive ‘E’, select ‘In- configured when you follow the instruc- board.
tel Chipset Products’, 810, VGA , Win9X, tions appearing on the screen properly. To 3. From ‘Suspend’ menu item in Win-
and Graphics, in that order, and double confirm that there are no unknown devices dows.
click on its ‘Setup.exe’ icon and follow the now, open ‘Device Manager’ and check all • ACPI. ACPI provides direct control
instructions on screen. After finishing, the items under ‘Other Devices’. to the operating system over the power
shut down the PC as per Windows shut- With installation of drivers for on- management as well as plug-‘n’-play func-
down procedure and restart to allow the board devices, hardware and software tions. Features include:
drivers to take effect. configuration of your multimedia PC 1. Power management control of
• On-board AC97 Codec sound is complete. Other secondary functions individual devices, add-on cards, video
driver. Click on ‘Start’ button, select set- such as power management functions— display, and HDD.
tings, select control panel, double click on APM (advanced power management) or 2. Methods for achieving less than
‘System’ icon, click on ‘Device Manager’, ACPI (advanced configuration and power 30W operation in ‘Power-on Suspend
go to ‘Other Devices’, double click on ‘PCI management interface)—can be incorpo- Sleeping State’ and less than 5W in ‘Sus-
multimedia’, select ‘PCI Audio’, click on rated later through pend to Disk Sleeping State’.
‘Remove button’ (since compatible soft- CMOS ‘Power Man- 3. A soft-off feature to power off the
ware drivers have not yet been installed to agement Setup’ fa- PC.
avoid conflicts), and then click on ‘refresh’ cility. Similarly, 4. Support for multiple wake-up events
button. you can install for the PC to resume normal operation.
Go back to control panel and, click Ethernet card for 5. Support for front-panel power and
on ‘Add new H/W’. A wizard guides you LAN and modem ‘sleep’ mode switch.
through rest of the process, and in due card for the Inter- • Ethernet card for LAN. Ethernet
course, a message “Found new hardware net, fax, and e-mail cards capable of running at 10Mbps to
– PCI multimedia audio, display, sound accessibility via 100Mbps, of different makes such as
video” appears. The program asks if you telecom lines. A Intel, Real Tek, Mercury and Dax, as
have disk (drivers). Click the ‘Browse’ brief information Ethernet PCI adapter are available in
button, select E:, ‘Intel Chipset Products’, on these additional the market.
810 , AC97 Sound, CS4299, Win98, in that functions is given Each card comes with a bracket, driver


diskette, and user manual. The bracket power to the PC should be ‘off’. ible internal modem cards are available
would have an LED and RJ-45 jack. When you switch ‘on’ the computer, from different manufacturers for instal-
This jack is used for running a twisted- it automatically detects its presence lation in any of the PCI slots. The modem
pair unshielded cable (max. length 100 and ‘New Hardware Wizard’ appears card will have a telephone line jack for
metres) between the card and the hub/ on the screen to guide you through the connection of telephone line from wall
concentrator (10Base-T or 100Base-Tx) installation process. It asks for location socket, a parallel phone jack for connect-
to which other computer’s LAN cards are of the drivers. The driver’s floppy can be ing a telephone set, and Mic and speaker
similarly connected. Once the cable is inserted in ‘A’ drive and path can be in- jacks for external mic and speakers for use
connected to the hub, the LED on Ether- dicated. You can then proceed further, as with voicemail and speakerphone facili-
net card would light up. Before installing, per instructions appearing on the screen, ties, respectively.
remove a cutout opposite the PCI slot to to complete its installation. For installing the drivers, the pro-
make space for the bracket of Ethernet • Modem. 56kbps PnP (plug-‘n’-play cedure would be similar to that used for
card. When you install the card, the compatible) and Windows 95/98 compat- installation of the Ethernet card. ❏

Readers’ comments: Q5. I have successfully assembled the Data; 2. N/C (not connected); 3. Ground;
Q1. The authors have shown irresponsi- PC as per the given procedure using a 4. Vcc; 5. Clock; and 6. N/C.
bility by planning to install a Pentium III 128MB RAM instead of a 64MB RAM. 2. Label Energy Star is awarded by
processor on a PGA 370 socket meant for Please answer the following regarding Environmental Protection Agency (EPA),
a Celeron or lower processor. this project: USA, for products which meet its specifi-
Adarsh Soodan 1. How should I proceed to partition cations. It was introduced in 1992. Green
Through e-mail my hard disk into four logical drives? PC is Energy Star program developed
Q2. The article is really interesting and 2. The booting speed of my PC is lower by EPA for minimising unnecessary en-
useful. Please clarify the following techni- than that of my colleague’s PC that uses ergy consumption and release of harmful
cal terms: 500MHz Celeron processor and 64MB chemicals during production, especially
1. PS/2 mouse connector RAM. Why so? chlorofluorocarbons (CFCs) that cause
2. Energy Star, Green PC 3. What is the difference between AMI depletion of ozone layer.
3. Audio modem riser (AMR) BIOS and AWARD BIOS? 3. The AMR (audio modem riser) card
R. Sreerekha Hareendran Narla Sankar is a new modular specification that inte-
Kollam, Kerala Through e-mail grates the audio/modem functions on the
Q3. I request the authors to clear the fol- Q6. Following the guidelines in the article, motherboard by assigning the analogue
lowing doubts. I have successfully assembled my PC using I/O functions to a riser card. Integration
1. Is there any single and reliable altogether a different processor (500MHz of the audio/modem function enhances
dealer in Chennai, Bangalore or Kerala AMD K6-2) and a different motherboard system capabilities while reducing costs.
from where I can procure all the com- (Tomato with SIS 530 Chipset) with The AMR interface is based on an AC-link
ponents. Award BIOS. All is well except that dur- that is compliant with Intel audio codec
2. Is the PC available in kit form? ing the first switching, it flashes “CMOS ’97 version 2.1 specification. It supports
3. Instead of a 35.5 cm (14-inch) colour checksum error” and “CMOS battery data, fax, and voice modes. The pin details
monitor, can I use a 43.2 cm (17-inch) col- failed”. The former message “Checksum of its 46-pin edge connector are given in
our monitor with this PC, without making error” does not appear on restarting the Table I.
any alterations. Further, is there any 43.2 PC. Is this problem due to wrong orienta- The general features of the card in-
cm LCD, colour monitor available for this tion of BIOS chip? clude:
PC. In that case what are all the altera- Vinod D. Buchia – Transmission protocols supported
tions required to be made? Gandhidham (ITU-T V.90 and K56flex, V.34, V.32is,
A. Venugopalan Unny Authors, K.C. Bhasin and Neeraj Kun- V.22bis, V.21, Bell 212A, and Bell 103)
Palakkad dra, state: – Maximum download speed of 56,000
Q4. Please clarify: A1. We have not only planned but bps
1. What is the difference between a also installed the Intel’s Pentium III – Virtual COM Port throughput
boot disk and a start-up disk? processor in PGA 370 socket, and the – 460.8 kbps
2. How can I increase the HDD capac- system is up and running superbly at – Call progress monitor
ity to 20 GB? Further, how can I partition EFY ever since. – On-/off-hook control
HDD into four sections (logical drives) and In fact, Fig. 5 showing its installation – DTMF detection and generation
CD-ROM drive as the fifth drive? in PGA 370 socket is from Intel Pentium – Distinctive ring for data, fax, and
3. Define primary master/slave and III processor installation notes which ac- voice
secondary master/slave. company the Intel Pentium III processor. – Call ID support (optional)
4. How can I configure HDD as second- So the remarks made by the reader are We will try to publish troubleshoot-
ary master and CD-ROM drive as second- totally unwarranted. ing procedures for the PC, in EFY, very
ary slave? A2. 1. PS/2-compatible keyboard and soon.
5. Provide a few tips for attaching a mouse connector are miniature 6-pin A3. 1. We have not carried out a mar-
CD-writer and also a DVD drive to the DIN connectors unlike the PCAT 5-pin ket survey of the cities/states mentioned
system. keyboard and 9-/25-pin (comport) connec- by you and as such we cannot provide you
T. K. Hareendran, Kadakkal tor for the mouse. The pin signals are: 1. any related information.


2. For complete kit or parts, you may
system files, a few other utilities such will be creating three logical partitions in
contact EFY associates, M/s IT Solutions
as Chkdsk.exe, Fdisk.exe, and Scandisk. the extended DOS partition of 50 per cent
(India) Pvt Ltd for quotations at itsolu-
exe to help you optimise and maintain drive space. Thus in the first line seen on
tions@pcbonanza.com. the system. page 49 of February issue, type 33% for
3. One can connect any VGA/SVGA 2. To increase the HDD’s capacity to the leftover disk space instead of pressing
compatible colour monitor or LCD monitor
20 GB, you can simply replace the exist- ‘Enter’. You will observe from the screen
to this PC. For example, LG Electronics'
ing HDD with either a higher-capacity that drive D: has been created.
38.4 cm LCD monitor 500 LC (Windows (20GB) HDD or use an additional HDD in Press ‘Esc’ to return to the menu on
95 plug-n-play compatible) can be directly
one of the two IDE channels (primary or page 1 and repeat the procedure for cre-
connected. secondary, connected to IDE1 and IDE2 ating the next drive, with the exception
A4. 1. A bootable disk is one that
connectors, respectively, on the moth- of typing 50% of the leftover drive space.
contains the basic system files, namely,
erboard) with each channel capable of For creating the last drive, follow the pro-
the two hidden files (IO.SYS and MSDOS.
supporting two devices (anyone as master cedure given in the starting paragraph on
SYS) and ‘command.com’ file. These files
and the other as slave). page 49 (February) in toto.
provide I/O resources for application The names ‘master’ and ‘slave’ have You would thus create all the required
programs as well as an environment to no sanctity in real terms. For configur- drives of required capacities. Note that if
execute programs and interact with theing a drive as master and the other as you install two HDDs in place of a single
operating system. slave, the position of jumpers at the rear HDD, then drive letter ‘D:’ is automati-
You can make a floppy bootable by just
on each HDD device should conform to cally kept reserved by the DOS for the
adding the system files. To do this, use
the settings for jumper block in Fig. 2 primary drive in the next HDD, and in

Windows Explorer, select 3½ floppy, and
above. The setting at serial No. 3 is not that case your four drives on the first HDD
right-click on ‘+’ sign on its left. Now from
applicable to the newer PCs that are all will be named C:, E:, F:, and G:. The last
the pull-down menu, select ‘format’. Select
compatible with ATA (advanced technol- drive name after partitioning of the next
‘copy system files only’ and click on its
ogy attachment) packet interface. The HDD will be assigned to the CD-ROM
start button to copy the above-mentioned
fourth setting (cable select) is meant drive. In the case of two physical HDDs,
files to make the floppy bootable. for computers that use CSEL option for the page 1 of menu in ‘Fdisk’ will show an
If you desire to view hidden files in
master and slave device by selecting or additional choice ‘5. Change current fixed
the disk, click ‘view’ on the menu bar of
deselecting pin 28 of the interface bus, by disk drive’.
Windows Explorer and select ‘view’ in the
jumpering pins 5 and 6. 3. The two devices connected to IDE1
‘folders’ option. Then under ‘hidden files’,
One can use the ‘IDE HDD auto connector (refer the motherboard in Fig.
select ‘show all files’ and click ‘apply’. You
detect’ option from the main menu for 2 of the article) are termed ‘primary’
can now see all files including hidden files
auto-detection of HDD parameters. In and those associated with IDE2 connec-
on the disk. most cases, the BIOS will auto-detect the tor ‘secondary’. Master and slave will be
A start-up disk on the other handHDD(s). If it does not, select the ‘User’ configured as per the shorting link’s posi-
has, in addition to the above-mentioned
option to manually enter the drive’s pa- tions. It is a normal practice to configure
rameters by referring the drive at extreme connector as master
Table I to its documentation and the one connected to middle connec-
AMR Connector Pin Definitions (AMR) that gives the values for tor as slave. (You can also configure them
Pin Signal Pin Signal cylinders, heads, and so vice-versa.)
number number on. The mode should be 4. The shorting link in jumper block
B1 Audio mute# A1 Audio_PWRDN set to LBA (logical block of CD-ROM drive (Fig. 9) will need to
B2 GND A2 Mono_phone addressing). short pins marked ‘SL’. For HDD, fol-
B3 Mono_out_/PC_beep A3
B4 A4 The procedure for low the guidance given in the preceding
B5 A5 creating one active paragraph. Both the devices should be
B6 Primary_DN# A6 GND (bootable) primary par- connected to the cable terminating on
B7 -12V A7 +5V dual/+5V SB tition (drive C:) and one IDE2 connector.
B9 +12V A9 GND
extended DOS partition 5. Attaching a CD-R (CD-recorder/
B10 GND A10 USB+ (drive D:) has already burner/r-drive). There are various ver-
B11 +5VD A11 USB- been covered in the sions. Some can be attached externally
(Key) (Key) article. Assume that we while the others can be installed like a
(Key) (Key) want a primary parti- CD-ROM itself inside the PC. Some will
B13 A13 S/P-DIF_IN tion of 50 per cent and be IDE-compatible and can be configured
B14 A14 GND three extended DOS using IDE cable referred above. Some ver-
B15 +3.3VD A15 +3.3V dual/3.3V SB partitions of equal size sions will be SCSI compatible (for higher
B16 GND A16 GND of the leftover disk space speed), but for that you will need an extra
for drives D:, E:, and SCSI adapter card in one of the vacant
B19 AC97_SDATA_IN3 A19 AC97_SDATA_IN1 F:, respectively. (Note. PCI slots. The latest ones are USB (uni-
B20 GND A20 GND Drive letter ‘G:’ will be versal serial bus) port-compatible. (The
B21 AC97_SDATA_IN2 A21 AC97_SDATA_IN0 automatically assigned USB port is available on your Pentium
B22 GND A22 GND to CDROM drive in the motherboard.) Some external recorders
process.) In effect, we can be connected via the printer port.


The newer models can write as well as POST operations. As time-out margins
read, and as such they can also function are fairly long, a lot of time could get
as CD-ROM drives. Some of the record- 1. wasted that way.
ing software accompanying these writers 2.
• Reload ‘command.com’ file to make
would also have a verification feature sure that it is not corrupt. Also check for
called ‘pre-mastering’ for comparing the 3. presence/removal of any virus using Nor-
recorded data against source file. Neces- 4. ton or other anti-virus program.
sary documentation including software We suggest you to refer the BIOS
drivers for installation, configuration, and FAQs posted by Pheonix at ‘www.
utilities will accompany the CD-R. Going pheonix.com/platform/awardbios.html’
through this literature, you can buy the before coming to any conclusion.
CD-R that suits you the best. 3. AMI (American Megatrends Inc.)
Attaching a DVD to the system. The and AWARD (AWARD Softwares, which
minimum system requirements for in- Fig. 2: Settings for jumper block merged with Pheonix Technologies Ltd
stalling a DVD in the same place where in Sept.1998) are the two renowned BIOS
CD-ROM goes include Pentium with bus the sound card’s internal audio-in con- suppliers. There are a few other suppliers
speed of 133 MHz (supported by 810E nector. Remove the monitor connector also in the field (e.g. Microid Research
chipset) or better (200 MHz is required from your graphics card and plug it into Inc., Chips & Technologies, etc). At the
for maintaining 30 frames/second rate), the appropriate connector on the rear of user’s level, one does not directly interface
Windows 95 or later version (Windows 98 your MPEG card. Find the VGA loop-back with the BIOS, except via the CMOS set-
has in-built DVD support), 16MB/32MB cable included in your DVD kit. Attach up options that are more or less similar,
RAM, graphics resolution of 800x600 pix- its one end to your graphics card and irrespective of the BIOS supplier. BIOS
els with 16-bit colour, and sound blaster- the other to the input connector on your is chipset-/hardware-specific. Hence it will
compatible card. You also need to install MPEG card. generally differ from one motherboard
an MPEGII decoder card in a spare PCI If you want to use a TV monitor with manufacturer to another. Even the same
slot for decompression of video and audio. your DVD drive, link the video-out connec- manufacturer may upgrade his BIOS by
(Software-based MPEG decoders are com- tor on your MPEG board to the monitor’s some hardware modifications to make it
paratively much slower.) video-in connector. Now proceed to install compatible with the new hardware. Only
While a CD can store around the drivers and DVD software. Power up options can be changed via the CMOS
650MB/700MB, a single-sided DVD can your PC. Windows will detect the MPEG set-up utility.
store 4.7 to 9 GB and a double-sided DVD board and ask you for a driver. Insert the A6. The BIOS chip orientation is
up to 18 GB. (A double-sided DVD needs driver floppy from your DVD kit and click correct, else you would not even see the
to be flipped to read the second side as ‘OK’. You may need to restart your PC initial setup screen or any message.
existing drives can read from a single before proceeding. Battery-backed CMOS chip orientation is
side only.) The DVD kit would comprise A5. 1. The first question has already also correct if your system time is chang-
ATAPI/EIDE-compatible controller (SCSI- been answered above. ing correctly, since battery-backed CMOS
compatible are also available in the mar- 2. The slow booting operation in PC chip is used for retaining the system
ket), an MPEGII decoder card, cables, and may be attributable to some other reason set-up data as well as the RTC (real-time
software including sample titles. Consider- rather than the processor. The booting clock) data.
ing an ATAPI/EIDE-compatible controller, process in the PC involves a number of It seems that either your battery-
configure DVD drive as primary slave by steps. Some of the probable reasons and backed CMOS chip is faulty or some of its
placing the shorting link across SL pins the suggested remedies are given below: pins are not making proper contact with
on its jumper block at the rear in the same • The power good (PG) signal may the base and hence its integrity is not get-
fashion as described above. not be building fast to its specified value ting verified during POST. Check if this
Read your DVD installation manual (4.5Vmin). For that, you need to check CMOS chip has popped up from its base
carefully, since there are various ways to your PCs’ SMPS. The specified power rat- or any of its pins are bent and rectify the
cable together the DVD drive, MPEG card, ing of the power supply to support Intel’s same. Else, try changing this IC. There
existing sound card, and existing CD-ROM 810 chipset is 145 watts for a typical could also be a track discontinuity problem
drive (if any). You should follow the docu- configuration. on your motherboard.
mentation for audio and video connections. • In the CMOS setup utility (refer Check proper setting of jumpers, es-
However, here is a typical approach: screenshot 4), edit the field against ‘Sys- pecially the CPU core voltage selection.
Connect the internal audio cable from tem BIOS Cacheable’ and ‘Video BIOS For AMD K6-2, this voltage setting is
the rear of the DVD drive to the first Cacheable’ to read ‘Enabled’ in place of 2.2V. This can be achieved by shorting
audio-in connector on the MPEG card. If ‘Disabled’. pins 7-8 of JP5, while leaving all oth-
you find an internal audio cable from your • Ensure that 3.3V SDRAM sticks ers open, in your Tomato motherboard.
existing CD-ROM drive fastened to your (DIMMs) used by you are 100MHz- Shorting is achieved by moving the link
sound card, disconnect that cable from compatible. to 1-2 and opening is achieved by mov-
the sound card and plug it into the MPEG • Ensure firm connections from moth- ing the link over 2-3. This information
card’s secondary audio-in connector. erboard to all peripherals. Improper con- may be included in the user manual of
Next connect an audio cable from the nections can result in BIOS taking time your motherboard. Else, you may get it
audio-out connector on the MPEG card to in identifying them/their settings during from‘http://www.zida.com/js_t530b.htm’.


Automatic Room Light
rejo g. parekkattu Parts List
IC1, IC2, IC3 - NE555, timer

IC4 - 74LS192, up/down decade
sually, when we enter our room BCD output of the counter, at any time, counter
in darkness, we find it difficult represents the number of persons inside IC5 - 74LS85, 4-bit magnitude
to locate the wall-mounted switch- the room. The output of the up/down comparator)
board to switch ‘on’ the light. For a counter is decoded by 7-segment decoder/ IC6 - 7447, BCD to 7-segment
stranger, it is tougher still as he has no driver and displayed on 7-sement display.IC7 - MCT2E, opto-coupler
knowledge of the correct switch to be Simultaneously, the output of counter is IC8 - 7805, +5V regulator
turned on. Here is a reliable circuit that compared by 4-bit magnitude compara- IC9(N1-N4) - 74LS00, quad 2-input
takes over the task of switching ‘on’ and tor. NAND gate

IC10(N5-N10) - 74LS14, hex schmitt
switching ‘off’ of the light(s) automatically The output of comparator remains inverter gate
when somebody enters or leaves the room high as long as BCD output of counter is T1, T2 - BC548, npn transistor
during darkness. This circuit has the fol- greater than zero. A logic gate is used to
T3 - SL100, npn transistor
lowing salient features: D1-D3
initiate energisation of a relay to switch - IN4001, rectifier diode
IRLED1, IRLED2 - Infrared LED
• It turns on the room light whenever ‘on’ the light when comparator output is
Resistors (all ¼-watt, ±5% carbon, unless
a person enters the room, provided that high and it is dark outside.
stated otherwise):
the room light is insufficient. If more than R1 - 3.3-kilo-ohm
one person enters the room, say, one after R2 - 10-kilo-ohm
the other, the light remains ‘on’. The circuit R3 - 100-ohm
R4, R5, R21 - 1.2-kilo-ohm
• The light turns ‘off’ only when the The detailed section-wise description of
R6, R7, R12 - 33-kilo-ohm
room is vacant, or, in other words, when the circuit shown in Fig. 2 is as follows:
R8, R9 - 180-kilo-ohm
all the persons who entered the room IR transmitter. The IR transmitter R10, R11 - 1-kilo-ohm
have left. R13-R19
circuit consists of an astable multivibra- - 470-ohm
R20 - 100-kilo-ohm
• A 7-segment display shows the tor built around NE555 timer IC1. The
VR1 - 10-kilo-ohm preset
number of persons currently inside the output of IC1 at pin 3 is a rectangular
room. waveform of around 36kHz frequency. C1 - 0.001µF, ceramic disk
• The circuit is resistant to noise and This output is used to drive two IR LEDs,C2, C3, C4 - 0.01µF, ceramic disk
errors since the detection is based on in- which transmit modulated IR light at C5, C6 - 4.7µF, 16V electrolytic
frared light beams. 36kHz frequency. Modulating frequency C7, C8 - 10µF, 16V electrolytic
C9 - 1µF, 16V electrolytic
• The circuit uses commonly available of 36 kHz is used because the IR receiver
components and is easy to build and test. modules used in this circuit respond to IR
M1, M2 - IR sensor modules
The functional block diagram of the signals modulated at 36kHz frequency. DS1 - LT542 (common anode
circuit is shown in Fig.1. It comprises The multivibrator frequency can be cor- display)
36kHz IR transmitter, two IR detector RL1
rectly adjusted with the help of preset VR1 - 12V, 200 ohm, 2 C/O.
LDR1 - LDR (Dark resistance > 120
modules, two monostable multivibrators, (10 kilo-ohm). Resistor R3 is a current kilo-ohm)
up/down-counter, 4-bit magnitude com- limiting resistor that keeps the IR LEDs,L1 - 230V, 100W electric bulb
parator, 7-segment decoder display, light current within the required range. - 12V power supply
sensor, and relay driver. IR detector modules. The IR de- - Printed circuit board
- IC sockets
Two pairs of IR transceivers are em- tector modules used in the circuit are
ployed in order to detect whether the
person is entering or leaving the room.
When a person enters the room, IR
detector 1 gets triggered, followed by
triggering of IR detector 2. Conversely,
when a person leaves the room, IR
detector 2 gets triggered, followed by
triggering of IR detector 1.
A priority detector circuit deter-
mines which of the two detectors is
triggered first and then activates an
up/down counter accordingly. The Fig. 1: Block diagram of automatic room light controller


Fig. 3: Timing waveforms

commonly available in or leaves the room, the infrared light

the market. These have beams are interrupted one-by-one and the
three terminals for Vcc output of each IR sensor module, in turn,
(+5V, here), ground, and goes high, which results in conduction of
the output signal, re- associated transistors T1 and T2. Which
spectively. In the normal transistor will turn ‘on’ first depends on
state, the output pin whether the person is entering or leaving
(pin 3) of this detector the room.
remains at high state, In the circuit, two NE555 timer ICs
and when an IR light (IC2 and IC3) wired as monostable multi-
of correct modulating vibrators are used. The pulse width of the
frequency is detected, output waveform (on time) for these mul-
its output pin goes low. tivibrators is fixed at about 0.9 seconds
The pin configuration by suitably selecting the values for the
of the IR modules may timing capacitors C5 and C6 in conjunc-
vary from one manufac- tion with their associated resistors R8 and
turer to the other. (Pin R9. These monostable multivibrators get
configuration of module triggered when their trigger input pins
TSOP 1136 for 36 kHz (pin 2) go low. Thus the multivibrators are
used by EFY is shown in triggered only when the IR light beams
Fig. 2.) (Articles based are interrupted. Although the output
Fig. 2: Schematic diagram of automatic room light controller

on the IR sensor module pulse width of both the multivibrators is

have been published in approximately the same, there is, how-
Nov. 2000 (also in Elec- ever, a phase difference corresponding to
tronics Projects Vol. 21) the elapsed time between the successive
and some other previous interruptions of the IR beams. Refer to
issues of EFY. Readers the waveforms shown in timing diagram
may refer the same for of Fig. 3.
more information about Priority-detector logic circuit. The
the module.) priority detector circuit uses three NAND
Since the IR trans- gates, five inverter gates, and two differen-
mitter in this circuit is tiators. The timing diagram given in Fig.
continuously ‘on’, emit- 3 helps in understanding as to how the
ting IR light, in the nor- priority-detector circuit detects a person
mal condition, the output going out of the room.
pins of both IR modules At first the outputs from the mon-
will be at low state. ostable multivibrators are NANDed
Therefore transistors T1 by gate N1 and its polarity is inverted
and T2 will remain cut- again by gate N7. At the same time, the
off. When a person enters outputs of monostable IC3 and IC2 get


differentiated by the capacitor-resistor The rectangular pulse at pin 4 of NAND high transition) and the output count
combinations of C7-R10 and C8-R11, gate N2 ends before the output of gate goes down by one count.
respectively. Each differentiated output N7 goes high and hence the output of Similarly, when a person enters
is passed via Schmitt inverter pairs of NAND gate N2 stays high, while both the room, pin 4 of counter IC4 remains
N5-N6 and N10-N9 to convert the differ- inputs to NAND gate N3 are simultane- high, while its pin 5 (count up) gets a
entiated pulses into rectangular pulses. ously high for the duration of rectangu- low-going pulse resulting into counter
The rectangular pulses obtained at the lar output of gate N9. As a result, the output advancing by one count. Values
output of gates N6 and N9 are again output of gate N3 applied to countdown of capacitors C7 and C8 and resistors
NANDed with the output of gate N7 in clock pin 4 of IC4 causes the counter to R10 and R11 can be varied for optimum
NAND gates N2 and N3, respectively. count down on its trailing edge (low-to- performance.
Up/down counter. Up/down decade
counter 74LS192 (IC4) is used as the
counter. When the power is turned ‘on’,
its outputs Q0 through Q3 are in the
low state. Whenever a person enters the
room, a low-going pulse is applied at its
count-up pin 5, while its count-down
pin 4 is held at logic 1 and its output
count advances by one. Similarly, when
the person leaves the room, a similar

pulse is applied at its countdown input
(pin 4) while its countup pin 5 is held at
logic 1 and its output decreases by one.
Thus the 4-bit output always represents
the number of persons still inside the
room. The output of the decade counter
is connected to 7-segment decoder/driver
IC6 (7447) that displays the number on
common-anode 7-segment LED display
Magnitude comparator. The output
of the up/down counter is also applied to
4-bit magnitude comparator that acts
as zero detector, i.e. it detects whether
Fig. 4: Actual-size, single-sided PCB layout for the circuit the number of persons inside the room
is greater than zero or not. The 4-bit
output of the decade counter is always
compared with a reference 4-bit number
(0000), and if a match occurs, the output
at pin 5 (P>Q) of the comparator goes
low to represent an ‘empty room’ condi-
tion. In all other cases (when the number
of persons in the room is greater than
zero), P>Q output will be at high state.
This output is given as one of the inputs
to NAND gate N4 (followed by inverter
gate N8). Thus, as long as the room is
not empty, one of the inputs to N4 gate
will be high.
The second condition for the light to
get switched ‘on’ is yet to be satisfied.
Whether there is sufficient light in the
room or not is checked by the light sensor
Light sensor. The light sensor is
wired around the opto-coupler MCT2E.
The resistance of the LDR depends upon
the amount of light in the room. An LDR
with resistance below 5 kilo-ohm in nor-
mal light and more than 120k resistance
Fig. 5: Component layout for PCB in darkness is required. When there is


(that is one or more persons are inside Fig. 6. The distance between the two sen-
the room and the ambient light is insuffi- sors (receiver modules) is about 40 cm.
cient), the output of NAND gate goes ‘low’ A steel pipe of 5mm diameter and 3cm
and that of inverter gate N8 goes ‘high’ to length can be placed in front of the IR
turn on transistor T3, thereby energising module in order to improve its directiv-
relay RL1. A 230V, 100W electric bulb is ity. After assembling the circuit, adjust
connected via the relay to the AC mains. preset VR1 (10k) until pin 3 of both the IR
Once the relay gets energised, the LDR is sensor modules go high (5V). If the circuit
effectively removed from the circuit (since still does not function properly, adjust the
Fig. 6: Proposed layout of IR transmitter the LDR is connected to the N/C contact of distance between the sensors. The metal
and receiver pairs the two pole relay) to prevent the flicker- cabinets of the IR modules must be con-
ing of the lamp with changing resistance nected to ground.
sufficient ambient light, the transistor of the LDR. Note that the circuit works with a
inside the opto-coupler is turned ‘on’ and regulated +5V supply, except the power
the input of NAND gate (pin 3) is driven supply to the relay coil. The circuit has
to low state. Thus the output of NAND Assembly and testing no off-time memory, and so its working is
gate remains at high state and that of in- The full circuit, with the exception of the interrupted during power failure.
verter gate N8 at low. However, when the IR transmitter, can be assembled on a Another disadvantage is that the cir-
light is insufficient, the resistance of the single general-purpose PCB. However, cuit can count only up to 9. But it is quite
LDR increases, turning off the transistor an actual-size, single-sided PCB for the unusual to have more than nine people in
inside the opto-coupler. The sensitivity circuit in Fig. 2 is shown in Fig. 4. The a normal living room.
can be controlled by adding a high-valued component layout for the PCB is shown Take care about the IR sensor module
variable resistance (about 680k) across in Fig. 5. pin connections. It may be damaged if con-
the LDR. The receiver-transmitter pairs are nected wrongly.
When both conditions are satisfied placed about a metre apart as shown in ❏


Water Level Controller
Sadhan Chandra Das

n coming years, the drinking water tank has become full. As a result, water ler circuit presented here. It has the fol-
is going to be one of the scarce com- keeps overflowing until the household lowing features:
modities. This would partly be at- people notice the overflow and switch • It can automatically switch on the
tributable to our mismanagement of the pump off. As the OHT, in general, is pump when the tank is empty and switch
water supply and its wastage. In normal kept on the topmost floor, it is not quite it off when the tank becomes full.
households, where pumps are used to fill convenient to go up frequently and see • It can check the ground tank (sump

the overhead tanks (OHT), it is usually the water level in the OHT. tank) water level from which the water is
observed that people switch on the pump This problem can be solved by using pumped into the overhead tank (OHT).
and forget to switch it off even when the the intelligent digital liquid level control- If the sump tank water level is below the

Fig. 1: Circuit diagram of water level controller


low and the display shows decimal digit
0. In this way the display circuit works
to show decimal digits 0 through 4, cor-
responding to the level of the water, as
defined by the position of the sensors at
different heights. Here the resistors R9
through R12 and R19 through R21 have
been used for passive pull-down.
Controller circuit. The controller
circuit is built around three quad 2-input
NOR ICs (IC3 through IC5) to switch
the pump motor on or off when certain
conditions are fulfilled. The conditions
to be met for switching-on/running of the
pump are:
Fig. 2: Power supply 1. The mains supply should be within
certain ‘low’ and ‘high’ cut-off limits (say
Digital display between 200V AC and 250V AC).
circuit (refer Fig. 1.) 2. The water level in the sump (ground
This circuit comprises a tank) is above certain optimum level (2'
quad 2-input XOR gate in Fig. 1).
IC1 (CD4030) for sum 3. Water in the overhead tank (OHT)
outputs, decimal to BCD is below the minimum level.
code converter using Once all the above-mentioned three
diode matrix of diodes conditions are satisfied, the pump motor
D3 through D7, a BCD would start running. The corresponding
to 7-segment decoder/ logic level at point A will be low (point B
driver IC2 (74LS47), will also be low automatically—not being
Fig. 3: Construction details of probes for mineral water and common-anode type in touch with the liquid), point C will also
7-segment dis- be low and point D will be high.
play LTS 542R. Once running, the pump will continue
When only to run even when the water rises above
the tip of sensor the minimum level in the OHT (i.e. when
probe (cathode) point A subsequently goes high), provided
No. 1 is in touch the first condition is still fully satisfied
with the water, and the water level in the sump has not
the voltage at fallen below that of sensor 1'. It will stop
pin 3 of IC1 be- only when either the maximum specified
comes logic high level in the OHT has been reached or the
(i.e. +5V), and water level in the sump has fallen below
hence voltage at sensor 1' position.
line No. 1 (L-1) Here the NOR gate pairs of N2 and
also becomes N3, and N6 and N7, form NOR-latches.
high. Now due When the ground tank (sump) water level
Fig. 4: Construction details of probes for non-conducting liquids
to conduction of is above the defined level 2', the voltage
diode D3, the BCD code at pin 11 of gate N6 is low. So diode D12
0001 (Q3 Q2 Q1 Q0) is cannot conduct. Also, if the mains voltage
predetermined level, the unit switches off
generated and converted to equivalent is within acceptable limits of 200-250V,
the pump to protect the pump from dry-
7-segment code by IC2 (74LS47) to dis- the voltage at output pin 3 of gate N12 is
run, even though the overhead tank may
play the decimal digit ‘1’. high and the voltage at collector of tran-
be completely empty.
Similarly, when the tips of the both sistor T2 is low. Diodes D8 and D11 are
• It includes under- and over-voltage
sensors 1 and 2 are in touch with water, thus cut off. So the voltage at input pin
cutout to switch off the pump if the voltage
the voltage at pin 3 becomes logic low 8 of gate N4 is pulled down to logic low
is not within specified low (200V) and high
(0V) while the voltages at pin 4 and line level by passive pull-down resistor R18
(250V) limits.
2 (L-2) become logic high (i.e. +5V). Now (56 kilo-ohm).
• It includes a circuit for digital dis-
due to conduction of diode D6, the cor- Now if overhead tank is empty, i.e.
play of the overhead tank level to indicate
responding BCD code 0010 is generated water level is below level 1, voltage states
water levels 0 through 4 as per positions
and decimal digit 2 is displayed on the at input pins 1 of gate N2, and pins 12
of the tips of the sensors inside the over-
7-segment display. and 13 of gate N1, are pulled down to
head tank.
When the tank is completely empty, logic low by passive pull-down resistors
• The sensors used in this project have
the outputs of all XOR gates of IC1 are R13 and R14 respectively. Hence volt-
a lifetime of more than five years.


Parts List
IC1 - CD4030 quad 2-input XOR
IC2 - 74LS47 BCD to 7-segment
IC3-IC5 - CD4001 quad 2-input NOR
IC6 - LM7812 regulator 12-volt
IC7 - LM7805 regulator 5-volt
T1-T2 - SL100 npn transistor
D17-D20 - 1N4001 rectifier diode
D16 - Red LED
DIS1 - LTS542R 7-segment common
anode display
Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise):
R1-R8 - 33-kilo-ohm
R9-R18 - 56-kilo-ohm
R19-R21 - 1.5-kilo-ohm
R22, R24 - 2.2-kilo-ohm
R23 - 1.2-kilo-ohm

R25 - 1-kilo-ohm
Fig. 5: Actual-size, single-sided PCB for water level controller R26, R27 - 220-kilo-ohm
R28-R34 - 330-ohm
VR1, VR2 - 100-kilo-ohm preset
C1-C4, C7 - 0.01µF ceramic disc
C5 - 470µF, 35V DC electrolytic
C6 - 2200µF, 35V DC electrolytic
C8,C9 - 10µF, 25V DC electrolytic
RL1 - 12V, 200-ohm 2 C/O relay
X1 - 230V AC primary to
(a) 0-15V, 750 mA, and
(b) 0-12V, 100 mA secondary
S1 - Push-to-on button
S2 - On/Off switch
- IC sockets
- Heat sinks for regulator ICs
- SS304, 5mm dia. stainless
steel rod for anode and 3mm
dia. for all cathodes - of ap-
propriate length
- Multi-core feed wire

10 go low. Transistor T1 is cut off and the

relay is kept disabled, even though the
Fig. 6: Component layout for the PCB overhead tank is fully empty. The relay
will be enabled only when the water level
ages at output pin 11 of gate N1 and pin 1 of gate N2 goes high. Already, the in the sump tank is above level 2'.
input pin 5 of gate N3 become logic high voltage levels at pin 11 of gate N1 and When the ground tank water level is
to force the output at pin 4 of gate N3 to input pin 5 of gate N3 are low. So the volt- above level 2' but the line voltage is out of
be latched low. This logic level will not ages at output pin 4 of gate N3 and input range, gate N12 output pin 3 goes low to
change until voltages at input pins 5 and pin 9 of gate N4 become logic high to turn cut off transistor T2, making diode D11
6 of gate N3 become low (0V) and voltage the output pin 10 of gate 4 to logic low level. conduct. In this state the output of gate
at pin 1 of gate N2 goes high (+5V). Since Thus relay RL1 is de-energised, to switch N6 and the output of gate N2 become logic
both inputs of gate N4 are low, hence its the pump off. low. Although diode D12 does not conduct,
output at pin 10 goes logic high to drive When line voltage is within the speci- diode D11 conducts and the output of gate
transistor T1 into conduction. Relay RL1 fied limits and ground water level goes N4 goes low to cut off transistor T1. This
is thus energised and the pump motor is below the defined level 1', the voltage at disables relay RL1 and the pump remains
switched ‘on’. output pin 11 of gate N6 becomes logic off, even though the overhead tank is com-
The water level of the overhead tank high to make diode D12 conduct. As a pletely empty.
starts rising. When the water level reaches result, the voltage at pin 8 of gate N4 Here two cathode sensors for sensing
the tip of the topmost sensor 5, voltage at becomes logic high to make its output pin ground tank water level have been used


instead of one, to provide some hysteresis One of its terminals is grounded while its rain water does not come in contact with
in the system. When ground water level other terminal, marked ‘G’, is connected the soldered joints. One has to use ortho-
is below level 1', the output of gate N6 to point ‘G’ of high/low cutout circuit in phosphoric acid or zinc-chloride to make a
becomes logic high (5V). When water level Fig. 1. The other secondary rated at 15V, soldered joint between stainless steel and
is above level 2', the output of gate N6 is 750 mA is used for deriving the regulated conducting part of the flexible feed wire.
logic low (0V). If the water level is in be- DC supplies required for operation of the The distance between the anode and
tween levels 1' and 2', there is no change circuit. the cathodes should not be more than 60
of state at output of gate N6, i.e. output Construction of sensors (Fig. 3). cm. Arrangement should be made in such a
remains at the last/previous state. The highlight of the circuit are its elec- way that no electrode touches the other.
Power supply (Fig. 2). The power trodes (Fig. 3) used for mineral/conductive The circuit can also be used for non-
supply circuit consists of step-down water, which are made of stainless steel conductive liquids such as pure distilled
transformer X1 (having two secondaries (grade SS-304) rods. These electrodes have water by using floats in conjunction with
with ratings of 12V, 100 mA and 15V, a life span of more than five years. Anode micro switches, as shown in Fig. 4. This
750 mA), a bridge rectifier (using four is a rod of 5 mm diameter and each of the arrangement can be used for distilled wa-
1N4001 diodes), a capacitor of 2200 µF for cathodes is of 3 mm diameter, as shown ter plants, research laboratories, and for
filtering purpose, regulator IC 7812 for in the figure. other nonconductive liquid level sensing
feeding the anode probes as well as relay The cathodes and the anode should be applications.
RL1, and regulator IC 7805 for feeding long enough so that their soldered termi- An actual-size, single-sided PCB for
regulated +5V supply to all digital ICs, nals are not in contact with water, even the circuits in Figs 1 and 2 is shown in Fig.
LEDs, and 7-segment display. The 12V when the tank is full. The joints should be 5, and the component layout is shown in
secondary is used for sampling the mains. covered with insulation in such a way that Fig. 6. ❏


a unique
Liquid Level Indicator
Sadhan Chandra Das

separate alternative circuit of a and the power
unique liquid level indicator supply circuit
to provide a display in terms of in Fig. 2 inde-
the percentage of full-scale level in OHT pendantly.
is shown in Fig. 7. It can either be used The latter

to replace the digital display circuit configuration
included in Fig. 1 (by simply connecting can be used
the 10% and 100% sensor probes of Fig. 7, when you do
additionally, to points marked ‘A’ and ‘B’ not desire to
respectively in Fig. 1, apart from connec- have auto-
tion of +5V and +12V supplies and ground matic control
points) or it can be used in conjunction for switching
with an audio alarm unit shown in Fig. 8 the pump mo- Fig. 8: Audio alarm unit

Fig. 7: Unique liquid level indicator


Display circuit. The
basic elements of the cir-
cuit, as shown in Fig.
7, comprise three quad
2-input XOR gates (IC1
through IC3) to get only the
sum outputs, a hardwired
decimal-to-BCD converter
(using diodes D1 through
D16), and a 74LS47 BCD-
to-7-segment decoder/driv-
er (IC4). When the tip of
sensor-1 is in touch with
the water, the line (L-1)
connected to pin 3 of IC1
(CD 4030) goes to logic 1
state (+5V).
When the tips of sen-
sors 1 and 2 both touch the
water, pin 3 of IC1 goes to
logic 0 (0V), while line L-2
connected to pin 4 of IC1
becomes high (+5V). Thus
Fig. 9: Actual-size, single-sided PCB for the unique liquid level indicator
which one of the lines (L-1
through L-10) will be at
logic 1 would depend on
which last sensor (counted
from bottom of the tank) is
in touch with the water. If
the tank is totally empty,
all the lines, L-1 through
L-10, would be at logic 0.
These lines (L-1
through L-10) represent the
decimal numbers 1 through
10. If line L-1 is at logic 1,
BCD code 0001 is gener-
ated due to conduction of
diode D9 only. Similarly, if
line L-3 is at logic 1, BCD
code 0011 is generated due
to conduction of diodes D6
and D16.
The voltages, corre-
sponding to their BCD
codes, are fed to the in-
puts of IC 74LS47 (7-seg-
Fig. 10: Component layout for the above PCB ment decoder/driver) to
drive 7-segment display DIS2. When
tor on and off but need only to be warned (Fig. 8) is tapped from line-1 and line-10 line L-10 is high, display DIS3 is driven
when water reaches 100% and also when representing 10% and 100% levels respec- by transistor T1 (SL100) for decimal
its level drops to 10% so that you may tively in Fig. 7. number 1.
manually switch the pump motor on or off, If, in place of displaying the liquid lev- Since all the time the unit place digit
as the case may be. el in percentage, one wants to display only of the percentage display is 0, the cath-
This level indicator can show the dis- the digits 0 through 10, then 7-segment odes of corresponding segments of DIS1
crete levels in percentage from 0 to 100% display DIS1 and LEDs (LED1 through have been permanently connected to
with 10% resolution. An audio alarm LED4) for ‘%’ symbol can be removed. This 0V (ground) through current-limiting
circuit has been incorporated to generate circuit can be used for premises which resistors of 330 ohms each. In this way
audio alarm when the tank level reaches have overhead tanks and the water supply the circuit displays 0 to 100 per cent
100% and also when the level drops to is provided by municipalities or corpora- of liquid level with 10 per cent resolution.
10%. The input to the audio alarm circuit tions etc. One may or may not use diode D1. In


Parts List Readers’ comments: done for resistors R19, R20, and R21.
Semiconductors: Q1. I have noticed, when the water level The anode voltage should be +12V to
IC1-IC3 - CD 4030 quad 2-input X-OR reaches the probe No 4, the C' segment +15V, which may or may not be regulated.
gate LED of DIS 2 (LT542) does not glow. You may also follow the modifications
IC4 - 74LS47 BCD to 7-segment The same is the case even when the shown in Fig. 1 (component numbers
IC5 - UM66 melody generator
water level reaches probe No. 5 and shown for Intelligent Water-Level Control-
DIS1-DIS3 - LTS 542 common anode probe No 6. Kindly suggest the correc- ler) to correctively display the water-level.
7-segment display tive actions. It is due to the fact that the output of
T1, T3, T4 - SL100 npn transistor M. Raja the CMOS ICs (4030) are loaded by 1.5k
T2 - BC 108 npn transistor Bangalore resistors.
D21, D22 - 1N4001 rectifier diode Q2. I have constructed the circuit which EFY: The circuit works satisfactorily with-
ZD1 - 3.1 volt zener diode is working perfectly. Instead of eleven out resistors R2 to R5.
LED1-LED4 - Red LED roads, I want to use a stainless-steel A2. Sensors using a stainless steel hollow
Resistors (all ¼-watt, ±5% carbon, unless hollow pipe that is sealed at one end pipe cannot be used in this circuit. Imag-
stated otherwise): and contains ten normally-open type ine the float is in between 5th and 6th
R1 - 3.3-kilo-ohm
R2-R5 - 1.5-kilo-ohm
R6-R24 - 330-ohm
R25-R34 - 56-kilo-ohm
R35-R44 - 33-kilo-ohm
R45 - 100-kilo-ohm

R46 - 2.7-kilo-ohm
R47, R48 - 680-ohm
C1 - 100µF, 25V electrolytic
LS - 8-ohms speaker 7.5 cm dia
- SS 304, 5 mm dia and 3mm
dia stainless steel rods of
appropriate length for anode
and cathodes respectively.
- Multi-core feed wire

this circuit the resistors of 56-kilo-ohm

are connected across the inputs of XOR
gates and ground, while resistors from
R2 to R5 have been used for passive pull-
down action.
Audio alarm unit. Fig. 8 shows
the circuit for audio alarm. The base of Fig. 1: Modification to level controller
transistor T2 (BC108) is connected to the
terminals of lines L-10 and L-1 via diodes magnetic reed switches on the inside reed micro switches, then no switch will be
D21 and D22 respectively and a common and one floating magnet on the outside closed and the display will show only 0,
resistor of 100-kilo-ohm. as the sensor. Could you suggest me the although the water level is in between 5th
When water touches the topmost sen- changes required in the circuit if this and 6th sensors. Moreover, the number
sor probe, transistor T2 conducts and tran- type of sensor is used? of wires from the reed switches remains
sistor T3 is cut off. As a result 3.1V devel- J.P. Thakkar the same.
oped across zener ZD1 becomes available Through e-mail Nowadays for non-conductive liq-
across pins 1 and 2 of melody generator The author, Sadhan Chandra Das, uid, coaxial or parallel-plate type ca-
IC7 (UM66). The amplified musical alarm replies: pacitors are used with a suitable circuit
is heard from the speaker. A1. Check IC1, IC2, and IC3 (4030), that employs a frequency-to-voltage
When the tank is neither 100% full and the continuity of the wires con- converter and displays the level of non-
nor it is above 10% (but less than 20%), nected to the sensors. If you find these conductive liquid. But for conductive
transistor T2 cuts off while transistor T3 alright, replace resistors R2 through R5 liquid like water, it is not advisable be-
is saturated to make the voltage across by 5.6k in the circuit before you switch cause due to electrolysis the sensors get
pins 1 and 2 of IC7 at almost 0V, and on the power. If you wish to construct damaged soon. The value of resistors R2
hence no sound is produced by the unit. the circuit Intelligent Water Level through R5 is 1.5k. Use 4.7k or 5.6k re-
A separate parts list and actual-size Controller' published in February issue sistors instead to avoid loading effect of
PCB layout as well as component layout of EFY, the same replacement may be ICs 4030. ❏
(Figs 9 and 10 respectively) are included
after integrating the power supply of Fig. 2
with liquid level indicator circuit of Fig. 7
and audio alarm unit of Fig. 8. ❏


Interface Your Printer
with 8085 Microprocessor
Shaila Ghanti

t is very convenient to interface a croprocessor know that its buffer is full,
printer to print 8085 programs. Here and it cannot accept any more characters Pin Assignments of Centronics
a simple hardware interface circuit until it prints out some of the already Interface Connector
with its driver software is described that stored characters. A common standard for Pin No. Signal Direction
would enable student to take printout of interfacing with parallel printers is the 2 Data bit 0 (D0) In
the 8085 programs in hexadecimal codes Centronics interface. 3 Data bit 1 (D1) In
along with their memory locations in the 4 Data bit 2 (D2) In
5 Data bit 3 (D3) In
format: xxxx DD, where XXXX is the 4-bit
hexadecimal address and DD is 2-bit hexa- Centronics interface 6
Data bit 4 (D4)
Data bit 5 (D5)
decimal data. Centronics printers usually have a 36-pin 8 Data bit 6 (D6) In
For most types of printers, the data to interface connector. The pin assignments 9 Data bit 7 (D0) In
1 Strobe (STR) In
be printed is sent to the printer as of the significant pins of Centronics inter-
14 Auto Feed (AF) In
face connector, used in this project, are 36 Device Select (DSL) In
given in Table 1. 31 Initialise (INIT) In
Fig. 1 shows the timing waveforms 11 Busy (BSY) Out
for transferring data characters to 13 Select (SEL) Out
32 Error (ERR) Out
the printer using the basic handshake 12 Paper end (PE) Out
signals. Assuming that the printer has 19 to
been initialised, first check the busy 30, 33 Ground —
signal pin to see if the printer is ready
to receive data. If this signal is low (not which is used for connecting 8255 to the
Fig. 1: Timing diagram busy), send an ASCII code on the eight printer, should normally have a 26-pin FRC
parallel data lines. After at least 0.5 µs, connector to meet with the corresponding
assert the STROBE connector on the kit, and the other end
signal low to tell the should have a 36-pin male Centronics con-
printer that a char- nector to go into the corresponding connec-
acter has been sent. tor on the printer.
The strobe signal Port A of 8255 is used for transferring
going low causes the the data to the printer. Port B is used for
printer to assert its checking the status signals coming from
Busy signal high. Af- the printer. Port C is used for sending the
Fig. 2: System's block diagram
ter a minimum time control signals required to activate the
ASCII characters on eight parallel of 0.5 µs the strobe signal can be raised printer. The interface signals between
lines. The printer receives the characters high again. Note that the data must be 8255 and the printer should be connected
to be printed and stores them in an inter- held valid on the data lines for at least 0.5 as show in Table 1.
nal buffer. When the printer detects a car- µs after the strobe signal is made high. (EFY Lab note. The maximum cur-
riage return (odH), it prints out the first When the printer is ready to receive the rent that an 8255 output pin can source
row of characters from the printer buffer. next character, the BUSY signal will be and sink is limited to 400 µA and 2.5 mA,
When the printer detects a second car- low. The process continues. respectively. To enhance this capability,
riage return, it prints out the second row The 8085 microprocessor is interfaced open-collector hex buffers/drivers 7407
of characters. The process continues until to the printer through 8255 program- shown in Fig. 3 were used for all output
the desired characters are printed. mable peripheral
Transfer of ASCII codes from the interface device as Table II
microprocessor to a printer needs to be shown in the block Port B of 8255—(Input) Status Signals
done on a handshake basis because the diagram (Fig.2) and Cent. Pin no b2 32 13 11
microprocessor can send characters much the detailed inter- Signal PE ERR SEL BSY Comments
faster than the printer can print them. face diagram (Fig.3). Data B3 B2 BI B0
The printer must in some way let the mi- One end of the cable, 0 1 1 0 =06H (status OK)


signal (DSL*)
to select the
printer. Read
the status to
find out wheth-
er the printer
is selected
and the Busy
signal is low.
Now send the
ASCII charac-
ter to print
the character,
followed by
pulse for 0.5
µs. The proc-
ess continues
Fig. 4: Actual-size, single-sided PCB for the
till the end of printer interface circuit
the program.

The end of the
program is in-
dicated using
The start-
ing location of
the program
to be printed
should be
stored in D
and E regis-
ters. The eight
MSBs and
eight LSBs of
memory loca-
tion should
be stored in
Fig. 3: Schematic diagram of the printer interface circuit D register and Fig. 5: Component layout for the PCB
E register, re-
port pins. For input port pins, there is no spectively. The complete software Parts List
danger of overloading, and hence these program is given with comments as Semiconductors:
pins were connected directly from the necessary. ICI, IC2 - 7407 hex buffer/driver (open
printer to the kit.) (EFY Lab note. The original program collector type)
Resistors (all ¼-watt, ±5% carbon, unless stated
was tried many times, but we did not suc- otherwise):
Printer driver program ceed. Finally, the program was extensively
modified and successfully run using Epson
R1-R12 - 1-Kilo-ohm (or use one-/two-
resistor networks
overview 9-pin printer. The program, along with Miscellaneous: - Centronics connector and
During initialisation, some memory loca- cable
Tables II and III showing the status and
tions are kept aside to
store the ASCII equiva- Table III
Port B of 8255—(Input) Status Signals
lent of the characters that
Cent pin no NU 14 31 1 NU 36 NU NU
are to be printed. This is Signal AF INIT STR DSL Comments
followed by configuration Data C7 C6 C5 C4 C3 C2 C1 C0
(initialisation) of 8255 by X 0 1 1 X 0 X X =30H
sending the mode con- X 0 0 1 X 0 X X =10H Printer
long delay initialisation
trol world to its control X 0 1 1 X 0 X X =30H
register. To initialise
the printer first send ini- X 0 0 1 X 0 X X =20H
tialisation (INIT*) pulse Short delay strobe
X 0 1 1 X 0 X X =30H
for a few microseconds.
Then send the select NU=Not Used


8085 Assembly Language Listing
Memory Instructions Code Comments Memory Instructions Code Comments
Location Location
7110 LXI H, 7000 21 7156 4F the status of printer
7111 00 7157 71
7112 70 7158 MVI B, 04 06 Else counter of 4 is initialised in B
7113 LXI D2A20 11 Initialise memory locations to Store 7159 04 register to print 4 digits of memory
ASCII codes of the program. 715A CALL 7220 CD address (use subroutine to transfer
7114 20 715B 20 data to printer in polling mode).
7115 2A 715C 72
7116 MOV A, H 7C To get the ASCII codes of address 715D INX H 23 Get next memory location
7117 CALL 70FC CD of memory location of the program to 715E DCR B 05 check whether 4 characters are
7118 FC be printed using the subroutine. 715F JNZ 715A C2 transferred.
7119 71 7160 5A
711A MOV A, H 7C 7161 71
711B CALL7100 CD 7162 MVI A, 20 3E send to (20) blank space to printer
711C 00 7163 20
711D 71 7164 OUT 08 D3
711E MOV A,L 7D 7165 08
711F CALL 70FC CD 7166 MVI A, 09 3E to generate STROBE pulse to printer
7120 FC 7167 09
7121 70 7168 OUT 0B D3
7122 MOV A, L 7D 7169 0B
7123 CALL 7100 CD 716A MVI A, O8 3E
7124 00 716B 08
7125 71 716C OUT 0B D3
7126 MOV A, M 7E To get the ASCII codes of the 716D 0B
7127 CALL 70FC CD contents of the program to be 716E MVI C, 02 0E Counter of 2 is initialised in C regis-
7128 FC printed using the subroutine. ter
7129 70 716F 02 to print 2 codes.
712A MOV A, M 7E 7170 CALL 7220 CD Use subroutine to transfer data.
712B CALL 7100 CD 7171 20 in polling mode.
712C 00 7172 72
712D 71 7173 INX H 23 Get next memory location.
712E INX H 23 Increment pointer to mem. location 7174 DCR C 0D Check whether 4 characters are
712F MOV A, M 7E Move contents of mem, into acc. 7175 JNZ 7170 C2 transferred.
7130 CPI CF FE Whether it is end of the program. 7176 70
7131 CF 7177 71
7132 JNZ 7116 C2 If not, start executing from 7116 7178 MVIA, 0A 3E send LF code to printer
7133 16 7179 0A
7134 71 717A OUT 08 D3
7135 MVIA, 43 3E If it is end of the program, 717B 08
7136 43 transfer the code for CF. 717C MVIA, 0D 3E send CR code to printer
7137 STAX D 12 717D 0D
7138 INX D 13 717E OUT 08 D3
7139 MVI A, 46 3E 717F 08
713A 46 7180 MVIA, 09 3E
713B STAX D 12 7181 09
713C DCX D 1B 7182 OUT 0B D3
713D LXI H 2A20 21 Initialise mem. Pointer to block 7183 0B
713E 20 (2A20) where ASCII code of charac- 7184 MVIA, 08 3E
713F 2A ters to be printed are stored. 7185 08
7140 MVI A, 82 3E Initialise 8255 7186 OUT 0B D3
7141 82 7187 MOV A,E 7B Check wheter the full program
7142 OUT 0B D3 Write control word in control register 7188 XRA L Ad code are transferred to printer
7143 0B of 8255 7189 JNZ 7158 C2 If not, continue to transfer next
7144 MVI A, 0B 3E Reset printer. 718A 58 codes.
7145 0B 718B 71
7146 OUT 0B D3 718C MOV A,D 7A
7147 0B 718D XRA H AC
7148 CALL 7200 CD Delay for a few microseconds. 718E JNZ 7158 C2 Else, stop executing the program
7149 00 718F 58
714A 72 7190 71
714B MVI A, 05 3E Send SELECT signal. 7191 RST 1 CF
714C 05
714D OUT 0B D3 Subroutine for converting hexadecimal to ASCII codes
714E 0B 70FC RRC OF Rotate right 4 times to get 4 MSB.
714F IN 09 DB Read the status of printer to find 70FD RRC OF
7150 09 out whether the printer is selected. 70FE RRC OF
7151 ANI 02 E6 70FF RRC OF
7152 02 7100 ANI OF E6 Mask 4 LSBs
7153 CPI 02 FE 7101 OF
7154 02 7102 CPI 0A FE Compare with 0A
7155 JNZ 714F C2 IF printer is not selected, again read 7103 0A


8085 Assembly Language Listing
Memory Instructions Code Comments Memory Instructions Code Comments
Location Location
7104 JC 7109 DC If it is less than 0A, 722D MOV A,M 7E Get the ASCII code from memory
7105 C6 722E OUT 08 D3 locations, send the data to printer to
7106 70 722F 08 print.
7107 ADI 07 C6 Add 07 to data 7230 MVI A,08 3E Send the strobe pulse with min
7108 07 7231 08 0.5µ duration.
7109 ADI 30 C6 Else add 30H to data to convert data 7232 OUT 0B D3
710A 30 into ASCII code. 7233 0B
710B STAX D 12 7234 MVI A,09 3E
710C INX D 13 7235 09
710D RET C9 7236 OUT 0B D3
7237 0B
Subroutine to transfer data in polling mode: 7238 MVI A,O8 3E
7220 MVI A 09 3E To generate the STROBE signal. 7239 08
7221 09 723A OUT 0B D3
7222 OUT 0B D3 723B 0B
7223 0B 723C RET C9
7224 IN 09 DB Find whether the printer is not Busy
7225 09 Subroutine for delay:
7226 ANI 01 E6 7200 MVI C, FF 0E Load C register with data FF.
7227 01 7201 FF

7228 CPI 00 FE 7202 DCR C 0D Decrement the contents of C reg.
7229 00 7203 JNZ 7202 C2 if the contents of C is not zero, goto
722A JNZ 7224 C2 7204 02 7202.
722B 24 7205 72
722C 72 7206 RET C9

modified program used by EFY

Addr. Hex code Label Mnemonics Remarks Addr. Hex code Label Mnemonics Remarks
9000 310095 LXI SP, 9500H ;Initialise stack pointer 9047 3E02 VI A,02H ;ASCII code for start of text
9003 11209D LXI D,9D20H ;Store location where 9049 D308 UT 08H
9006 EB XCHG ;data to be printed starts 904B CD5092 ALL 9250H ;Call status
;into register pair DE 904E CD7092 ALL 9270H ; Call strobe
9007 11209A LXI D, 9A20H ;Location where ASCII 9051 0604 X4: MVI B,04H ;Counter of 4 for printing
;stored 9053 CD249 X2: CALL 9224H ;four digits of addresses
900A 7C X1 MOV A,H 9056 23 INX H ;of memory location
900B CDFC90 CALL 90FCH 9057 05 DCR B
900E 7C MOV A,H 9058 C25390 JNZ X2
900F CD0091 CALL 9100H 905B 3E20 MVI A,20H ;Send blank space to printer
9012 7D MOV A,L 905D D308 OUT 08H
9013 CDFC90 CALL 90FCH 905F CD5092 CALL 9250H ;Call status
9016 7D OV A,L 9062 CD7092 CALL 9270H ; Call strobe
9017 CD0091 CALL 9100H 9065 0602 VI B, 02H ;Counter of 2 for printing
901A 7E MOV A,M ;Convert data to be 9067 CD2492 X3: CALL 9224H ;two digits of data
901B CDFC90 ALL 90FCH ;printed into ASCII 906A 23 INX H
901E 7E MOV A,M 906B 05 CR B
90IF CD0091 CALL 9100H 906C C26790 JNZ X3
9022 23 INX H 906F CD9092 CALL 9290H ;Call LFCR
9023 7E MOV A,M 9072 7B MOV A,E ;Check whether all data
9024 FECF CPI CFH ;End of data? 9073 AD XRA L ;has been transfered for
9026 C20A90 JNZ X1 ;printing
9029 3E43 VI A,43H ;ASCII code of C 9074 C25190 JNZ X4
902B 12 STAX D 9077 7A MOV A,D
902C 13 NX D 9078 AC XRA H
902D 3E46 MVI A,46H ;ASCII code of F 9079 C25190 JNZ X4
902F 12 TAX D 907C 3E03 MVI A,03H ;ASCII code for end of text
9030 1B CX D 907E D308 OUT 08H
9031 21209A XI H,9A20H ;Initialise mem. Pointer 9080 CD5092 CALL 9250H ;Call status
;to start of ASCII codes 9083 CD7092 CALL 9270H ; Call strobe
9034 3E82 VI A,82H ;Initialise 8255 9086 3E04 MVIA,04H ;ASCII code for end of
9036 D30B UT 0BH 9088 D308 OUT 08H ;transmission
9038 3E30 VI A,30H ;Initialise Printer 908A CD5092 CALL 9250H ;Call status
903A D30A UT 0AH 908B CD 7092 CALL 9270H ; Call strobe
903C 3E10 VI A,10H 9090 76 HLT
903E D30A UT 0AH
9040 CD0092 ALL 9200H ;Call delay ;Subroutine for converting hex to ASCII
9043 3E30 VI A,30H 90FC 0F RRC ;Rotate four times to get MSB
9045 D30A UT 0AH 90FD OF RRC


Addr. Hex code Label Mnemonics Remarks Addr. Hex code Label Mnemonics Remarks

90FE OF RRC 925B CA6692 JZ X11

9100 E60F ANI 0FH ;Mask four bits of LSB 925F C25392 JNZ X8
9102 FE0A PI 0AH 9262 05 DCR B
9104 DA0991 C X5 9263 C25192 JNZ X9
9107 C607 DI 07H 9266 C1 X11: POP B
9109 C630 X5: ADI 30H 9267 C9 RET
910B 12 STAX D
910C 13 INX D ;Strobe subroutine
910D C9 RET 9270 3E20 MVI A,20H
9272 D30A OUT 0AH
;Output Subroutine 9274 C5 PUSH B
9224 7E MOV A,M ;Output one byte of data 9275 0EFF MVI C,FFH
9225 D308 OUT 08H 9277 0D X10: DCR C
9227 CD5092 CALL 9250H ;Call status 9278 C27792 JNZ X10
922A CD7092 CALL 9270H ;Call strobe 927B C1 POP B
922D C9 RET 927C 3E30 MVI A,30H
927E D30A OUT 0AH
;Delay subroutine 9280 C9 RET
9200 C5 PUSH B
9201 06FF MVI B,FFH ;Line feed and Carriage return Subroutine
9203 0EFF X7: MVI C,FFH 9290 3E20 MVI A,20H ;ASCII code for space
9205 0D X6: DCR C 9292 D308 OUT 08H
9206 C20592 JNZ X6 9294 CD5092 CALL 9250H ;Call status
9209 05 DCR B 9297 CD 7092 CALL 9270H ;Call strobe
920A C20392 JNZ X7 929A 3E0A MVI A,0AH ;ASCII Code for Line feed
920D C1 POP B 929C D308 OUT 08H
920E C9 RET 929E CD5092 CALL 9250H ;Call status
92A1 CD7092 CALL 9270H ;Call strobe
;Status subroutine 92A4 3E0D MVI A,0DH ;ASCII code for Carriage
9250 C5 PUSH B ;Return
9251 06FF X9: MVI B,FFH 92A6 D308 OUT 08H
9253 0EFF XS: MVI C,FFH 92A8 CD5092 CALL 9250H ;Call status
9255 DB09 IN 09H ;In port B 92AB CD 7092 CALL 9270 H ;Call strobe
9257 E60F ANI 0FH ;Compare with 06H 92AE C9 RET
9259 FE06 CPI 06H

control signals that have been used in Port A (output): 08H onward ASCII conversion of data to be
program implementation, is included for Port B (input): 09H printed starts at 9A20H. Data to end with
the benefit of readers, who may try both Port c (output): 0AH CFH as the last byte.
the programs, if desired.) Control word register: 0BH The actual-size, single-sided PCB lay-
Address map of devices used: Important memory location: out of the printer interface circuit and the
RAM locations used: 9000H to 92AEH Stack pointer initialised: 9500H component layout are shown in Figs 4 and
(70FCH onwards used by author) Data to be printed is stored at: 9D20H 5, respectively. ❏


Junomon Abraham

rse code, introduced by Samuel been used, which relieves the micro- 7-segment display pattern employed
Morse, is still used universally processor from scanning the keyboard for different characters is shown in
even though better modes of and display. Here, 25 keys, includ- Table I.
communication are now available Follow- ing SHIFT and CTRL keys, and six Two hardware interrupts, RST5.5
ing are the main reasons for its preference 7-segment common cathode character and RST6.5, are used for reading the key
over other means of communication. displays are used. Though 7-segment entries. These are driven by the IRQ line
1. It enables communication with displays are not suitable for alpha- from the keyboard/display interface IC
distant stations, using low-power trans- numeric characters, these have been 8279.

mitters. used here with some compromise for A buffer (IC8) is connected at the
2. It avoids the problem of regional reducing the overall cost. (Note: The display output of 8279 to drive the
accents and pronunciation. use of dot-matrix LCD display avoids 7-segment displays. The encoded scan
3. It has the ability to override noise the difficulty in displaying characters lines (SL2-SL0) are decoded by an octal
as it occupies only a fraction of the in 7-segment format. One can go for a decoder 74LS138 (IC9), whose outputs
bandwidth microcontroller design, if needed.) The drive the common cathode of displays
required for via transistor switches. The keys are
a radio te- TABLE II wired in such a way that those can be
lephony sig- Address Distribution represented by the seven higher order
nal. Device Address rate of the keyboard data.
The cir- EPROM 0000 to 03FF Morse signals in the form of sound are
cuit presented RAM 1000 to 17FF converted to microprocessor-compatible
here converts 8279: signals. The arrangement comprises con-
Command Port 21
text into the Data Port 20
denser microphone, preamplifier, and
correspond- retriggerable monostable multivibrator
ing Morse
code, and vice
versa. The
high light of
this circuit is
that is can in-
terpret Morse
signals avail-
able in the
form of sound
from ham
radio or any
other source.
It is very use-
ful for not
only learning
but also for transmission and reception of
Morse code. It can find application in ham
radio, telegraphy, etc.

The circuit is configured around the
basic 8085 microprocessor. For simplify-
ing the overall design, a programmable
keyboard/display interface 8279 chip has


PARTS LIST and also acts as a stack. One can en- firmware is divided into the following
Semiconductors: ter/store a maximum of approximately modules: (a) booting, (b) keyboard, (c)
IC1 - 8085A microprocessor 1,750 characters in the RAM. This is transmit, (d) receive, (e) play, and (f)
IC2 - 74LS373 octal D-type latches adequate for normal applications. lookup table.
IC3 - 6116 RAM (2 kB)
IC4 - 27C32 EPROM (4 kB) In case one needs to store lengthy The logic of the program can be gener-
IC5 - 8279 keyboard/display decoder text, one should use a larger capac- ally understood from the Assembly lan-
IC6, IC9 - 74LS138 3-bit binary ity RAM. Battery backup may be guage listing given in Appendix A. A brief
decoder used for avoiding loss of data due to description of each module is, however
IC7 - 74LS123 retriggerable monosta-
power failure. The low-level address/ given below:
ble multivibrator
IC8 - 74LS244 octal bus driver data lines of 8085 are demultiplexed (a) Booting: The section initializes
IC10 - 7805 +5 volt regulator using an octal transparent latch stack pointer 8279 and the interrupts. It
T1 - BC548 npn transistor IC 74LS373. also fixes defaults speed for Morse code.
T2 - BC549 npn transistor The address bits A12 and A13 are de- It is the first module executed when you
T3-T8 - BC558 pnp transistor
Dl - 1N4148 switching diode coded by IC6 to generate chip select (CS) switch on the power supply.
LED1 - LED signals to various ICs. The address map of (b) Keyboard: When a key is
DIS1-DIS6- LTS543 common-cath- devices is indicated in Table II. pressed, IRQ pin of 8279 interrupts
ode 8085. The ISR (interrupt service rou-
tine) reads the keyboard data and, if
Resistors (all ¼ watt, ±5% carbon, unless Firmware needed, does some manipulations. It also
stated otherwise) The software driver routines for the cir- displays the entered characters in the
Rl - 68-kilo-ohm
R2 - 3.3-kilo-ohm cuit, along with their Assembly language 7-segment display. (Table III has been
R3 - 2.2-kilo-ohm code, are listed in Appendix A. Basically, included by EFY for ready reference by
R4 - 5.6-kilo-ohm the following functions are performed by the readers to know the hex data gen-
R5 - 1-mega-ohm
R6 - 15-kilo-ohm the software program: erated by 8279 when any key is either
R7, R8 - 1-kilo-ohm 1. Initialisation of the peripherals. pressed alone or in combination with
R9-R16 - 68-ohm 2. Reading the depressed key data and SHIFT or CTRL key.)
R17-R22 - 220-ohm
R23 - 180-ohm its storage in RAM. (c) Transmit. This module converts
VR1 - 2.2-kilo-ohm preset 3. Writing data into the display RAM each character in the RAM to its corre-
VR2 - 100-ohm preset
in 8279. sponding Morse code signals which are
C1 - 2.2uF, 16V electrolytic
4. Generation of Morse code. output through the SOD line. The speed
C2, C4, C6 - 0.luF ceramic disc 5. Recognition of Morse code from its of transmission or words per minute de-
C3 - 10uF, 16V electrolytic sound. pends on the value entered in the setup
C5 - 0.001uF ceramic disc
C7 - 10pF ceramic disc 6. Giving proper messages at appropri- menu.
Miscellaneous: ate time. (d) Receive. The acquisition of
PZ1 - Piezo buzzer Since Morse code is a time-dependent Morse code is done by checking the
MIC - Condenser microphone code, the program contains many jump presence of sound with time. The
S1-S26 - Tactile switches for instructions. The program has been module continuously monitors the SID
XTAL - 6.144 MHz crystal make interactive and user-friendly. The pin of 8085 microprocessor, where the

74LS123 (IC7). The out-

put of IC7 drives SID pin Table IV
Lookup Table
of 8085 and it is in ‘high’
logic state when a sound Chr/word Address Hexcode Chr/word Address Hexcode Chr/word Address Hexcode
is detected by the micro- 0 0300 3FAA0E00 J 034C IE A9 03 00 . 03B4 80 99 39 00
phone. The sensitivity of 1 0304 06 A9 0E 00 K 0350 70 E6 00 00 , 03B8 04 5A 3A 00
2 0308 5BA5OEOO L 0354 38 59 03 00 ; 03BC 84 66 36 00
the amplifier can be ad- 3 030C 4F95 0E00 M 0358 55 3A 00 00 ? 03C0 D3 A5 35 00
justed by preset VR2. 4 0310 66 55 0E 00 035C 46 - 03C4 08 56 39 00
The converted Morse 5 0314 6D55 0D00 03C8 00 3F 00 00
code drives a piezo buzzer 6 0318 7D 56 0D 00 N 0380 54 36 00 00 EOM* 03CC OF 99 0D 00
7 031C 07 5A0D00 O 0384 5C EA 00 00 WAIT* 03D0 7E 59 0D 00
via a transistor connected
8 0320 7F 6A 0D 00 P 0388 73 69 03 00 BT* 03D4 49 56 0E 00
at the SOD line of 8085 9 0324 6F AA 0D 00 Q 038C 67 9A 03 00 SK* 03D8 4F 95 39 00
microprocessor. Intensity A 0328 77 39 00 00 R 0390 50 D9 00 00 SELECt 03DC 6D 79 38 79
of the sound can be con- B 032C 7C 56 03 00 S 0394 6D D5 00 00 03E0 39 78 78 50
trolled by potentiometer C 0330 39 66 03 00 T 0398 78 0E 00 00 trAnst 03E4 77 54 6D 78
D 0334 5E D6 00 00 U 039C 3E E5 00 00 M oVEr 03E8 55 00 5C 2A
VR1. E 0338 79 0D 00 00 V 03A0 2A 95 03 00 rECEIE 03EC 79 50 50 79
The firmware is F 033C 7165 03 00 W 03A4 6A E9 00 00 03F0 39 79 30 79
stored in 27C32 (4k G 0340 3D DA 00 00 X 03A8 52 96 03 00 SEtup 03F4 6D 79 78 3E
EPROM—only 1 kB H 0344 76 55 03 00 Y 03AC 6E A6 03 00 03F8 73 00 00 00
I 0348 30 35 00 00 Z 03B0 4B 5A 03 00 03FC 00 00 00 00
is needed for the pro-
gram). RAM 6116 stores *Notes: 1. EOM=End of message= 3 2. WAIT= 8
the keyboard entries 3. BT=Sentence separation=
3 4. SK=End of work= 3




sound-converted logic level (depending
on whether the sound is present or not)
is available. It compares this logic level

Size 215×100 mm
with a prefixed time value and accord-
ingly decides whether the sound was
due to dot or dash. Moreover, it displays
characters corresponding to the entered
Morse code.
(e) Display. This module displays
characters in the moving display format
as per the entered message. The speed
of movement is fixed to approximately
three characters per second.
(f) Lookup table (Table IV). This
is a block of data, which contains the
7-segment data for every character
and the data needed for Morse code
generation or reception. Each character
takes four EPROM locations. The first
location indicates the 7-segment data,
while the second and third locations
hold the Morse data code. The fourth
location is unused. (EFY Note. We
have included Table IV showing the
hex data generated by depression of
any key alone or in combination with
SHIFT or CTRL keys, for ready refer-
ence by the readers.)

Control-key functions
Before going to the operating procedure,
we have to know the functions of key as-
sociated with CTRL key.
CTRL+SETUP (8EH). The default
speed is initialized for approximately
5 words/minute. If you want to change
this setting, you can do so by using this
control key combination. When you press
this combination k, the message ‘SEtUP’
is displayed. Here you can enter any
one of the characters ranging from ‘1’
through ‘9’ and ‘A’ through ‘K’ to change
the speed. Note that the minimum speed
is associated with ‘K’ and the maximum
with ‘1’.
CTRL+CLEAR (98H). It clears the
RAM content.
used for displaying the RAM content in
moving format. You can interrupt any
process by pressing any control key that
has no function.
CTRL+CONT (86). It is used for
continuing the play operation if it were

Operating procedure
1. Switch on the power supply. A message Fig. 2: Actual-size, single sided PCB for the Morse processor


Addr. Opcode Label Mnemonics Comments Addr. Opcode Label Mnemonics Comments
Booting 0077 3A5017 LDA 175OH The following CNTL
0000 31FF17 LXI SP.17FFH 007A B7 ORAA key functions are only for
Initialise stack pointer TRANSMIT mode
0003 3E10 MVIA.10H 007B CA8000 JZ 0080H Checking whether we were
Initialise 8279 in the TRANSMIT mode
0005 D321 OUT 21H 007E FB El
0007 3E40 MVI A.40H 007F 76 HLT
0009 D321 OUT 21H 0080 F1 POPPSW Getting key closure data
000B 3E0D MVI A.0DH which is stored in stack
000D 30 SIM 0081 FE92 CPI92H Checking CNTL+<—key
Activating RST6.5 0083 C28900 JNZ 0089H
000E 325017 STA 1750H 0086 2B DCXH Shifting the characters
Updating mode and position 0087 2B DCXH right by one place
data 0088 C9 RET
0011 211D00 LXI H.001DH 0089 FE90 CPI90H Checking CNTL+ßkey
0014 225117 SHLD 1751H 008B C8 RZ Shifting the characters by
0017 21246C LXIH.6C24H Fixing one place
default setup 008C FE80 CPI80H Checking CNTL+TABR key
001A 227017 SHLD 1770H 008E C29600 JNZ 0096H
001D 11DC03 LXI D.03DCH 0091 110500 LXID.0005H Shifting the characters left

0020 CDE000 CALL DISPLAY Display ‘SELECt’ by six places
0023 FB El 0094 19 DAD D
0024 76 HLT Halt 0095 C9 RET
0096 FE82 CPI 82H Checking CNTL+TABL key
RST 5.5 0098 C2A000 JNZ 00A0H
002C C3F700 JMP 00F7H Go to ISR of RST5.5 009B 11F9FF LXI D.,FFF9H Shifting the characters right
by six places
RST 6.5
009E 19 DAD D
0034 DB20 IN 20H Reading keyboard data from
009F C9 RET
IC 8279
00A0 FE88 CPI88H Checking CNTL+ START
0036 F5 PUSHPSW Store it in the stack
00A5 FE96 CPI 96H Checking CNTL+DEL key
0039 CA0002 JZ RECEIVE
00A7 C2BA00 JNZ 00BAH
003C FE8C CPI8CH Checking CNTL+
00AB 46 MOV B,M Delete one character in the
left most position of the display
0041 FE84 CPI 84H Checking CNTL+PLAY key
0043 CAD001 JZ PLAY
00AD 70 MOV M,B
0046 FE86 CPI 86H Checking CNTL+
00AE 23 INX H
00AF 23 INX H
0048 CAD501 JZ 01D5H
00B0 7C MOVA.H
004B FE98 CPI98H
00B1 FE17 CPI 17H
Checking CNTL+ CLEAR
00B3 DAAB00 JC 00ABH
00B6 El POPH
004D C26000 JNZ 0060H
00B7 2B DCX H
0050 210010 LXIH.1000H Clearing the RAM
00B8 2B DCX H
0053 36C8 MVI M.C8H
00B9 C9 RET
0055 23 INXH
00BA FE94 CPI 94H Checking CNTL+INS key
0056 7C MOV A, H
00BC C2D100 JNZ 00D1H
0057 FE17 CPI 17H
00BF 2B DCX H Inserting a space for adding
0059 DA5300 JC 0053H
005C 2A5117 LHLD 1751H Return to mode from 00C0 E5 PUSH H
005F E9 PCHL where clearing action is 00C1 46 MOVB.M
called 00C2 36C8 MVI M.C8H
0060 FE8E CPI8EH Checking CNTL+ SETUP 00C4 23 INX H
key 00C5 7E MOV A,M
0062 C27700 JNZ 0077H 00C6 70 MOV M,B
0065 3E0E MVIA.0EH Activating RST5.5 00C7 47 MOV B,A
0067 30 SIM 00C8 7C MOVA.H
0068 11F403 LXI D.03F4H 00C9 FE17 CPI 17H
006B CDE000 CALL DISPLAY Display the message ‘SEtUP’ 00CB DAC400 JC 00C4H
006E FB El 00CE E1 POPH
006F 76 HLT 00CF 2B DCX H
0070 3E0D MV1A.0DH Activating RST6.5 00D0 C9 RET
0072 30 SIM 00D1 FE7F CPI7FH Checking whether key data
0073 2A5117 LHLD 1751H is valid character
0076 E9 PCHL Return to mode from where 00D3 D2CF00 JNC 00CFH
setup action is called 00D6 07 RLC


Addr. Opcode Label Mnemonics Comments Addr. Opcode Label Mnemonics Comments

00D7 77 MOVM,A Enter it into the RAM 0156 217017 LXI H.1770H
00D8 C9 RET Return 0159 46 MOVB.M
015A CD7001 CALL DELAY1 Waiting
015D 05 DCRB
00E0 0E06 DISPLAY: MVI C,06H Display six characters taken
015E C25A01 JNZ015AH
from lookup table
0161 Fl POPPSW
00E2 1A LDAX D Lookup table is pointed to
0162 0F RRC
by DE -reg pair
0163 0F RRC
00E3 D320 OUT 20H
0164 0D DCRC
00E5 13 INX D
0165 C22501 JNZ 0125H
0168 C32101 JMP 0121H
00E7 C2E200 JNZ 00E2H
00EA CDCOO1 CALL DELAY2 Wait for some time
0170 E5 DELAY1: PUSH H Executing these instructions
00F0 C9 RET Return
require approximately
0171 21CF01 LXIH.01CFH 3 msec
0174 2B DCXH
00F7 DB20 IN 20H Reading key closure data
0175 7C MOVA.H
from 8279
0176 B5 ORAL
00F9 E63F ANI3FH
0177 C27401 JNZ0174H
00FB 07 RLC
017A E1 POPH
00FC 327017 STA 1770H Storing clot value
017B C9 RET
00FF 47 MOV B,A
0100 80 ADD B
0101 80 ADDB
0180 AF KEYBOARD: XRAA Updating mode and positing
0102 327117 STA 1771H Storing dash value
0105 C9 RET Return
0181 325017 STA 1750H
0184 218001 LXIH.0180H
0187 225117 SHLD 1751H
018A 11E203 LXI D.03E2H Displaying message
0113 7C MOVA.H
018D CDE000 CALL DISPLAY ‘trAnSf for indicating the
0114 FE17 CPI17H Checking end of mem.
0116 D2B301 JNC 01B3H
0190 31FF17 LXI SP.17FFH
0119 1603 MVID.03H
0193 210610 LXIH.1006H Entering keyboard data to
011B 5E MOVE.M
the RAM
011C 1A LDAX D
011D D320 OUT20H Display character in the
0199 19 DADD
019A 0E06 MVI C.06H
011F F3 DI
019C 1603 MVID.03H
0120 E5 PUSHH
019E 5E MOV E,M
0121 0EO4 MV1C.04H Morse code generation
019F 1A LDAX D
0123 13 INXD
01A0 D320 OUT20H
0124 1A LDAX D
01A2 23 INX H
01A3 0D DCRC
0126 217017 LXIH.1770H
01A4 C29E01 JNZ 019EH
0129 E603 ANI 03H
01A7 7C MOVA.H
012B FE01 CPI01H
01A8 FE17 CPI17H Checking end of mem.
012D CA4801 JZ 0148H
01AA DAB301 JC 01B3H
0130 23 INXH
01AD 11E803 LXI D.03E8H
0131 FE02 CPI02H
01B0 CDE000 CALL DISPLAY If mem. is over display
0133 CA4801 JZ 0148H
0136 FE03 CPI 03H
01B3 FB El
0138 CA5901 JZ0159H
01B4 76 HLT
01B5 C39601 JMP 0196H
013C El POPH
0131 FB El
013E 7E MOVA.M
01C0 0E9F DELAY2: MVIC.9FH Wait approximately
013F 23 INXH
400 msec
0140 FECC CPICCH Checking end of message
01C5 0D DCRC
0142 C21001 JNZ0110H
01C6 C2C201 JNZ 01C2H
0145 C3B301 JMP01B3H
01C9 C9 RET
0148 3ECD MVIA,CDH Setting SOD line
014A 30 SIM
014B 46 MOVB.M
01D0 1603 PLAY: MVI D.03H
014C CD7001 CALLDELAY1 Waiting
01D2 210510 LXI H.1005H
014F 05 DCRB
01D5 F3 DI
0150 C24C01 JNZ 014CH
01D6 23 INXH
0153 3E4D MVIA.4DH Resetting SOD line
01D7 7C MOVA.H
0155 30 SIM


Addr. Opcode Label Mnemonics Comments Addr. Opcode Label Mnemonics Comments

01D8 FE17 CPI 17H Checking end of mem. 0258 OF RRC

01DA D2EB01 JNC 01EBH 0259 OF RRC
025A B2 ORA D
01DF D320 OUT20H Displaying data in RAM 025D C22902 JNZ 0229H
0260 El POP H
01E1 CDC001 CALLDELAY2 Wait for some time 0261 71 MOVM.C
01E4 FB El 0262 23 INX H
01E5 7E MOVA.M 0263 C32302 JMP 0223H
0266 79 MOVA.C
01E6 FECC CPICCH Checking end of mem. 0267 OF RRC
symbol’]’ 0268 OF RRC
01E8 C2D501 JNZ 01D5H 0269 F6C0 ORIC0H
01EB C3B301 JMP01B3H Go to keyboard module 026C CA7402 JZ 0274H
0271 C36B02 JMP 026BH
0200 3EFF RECEIVE: MVIA.FFH Updating mode and position 0274 El POP H
data 0275 77 MOV M,A
0202 325017 STA 1750H 0276 0638 MVI B.38H
Comparing obtained
0205 210002 LXI H,0200H 0278 21FD02 LXI H.02FDH moree
0208 225117 SHLD 1751H code data with
020B 11EE03 LXI D.03EEH lookup data
027B 3A8017 LDA 1780H
020E CDE000 CALL DISPLAY Display message ‘rECEIE’ 027E 23 INXH

0211 11FA03 LXI D.03FAH 027F 23 INXH
0214 CDE000 CALL DISPLAY Clear the display 0280 23 INX H
0281 23 INXH
0217 FB El 0282 05 DCR B
0218 110510 LXI D.1005H Morse code aquisition 0283 C29102 JNZ 0291H If given
021B 13 INXD morse code is
invalid, display V
021C D5 PUSH D 0286 FE04 CPI 04H
021D 218117 LXIH.1781H 0288 DA1D02 JC 021DH
0220 3600 MVI M.00H 028B 215C03 LXI H.035CH
028E C39F02 JMP 029FH
0222 2B DCX H 0291 BE CMPM
0223 E5 PUSH H 0292 C27B02 JNZ 027BH
0224 0E00 MVI C,00H 0295 3A8117 LDA 1781H
0298 23 INXH
0226 1E04 MVI E.04H 0299 BE CMP M
0228 61 MOVH.C 029A 2B DCX H
0229 0600 MVI B.00H 029B C27B02 JNZ 027BH
029E 2B DCX H
022B CD7001 CALL DELAY1 029F Dl POPD
022E 04 INR B 02A0 7A MOV A,D
022F 20 RIM 02A1 FE17 CPI 17H
Reading the SID pin Checking end of mem.
02A3 D2D102 JNC 02D1H
0230 07 RLC 02A6 7E MOVA.M
0231 DA2B02 JC 022BH 02A7 D320 OUT 20H Display
0234 24 INR H the character
02A9 7D MOV A,L Store
0235 3A7117 LDA 1771H data, corresponding
0238 BC CMPH 02AA 12 STAXD to
Checking for the space displayed character, in
the RAM
between characters 02AB 0600 MVI B,00H
0239 DA6602 JC 0266H 02AD 217017 LXI H.1770H
023C 78 MOV A,B 02B0 7E MOVA.M
02B1 07 RLC
023D FE02 CPI02H 02B2 23 INX H
023F DA2902 JC 0229H 02B3 86 ADD M
0242 2600 MVI H.00H 02B4 D2B802 JNC 02B8H
02B7 04 INRB
0244 1640 MVI D,40H 02B8 4F MOV C,A
0246 3A7117 LDA 1771H 02B9 0B DCX B
02BD 20 RIM
024A B8 CMPB 02BE 07 RLC
Checking for dot and dash 02BF DA1B02 JC 021BH Check
024B D25702 JNC 0257H for space between
02C2 78 MOVA.B words
024E 7A MOV A,D 02C3 B1 ORAC
024F 07 RLC 02C4 C2B902 JNZ 02B9H
0250 57 MOV DA 02C7 AF XRAA
02C8 D320 OUT 20H Giving
0251 00 NOP space in display
0252 00 NOP 02CA 13 INX D
0253 00 NOP 02CB 3EC8 MVI A,C8H
02CD 12 STAX D Store
0254 00 NOP the apace data in the
0255 00 NOP RAM
0256 00 NOP 02CE C31B02 JMP021BH Repeat
the process
0257 79 MOVA.C 02D1 76 HLT Halt
Constructing morse code


‘SELECt’ will be displayed. By depressing
the appropriate key, you can select any
one of the following modes: (a) transmit,
(b) receive, (c) setup, (d) play, (e) continue,
and (f) clear.
2. Press CTRL+TRANSMIT keys
for entering into the transmit mode.
A message ‘trAnSt’ appears for a sec-
ond, after which you can enter your
3. At the end of the message you have
to enter ‘]’ symbol (by pressing SHIFT+]
keys, i.e. 66H) for invoking the micro-
4. By the use of arrow key ( or 
or by TAB (TAB R or TAB L) keys, set
the location in the message at which the
transmission is to start. If you want to
transmit the message from beginning
depress CTRL+TRANSMIT keys again
for getting into the first character.
5. Press CTRL+START keys for get-
ting Morse code of the message.
6. You can go to any other mode by
selecting the correspond mode before fin-
ishing the transmission or later.
7. For entering into the receive
mode, press the CTRL+RECEIVE keys.
You will see the ‘rECEIE’ message for
one second.
8. Generate Morse code using a buzzer,
voice, or some other source (such as ham
radio and recorded tape).
9. The acceptance of sound will
be indicated by LED1 for duration of
‘Dit’/’Dash’. If LED does not light, adjust
the gain of the amplifier using potmeter
10. The converted data can be replayed
by pressing the CTRL+PLAY keys.
Note. 1. The clear and setup control
keys can be used, at any time, if needed.

PCB designed particularly for this
circuit (as given in Fig. 2, with compo-
nent layout shown in Fig. 3) is needed
for making this circuit. IC bases are
preferred for fixing the ICs. For con-
tinuous operation, provide a heat
sink for the regulator IC. Since this is
based on time comparison, it is neces-
sary to use the correct frequency crystal
(6.144 MHz).
Fig. 3: Component layout for the PCB

Readers’ comments: Going through the software, we found an anomalies in the software.
Q1. In the software part of this project error at the address 003CH, after which Sidharth M. Modi
some steps are missing, due to which the processor doesn’t jump to the transmit Mumbai
the processor is not functioning properly. mode and hangs up. Please correct the Q2. The project ‘Morse Processor’ pub-


lished in March issue correctly outputs in The author, Junomon Abraham, re- is absolutely correct. If the same condi-
the initial stages but displays the message plies: tions still persist, the problem is with
‘transt’ on going to the transmit mode. A1. The firmware is correct and the your hardware.
After this when I press any key, it doesn’t same was duly tested at EFY. “You need A3. It is possible to add a CRT control-
take the input and doesn’t display the not doubt the code at location 003CH, ler to 8085 by changing the firmware. You
same in the 7-segment display. As a corol- where it checks for the Ctrl+Transmit can use the easily available 6845 CRT
lary, it’s also not giving the corresponding key. From here, it goes to the keyboard controller. The article based on this IC
Morse code. routine and feeds the message to the was published in the book Learn to Use
Sunil Kumar B. RAM. The actual conversion process Microprocessors by K. Padmanabhan pub-
Through e-mail starts when we press Ctrl+Start key, lished by EFY. The project ‘Video Display
Q3. How can I interface CRT display during which the processor goes to the Add-On Board for the 8085 Kit’ based on
with 8085 microprocessor? Also provide transmit routine. 9364 chip was published as a technical
me the complete circuit along with the IC A2. Make sure that you have loaded article on page 21 in EFY’s Aug. ’83 issue.
numbers. the look-up table (Table IV) in the The same is also reproduced in Chapter XI
Anwar Ali, Hyderabad EPROM and that the entered program of the above titled book.



Access-Control System
bhaskar banerjee

he easy-to-construct access control If any one or more of the six consecu- IC4). Each CD4508 contains two complete-
(code lock) circuit presented here tive keyboard-entered digits do not con- ly independent 4-bit data latches having a
incorporates the following unique form to the predetermined code, an alarm common power supply. The 6-digit code is
features: generator sounds the alarm to indicate stored in these latches.
(a) Many people can use the same sys- wrong code. If the result of final compari- The 4-bit data bus originating from
tem with their own unique 6-digit code. son of all the six digits is correct, a mono the output of IC1 is connected to data
(b) A single-digit system code has been multivibrator, serving as lock driver for
Parts List
included, which is common to all users of opening/closing a lock, gets activated for
the system. It can be easily changed with a fixed preset duration. Semiconductors:
IC1 - 74C922 16-key encoder
the help of DIP switches. The detailed description of individual IC2-IC4 - CD4508 dual 4-bit latch
units, as shown in Fig. 2, is as follows: IC5 - CD4017 decade counter
Keyboard and keyboard encoder. IC6 - 27C32 EPROM
Description The keyboard consists of 16 push-to-on IC7-IC9 - CD4063 4-bit magnitude
The block diagram of the system shown type keys in a 4x4 matrix format. It can be IC10 - CD4528 dual retriggerable
in Fig. 1 provides an overall view of its made using data switches or one can use monostable
composition and working. A 16-digit key- membrane-type keyboard at some extra IC11 - NE555 timer
pad is used for sequentially entering six cost. The keys should be numbered in Hex IC12 - CD4069 Hex inverter
Hex numbers, which are decoded by the as shown in the figure. T1-T4 - BC547 npn transistor
T5 - SL100 npn transistor
keyboard encoder into their equivalent The encoder is built around 74C922 T6 - 2P4M SCR
binary numbers and stored in separate (IC1), which is a 16-key keyboard encoder. D1, D2, D4 - 1N4148 switching diode
data latches in binary form. It generates a 4-bit binary number corre- D3 - 1N4007 rectifier diode
The first three Hex numbers are used sponding to the key pressed; for example, LED1-LED3 - Red LED
LED4 - Green LED
as an address for an EPROM, which shorting pin 1 (R1) with pin 11 (C1) gener-
stores a predetermined code at prefixed ates the binary equivalent of digit ‘0’. Resistors (¼-watt ±5% carbon, unless stated
addresses allocated to separate users or Whenever a key is pressed, the signal R1, R3, R4,
used for separate purposes. The code data generated by this encoder IC is available R15, - 10-kilo-ohm
output from EPROM (one byte/two nibbles) as logic ‘high’ output at pin 12 and is used R2, R5, R8,
at a specified address is compared with to activate a piezo-buzzer (PZ1) via tran- R21, R22 - 4.7-kilo-ohm
R6 - 18-kilo-ohm
the next two keyboard entries in two 4-bit sistor T1 (BC547). The continuous tone of R7 - 10-mega-ohm
comparators that are cascaded together. PZ1 indicates that a key is pressed. The R9 - 2.2-mega-ohm
The resultant outputs of these two key-pressed signal is also used to store R10, R11,
comparators are connected to the next data in the latches. R17-R20 - 1-kilo-ohm
comparator stage, in which the last The output from pin 12 is connected to R12-R14 - 470-ohm
R16 - 47-kilo-ohm
keyboard digit (i.e. sixth Hex digit) is pin 13 of IC5 (CD4017 counter) for clock- R23 - 47-ohm
compared with the system code selected ing at its trailing edge. On each clocking, Capacitors:
by DIP switch. counter IC5 advances by one count and C1, C7, C8,
thereby stores C12 - 0.1µF ceramic disc
data in separate C2 - 2.2µF, 25V electrolytic
C3, C5, C6,
data latches one
C9, C10 - 22µF, 25V electrolytic
after the other. C4, C13 - 47µF, 25V electrolytic
IC1 also holds C11 - 470µF, 25V electrolytic
the last number Miscellaneous:
at its output S1 - Push-to-on switch
pins. S2 - Push-to-off switch
- 4x4 keyboard matrix
Data latch-
PZ1 - Continuous tone-type piezo-
es. There are buzzer
six data latches RL1 - 9V, 200-ohm, 1 C/O relay
formed from S3 - 4-way DIP switch
three CD4508 - Regulated 5V power supply
Fig. 1: Block diagram of the access-control system ICs (IC2 through



Fig. 2: Schematic diagram of access-control system
(IC6). Out of the six Hex digits, first five
digits are used as personalised code, and
out of these five digits, the first three are
used to form an address for EPROM.
The leftmost digit of the code is the
MSD (most significant digit) and the third
digit from left is the LSD (least signifi-
cant digit) of the 12-bit wide address for
IC6. The fourth and fifth digits from left
are to be the same as the data stored in
IC6 (beforehand) at that particular ad-
dress. Thus, when a code is entered via
the keyboard, the fourth and fifth digits
are compared with the data stored at the
address formed by the first three digits.
(The EPROM can be programmed with
the help of ‘Manual EPROM Programmer’,
and may be replaced by an EEPROM for
better reliability.)
Code comparator. There are three
4-bit comparators (IC7 through IC9)
used in the circuit, which are cascaded
together to form a 12-bit comparator.
Comparators IC7 and IC8 compare the
8-bit data output of EPROM with the cor-
responding fourth and fifth digits entered
via the keyboard and stored in latches
IC3B and IC4A.
While IC7 compares the upper 4-bit
output of IC6 with the contents of IC3B
(i.e. the fourth digit from left), IC8 com-
pares the lower 4-bit output of IC6 with
the contents of IC4A (i.e. the fifth digit
from left). Similarly, IC9 compares the
last digit (i.e. the contents of IC4B) with
the code entered/formed by 4-way DIP
switch S3 (marked A through D), which is
referred to here as the system code. This
system code digit can be changed from
time to time.
The result of the comparison by the
three comparators is finally available from
Fig. 3: Actual-size, single-sided PCB layout for access-control system IC9. If the entered code matches with the
stored data, pin 6 of IC9 goes high, indi-
input pins of all the six latches in parallel. to be stored and available at the output cating a correct code. Otherwise, either of
For example, pin 17 (QA) of IC1 is con- of IC2A. pins 5 and 7 goes high depending upon the
nected to the corresponding pins 4 and 16 Similarly, when the second key is magnitude of the data. Pins 5 and 7 are
of all the latches as the LSB of 4-bit binary pressed, new data is stored in IC2B with- connected together via diodes D1 and D2
output from IC1. Initially, pin 3 of IC5 out affecting the previously stored data in and used as the trigger for alarm circuit.
provides a high output to ‘clear’ and ‘store’ IC2A. The outputs from first three data The outputs from IC9 are available only
pins 1 and 2 of IC2A, thereby clearing its latches are connected to address pins of after entering the last digit.
4-bit register. EPROM 27C32 (IC6). The outputs from Alarm generator. The alarm gen-
When a key is pressed, the equivalent fourth and fifth data latches are connected erator is built around a 555 timer (IC11).
binary code is present at data input pins to two 4-bit magnitude comparators IC7 The logic ‘high’ output from pin 5 or pin 7
of all the latches. On releasing the key, and IC8 (CD4063), and the output from of IC9 triggers the SCR and applies Vcc
pin 12 of IC1 changes its state from ‘high’ sixth data latch is connected to a similar supply to IC 555 to make it oscillate. The
to ‘low’, thereby generating the required 4-bit magnitude comparator IC9 for fur- output from pin 3 of IC11 is used to drive
clock pulse for IC5. This clocking makes ther processing. transistor T2 (BC547) to generate a long-
pins 3 and 2 of IC5 low and high, respec- The memory. All 8-bit codes, except duration alarm tone from PZ1.
tively, causing the binary data correspond- the 4-bit system code, are stored at differ- A common buzzer is used for key-press
ing to the first Hex digit keyboard entry ent locations (addresses) in the EPROM audio indicator and alarm generator to


gering, pin 6 of IC10 becomes high and
remains in that state for a predeter-
mined time period. The output at pin 6
of IC10 drives transistor T5 (SL100) to
operate relay RL1. When the system is
locked, red LED1 glows, and when it is
unlocked, green LED4 glows.
The other half of IC10 is used to keep
the keyboard activated for a predeter-
mined time. The keyboard is activated
by pressing switch S1. This feature im-
proves the security of the system.

Data input/output pins are to be con-
nected with utmost care because im-
proper connection will force the system
to work unpredictably. Also, care should

be taken while using IC1, as it is quite
costly. The points marked Vcc should be
connected to the power supply directly.
The system can be built on a general-
purpose PCB or a veroboard. A single-
sided PCB layout for the circuit is, how-
ever, shown in Fig. 3, with its component
layout shown in Fig. 4.

Initially, when IC1 is disabled by IC10,
no code can be entered. To activate the
keyboard, press switch S1 momentar-
ily. This will activate the keyboard for
a predetermined time. The code should
be entered within this time. Using the
4-way DIP switch S3, the system code
can be changed at any time for extra
If wrong code is entered, the buzzer
sounds alarm and the red LED starts
Fig. 4: Component layout for the PCB flashing. In this case, you can reset the
circuit by a momentary depression of
switch S2. It is to be noted that no dis-
keep the cost low. The output from pin 3 MMV and lock driver. When a valid play unit is used, to keep the code secret.
of timer also drives LED2, which flashes code is entered, pin 6 of IC9 becomes high But if you still prefer to have one, the
at the output frequency of the astable and triggers monostable multivibrator same could be included.
oscillator. CD4528 (IC10) via transistor T3. On trig- ❏

Readers’ comments: Praveen Shanker, Haridwar Now assume data stored is B5 (Hex), i.e.
Q1. The construction project is very inter- A1. EFY: Though programming of 1110 0101 at the above mentioned ad-
esting and useful. However, how memory EPROM is well explained by the author, dresses. Let the system code be E (Hex),
dump is to be programmed in EPROM here is an example of coding. Let us say i.e. 1010. For getting this system code
IC6 is not given. Though different people address of the EPROM where a specific close DIP switches B, C, D, and leave A
would like to program different codes, at code is stored is 41A (Hex). It is equiv- open (in S3).Thus access code=41A B5E
least one example should have been given atent to 0100 0001 1010, which is used as (Hex) or MSB.......................LSB 0100
to illustrate this. address All through AO of the EPROM. 0001 1010 1011 0101 1110 (Binary).


Telephone Line-Interfaced
Generic Switching system
ajay subramanian and nayantara bhatnagar

Q uite a few projects using DTMF-

to-BCD decoder ASIC MT 8870/
KT 3170 have appeared in EFY
during the past few years. The project
the telephone line and also generates
control signals for hanging up (HUP) and
a universal reset pulse, which is used by
the authentication circuit for its opera-
• Detects an incoming call. Counts
up to a programmable number of rings
and then simulates handset off-cradle
presented here also uses the same ASIC, tion. Its design may be altered to achieve condition.
but it is used here as part of a circuit in connectivity to another network, which is • Once off-hook, it must decode DTMF
which a fairly advanced switching logic capable of providing certain control and signals on the telephone line within a
with adequate foolproofing and authenti- data signal sequences. fixed time and generate appropriate BCD
cation is implemented. The major features The authentication unit stores four data and StD pulse for indicating a valid
of this circuit are: presettable digits of code data and data condition. The positive edge of this
• Programmable password protection compares the same against the 4-digit StD pulse is used for subsequent opera-
over a public network DTMF code sent via the telephone lines tions.
• Foolproof mechanisms for events before the time-out occurs. If the 4-digit • Generates a universal Reset signal
such as time-out delays, incorrect pass- code is found valid, the authentication that includes a time-out and a power-on-
word, and power-on initialisation unit issues an authorisation signal to reset. This Reset signal is an active low
• Expandable design the main device selection and switching pulse of programmable duration.
The primary objective of this circuit is unit. However if an incorrect password • Generates a hang-up (HUP) signal
to make a fairly low-cost device for control- is entered, the device terminates the on expiry of the time-out and uses this
ling up to a hundred household switches call by returning to the off-hook condi- signal internally to take the device off-
remotely over any public/private telephone tion. line.
network. The fifth DTMF digit determines the When a call arrives, a 75-80V AC ring
address of the group to be selected, while signal is available on the lines. This ring
the sixth digit determines the device signal is coupled to optocoupler Opto-1
Description number that is to be selected within that (MCT2E) via DC blocking capacitor C1
The block diagram of the system is shown group. The selected device can be switched and current-limiting resistor R1. LED1
in Fig. 1. It consists of the following three on or switched off by a momentary depres- serves as a ring indicator and as an anti-
units: sion of the telephone keypad switches parallel diode to the in-built LED of the
1. The interface and control unit marked * (code1011 binary) and # (code optocoupler for working with AC ring
2. The authentication unit 1100 binary), respectively. Thus you can signal. The output of optocoupler triggers
3. The main device selection and select any one of the hundred devices, timer IC1, which is configured as a mon-
switching circuit divided into ten groups, to be switched on/ ostable retriggerable flip-flop to provide a
The interface and control unit provides off, as desired—one at a time. pulse output to be used as a clock for dec-
control signals and BCD data to the other The interface and control unit ade counter IC2 (CD4017) with decoded
two units. It handles interfacing with (Fig. 2). This unit performs the following outputs.

Fig. 1: Block diagram of telephone line-interfaced generic switching system


Fig. 2: Circuit diagram of the interface and control unit

The pulse-width of monostable should the call has not been answered yet (local a pre-programmed number of rings).
be slightly greater than 0.6 second to telephone handset still on cradle), the MT8870 (IC4) generates an StD pulse
ensure that the pulse does not terminate counter (IC2) is frozen and ‘D’ flip-flop whenever fresh data is latched onto its
during the 0.2-second pause between a (IC3A) is set. This activates relay RL1 outputs. This signal is used as a ‘data
pair of ring signals of 0.4-second duration. that places a 220-ohm load across the valid’ gate wherever appropriate. Also,
Thus the monostable produces one pulse lines to simulate handset off-cradle con- when a key is pressed, an ESt (Early
for each ring (in fact, a pair), which clocks dition and also enables MT8870 (IC4) steering) pulse is generated at its pin 16,
CD4017 counter. by applying a ‘low’ at its inhibit (active which lasts till the key is pressed. This
IC2 will freeze after counting a high) pin 5. This causes the ring signal, ESt pulse is used for clocking IC12B in
pre-programmed number of rings. This in turn, to be taken off the telephone the authentication and control unit and
number is determined by its output pin lines (by telephone exchange) and es- retriggering monostable multivibrator
which is tied to its pin 13. In Fig. 2 pin tablish a connection (analogous to the 74123 (IC5), extending the duration of
9 (O8 output) is shorted to pin 13. Thus maturity of a call). The circuit is now Reset pulse. This ensures that the circuit
count of IC2 is frozen at the beginning of ready to receive signals from the remote- will operate as long as the user presses
the eighth ring. end telephone. keys within preset time intervals, or else
The first pulse from IC1 also triggers In case the call is answered from the a time-out is decreed and the device is
the first stage of monostable multivibra- local telephone before the preset count of reset.
tor 74123 (IC5), which causes the Reset IC2 is reached, the ring ceases as the local The resetting process includes hang-
output to go high. As a result, CD4017 telephone is in off-hook condition. Since up (HUP) state, clearing the authenti-
(IC2) is enabled (which was otherwise there is no other way of re-triggering IC5, cation circuit status, and consequently
reset, when no ring signal was present). a time-out eventually occurs and the de- deactivating the main switching circuit,
Also, the authentication circuit is ena- vice reinitialises all units automatically. thus restoring the device to its initial
bled to receive BCD data and control sig- The device is also protected against acti- state. (The flip-flops, which control de-
nals, as and when generated by MT8870 vation by dialing from a parallel phone vices in the main device selection and
(IC4). instrument, since the ring signal is neces- switching unit, are allowed to retain
If the preset count is reached and sary to power up the ASIC MT8870 (after their states.)


The power-on-reset
circuit comprises resistor
R5 and capacitor C10. It
resets the device when
power to the circuit is
switched on. Since it is low
for some time after power
is switched on, it resets the
flip-flop (IC3A) and decade
counter CD4017 (IC2). Fig.
4 shows the relative tim-
ing waveforms pertaining
to this unit.
LED2 through LED5
are used to show the BCD
output for the DTMF code
received over the telephone
lines (decoded after relay
RL1 has energised).
The authentication
unit (Fig. 3). This circuit
receives BCD data and
StD control signal initially.
It outputs authorisation
(Auth) signal only when
the correct security code
has been entered. Control
pulses can reach the ‘main
switching unit’ only when
this signal is low (implying
that authentication of the
four digit code sent over the
telephone lines has been
Note that when a
wrong code is received,
IC9A clocks IC9B and a
low is latched by IC9B. As
Fig. 3: The authentication unit circuit diagram

a result the Q2 output of

IC9B goes high and satu-
rates transistor T2 in the
interface and control unit
and thereby shunts ca-
pacitor C10 to ground, thus
simulating a power-on-reset
condition. As a consequence
CLR signal (at output of
IC6A) is activated and
the line interface circuit is
initialised. Also, since the
monoshot IC5 is cleared,
Reset goes low (active) and
resets the authentication
If the time-out period expires, the to hang up, and inhibit IC4. It resets unit also. When the Au-
Reset pulse falls and the falling edge CD4017 (IC2) counter that counts the thentication unit is initialised, IC9A and
is used to trigger the second stage of number of rings. Also, as a Reset pulse 9B are set, which causes Q2 output of IC9
monostable multivibrator 74123 (IC5). goes low, it resets the authorisation to be reset, and thus transistor T2 is cut off
The complemented output 2Q of the circuit. again. Capacitor C10 now charges through
second stage of IC5 is a HUP (hang-up) The additional circuitry around the resistor R5 as it did when the circuit was
signal that clears relay driver flip-flop input of IC4 protects inbuilt op-amp input initially switched on.
74LS74 (IC3A), thus causing the device terminals within the chip. The Reset signal is initially low. As


pared and the result is latched, O4 out-
put of CD4017 (IC13) goes high, and as
a result, IC12A is clocked and latches
a ‘high’ at its Q output and the input to
inverter gate IC11E and ‘D2’ pin of flip-
flop IC12B goes high. Simultaneously, sig-
nal at the output of gate IC11E goes low.
Fig. 4: Signal waveforms of the interface and control unit This low signal at pin 12 of IC10D AND
gate disables the gate from accepting any
inputs of 4-bit comparator IC 74LS85 further StD pulses. So the authentication
(IC8). LED7 through LED10 indicate the unit is bypassed and subsequent BCD
preset data present at ‘P’ inputs of the data and StD pulses are transmitted to
comparator. The other 4-bit ‘Q’ inputs the main switching unit. The ESt pulse
for comparison are obtained from the associated with fifth BCD data, latches
BCD output decoded by IC4 upon press- the high signal at D2 input of IC12 to
ing a DTMF telephone key at the remote its Q2 output, while its Q2 output (Auth)
end. This comparator result is available goes low to activate the main device se-
at pin 6 of IC8 before the arrival of StD lection and switching unit at the start of
pulse. fifth code.
On the arrival of StD pulse, the output When the Reset signal goes high,

of the comparator is latched into ‘D’ flip- the output of inverter gate IC11F goes
flop (IC9A). Initially, both flip-flops (IC9A low. This enables IC13 (CD4017) again
and 9B) are set, as explained earlier. So by taking its MR pin low. At the same
the ‘CLK’ input of the second flip-flop time, the high ‘Preset’ signal at both the
Fig. 5: Method of programming code using (IC9B) is low. flip-flops (IC9A and IC9B) keeps them
DIP switches enabled.
If at any instant, a low is latched into
the first flip-flop IC9A (as a result of a When the code is not entered within
a result, this circuit is in its initialised failed match between the preset code and preset period, the Reset signal goes low
state, wherein IC13 (CD4017) is reset and the code entered via the remote telephone on expiry of the time-out period, the
ICs 9A and 9B (7474) are set (i.e. their Q set), the second flip-flop (IC9B) is clocked, circuit again goes back to its initial state
outputs are high and Q outputs are low). and it latches a low at its Q output. This by taking the preset pin on the flip-flops
Also, IC12A has its CLR pin low and it resets decade counter IC13 via inverter (IC9A and 9B) low and MR pin of CD4017
is in reset state with its Q pin low. As IC11F. The Q2 output of IC9B is nor- (IC13) high. Simultaneously, IC12A is
stated earlier, the Auth signal is initially mally low. But when a wrong password is cleared (its Q output goes low). As a
high. entered, this output goes high. As a result, result, Auth output goes high and the
The password consisting of four 4-bit transistor T2 (2N2222) of the interface main device selection and switching
words is applied at the input pins D0-0 and control unit, grounds the power-on- circuit is initialised and deactivated.
through D0-3 to D3-0 through D3-3 of reset capacitor C10, as stated earlier. Since the initialised state is maintained
74LS244 ICs 15 and 14 respectively as Thus the unauthorized call is terminated as long as the Reset signal is low, any
shown in Fig. 3. These words may be when the CLR signal (from the output of possibility of noise triggering is elimi-
programmed using thumbwheel switches IC6A) is activated. As a result, IC2 and nated.
or arrays of DIP switches with pull-down IC3A are reset (asynchronously) and the Main device selection and switch-
resistors as shown in Fig. 5. off cradle simulation circuit is deactivated. ing unit (Fig. 6). This circuit receives
As soon as the device establishes Also since the Reset signal is low, all other StD control signal after a successful au-
a call (i.e. relay RL1 energises after a units are initialised. This feature ensures thentication of the four-digit code by the
preprogrammed number of rings), the that a denial-of-service attack (wherein authentication unit. The AUTH and its
authentication unit (and not the main unauthorised agents engage the system inverse AUTH signals available on code
device selection and control unit) is ac- and thus prevent authorised users from authentication are used in this circuit for
tivated due to a high Reset pulse that is using it) is discouraged. enabling various chips such as IC23 and
generated as soon as the ring arrives and However, if correct codes are entered, IC24 (74LS195), IC25 (CD4017), IC27
also on every pressing of a key due to (ESt) each time when a StD pulse arrives, it through IC29 (74LS154), and StD gate
signal from IC4 via OR gate (IC7A), which clocks CD4017 (IC13) counter so that IC19C (7408).
triggers IC5. the next word is applied at the input of A combinational logic circuit, compris-
Now the caller is expected to enter the comparator. The result of the current ing three 3-input NOR gates inside 7427
the 4-digit password sequence from the comparison (high) is latched into the first (IC16) and two inverter gates (IC17B and
remote telephone set in DTMF mode. ‘D’ flip-flop (IC9A). 17C) of 7404, has been used to discrimi-
Initially, only the first word (nibble) of When the user presses all four keys nate between an address (numeric digit)
the array of tri-state buffer drivers (ICs in the correct sequence, the first flip-flop and a switching signal (‘*’ for ‘on’ and ‘#’
74LS244) is enabled by O0 output of IC13 always latches a high and the second for ‘off’). DTMF digit switches 1 through 9
(CD4017). As a result, the first 4-bit flip-flop is never clocked. At the end of and 0 (0 on the telephone keypad stands
programmed word is applied to the ‘P’ the sequence, when the last digit is com- for decimal 10 and the decoded output


from MT8870 is the equivalent binary remote telephone keypad is depressed im- Parts list
number 1010) generate a logic-1, R_EN mediately after AUTH signal goes active Semiconductors:
(register enable) signal, while keys low, R_EN signal goes to logic 1 (while IC1 - NE555 timer
marked ‘*’ and ‘#’ generate a logic-1, S_EN is logic 0). As a result, Std pulse IC2, IC13, IC25 - CD4017 decade counter
IC3, IC9, IC12,
S_EN (switching enable) signal. Thus passing through NAND gates IC18B and
IC21, IC22 - 7474 dual ‘D’ flip-flops
this combinational logic differentiates IC18C clocks IC25 with its leading edge. IC4 - MT8870 DTMF decoder
between register enable (R_EN) and IC25 is in reset condition before code au- IC5 - 74123 dual retriggerable
device switching enable (S_EN) signals. thentication due to ‘high’ AUTH signal, monostable multivibrator
The R_EN and S_EN outputs for various and its Q0 (pin 3) is ‘high’. On clocking, IC6 - 7411 triple 3-input AND
key depressions of the telephone keypad shifting of ‘high’ state from Q0 to Q1 IC7 - 7432 quad OR gates
are shown in Truth Table. (pin 2) enables AND gate IC19B, while IC8 - 74LS85 4-bit magnitude
The combinational logic circuit is fol- AND gate IC19 is still disabled. Thus the comparator
lowed by the RCLK and SCLK generation trailing edge of RCLK passes through IC10, IC19 - 7408 quad 2-input AND
circuitry comprising ICs 18, 19, 25, and IC19B to latch the MT8870-decoded data
IC11, IC17 - 7404 hex inverters
26, which allows the following functions corresponding to the mentioned numeric IC14, IC15 - 74LS244 octal buffers/line
to be performed: key depression, which is available at the drivers
• After AUTH signal at Q (pin 8 of input of group select register IC24, at its IC16 - 7427 triple 3-input gates
IC12B in Fig. 3) goes low (active), one output. This is the group select address. IC18 - 7400 quad 2-input NAND
can select a group and a device within the The group select address is applied IC20 - 74125 quad bus buffers
selected group by next two DTMF switch to the address lines of 4-line-to-16-line IC23, IC24 - 74195 4-bit parallel access
depressions on the telephone keypad, decoder IC29 (group selector). In the shift registers
while a third key depression of ‘*’ or ‘#’ normal telephone keypad, we use only IC26 - 7414 hex Schmitt invert-
results into switching ‘on’ or ‘off’ of the ten numeric keys (1 through 9 and 0)
IC27-IC29 - 74LS154 4-line to 16-line
desired device. and hence only ten outputs (Y1 through decoders
• Multiple devices can be switched on/ Y10) are available from IC29. The other Opto-1 - MCT2E opto-coupler
off one after the other, once authorisation six outputs Y0 and Y11 through Y15 are T1,T2 - 2N2222 npn transistor
signal AUTH becomes active (low) without not used. Thus we can select any of the D1,D2 - 1N4001 rectifier diode
D3, D4 - 1N4148 switching diode
a system reset. groups 1 through 10 via outputs marked ZD1, ZD2 - Zener diode 5.1V
• The system can be reset after or Y1 through Y10 of IC29. LED1-LED10 - Red LEDs
before switching ‘on’/‘off’ of the desired The output corresponding to the ad- Resistors (1/4W ± 5% carbon, unless specified
device with the help of remote telephone dress present at IC29’s input pins goes otherwise)
keypad. This feature can also be used for low (active). This low (active) output R1, R2, R5, R29 - 10-kilo-ohm
R3, R12, R30 - 100-kilo-ohm
avoiding switching on/off of a device if selects/enables another IC 74LS154 R4 - 220-ohm
the user perceives that he has selected a representing the corresponding group. R6-R9 - 51-kilo-ohm
R10 - 39-kilo-ohm
wrong device. (Please note that this is only a demo ver- R11 - 56-kilo-ohm
When R_EN signal is logic 1, IC25 sion circuit, wherein only two groups, out R13 - 330-kilo-ohm
(CD4017) is clocked at the leading edge of ten possible groups, can be accessed R14-R18 - 1.2-kilo-ohm
R19 - 20-kilo-ohm
of StD pulse, while one of the 74LS195 using IC27 and IC28. Pin 19 of IC27 and R20, R27, R28 - 1-mega-ohm
registers (IC23 or IC24, as enabled by IC28 can be connected to any of the group R21-R24,
one of the Q outputs of IC25) is latched select pins Y1 through Y10 of IC29, as R31-R34 - 470-ohm
R25,R26 - 1-kilo-ohm
at the trailing edge of the delayed Std desired. Once connected, the specific R31-R34 - 4.7-kilo-ohm
pulse (RCLK) as indicated by the direc- group numbers will get allocated to IC27 Capacitors:
tion of arrow on RCLK pulse in Fig. and IC28.) C1 - 0.47µF, 160V polyester
6. The resistor-capacitor combinations Device selection within the se- C2,C4-C6 - 0.01µF ceramic disc
C3, C9, C13 - 10µF, 16V electrolytic
R26-C11 and R25-C12 wired around lected group. The next DTMF number C7, C8, C14 - 0.1µF ceramic disc
Schmitt inverter gates A through D of key depression (i.e. the sixth after C10 - 100µF, 16V electrolytic
IC26 (7414) provide the necessary delay energisation of relay RL1 or the second C11, C12 - 47µF, 16V electrolytic
for reliable latching of the data in IC23 after the 4-digit authentication code)
Xtal - 3.57946MHz quartz crys-
and IC24. Resistors R27 and R28 across causes shifting of ‘high’ on pin 2 (Q1) of tal
capacitors C11 and C12, respectively, IC25 to pin 4 (Q2) in synchronism with RL1 - Relay 6V, 100-ohm, 1 C/O
serve as bleeders for discharging the the leading edge of StD pulse clocking - 5V, 1A regulated power
respective capacitors. IC25. As a result, AND gate IC19A - Berg stick/FRC connectors
When S_EN signal is logic 1, clocking is enabled while AND gate IC19B is - Ribbon cable etc.
of 7474 ‘D’ flip-flops via active 74LS125 disabled.
gates occurs corresponding to the leading The trailing edge of delayed StD
edge of Std (SCLK) pulses, while the trail- pulse (RCLK) causes the data corre- parallel. However, since only one group
ing edge resets IC25 via capacitor C14, to sponding to the mentioned numeric key IC is in selected condition (as explained
enable receiving of fresh group and device to be latched at the output of device earlier), the device control output cor-
selection data. select register IC23. This device select responding to the device select address
Group selection. When any of DTMF address is applied to address input pins present at the active group input is
numeric keys 1 through 9 and 0 on the of all group ICs (IC27 and IC28, here) in pulled low. This active low output is used



Fig. 6: Main device selection and switching unit
as the control signal for a corresponding
tri-state gate of 74LS125 (IC20).
We have shown only four gates, out
of possible 100, in this circuit. The output
pins of tri-state gates are connected to
the clock inputs of the corresponding ‘D’
flip-flops (only four out of possible 100 are
shown). The clock pins of IC21 and IC22
have been pulled high to avoid any noise
triggering when tri-state buffers are in
high-impedance state.
Switching the selected device.
Only one device corresponding to
the digit in the registers—IC24 for
group address and IC23 for device
address—is enabled to be affected by
the signal (‘*’ or ‘#’) as the seventh (or
the third after authentication) code.
On pressing DTMF keypad switch ‘*’
or ‘#’, the selected device is switched
on or switched off depending on the
key pressed. D0 bit of the decoded
switching signals ‘*’ and ‘#’ is applied
to data pins of all 7474 flip-flops in
parallel. Only the data corresponding
to the selected device gets clocked via
the corresponding tri-state gate of
The Q2 output of IC25 is still high
when SCLK is generated and, as a result,
AND gate IC18D is enabled to allow ap-
plication of SCLK to all 74LS125 gates
Fig. 7: Actual-size, single-sided PCB for the circuits in Figs 2 and 3 on depression of either ‘*’ or ‘#’ on the
remote keypad. Switching takes place at
the trailing edge of SCLK pulse, while the
trailing edge of SCLK pulse causes reset-
ting of IC25, thereby creating conditions
that were unavailable just before the pre-
vious group selection. Subsequently, you
can select any other (or the same) group
and any other (or the same) device. You
can switch on or off the selected device by
following the same procedure.
Switching on or off refers to Q output
of the corresponding ‘D’ flip-flop (7474)
going high or low, respectively. You may
suitably use the flip-flop outputs to ener-
gise a relay or fire a triac or control the
corresponding device/devices.
If you press any number key (1
through 9 or 0) instead of ‘*’ or ‘#’ key
on the DTMF keypad, IC25 will receive
a clock pulse via AND gates IC18B and
IC18C, and the ‘high’ state will shift from
Q2 to Q3 (pin 7 of IC25). Since Q3 output
is coupled to the base of transistor T2 via
diode D4, it will result into a system reset.
A system reset implies that you have to
redial the local telephone number from
remote telephone. When relay RL1 again
Fig. 8: Actual-size, single-sided PCB for the circuit in Fig. 6 energises, redial the four-digit authentica-


tion code, followed by group select, device
select, and switch on (*) or switch off (#)
codes, as explained earlier.
Thus, after dialing two digits iden-
tifying the group and the device within
that group, if we press a third numeric
digit instead of ‘*’ or ‘#’ on the remote
telephone keypad, a system reset can be
achieved remotely. This feature can also
be utilised to bypass switching operation
if the user realises that he has selected a
wrong group/device.
Operation summary. The entire op-
eration can be summarised as below:
• Using the remote telephone keypad,
dial the local number of the telephone to
which the circuit is connected.
• If the local handset is lifted before
the programmed number of rings, a nor-
mal conversation can be ensured.

• If the handset is not lifted before
the programmed number of rings, wait
for simulated off-hook status of the local
telephone handset (indicating energisation
of relay RL1).
• Now dial the four digits of the
preset authentication code in a proper
sequence from the remote keypad within
the preset duration. A system reset
will occur in case the 4-digit code is not
dialed within the preset duration or
the code used is wrong, which causes
Fig. 9: Component layout for PCB-1 de-energisation of the relay and creates
conditions similar to on-hook state of
the local telephone handset. So you will
have to repeat all steps from the begin-
• If the 4-digit authentication code
matches the preset code, you can dial the
next two digits identifying the group and
the device within that group selected for
the purpose of switching on or off (or even
as a dummy operation for the purpose of
forcing a system reset).
• Dialing ‘*’ from the remote tel-
ephone keypad will result into switching
on of the selected device, while dialing
‘#’ will result into switching off of the
selected device. (Dialing any number, 1
through 9 or 0, causes a system reset.
Relay RL1 will be de-energised, and you
will have to restart from the initial step.)
You can proceed with the same procedure
to switch on/off the next selected device.
The procedure can be repeated for any
number of devices (one-at-a-time) with-
out affecting the status of non-selected
Testing. It is recommended that the
circuit be built in stages, verifying proper
Fig. 10: Component layout for PCB-2 operation at each stage. The main switch-


Truth Table for Device Selection and Switching at various points. The ring pulse generator and decade
Keypad Decoded data input Switch and register The authentication counter, CD4017, comes next. Finally,
Key from MT8870 enable outputs circuit is also self- interface connections between the various
No. D3 D2 D1 D0 S_EN R_EN contained and may circuits should be made after verifying
1 0 0 0 1 0 1 be assembled and the proper functioning of each circuit in
2 0 0 1 0 0 1 debugged independ- isolation.
3 0 0 1 1 0 1 ently. A single-sided PCB for the circuits
4 0 1 0 0 0 1
5 0 1 0 1 0 1 H o we v e r, ca re in Figs 2 and 3, is shown in Fig. 7, while
6 0 1 1 0 0 1 must be taken while another single-sided PCB for the circuit in
7 0 1 1 1 0 1 assembling the inter- Fig. 6 is shown in Fig. 8. The component
8 1 0 0 0 0 1 face and control unit. layouts for both the PCBs are given in
9 1 0 0 1 0 1
The ASIC must be Figs 9 and 10, respectively. Suitable con-
0(10) 1 0 1 0 0 1
* (11) 1 0 1 1 1 0 assembled first and nectors are provided to enable isolation
#(12) 1 1 0 0 1 0 tested for proper op- and joining of individual circuits using
eration and output jumpers/connectors, for easy testing and
ing circuit may be assembled conven- levels, followed by rigging and testing of fault analysis during assembly.
tionally, with logic operation tested monostable multivibrators in the 74123. ❏

Readers’ comments: EFY: 1. The interface and control section. number in the selected group are not
We have the following queries regarding Only one of the ten outputs of IC2 decade connected in parallel and only their
the project: counter needs to be connected to its pin address (input) pins are connected in
1. The interface and control section. In 13 [and pin 3 of IC3(A)] to freeze IC2 parallel, which are controlled by device-
IC2 (CD4017), where would be pins 3, 2, and create a condition simulating lifting select outputs from IC23. However, the
4, 7, 10, 1, 5, 9, 6, 11, and 12 connected? of handset after waiting for a few rings. selection of a group is dependent on IC29,
Also show the connections of available pin This is well explained in the article. The which, in turn, is controlled by group-
11 (RST) in IC5 (74123). maximum number of rings can be nine, to select IC24.
2. The authentication section. Show avoid false ring condition on the line. Output connections Y1 and Y10 from
the connections of pins 1, 5, 6, 9, 10, 11, RST and Reset outputs are not going IC27 pertain to device Nos. 1 and 10,
and 12 in IC13 (CD4017). to part II and have been used via IC6(A) respectively, of group 1, while connec-
3. The selection and switching unit. in part I itself. The flags just indicate the tions Y1 and Y10 from IC28 pertain to
(a) Pins 2 to 11 (Y1 to Y10) of IC27 label of these signals. device Nos. 1 and 10, respectively, of
(74LS154) and IC28 (74LS154) are 2. The authentication section. The group 10. Each device is controlled via
connected in parallel. Pins 2 and 11 of mentioned output pins of IC13, excluding 74LS125 gate in conjunction with one
IC27 are connected to pins 1 and 4 of pin 10, are not used/connected. Pin 10 is flip-flop from 7474 IC. In the circuit only
IC20 (74LS125), respectively, and pins Q3 and is used as clock for IC12(A). two groups (1 and 10), with two devices
2 and 11 of IC28 are connected to pins 3. The selection and switching unit. (1 and 10) from each group, have been
10 and 13 of IC20 (74LS125), respec- (a) The first four digits dialled from the shown instead of all the ten groups and
tively. Pins 2 to 11 (Y1 to Y10) of IC29 remote telephone keypad are used for a hundred (ten per group) devices. You
(74LS154) are connected to the normal tel- matching the authentication code. After should be able to correlate as to which
ephone keypad. Are all these connections authentication, the fifth digit selects the 74LS125 (IC20) gate and 7474 section
correct? group. If the fifth digit is ‘1’ then IC27 (IC21 and IC22 pair) select which device
(b) After entering IC16 (7427), four (group 1) will be selected, and if the fifth out of which group.
data lines D0 through D3 go to IC23 digit is ‘0’ (code 1010 or ten decimal) then (b) Data lines D0 through D3 are com-
(74LS195) and thereafter IC24 (74LS195) IC28 (group 10) will be selected. The sixth ing from IC4 and go into pins labelled D0
and then go out as shown in the PCB dialled digit selects the device inside the through D3 of IC8, IC16, IC17, IC23, and
layout. Please explain which data goes in selected group. The seventh dialled digit IC24, respectively. They are thus related
IC16 and where does it output in IC24. Are (‘*’ for ‘on’ or ‘#’ for ‘off’) of the selected to PCB1.
these connections related to PCB1? device or ‘0 through 9’ for circuit reset can The Auth signal is correctly con-
Ranjit Singh be used as desired. nected to IC27, IC28, and IC29 in Fig. 7
Amravati The output pins reflecting the device and there is no ambiguity.


Melody Generator
Vyjesh m.v.

number of melody generator cir- key to another is very short, the required half notes. So each octave has twelve
cuits based on chips like UM3481, notes can be played properly and hence notes. On a piano keyboard, black keys
UM3482, UM34815A, UM66, etc the tune can be heard. The notes can also in between white keys produce the av-
have appeared in EFY. All these UMC have breaks in between. This feature can erage frequency of adjacent keys. For
chips contain preprogrammed masked be explained by considering five notes example, ‘Sa’ has a frequency of 595

ROM and are not field-programmable as written in the following two ways: Hz and ‘Re’ has a frequency of 668 Hz.
such. 1. Sa Re Ga Ma Pa When a black key in between them is
Here is the detailed design of a typical 2. Sa---Re Ga---Ma Pa pressed, a frequency of 631.5 Hz is pro-
melody generator circuit using different In the first case the notes are continu- duced. These black keys are called half-
types of memories, including EPROM, ous. In the second case there are breaks note keys.”
RAM, and ROM (hard-wired). (no sound), indicated by ‘—’ for a stipulat- Here we have selected a total of 28
As soon as the power is switched on ed amount of time, in between Sa and Re notes, including all notes from the middle
to UMXX series melody generators, a as well as Ga and Ma. Each of the circuits octave, eleven notes from upper octave,
tune is heard, which stops after a while. explained in this project incorporates the and a few from the lower octave. All the
When a switch on the melody generator is break (no sound) feature. 28 notes with their respective frequencies
pressed, the second tune is heard. If the You should make sure that you have are given in Table I.
chip is capable of producing twelve tunes, access to a musician before attempting
each successive depression of the switch any of the circuits. In addition, you would Software and testing
results in a new tune being played. After need a computer and a frequency meter
the twelfth tune has been played, the next or a digital multimeter. The computer is of notes
depression of the switch causes the first required to test the tunes, i.e. to make Before moving to the software program,
tune to repeat, and so on. The circuit pre- sure that the given notes match the tune let us see how the notes for a tune can
sented here can be programmed exactly of a given song. be obtained. Give your musician the
the same way. A brief on music from the software song for which you need notes. Write those
article ‘Generation of Indian Classical notes in terms of Sa Re Ga etc, making
Music on a Microprocessor’ by Prof. V.V. sure that all the notes of the tune lie with-
Basics of music Athani, published in April ’94 issue of in the range of the 28 notes given in Table
Generally, an electronic organ or piano EFY, is as follows: I. No sound in between the notes, includ-
is played with both hands. Now imagine “Taking into account only one elec- ing its duration, as also the duration of
playing a 32-key organ with a single tronic organ (piano), the number of notes each particular note, should be taken into
finger. In that case, only one key can in music are only seven—Sa Re Ga Ma account. For example, if in a tune the time
be pressed at a time and hence only one Pa Dha Ni. But these basic notes are period of a note SA is 500 ms and that of
note can be heard. Considering that the divided into three octaves (refer Fig. 4), Re 1500 ms, the two notes can be written
time taken by the finger to move from one where each octave also has notes called as Sa Re Re Re. Similarly, no sound in
between can be written
as Sa Re-Re-Sa.
The notes so ob-
tained have to be con-
verted into data char-
acters. This can be done
directly by using Table I;
for example, Sa-Re Re
Ga---Ma can be written
as C-E E G---H.
Execute the program
Fig. 1: Block diagram of EPROM-/RAM-based melody generator


(refer Appendix ‘A’ for
the source code of the
program) and enter the
delay value (say, 300).
Now enter the first line
of the tune and press
‘Enter’ key. The tune can
be heard. This tune can
be repeated by pressing
‘R’. If this tune needs to
be changed, or a new tune
is to be entered, press any
key. In this way all the
lines in a tune are tested
line by line. After testing
all the lines, enter all
the lines of the tune once
again and recheck the
tunes until you are satis-
fied. Press ‘E’ to quit the
program. Now convert the
tunes (data characters) to
hexadecimal values using
Table I. These hexadeci-
mal values are to be en-
tered into EPROM/RAM
at consecutive locations to
get the tune.

based melody
Since most parts of the
circuits for EPROM- and
RAM-based melody gen-
erators are similar, the
main circuits for both
versions have been inte-
grated in Fig. 2. Relevant
changes have been de-
Fig. 2: Main circuit of EPROM-/RAM-based melody generator

scribed appropriately.
The common block
diagram for EPROM-
and RAM-based melody
generators is shown in
Fig. 1. A low-frequency
oscillator followed by a
binary counter is used to
generate the addresses for
In the case of EPROM,
the preprogrammed data
output is directly coupled
to two 1-of-16 decoders
(one for upper nibble and
the other for lower nibble
of data).
However, in RAM
based-circuit, a keyboard


state (all outputs zero). two CD4514 (IC4 and IC5) will have
The binary outputs of binary 0000 at its address input. The Q0
IC2 serve as the ad- output of these ICs is not used for gen-
dress for memory loca- erating any note. The hex data 00 (i.e.
tions in the EPROM, 0000 0000) is, in fact, used for no sound.
where the data for the Similarly, hex values 01 (0000 0001) and
notes is stored. For the 10 (0001 0000) are used for ‘Reset’ and
EPROM version, the ‘Stop-clock’ functions.
pins of connector K2(F) The remaining 14 outputs from each
are to be kept shorted to of the two CD4514 (IC4 and IC5) are
the corresponding pins used together for generating one of the
of connector K3(M). Suf- 28 notes corresponding to the hex data
fixes ‘F’ and ‘M’ within stored and the output from a specific
parentheses indicate memory location. The Q2 to Q15 outputs
female and male connec- of IC4 and IC5 are connected via diodes
tors, respectively. D101 (and preset VR101) through diode
Fig. 3: Tone oscillator Data bits of the D128 (and preset VR 128), respectively,
lower nibble (D0 to the tone oscillator circuit built around
through D3) are con- timer NE555 (IC101), as shown in Fig. 3.
nected from EPROM (EFY lab note. The numbering of diodes

to the address pins of and other components of this circuit has
1-of-16 decoder IC4 been done for convenience.)
(CD4514) and those of IC101 is wired with presets to form
the higher nibble (D4 an oscillator. At any time, only one of
Fig. 4: Piano keyboard through D7) to the ad- diodes D101 to D128, depending on the
dress pins of another 1-of-16 decoder IC5 current note selected via EPROM’s ad-
is deployed at the time of writing the (CD4514). dressed location, will be forward biased
data at specified locations (addresses) The ‘Hex value’ column in Table I and its corresponding preset will form
into the RAM. Thereafter the keyboard indicates that either the lower nibble part of the oscillator circuit. Each preset
is detached and data output pins are or the upper nibble, or both nibbles, of is adjusted to a value (refer Table I) to
connected to two 1-of-16 decoders, as in
stored hex data in memory will always obtain the frequency corresponding to
EPROM-based circuit. Only 28 outputs
(out of 32 outputs) of the two decoders, be zero. It means that at least one of the the selected note.
with each representing a unique note, are No sound (00 hex). Breaks are
used in conjunction with individual pre-
sets to control the oscillator’s frequency
and thus the resulting sound from the

EPROM-based circuit
In Fig. 2, NE555 timer (IC1) is wired in
astable mode, which provides clock pulses
for the 12-stage binary counter CD4040
(IC2). In the EPROM ver-
sion, jumper J1 is used to
permanently short pin 3
of IC1 and pin 10 of IC2,
while there is no need
to operate push-to-on
switches S2 and S3 and
you can leave them open
(i.e. in off state).
An 8-bit, 4k EPROM
2732 is used for IC3.
Since its pin 21 is address
A11, switch S6 is to be
kept in position ‘a’ to con-
nect it to O11 output of
Fig. 5: Flow IC2. When clock pulses
chart of door- are fed to IC2, it starts
bell counting up from its reset Fig. 6: Actual-size single-sided PCB-1 layout for circuit of Fig. 2


necessary Parts List
in between (Common to EPROM, RAM and ROM)
the notes Semiconductors:
to make a IC101 - NE555 timer
tune sound IC201 - 7805 +5V regulator
perfect. The D101-D128 - 1N4007 rectifier diode
D201-D204 - 1N4001 rectifier diode
break period,
Resistors (¼-watt ±5% carbon, unless other-
termed as wise stated)
‘no sound,’ is R101 - 5-kilo-ohm
obtained by VR101-VR128 - Refer Table I
outputting VR129 - 10-kilo-ohm preset
hex value Capacitors:
00 from the C101 - 0.1µF ceramic disc
EPROM. C102 - 0.22µF ceramic disc
C103 - 10µF, 12V electrolytic
During this
C201 - 100µF, 25V electrolytic
input to the C202 - 1000µF, 16V electrolytic
two 1-of-16 Miscellaneous:
decoder ICs LS101 - 8-ohm, 4W loudspeaker
(IC4 and X201 - 230V AC primary to 0-6V,
IC5), the Q0 500mA sec. transformer
outputs of (for EPROM and ROM)
both decoder Semiconductors:
ICs go high. IC1 - NE555 timer
Since IC2 - CD4040 counter
IC3 - (1) 2732 EPROM
Q0 outputs - (2) 6116 RAM
are not con- IC4, IC5 - CD4514 1-of-16 decoder
nected to the IC6 - CD4011 quad NAND
tone oscilla- gate
T1-T8 - BC547 npn transistor
tor circuit
D1-D64 - 1N4007 rectifier diode
(or anywhere LED1-LED20 - Red LED
else), no note Resistors (¼-watt ±5% carbon, unless other-
or sound is wise stated)
Fig. 7: Actual-size single-sided PCB-2 layout for circuit of Figs 3 and 11
R1, R7 - 10-kilo-ohm
R2 - 22-kilo-ohm
R3, R8 - 470-ohm
R4 - 1-mega-ohm
R5, R9-R16 - 1-kilo-ohm
R6 - 2.2-kilo-ohm
R17, R18 - 100-ohm
R19 - 330-ohm
VR1 - 100-kilo-ohm preset
C1 - 22µF, 12V electrolytic
C2 - 0.1µF ceramic disc
C3 - 0.01µF ceramic disc
C4 - 0.22µF ceramic disc
S1 - Push-to-off switch
S2-S5 - Push-to-on switch
S6 - SPDT switch
J1, J2 - Jumper
K1-K5 - Connectors

produced for hex value 00, and there is

only time elapse. ‘No sound’ code is used
as break between the notes.
Reset (01 hex). When the data output
of EPROM corresponds to 01 (hex), Q1
output of IC4 goes high. Since Q1 output
of IC4 is connected to MR (master reset)
pin 11 of counter IC2 via resistor-capacitor
network R2-C3, IC2 is reset when data 01
Fig. 8: Component layout for PCB-1 hex appears at the output of EPROM.
Stop-clock signal (10 hex). When
breaks/‘no open, there is no
sound’ peri- effect.
ods) for the Similarly, when
first tune binary data corre-
are stored, sponding to note SA ❚

a stop-clock (05 hex) is output

data (10 hex) by the EPROM, Q5
is stored at of IC4 and Q0 of
the end of IC5 go high. The Q5
tune-1 that output of IC4 brings
stops after into circuit the cor-
the first responding preset
tune. Now tuned to the frequen-
on pressing cy of SA (1190 Hz).

push-to-off The Q0 output of IC5

switch S1 has no effect, as Q0
momentar- is open. In this way
ily, the clock both the ICs (IC4 Fig. 12: Flow chart
advances and IC5) function in of car-reverse horn
to start the accordance with data

second tune at their inputs to pro-
(tune-2). duce the corresponding notes.
Thus each Power supply. The circuit shown in
tune is made Fig. 11 is used to obtain the regulated 5V
to end with DC using IC 7805.
10 hex code The actual-size, single-sided PCB
for stop sig- layouts for the circuits of Figs 2 and 3
nal. When (common for EPROM and RAM versions
all tunes of of the melody generator) are shown in
the doorbell Figs 6 (PCB-1) and 7 (PCB-2), respec-
are exhaust- tively. The component layouts for PCBs of
ed, the last Figs 6 and 7 are shown in Figs 8 and 9, re-
Fig. 9: Component layout for PCB-2
stop-clock data is followed by a reset data spectively. The power supply circuit (Fig.
(01 hex), so that one goes to the start of 11) has also been integrated in PCB-2.
the data output of EPROM corresponds tune-1 (on reset), and the cycle repeats. This circuit can be used as a door-
to 10 (hex), Q1 output of IC5 goes high, For instance, the hexadecimal value bell, or even as a car-reverse horn. The
which after inversion of ‘SA’ is 70H (refer Table I) or binary flow chart for car-reverse horn is shown
by NAND gate N1 is ap- 0111 0000, which means that binary in Fig. 12. The necessary connections
plied to pin 4 of IC1 via data at the input of IC4 and IC5 is 0000 are shown in Fig. 13. When the circuit
normally-closed contacts and 0111, respectively. As a result, only is used as a car-reverse horn, data flows
of push-to-off switch S1. Q7 output of IC5 goes high. This output from the next address location to where
As a result, IC1 stops os- brings the associated preset resistor it stopped earlier.
cillating and producing tuned to the frequency of SA (595 Hz)
clock pulses. The active into the oscillator circuit. Simultaneously,
‘high’ Q1 output of IC5 data 0000 at the input pins of IC4 causes Preset adjustment
is therefore referred to its Q0 pin to go high. But since Q0 is left Connections to join the two PCBs should
as stop-clock signal in be made only after the adjustment of pre-
this circuit. Pushing sets on PCB-2 using any of the following
switch S1 at this stage three procedures:
removes logic ‘high’ in- Using frequency
put from NAND gate N1 meter. Assemble all the
and the clock oscillator components of PCB-2.
starts oscillating. Connect a probe to the
The flow chart for Vcc using a crocodile
a doorbell given in Fig. clip at the other end.
5 shows the order in Switch on the 5V power
which the data is en- supply and connect the
tered/read. First, the output from the tone
data pertaining to the Fig. 10: Flow oscillator on the PCB
first tune is stored. Once chart for re- to the frequency me-
all the notes (including adjustment Fig. 11: Power supply ter. Now connect the
probe to the anode
choose the main notes in the mid- adjusting the
dle octave. Connect the probe to the variable resis-
respective diode of SA and tell the tors to lower
musician to adjust the variable resistor values in the
to the frequency of SA. Now connect table may be
the probe to the respective diode of RE very tedious.
and adjust the variable resistor to the Any method
frequency of RE, and so on. After ad- may be used to
Fig. 13: Wiring connections for car-reverse horn justing main notes, adjust half notes. adjust all the
(In Table I, music notes shown in small variable resis-
of diode D101 and adjust preset resis- letters are half notes.) This method will tors. But after
tor VR101 for 446 Hz (refer Table I). be successful only if the musician is well playing a tune,
In this way all the variable resistors trained in music. it may be felt
are adjusted one by one by connecting Using digital multimeter. First, that the tune
+5V from the probe to the corresponding assemble only preset resistors VR101 doesn’t sound
diodes. through VR128. Now adjust the variable proper, even if
With the help of a musician. You resistors to their respective values (shown it sounded right
can seek the help of a musician if you in column 6 of Table I) using a digital with computer.
don’t have access to a frequency meter or multimeter. Use the variable resistors The reason can Fig. 14: LED indicator
a digital multimeter. Connect the output with maximum value as given in column be that the re- circuit
from the tone oscillator to the speaker 7 of Table I. You can also use the values sistors were not
and switch on the power supply. First, shown in the circuit diagram of Fig. 3, but properly tuned or it may be due to
minute imperfections in output voltages
from IC4 and IC5. These imperfections
Table I
can be overcome by readjusting the resis-
Music Frequency Data Hex Variable Variable Maximum
note of music character value resistor resistor value of tors by the method given below.
note (preset) in-circuit variable The imperfections can only be ad-
(Hz) number value (ohm) resistor justed when data from the EPROM is
Lower octave heard. But, the notes of a tune will not
Pa❚ 446 1 20 vr101 8274 10k
be in an increasing frequency sequence.
dha❚ 472 2 30 vr102 7740 10k The sequence should be PA , dha , ----- to
❚ ❚

dha❚ 500 3 40 vr103 7230 10k ----- DHA , ni . To do this, include at least
❚ ❚

ni❚ 530 a 50 vr104 6744 10k two sets of sequence data from Table I
NI❚ 561 b 60 vr105 6288 10k with 2-3 bytes of gap in between succes-
Middle octave sive sequences, after all the tunes, as
sa 595 c 70 vr106 5850 10k shown in the flowchart of Fig. 10. This
re 630 d 80 vr107 5445 10k method of readjustment is used only to
re 668 e 90 vr108 5055 10k prevent disconnection of PCB of Fig. 7
ga 707 f a0 vr109 4698 5k from PCB of Fig. 6 and tuning the resis-
ga 749 g b0 vr110 4356 5k tors again and again.
ma 794 h c0 vr111 4029 5k Remove jumpers J1 and J2. Switch
ma 841 i d0 vr112 3726 5k
on the power supply. Press switch S4
pa 891 j e0 vr113 3438 5k
dha 944 k f0 vr114 3165 5k
to provide clock pulses for IC2. Say, if
dha 1000 l 02 vr115 2910 5k the EPROM contains 10 tunes, after the
ni 1062 m 03 vr116 2655 5k tenth tune release S4. Now keep pressing
ni 1120 n 04 vr117 2445 5k S2 momentarily until the first note of the
Upper octave sequence (PA ) sounds. Now connect the

sa❚ 1190 o 05 vr118 2220 5k frequency meter at the speaker terminals

re❚ 1260 p 06 vr119 2016 5k (disconnect speaker if necessary) and ad-
re❚ 1335 q 07 vr120 1824 2k just VR101 if the value of the frequency
ga❚ 1414 r 08 vr121 1644 2k meter reading is not consistent with the
ga❚ 1498 s 09 vr122 1473 2k value in the Table I. Press S2 again to
ma❚ 1588 t 0a vr123 1308 2k adjust VR102, and so on. After the read-
ma❚ 1682 u 0b vr124 1158 2k justment process insert jumpers J1 and
pa❚ 1782 v 0c vr125 1014 2k
J2 and press S3 to reset IC2.
dha❚ 1888 w 0d vr126 876 1k
dha❚ 2002 x 0e vr127 747 1k
ni❚ 2122 y 0f vr128 624 1k
RAM-based circuit
no sound — — 00 — — —
The only difference between the EPROM-
Reset  01
and RAM-based circuits is the use of
stop-clock  10
RAM chip in place of EPROM and a key-


Fig. 15: Keyboard and probe for programming RAM

board for programming the RAM in of 6116 is WE (write enable – active low). The inputs of N1 are shorted and connected
RAM-based circuits. Besides, an LED Switch S6 is to be kept in position ‘b’ while to the ground via resistor R7. So the output
panel is used for displaying the selected working with RAM. of N1 becomes high, which keeps IC1 oscil-
RAM address. At the time of writing (programming) lating.
Switch S2 is used to manually provide data into the RAM, there is no connection After a stop-clock (active ‘high’) sig-
clock pulses to IC2. Similarly, switch S3 between connectors K2(F) and K3(M). nal appears at the input of NAND gate
is used to manually reset IC2 before and Also, jumper J1 is removed. To program N1, its output goes low. When switch S1
after programming. Both switches (S2 and the RAM, K4(M) is to be mated with is pressed, the output of N1 goes high
S3) are integrated into Fig. 2. The connec- K2(F). After programming is over, K2(F) and IC1 starts oscillating again. Gates
tor K1 in between IC2 and IC3 is used is connected to K3(M). N2 and N3 are used to provide read and
to connect to K5(M) connecter along IC6 (CD4011) contains four NAND write logic for RAM. In read condition,
with the associated LEDs as shown in gates, of which NAND gate N1 is used for the output of N3 is at logic 0 because its
Fig. 14. EPROM 2732 (IC3) is replaced stop-clock signals. It functions in the same inputs are at logic 1. Pressing of switch
with an 8-bit, 2k SRAM (6116). Pin 21 manner as in an EPROM-based circuit. S5 provides ‘write’ condition, since the

Appendix ‘A’
#include <stdio.h> } case’F’:sound(707); break;
#include <dos.h> } break; case’S’:sound(1498);
#include <stdlib.h> void play(char *str,int d) case’G’:sound(749); break;
#include <conio.h> { break; case’T’:sound(1588);
#include <ctype.h> int i=0; case’H’:sound(794); break;
void play(char *str,int d); while(str[i]!=’\0') break; case’U’:sound(1682);
void main() { case’I’:sound(841); break;
{ switch(str[i]) break; case’V’:sound(1782);
int f,d=200; { case’J’:sound(891); break;
char ch1[180],ch2; case’1':sound(446); break; case’W’:sound(1888);
clrscr(); break; case’K’:sound(944); break;
printf(“\n Enter delay value:”); case’2':sound(472); break; case’X’:sound(2002);
scanf(“%d”,&d); break; case’L’:sound(1000); break;
while(1) case’3':sound(500); break; case’Y’:sound(2122);
{ break; case’M’:sound(1062); break;
printf(“\n enter tune :”); case’A’:sound(530); break; case’-’:nosound();
scanf(“%s”,&ch1); break; case’N’:sound(1120); break;
play(ch1,d); case’B’:sound(561); break; }
a:ch2=getch(); break; case’O’:sound(1190); delay(d);
if (tolower(ch2)==’r’) case’C’:sound(595); break; i++;
{ play(ch1,d); break; case’P’:sound(1260); }
goto a; case’D’:sound(630); break; nosound();
} break; case’Q’:sound(1335); }
if (tolower(ch2)==’e’) case’E’:sound(668); break;
exit(0); break; case’R’:sound(1414);


tor K4(M) should consistent with the hex value shown on
be connected to the tab/circle. After checking, disconnect
K2(F) during pro- resistor R18.
gramming. The Connector K3 should be soldered to
circles shown with the PCB by using a ribbon cable of ad-
the corresponding equate length, so that it could be easily
hex values are connected to K2(F) after programming.
Fig. 16: Block diagram of ROM-based melody generator simple metallic The outputs from IC4 and IC5 go to
contacts (or tabs) preset-array part of the tone oscillator.
output of gate N3 is at logic 1 and that of that avoid the use of a large number of Wiring is done similar to that in an
gate N2 at logic 0. switches. To enter the hex data, the probe EPROM version.
LED connector. A separate male connec- is touched to the corresponding metallic Programming. Connect LED con-
tor K5(M) is fabricated with LEDs as shown in contact tab. nector K5(M) to K1(F) and keyboard
Fig. 14. This connector should be connected to The keyboard can be easily wired us- connector K4(M) to K2(F). Press switch
K1(F). The LEDs indicate addresses of memory ing a general-purpose board. To test the S3 momentarily to reset IC2. No LED
locations of RAM. Glowing of LED1 through keyboard after wiring, connect point ‘A’ to glows on the LED connector, indicating
LED11 together means that last RAM loca- the ground via a 100-ohm resistor (R18) the initial address as zero. Now touch the
tion is being addressed. (We are using a 2kB as shown in Fig. 15. Now touch each and tab marked ‘00’ with the probe. Press S5
RAM.) every tab one by one using the metallic momentarily and lift the probe. Glowing
Keyboard. The circuit diagram of key- probe and verify that the data shown by of no LED on the keyboard indicates that
board is shown in Fig. 15. Male connec- the LEDs (LED13 through LED20) is ‘00’ is entered in the initial memory loca-

Fig. 17: Schematic diagram of ROM-based melody generator


tion. (It is good to enter ‘00’ in the first
memory location.)
Now get the hex dump values of the
tunes. Press switch S2 to go to the next
memory location, indicated by LED1 (cor-
responding to address line A0), on the LED
connector strip. Touch the appropriate tab
with the probe to enter the corresponding
hexadecimal value at memory location 1.
Press switch S5 and lift the probe. The
data entered into memory location 1 is
shown by keyboard LEDs in binary form.
Hex data values (refer Table I) are
such that any of the four LEDs cor-
responding to either D0 through D3
bits or D4 through D7 bits would glow
to show the data entered. So it is easy
to identify whether the data entered is
correct or not. If necessary, make a table
of binary data along with corresponding

hex values.
After entering all the tunes, discon-
nect keyboard from K2(F) and connect
K3(M) to K2(F). Now connect external
jumper J1 as shown in the circuit dia-
Switch S4 across jumper J1 termi-
nals is not necessary but it may prove
useful if any readjustment of variable
resistors is needed (as in the case of
EPROM), or for checking each and every
tune one by one.
The programming steps are summa-
rised as below:
1. Press switch S3.
2. Touch tab 00 with the probe.
3. Press and release switch S5.
4. Lift the probe. Fig. 18: Actual-size, single-sided PCB layout for the circuit
5. Press S2 to go to the next memory
the circuit of a ROM-based programmable
6. Repeat from step 2 onwards for the
PARTS LIST melody generator is totally a new one.
next hex value programming.
The ROM, as stated earlier, is home-built
Semiconductors: 7. After last data is entered, press
using discrete components, which can be
IC1 - NE555 timer S3.
used for storage of 100 bits (100 notes).
IC2, IC3 - CD4017 decade counter 8. Keep S4 pressed to check all the
IC4, IC5 - CD4069 hex inverters The block diagram of the ROM-based
tunes that have been entered.
T1-T10 - BC547 npn transistor melody generator is shown in Fig. 16.
9. Connect jumper J1 if all tunes are
T11-T110 - BC558 pnp transistor Note that the last block comprising
variable resistor array is identical to that
Resistors (¼-watt ±5% carbon, unless other- The data table (Table I), writing of
wise stated) used in EPROM/RAM version (refer Fig. 3
musical notes, conversion of notes to hex
R1 - 10-kilo-ohm in Part I of the article). The power-supply
values, preset-array alignment, and flow
R2 - 100-kilo-ohm circuit shown in Fig. 11 can also be used
charts for door-bell and car-reverse tune
R3 - 680-ohm for ROM-based melody generator. Thus
are also applicable for the RAM version.
R4 - 1-mega-ohm PCB and component layouts shown in Figs
R5 - 1-kilo-ohm Now we shall study a programmable
7 and 9 can be used without any modifica-
R6 - 68-ohm melody generator using home-brewed
tion in this system.
There were only a few differences be-
C1 - 2.2µF, 12V electrolytic
C2, C3 - 0.01µ ceramic disc
tween the circuits of RAM- and EPROM- ROM-based circuit
based programmable melody generators
Miscellaneous: The circuit diagram of ROM-based mel-
and as such we could integrate the com-
S1 - Push-to-off switch ody generator is shown in Fig. 17. Here
mon portion of the two circuits into a
timer NE 555 (IC1) is wired as an astable
single schematic/PCB design. However,


clock’ and ‘Reset’
functions) from the
100-transistor ar-
ray. Transistors T1
through T10 are
used to switch on
Vcc to transistors
T11 through T110.
Fig. 20: Flow chart
for repetitive playing
of 99 notes (single
Initially, when power
is switched ‘on’ to the
circuit, IC2 and IC3 are
in Reset condition. So
only pin 3 (Q0) of IC2
and IC3 will be at ‘high’
logic. These high outputs
are applied to the base
of transistor T1 and the
input of inverter N1. As
a result, transistor T1
Fig. 21: is switched on and +5V
Flow chart Vcc is available at the
for repetitive
playing of a emitter of transistor T1.
number of
tunes This potential is extended
to the emitters of T11, T21, T31,…, T91
and T101. Simultaneously, the output of
inverter N1 will be at logic ‘0’, which is
applied to the bases of pnp transistors
T11 through T20.
Since transistor T11 is the only transistor that
has both Vcc at its emitter and nearly 0V at its base
Fig. 19: Component layout for the PCB simultaneously, it gets forward biased and its collec-
tor is pulled toward its emitter voltage (Vcc). Thus
multivibrator. The output pulses from through T110 for 28 notes as well as for initially, on powering the circuit, transistor T11 is
IC1 are used as clock for decade counter the ‘Stop-clock’ and ‘Reset’ functions. activated and its collector goes high.
CD4017 (IC2). The ten sequential outputs However, both ‘Stop-clock’ and ‘Reset’ The initial state lasts for a few
from IC2 are applied to npn BC547 tran- functions are optional, depending upon seconds and as soon as IC1 generates a clock pulse
sistors T1 through T10. the number of tunes and number of notes.
(which is applied to the clock pin of IC2), Q1 (pin
Similarly, the outputs from another For ‘Stop-clock’ function, the output from a
2) of IC2 goes ‘high’ and pin 3 goes ‘low’, while no
similar decade counter IC3 are connected transistor is applied to inverter N11 whose
to pnp BC558 transistors T11 through output is connected to reset pin 4 of IC1. change takes place in IC3. Now transistor T2 is
T110 via inverter gates N1 through N10 Similarly, for ‘Reset’ function, the output switched on.
of IC3 and IC4 (CD4069). Each of these from a transistor is applied to pins 15 of Since the base of transistor T12 is at
100 transistors (T11 through T110) IC3 and IC4. low potential, the positive voltage will be
provides one bit for one note. The out- The collectors of transistors pro- available at its collector. Thus transistors
puts are taken from the collectors of grammed for each specific note (including T11 through T20 will be switched on and
transistors and connected to the ‘variable- ‘Stop-clock’ and ‘Reset’ functions) are to be off sequentially with the arrival of each new
resistor array and tone oscillator’ circuit. strapped (shorted) together for connection clock pulse.
(Note: Collectors of transistors represent- to the corresponding input points of the At the beginning of tenth pulse, the
ing identical notes are shorted together.) ‘variable-resistor array and tone oscil-
carry-output pulse from pin 12 of IC2 is
As in the previous circuits of RAM- lator’ circuit, while the ‘Stop-clock’ and
applied to clock pin 14 of IC3. Now pin 3
and EPROM-based melody generators, ‘Reset’ lines are to be connected as shown
here also ‘Stop-clock’ and ‘Reset’ signals in Fig. 17. (Q0) of IC2 and pin 2 (Q1) of IC3 go ‘high’.
are made available. You may program We can have a maximum of 30 output Therefore, transistors T21 through T30 are
any/all of the hundred transistors T11 lines (28 for the notes and two for ‘Stop- now switched ‘on’ and ‘off’ in a sequential


fashion. In this way one out of 100 transis- the wiring, label diodes D101 through delay, we use Reset. For this, the output
tors is switched ‘on’ sequentially to produce D128 of ‘variable resistor array oscil- from the next transistor after the last note
lator’ PCB (Fig. 7 and 9) in terms of is connected to point marked ‘RESET’ on
an output to drive the ‘resistor-array tone their respective notes i.e. label D101❚
oscillator’ according to the tune data. Thus as PA❚, D102 as dha❚, ..., D128 as NI , PCB. When the pulse appears at pin 15 of
when power is switched on, the tune is and so on. IC2 and IC3, the circuit resets.
produced. Now starting from transistor T11 Stop-clock. Stop-clock is used when
connect the transistor outputs (refer more than one tune is to be programmed.
PCB of Fig. 18) to diodes D101 through
D128 according to the tune note that If the clock is to be stopped, say, after the
PCB layout and assembly each transistor (T11 through T110) 1st tune, we use stop-clock. For this, the
The PCB design should ideally be double- sequentially represents. Extreme care output from the next transistor after the
sided for such types of transistor arrays. should be taken while wiring, because if last note of the tune is connected to the
However to keep the cost down, we have any error occurs, it will be very tedious stop-clock point in the PCB. Please refer to
included only a single-sided PCB layout, to find out. flow charts of Fig. 20 and 21, which show
which is shown in Fig. 18 with its compo- Let us consider the example of five occurance of automatic reset and use of
nent layout in Fig. 19. notes ‘SA RE—GA SA PA’. In this case stop-clock and reset functions.
First, assemble transistors T11 programming can be done as under: Housing. There is a lot of wiring in
through T110. Solder the transistors, Connect between the ROM circuit of Fig. 17 and
leaving a length from the PCB. Now take T11SAD6 the resistor-array oscillator. So the en-
a thin, bare wire and connect the emitter T12RED8 closure must have enough space for all
leads of transistors T11, T21... T91 and T13NO connection, leave open (be- the wires to fit properly without getting

T101 together from the components side. cause the data is no sound) detached from the PCB while installing.
Similarly connect emitters of other rows of T14GAD10 [EFY note. To overcome this problem to
transistors. Suitable pads for the purpose T15SAD6 (Again to D6) some extent, a 28-pin (16+12) SIP con-
have been provided on the PCB. T16PAD13 nector (with pins projecting towards both
Similarly the collectrors of transis- Reset. With this circuit a maximum sides of the PCB) may be used. This will
tors T1 through T10 may be connected of 100 notes are feasible. However if all obviate the need to run loose wires between
together using bare wire from the ROM PCB and variable-resistor array
components side. Now assemble all the notes are not utilised, Reset is necessary
remaining components. after the last utilised note. Because if the oscillator PCB. Wires originating from the
total number of notes is less than 98, for collectors of the transistor array may be
connected to one side of the connector on
Programming example, 86, then after 86th note there are
ROM PCB itself and a ribbon cable with
In this circuit, programming means hard 14 more bits to reach for an automatic reset
wiring. You should have a lot of patience to occur. (The circuit automatically resets 28-pin SIP connector on both sides can be
to do all the hard wiring. No hexadecimal itself after 100th bit.) So there is a big delay used between the two PCBs.]
values are required. Before starting with for the tune to get repeated. To skip the ❏


Auto Control for
3-phase Motors
d. dinesh

nduction motors widely used in work- • Automatic starting/tripping. Parts List
shops, irrigation pump sets, etc re- • Programmable timer with battery Semiconductors:
quire a 3-phase supply. Normally, backup to count the motor’s run time. IC1-IC3 - MCT2E optocoupler
these motors are connected to 3-phase sup- • Latching circuit to prevent the IC4 - CD4027 J-K flip-flop
ply from electricity boards using thermal motor from frequently starting and trip- IC5, IC6 - NE555 timer
IC7, IC9, IC10 - CD4017 decade counter
bimetal relays and relay contactors. Ther- ping. IC8 - CD4060 14-stage counter
mal relays protect the motor from over- • Easy operation with just two switch- and oscillator
load. Relay coils having hold-on contacts es for time set and reset. IC11 - 7805 5V regulator
with push-to-‘on’ and push-to-‘off’ switches The phase-sequence detector protects D1-D30 - 1N4007 rectifier diode
ZD1, ZD2 - 3.3V zener diode
are used for activating and deactivating the motor before starting, while the LED1-LED4 - Red LED
the relay contacts. current-sensing circuit protects it during Resistors (1/4W ± 5% carbon, unless specified
Single-phasing, line dropout, and running. This double protection makes the otherwise)
reverse phasing are harmful for 3-phase motor operation really safe. R1-R3 - 100-kilo-ohm, 0.5 watt
motors. In the event of line dropout and R4-R6, R16,
single-phasing, the motor draws a heavy R18-R23, R25,
current from the existing phases, and dur- Circuit description R30, R31, R38,
R47, R49 - 4.7-kilo-ohm
ing phase reversal the motor simply rotates The schematic circuit diagram of induction R7, R24 - 27-kilo-ohm
in reverse direction. Further, an operator motor controller is shown in Fig. 1. R8-R10 R17,
(attendant) for switching ‘on’/‘off’ the motor 3-Phase sequence checker. The volt- R26, R29, R32,
R37, R39, R43,
is always not possible, especially when the age from each of the three phases is con- R44, R46, R48,
motor has to be operated round the clock. nected to optocouplers IC1 through IC3 via R51-R53 - 10-kilo-ohm
Also the protection provided by the thermal rectifier diodes D1 through D3. The out- R11, R28, R34 - 1-kilo-ohm
relay in the starter assembly is inadequate, puts from the optocouplers are half-wave R12 - 220-kilo-ohm
R13, R41 - 1-mega-ohm
since it involves some delay in activation. rectified DC pulses with a phase difference R14, R35, R36,
Thus some damage to the windings of the of 120° (during the conduction period of R45, R50 - 470-ohm
motor can take place, especially if overload diodes), which are applied to a positive- R15 - 470-ohm, 0.5 watt
conditions occur frequently. edge-triggered, dual JK flip-flop IC4. R27 - 180-kilo-ohm
R33 - 2.2-kilo-ohm
The circuit presented here incorpo- When the red phase rises, the output R40 - 22-kilo-ohm
rates the following features to overcome of IC1 goes from ‘low’ to ‘high’, resulting R42 - 82-kilo-ohm
all the above-mentioned problems: in clearing of both flip-flops FF1 and FF2 VR1 - 4.7-kilo-ohm preset
• Electronic sensing of phase sequence through 0.1µF capacitor C1. While the red VR2 - 47-kilo-ohm preset
with under-frequency cut-out. phase is still ‘high’, the yellow phase rises, Capacitors:
• Current sensing for single-phasing resulting in the output of IC2 going ‘high’ C1-C3, C6,
C13 - 0.1 ceramic disk
prevention. and providing a clock pulse to FF1. As a C4, C7, C11, C17 - 100µF, 63V electrolytic
• Current sensing for overload result, Q output of FF1 goes ‘low’ (since C5, C14-C16,
cut-out. J1 input of FF1 is already ‘high’ when the C18, C19 - 10µF, 25V electrolytic
clock pulse arrives at CLK1 pin). Now, C8, C10, C12 - 47µF, 25V electrolytic
C9 - 1000µF, 63V electrolytic
Table I when the blue phase rises, the output of
Phase sequence Signal OK LED RL1 IC3 goes ‘high’, while the output of IC2 is
X1-X3 - Current-sensing trans-
Correct On On already ‘high’, resulting in the output Q of formers
Incorrect Off Off FF2 going ‘low’. X4 - 0-230V AC primary to
The above process 12V-0-12V, 500mA sec-
Table II ondary transformer
repeats once dur-
Motor Core Core Primary Secondary S1 - ‘On’/‘off’ switch
ing each 50Hz cy- S2 - SPDT switch
HP size area Max SWG Turns S W G
Turns cle. If Q outputs S3 - 7-way rotary switch
(Max) amps of both FF1 and - 1.5V X4 battery
FF2 are ‘low’, the - Starter assembly
6 17 0.25 10 14 14 38 170 - Cabinet
20 23 0.56 22 11 9 38 110 phase sequence is



Fig. 1: Schematic diagram of auto control for 3-phase motor

correct and both diodes D28 and D29 are As a result, IC5 is triggered and hence retriggerable monoshot. Its time period
in blocking mode. The base of transistor ‘sequence OK’ LED connected to pin 3 of is set at 25 milliseconds (approx.). If the
T1 is pulled towards ground via resistor IC5 via resistor R14, glows. monoshot is not retriggered within 25
R11 and transistor T1 starts conducting. IC5 is a popular 555 timer wired as a milliseconds, the ‘sequence OK’ signal goes


put of CD4017 (IC7) goes ‘high’, relay
RL2 energises through transistor T9
(SL100). N/O contacts of RL2 are con-
nected across ‘on’ switch of starter
assembly, as stated earlier and the
starter’s relay coil energises. The next
clock pulse to IC7 deactivates relay
RL2, but starter remains in ‘on’ state
due to hold-on contact (the fourth con-
tact of contactor in starter assembly).
When Q9 (pin 11) of IC7 goes ‘high’, its
CK pin 14 is muted due to conduction of
transistor T8 (which pulls it to ground)
to prevent further counting. The Q9
output of IC7 is also used in the motor
‘on’/‘off’ timer circuit, explained later.
The supply to starter is connected
through primaries of three small cur-
rent transformers used for sensing the
load in each phase. These transformers
can be constructed using common EI
laminations generally used for power
transformers. Core number 23 or 17
may be employed as per details given
in Table II.
The secondaries of these transform-
ers are connected to the current-sensing
circuit wired around transistors T3
through T5. If any phase goes ‘off’, it
cuts off the corresponding transistor
and thereby provides forward bias to
transistor T6.
The outputs of transistors T3
through T5 are wired-OR via diodes
D15, D16, and D17. Any excessive in-
crease in load current (overload) results
in forward biasing of transistor T7. The
excess current limit can be set with the
help of preset VR1.
The conduction of transistors T6
and/or T7 causes their common col-
lector junctions to be pulled low. This
Fig. 2: Actual-size, single-sided PCB layout for the circuit ‘low’ signal is coupled to transistor T2 via
diode D30. As a result, relay RL1 deacti-
‘low’. The circuit operates smoothly at contacts are wired in parallel with the vates to trip the starter and thus stop the
frequencies up to 42 Hz. ‘on’ switch of starter assembly. induction motor. The above conditions are
If any of the phase fails, the phase Auto-starter and current-sensing summarised in Table III.
sequence is disturbed, resulting in the circuit. As soon as the phase sequence is
output of IC5 going ‘low’ and ‘sequence OK’ detected to be correct (as
LED goes ‘off’. The LED status in relation explained in the previous Table III
to the phase sequence is shown in Table I. section), the output of IC5 Truth Table of Current Sensing Circuit
The output of IC5 is also used for driving goes ‘high’. This output, Phase R Phase Y Phase B T6 T7 RL1
relay RL1 via transistor T2 (SL100). via resistor R15, is used to (ON) (ON) (ON) R.B. R.B. Energised
Normally-open (N/O) contacts of relay reset IC7 and enable IC6, (ON) (ON) (OFF) F.B. R.B. De-energised
(ON) (OFF) (OFF) F.B. R.B. De-energised
RL1 are wired in series with ‘off’ switch of besides acting as a clock (OFF) (OFF) (ON) F.B. R.B. De-energised
starter assembly as shown in the Fig. 1. for decade counter IC10. (OFF) (ON) (OFF) F.B. R.B. De-energised
Thus when phase sequence is correct and IC6 is an NE555 timer (ON) (OFF) (ON) F.B. R.B. De-energised
the frequency is above 42 Hz, the relay wired in astable mode to (OFF) (ON) (ON) F.B. R.B. De-energised
In case of overloading
is in energised state and it is feasible to provide clock pulses to dec-
in any phase — X F.B. De-energised
switch on the starter by momentary ade counter CD4017 (IC7).
Eventually, when Q8 out- Note: R.B. = Reverse bias; F.B. = Forward bias; X = Don’t care
energisation of relay RL2, whose N/O


tor T11 via resistor R38 (as referred
in ‘auto-starter and current-sensing
circuit’). Thus the collector of transistor
T11 goes ‘low’ to activate the oscillator
circuit of CD4060 (IC8), while the motor
is running. Prior to that, the oscillator
circuit of CD4060 was inactive because
its pin 11 was at logic ‘1’, being connect-
ed to +ve rails via resistors R39, R40 and
diode D22. The frequency of oscillation
is set by R-C network comprising 47µF
capacitor C8 and resistor R42 in series
with preset VR2.
A timing of either 30 minutes or 60
minutes can be selected with the help
of switch S2 for the output of ‘on’/‘off’
timer to go from ‘low’ to ‘high’ state.
The output from the pole of switch S2
is connected to the clock input of decade
counter IC9. The outputs of IC9 go ‘high’

sequentially after 30/60-minute time
intervals, depending on the selection
made via switch S2. Thus multiples
of 30-/60-minute basic timing can be
selected with the help of 7-way rotary
switch S3. (The 7-way rotary switch may
be substituted with decade thumb-wheel
switch, if desired.)
The output available at the pole of
rotary switch S3 goes ‘high’ after the
selected duration to forward bias tran-
sistor T12, which, in turn, causes de-en-
ergisation of relay RL1. Also, when the
selected run time is over, the oscillator
of IC8 (CD4060) gets inhibited because
oscillator pin 11 of IC8 goes ‘high’ due to
the feedback from the pole of switch S3
via resistor R43 and diode D23. LED1
glows to indicate that run time is over.
To restart the motor, IC8 and IC9 can
be manually reset by closing and then
opening switch S1. The timer may be
Fig. 3: Component layout for the PCB
bypassed by keeping switch S1 closed.
The timer section requires very low
Motor on/off counter and latch. start, pin 7 (Q3) goes ‘high’ and transis- power in standby mode and is powered
Frequent start and stop operations subject tor T13 gets forward biased. As a result, by four 1.5V cells as standby supply. A
the motor to lot of fatigue due to heavy CK pin 14 of IC10 is pulled low to stop battery-low indicator is provided to warn
currents, which may damage the motor. In any further clock to the decade counter, the user about the low battery condition.
this circuit, automatic restarting of motor which thus gets latched and LED3 glows Power supply. The normal DC power
is limited to three attempts for each power to indicate the latched state of the counter. supply for the circuit is provided by a
‘on’, by using another decade counter Simultaneously, this ‘low’ signal causes small step-down transformer X4 connected
CD4017 (IC10). It monitors each ‘on-off’ transistor T2 to cut off and de-energise between R (red) phase and neutral, fol-
cycle of the motor by advancing the count relay RL1. Thus the motor cannot restart lowed by rectifier and filter capacitor. The
of decade counter by one on every start. automatically and only complete resump- unregulated voltage is used for operation
The clock for IC10 is obtained from tion of power can reset the latch. of the relays, while the 5V regulated sup-
the output of IC5 via resistor R15. This Motor on-off timer. A timer is provided to ply is used for the remaining circuit.
point i.e. the junction of resistor R15 and run the motor for a predetermined time. It counts
diode D30 is also used as supply point for run time of the motor and thereafter switches off
transistors T6, T7, T12 and T13 as also the motor automatically. The signal from pin 11 Construction and testing
for reset pin of timer IC6. On the third (Q9) of IC7 is connected to the base of transis- An actual-size, single-sided PCB for the


Now adjust preset VR2
such that 30-minute-du-
ration pulse train (time
period 60 minutes) is
available at pin 14 of IC8
(CD4060). Flip switch S2
to 30-minute position. Se-
lect the required run time
using rotary switch S3. On
completion of the selected
run time, ‘time over’ LED
should glow and the timer
should stop. Relay RL1 Fig. 5: Creation of virtual neutral from 3-phaes 3-wires
should de-energise.
After resetting the timer with the all the wires to the starter point and the
help of switch S1, relay RL1 should load. Keep wiper contact of VR1 towards
energise once again. Then after a delay ground side and switch on the 3-phase
of 15 seconds, relay RL2 should again supply. Relay RL1 activates. After 5 sec-
energise for one second. Now short onds, relay RL2 also activates and the mo-
Fig. 4: Layout of cabinet for mounting trans-
former relays and the PCB momentarily pin 14 of counter CD4017 tor starts running. Now slide the wiper of
(IC10) to ground thrice. On the third VR1 and mark the position just before the
motor controller circuit of Fig. 1 is shown touching, Q3 of IC10 will go ‘high’ and motor trips. (Remember that such trips
in Fig. 2, with its component layout shown LED3 will glow, followed by de-energi- will be counted by latching counter.)
in Fig. 3. It is recommended to use bases sation of relay RL1. The mains should be Caution. Some parts of this circuit
for ICs. interrupted completely to reset IC10. contain live 3-phase voltages. So avoid
Before connecting the circuit to starter Current transformers X1 through X3, touching the circuit with bare hands.
assembly, a bench test is required for step-down transformer X4, and relays Note. In the case of non-availability
the adjustment of timer. Apply 3-phase RL1 and RL2 may be mounted side by of neutral terminal, assembler a circuit as
power to the circuit. Observe pin 3 of IC5 side in a compact box as shown in Fig. shown in Fig. 5. Connect ‘N’ marked wire
(NE555), which should go ‘high’, provided 4. The PCB may be mounted over the (shown in Fig. 1) to two more transformers
the sequence is correct. Else, interchange transformers and relays using insulated X5 and X6 that are identical to X4. The
any two phase wires. As ‘sequence OK’ spacers. Current transformers are to secondaries of these transformers (X5 and
signal at pin 3 of IC5 goes ‘high’, relay RL1 be connected before the starter relay X6) are kept open, while the secondary of
energises and IC6 (IC555) is activated. As contacts. X4 is connected to the power-supply circuit
a result, relay RL2 energises after a delay Over-current adjustment can be done as shown in Fig. 1.
of 15 seconds for one second. only after connecting the load. Connect ❏

Readers’ comments: 1. Can I use star-delta starter (which 1. In Table II, the turns ratio of cur-
Q1. Please clarify the following: can reduce the starting current and can rent transformers (CTs) is 12 for both 6HP
1. Which starter in the circuit starts be used for motors up to 25 HP) instead of and 20HP motors. If the ratio is same, the
the motor? the contactor-type starter? If no, suggest a secondary currents of CTs work out to be
2. Is the starter manually operated or proper alternative as the starting current of different, i.e. 1.8A for 20HP motor and
automatically? up to 40A may affect other components. 0.8A for 6HP motor.
Ramaswamy Iyer 2. Are there any current-reducing 2. In the phase-sequence indicator cir-
Through e-mail circuits used to withstand the high start- cuit, you have connected an RC (1-mega-
Q2. When a 3-phase motor is started, it ing current while using the contactor-type ohm-0.1µF) combination to the reset pin of
takes six times the rated current. So the assembly? IC5 (NE555). In such a case, can the reset
current sense circuit will trip the motor 3. At the time of testing, what HP mo- pin get a high input.
during start-up. If we adjust the overload tor was used with contactor-type starter Abhijeet S. Bhosle
current setting for starting current, this assembly? Through e-mail
will not trip the motor during normal 4. The 12V, 300-ohm, 1 C/O relays (RL1 EFY: A1. 1. The starter comprises a con-
running current through the load. Is and RL2) specified in the circuit are not tactor, an ‘on’ button (N/O), and an ‘off’
there any initial bypass provided for over- available. The available relays are 12V, button (N/C). The contactor in Fig. 1 of
current trip? 200-ohm, 1 C/O and 12V, 150-ohm, 1 C/O. the project uses three main N/O contacts
G. Saravana Mohan So which relay should I use? What is the connected to R, Y, and B phases and one
Salem purpose of using VR2? auxiliary N/O contact, which is wired
Q3. The contactor-type starter can be used Ramaswamy Iyer as shown in Fig. 1. The contactor coil is
for starting motors up to 10 HP. As I need Through e-mail rated at 415V AC. At EFY, we used ML1
to control motors of 15 to 20 HP, please Q4. I am facing the following problems in contactor from L&T to make the starter
clarify the following: the project: assembly.


2. You can manually operate the start- for a higher HP motor, provided that A4. 1. Current transformers are used
er by making use of ‘on’ and ‘off’ buttons. star-to-delta changeover is done either to sense the load current and these draw
In automatic operation you don’t have on releasing the ‘on’ pushbutton or after a only a few milliamperes of current to bias
to use these switches. The circuit does it fixed time delay. A typical semi-automatic the transistor. The bigger core is used to
through relays RL1 and RL2 as per the star-delta starter made by L&T is Mark1 cater to the wire gauge. One can use a
logic explained in the project. type bearing catalogue No. SS96255. smaller core to hold this gauge by main-
The author, D. Dinesh replies: 2. A delay is provided by capacitor C12 taining the specified turn ratio.
A2. A heavy current flows through to bypass the power-on surge current. 2. Pulses at pin 14 of IC08 (CD4060)
the motor winding for a moment only. A 3. The circuit was tested using 6HP should be adjusted to obtain 30-minute
certain delay is provided by capacitors borewell pump. delay by varying preset VR2. Pin 4 of IC5
C12 (47 µF) and C17 (100 µF) to account 4. If the specified relay is not avail- is wired through RC network for delayed
for this. able, one can also use 12V, 200-ohm, reset at power-on (starting).
A3. 1. One can use star-delta starter 1C/O relay.



Remote Control

elephone remote control implies operation is as
control of devices at a remote follows:
location via a circuit interfaced to 1. From the
the remote telephone line/device by dialing local telephone,
specific DTMF (dual-tone multi-frequency) dial the number
digits from a local telephone. The tel- of the remote tel-
ephone remote control system described ephone to which
here has the following features: the circuit is con-
1. It can control multiple channels/ nected. In a short
relays. while you will
2. It provides you feedback when the hear a musical
current is in energized state and also note indicating
sends an acknowledgement indicating that the circuit
action w.r.t. the switching ‘on’ of each connected to the
requested relay and switching ‘off’ of all remote telephone
relays (together). is active.
3. It can selectively switch ‘on’ any 2. Now if you
one or more relays one after the other and want to switch
switch ‘off’ all relays simultaneously. ‘on’ a particular
relay/device, press
‘*’ button on the
Operation telephone keypad
Instead of straightway proceeding with followed by any
the circuit description, we shall start one of digits 1
with the operation as this would help us to 7 correspond-
in understanding the circuit better. The ing to the device/
relay number
Table I(a) that you desire to
switch ‘on’. The
Input Output
A2 A1 A0 Qn = addressed switching ‘on’ of
L L L Q0 the relay will be
L L H Q1 acknowledged/in-
L H L Q2 dicated by a mu-
L H H Q3 sical note. Now
H L L Q4
you may keep the
H L H Q5
H H L Q6 handset on the
H H H Q7 cradle.
3. If you want
Table I(B) to switch ‘off’ the
WR R Q Q relays, press ‘*’
addressed un-addressed and them press
L L = DATA hold key for digit 8.
L H = DATA L A musical note
H L hold hold
is heard, which
indicated that all
H = High; L = Low
the relays have Fig. 1: Schematic diagram of the telephone remote control


IC1 - CA3140E op-amp
IC2 - NE556 dual timer
IC3 - CD4011 quad NAND gate
IC4 - CD406014-stage counter/
IC5 - NE555 timer
IC6 - UM66 melody generator
IC7 - CM8870 DTMF-decoder
IC8 - CD4099 8-bit addressable
IC9 - 7805 regulator +5V
T1 - BC548 npn transistor
T2-T9 - BC547 npn transistor (only
T2 and T6 shown)
LED1, LED2 - Green LED
LED3 - Yellow LED
LED4 - Red LED
D1, D2 - 1N4148 switching diode
D3-D10 - 1N4007 rectifier diode (only
D3 and D4 shown)
Resistors (all 1/4-watt, ±5% carbon, unless

otherwise stated)
R1, R16. R17 - 150-kilo-ohm
Fig. 2: Actualsize, single-sided PCB for the circuit R2. R21 - 10-kilo-ohm
R3 - 33-kilo-ohm
R4 - 680-kilo-ohm
R5 - 560-ohm
R6, R10 - 22-kilo-ohm
R7 - 1-mega-ohm
R8, R15 - 390-ohm
R9, R12 - 15-kilo-ohm
R11 - 270-ohm
R13, R14 - 3.3k-kilo-ohm
R18 - 330-kilo-ohm
R19, R22-R27- 4.7-kilo-ohm (R22-R27 not
shown in the figure)
R20 - 220-ohm
VR1 - 10-kilo-ohm preset
VR2 - 1-mega-ohm preset
VR3 - 220-kilo-ohm preset
VR4 - 470-kilo-ohm preset
C1 - 0.22uF ceramic disk
C2 - 220uF. 10V electrolytic
C3 - 100uF, 10V electrolytic
C4, C5, C8 - 0.0luF ceramic disk
C6, C11, C12 - 0.1uF ceramic disk
C7 - 10uF, 10V electrolytic
C9 - 0.02uF ceramic disk
CIO - 0.47uF, 100V polyester
Fig. 3: Component layout for the PCB X PAL - 3.58MHz crystal
RL-RL7 - 9V, 150-ohm 1C/0 relay (only
been switched ‘off’. Keep the handset on When a ring is detected by IC1, its RL4 shown)
cradle. output triggers one of the timers in IC 556.
The output of the timer after inversion by is still persisting) applied to pin 9 of the
one of the NAND gates of IC3 (CD4011), same NAND gate (after inversion by an-
The Circuit enabled IC4 (CD4060) by taking its reset other NAND gate) will pass through it to
At the remote telephone end, the ringing pin 12 ‘low’. (IC4 is an oscillator-cum-14- trigger the second monostable inside IC2
signal is detected by a high-input-imped- bit binary counter.) As a result, IC4 starts (NE556) as well as IC5 (NE555), which
ance op-amp CA3140E that is wired as a counting when the ring signal strikes the is again wired as a monostable. This ar-
comparator. Since the op-amp output is input of the circuit. rangement avoids the circuit of being
open-controller type, the output pin has After some time, decided by the set- triggered by any transients or false ring
been pulled Vcc via 10-kilo-ohm resistor ting of preset VR3, Q12 output of IC4 signals on the telephone line.
R21, IC2 (NE556) comprised two timers goes ‘high’. This output coupled to pin 8 The output of the second monostable
(NE555 type) that have been configured of a NAND gate inside IC3 will enable it. of IC2, available at its pin 9, drives tran-
as monostables. The detected ring signal (if the ring signal sistor T2 and shunts the telephone line


voltage drops to around 10 to 12 volts. decimal digits 0 through 7) are connected
This is equivalent to the lifting of the tel- to the address inputs, while the MSB line Alignment
ephone handset of the remote telephone. is connected to reset pin 2 of IC8 (CD4099, 1. Connect the circuit to the telephone
As mentioned earlier, both IC5 and the an 8-bit addressable latch). When a valid line.
second monostable of IC2 are triggered DTMF tone is detected at the input of IC7, 2. Adjust preset VR1 so the ringing
simultaneously. The output of monostable its pin 15 goes ‘high’ to enable IC8 after pulse causes LED1 to flicker. For better
IC5 starts melody generator IC6 (UM66) inversion by NAND gate of IC2. At the performance, set the voltage at pin 3 of
and the musical note obtained from it is same time, it triggers IC5 for informing IC1 at approximately 2 volts.
coupled to the telephone line. This informs the caller that his key-press is accepted. 3. The time required to activate ener-
the caller that the remote circuit is in Numbers 1 to 7 on the local keypad gise the circuit is adjusted by preset VR3
energized state. cause latching of the corresponding relays, with the help of LED2.
As the remote circuit is in energized while number 8 causes reset operation, 4. The time available for remote
condition, the next step for the operator which means that we can switch ‘on’ switching action can be set by preset VR2
at local telephone is to press the ‘*’ button, seven relays independently one by one with the help of LED4. Indirectly, the set-
which makes the local telephone to oper- and switch ‘off’ all relays simultaneously ting of preset VR2 determines the charge
ate in the long-dialing mode. The digits by pressing number 8. The output of IC8 that will have to be paid to the telecom
that are pressed after pressing the ‘*’ but- drives the relays via the relay driver department.
ton are converted to DTMF tones. transistor. Truth tables I(A) and I(B) of 5. The period of the musical note can
The tone is decoded by IC7 and its CD4099 indicate relay operation. be controlled by the adjustment of VR4
three LSBs (covering binary equivalent of with the help of LED3. ❏

Readers’ comments: Devjyoti Biswas be achieved with discrete ICs also, but
Q1. In the circuit, if anyone makes a Through e-mail the microcontroller method is better
call to the connected telephone line The author, Junomon Abraham, and flexible.
and presses the consecutive switches, replies: EFY: Please refer to ‘Microcontroller-Based
the unauthorised person can also A1. It is possible to incorporate the Access Control System’ and ‘Multichannel
switch the circuit on/off. Can the circuit facility as desired by you by using a mi- Access Control System’ projects published
be altered such that switching on/off crocontroller. The microcontroller will in October and November issues of EFY for
the circuit is possible only after enter- receive the signal from DTMF decoder implementation of the password authenti-
ing the authorisation code via telephone and it will verify whether the correct pass- cation schemes used in such a system.
keypad? word has been received. The same can


School Timer
U. B. Mujumdar

he basic requirements of a realtime PARTS LIST
programmable timer generally
used in schools and colleges for IC1 - 68HC705JIACP Microcontrol-
sounding the bell on time are: ler
• Precise time base for time keeping. IC2 - CD4532 8-bit priority En-

• Read/write memory for storing the coder
bell timings. IC3 - 74LS138 3-line to 8-line de-
• LCD or LED display for displaying IC4 - 74LS47 BCD-to-7-segment
real time as well as other data to make the decoder/driver
instrument user-friendly. T1-T3 - BC547/BC147 npn transistor
• Keys for data entry. T4-T7 - 2N2907 pnp transistor
Fig. 1: MC68HC705J1A pin assignment D1-D7 - 1N4007 diode
• Electromechanical relay to operate ZD1 - 5.6V, 0.5 watt zener
the bell. The time-keeping section. Ac- Resistors (1/4-watt, ±5% carbon, unless stated
We are describing here a sophisti- curate time-keeping depends on the otherwise)
cated, yet economical, school timer based accuracy of time base used for driving R1 - 210-ohm, 0.5 watt
on Motorola’s 20-pin MC68HC705J1A the microcontroller. In this project, the R2 - 27-ohm
microcontroller. microcontroller is driven by AT-cut R3, R12-R14,
R24-R-27 - 1-kilo-ohm
parallel resonant crystal oscillator that
R4-R8 - 100-kilo-ohm
is expected to provide a very stable clock.
Description A 3.2768MHz crystal provides a time
R23, R29 - 10-kilo-ohm
The pin assignments and main features of base to the controller. The frequency R15-R22 - 47–ohm
the microcontroller are shown in Fig.1 and (fosc) of the oscillator is internally divided R28 - 10-mega-ohm
the Box, respectively. The complete sys- by 2 to get the operating frequency (fop). Capacitors:
tem is divided into four sections, namely, This high-frequency clock source is used C1 - 350µF, 25V electrolytic
C2, C3 - 1µF, 16V electrolytic
the time keeping section, the input section to control the sequencing of CPU instruc- C4, C5 - 27µF ceramic disk
(keyboard), the output (display, indicators, tions. C6 - 0.1µF ceramic disk
and relay driving) section, and power sup- Timer. The basic function of a timer Miscellaneous:
ply and battery backup. is the measurement or generation of S1-S5 - Push-to-on switch (key)
time-dependant events. Timers usu- S6 - On/off switch
PZ1 - Piezo buzzer
RL1 - Relay 12V, 300-ohm, 1C/O
Main features of mc68h705j1a XTAL - 3.2768MHz AT-cut crystal
X1 - 230V AC primary to 12V-0-
• 14 bidirectional input/output (I/O) lines.
12V, 500mA secondary trans-
(All the bi-directional port pins are programmable as inputs or outputs.)
• 10 mA sink capability on four I/O pins (PA0-PA3). DIS.1-DIS.4 - LTS542 common-anode dis-
• 1,240 bytes of OTPROM, including eight bytes for user vectors. play
- 4 x 1.2V Ni-Cd cells
• 64 bytes of user RAM.
• Memory-mapped I/O registers.
• Fully static operation with no minimum clock speed. ally measure time relative to the internal
• Power-saving stop, halt, wait, and data-retention modes. clock of the microcontroller. The MC68H-
• Illegal address reset. C705J1A has a 15-stage ripple counter
preceeded by a pre-scaler that divides the
• A wide supply voltage range from-0.3 to 7 volts.
internal clock signal by 4. This provides the
• Up to 4.0 MHz internal operating frequency at 5 volts.
timing references for timer functions.
• 15-stage multifunction timer, consisting of an 8-bit timer with 7-bit pre-scaler.
The programmable timer status and
• On-chip oscillator connections for crystal, ceramic resonator, and external clock.


timer interrupts will be generated after
every 10 ms (100 Hz). That is, 100 inter-
rupts will make 1 second.
Now time-keeping becomes very sim-
ple. As we are having a precise 1-second
time count, a real-time clock can be easily
The MC68HC705J1A has a 64 byte
RAM that is used for data storage, Real
time (in terms of seconds, minutes, hours,
days of a month, and months) is stored in
this RAM. Thus an accurate real-time clock
is generated.
The input section. For setting the
real-time clock and storing operating times,
the timer requires to be programmed exter-
nally. Data is fed using the keyboard.
Press-to-on type keys are interfaced to
the microcontroller using an 8-bit priority
encoder CD 4532. This encoder detects
the key-press operation and generates
the equivalent 3-bit binary data. Its truth
table is shown in Table II. The priority
encoder is interfaced to port A of the mi-
Various keys used in the timer,
along with their functions, are described
Time (4): For setting real time in
minutes and hours.
Bell (5): For setting the bell’s operat-
ing timings.
Digit Advance (6): Data setting is
done digitwise (hour’s digit followed by
minute’s digit). The Digit Advance key
shifts the decimal point to the right.
Store (7): For storing the data (real
time or bell time).
Delete (3): For deleting a particular
bell timing.
Here, the figures within parentheses
indicate the decimal equivalents of 3-bit
binary data from the keyboard.
Set and run modes. Data setting is
possible only in set mode. Set mode or
run mode can be selected by toggle switch
S6. By using a lock switch for S6, the
timer can be protected from unauthorized
data entry/storage.
In run mode if you press ‘Bell’
key once, the display shows the bell’s
various operating timings one after the
other, in the same order in which these
had been previously stored. In case you
want to discontinue seeing all the bell
Fig. 2: Schematic diagram of the microcontroller-based school timer timings, you may press ‘Time’ key at
any stage to revert back to the display
control register (TSCR) is used for de- cycles. In Table I, the control word is set to of real time.
ciding the interrupt rate. It can be pro- provide the interrupts after every 16,384 The output section. Seven-segment
grammed to give interrupts after every cycles. For a 32,768MHz crystal, the displays are used for data display. As
16,384, 3,2768, 65,536, or 131,072 clock interrupt period will be 10ms. Thus, LEDs are brighter, these have been used


in the system. There are two techniques inputs fast enough, your eyes see the re- backed power supply, so that in the
for driving the displays: (i) driving each sult as a continuous display. With LEDs, case of power supply, so that in the
display using a separate driver (like only one digit is lighted up at a time. This case of power failure the functioning
74LS47 or CD4511) and (ii) using multi- saves a lot of power and also components, of the controller’s timer section is not
plexed displays. making the system economical. affected. During power failure the
The first technique works well, Generally, displays are refreshed at a timer is taken to ‘low power’ mode (called
but practically it has two problems: it frequency of 50 to 150 Hz. Here, displays ‘wait’ mode). In this mode the controller
uses a large number of IC packages and are refreshed at a frequency of 100 Hz draws a very small current. So small Ni-
consumes a fairly large amount of cur- (after every 10 ms). The display-refreshing Cd batteries can provide a good backup.
rent. By using multiplexed display both program is an interrupt service routine A simple diode-resistance (27-ohm,
the problems can be solved. In multiplex- program. BCD-to-7-segment decoder/driv- ¼-watt) charger maintains the charge of
ing only one input is displayed at any er 74LS47, along with transistor 2N2907, the battery at proper charging rate.
given instant. But if you chop or alter and 3-line-to-8-line decoder 74LS138
are used for driving
common-anode dis- Software
plays. Motorola offers Integrated Development
In multiplexed Environment (IDE) software for program-
display, the current ming its microcontroller and complete
through the seg- development of the system. The develop-
ments is doubled to ment board comes with Editor, Assembler,

increase the display’s and Programmer software to support
brightness. 74LS47 Motorola’s device programmer and soft-
is rated for sinking ware simulator. The ICS05JW in-circuit
a current of up to 24 simulator and non-real-time I/O emula-
mA. As the current tor for simulating, programming, and
persists for a very debugging code for a MC68HC705J1A/KJ1
Fig. 3: Power supply circuit for the school timer small time in multi- family device.
plexed display, it is When you connect the pod to your
peaky and can be as host computer and target hardware, you
high as 40 mA per can use the actual inputs and outputs of
segment. the target system during simulation of
The decimal the code. You can also use the ISC05JW
point is control- software to edit and assemble the code in
led individually by standalone mode, without input/output
transistor BC547, to/from pod. The pod (MC68HC705J1CS)
as 74LS47 does not can be interfaced to any Windows 3.x-or
support the decimal Windows 95-based IBM computer using
point. PA0 and PA1 serial port.
bits of port A are The software for the timer has been
used for controlling so developed that the system becomes
the electro-mechani- as user-friendly as possible. The main
cal relay and buzzer, constraint is read/write memory (RAM)
respectively. space. As mentioned earlier, the micro-
Power supply controller has only 64 byte RAM. About
and battery twenty bell operating timings are required
backup . T h e to the stored. So the efficient use of RAM
microcontroller becomes essential.
and the associ- The software routines for the timer,
ated IC packages along with their Assembly language codes,
require a 5V DC are listed in a folder. (Note: This folder,
supply, while the containing source code (.asm) and listing
relay and the file (.lst) will form part of the EFY-CD
buzzer require provided with the August 2001 issue. As
12V DC supply. files are quite large, it is not feasible to in-
A simple rectifier clude them here.) Basically, the following
along with zener functions are performed by the software
diode-regulated program:
power supply 1. Initialisation of ports and the
is used. The mi- timer.
crocontroller is fed 2. Reading of keypressed data.
Fig. 4: Actual-size single-sided PCB for the circuits in Figs 1 and 2 through a battery- 3. Storing of real time and bell


Table I Set. The real time and bell timings
Timer Status and Control Register (TSCR) are stored using this part of the software.
Bit 7 6 5 4 3 2 1 0 Data is entered digitwise; for example,
Signal TOF RTIF TOIF RTIE TOFR RTIFR RTI RTO 08:30 a.m. will be stored a 0, followed by 8,
Reset 0 0 0 0 0 0 1 1 followed by 3, and finally 0. Data is stored
TOF: Timer overflow flag RTIE: Real-time interrupt enable
in 24-hour format.
RTIF: Real-time interrupt flag RTI and RTO: Real-time interrupt select bit
Data fed from the keyboard is con-
verted into equivalent hex and stored in
RTI RTO Interrupt period
RAM. Any particular operating timing can
0 0 fop ÷ 214 For 3.2768 MHz crystal
be deleted from the memory using ‘Delete’
0 1 fop ÷ 215 Frequency of operation (fop)
key, provided the timing is already stored
1 0 fop ÷ 216 = 3.7268x106/2 = 1.638x106MHz
in the memory.
1 1 fop ÷ 217 For RTI=RTO=0
Run. Here the real time is compared
Interrupt period = 10ms (100Hz)
with bell operating time. If the two match,
the relay is operated.
Table II DataCon. This part of the software
Truth Table for Priority Encoder CD4532 is used for finding out the decimal equiva-
Keys E1 D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0 lent of hex data. The microcontroller
Store 1 1 X X X X X X X 1 1 1 manipulates the hex data and converts it
Digit Adv. 1 0 1 X X X X X X 1 1 0 into BCD format for display.
Bell 1 0 0 1 X X X X X 1 0 1 Timer. The timer of the microcontrol-
Time 1 0 0 0 1 X X X X 1 0 0 ler is initialized to give an interrupt after
Delete 1 0 0 0 0 1 X X X 0 1 1 every 10 ms. A real-time clock is gener-
ated using the interrupt. Also the display
timings. 5. Display of data. is refreshed during the interrupt service
4. Comparison of real time and bell 6. Time-keeping. routine.
time. If the two match, the bell rings. For a user-friendly system, the as- For real-time systems battery backup
sociated software is is very essential, because power failure
required to perform affects the time keeping. In interrupt
many data manipula- service routine, the availability of
tion tricks and inter- power supply is checked. If the power is
nal branching. The available, displays are refreshed and
operation and logic the timer operates normally. However,
can be understood during the power-failure period, dis-
from the Assembly plays are off and system is taken to ‘low
language listings. The power’ mode. In this mode only the
software is mainly di- timer part of the microcontroller remains
vided into the follow- activated while operations of all other
ing modules: peripherals are suspended. This consid-
Keyboard. When erably reduces the power consumption.
a key is pressed, When the supply gets restored, the
CD4532 sends the controller starts operating in normal
corresponding data. fashion.
After reading the
data, the controller
decides on the action.
Operating procedure
‘Set/ Run’ key (S6) When the power is switched on, the
is connected to port display shows 12.00. Two settings are
PA4. required in the timer: (a) setting of real
Bell. This part time and (b) setting of bell operating tim-
of the program is ings. For setting real-time clock ‘Time’
used for displaying key is used.
the bell operating Storing of real time. To store real
timings stored in the time, say, 05:35 p.m., flip ‘Run’/’Set’ key
RAM. The operating (S6) to set mode. The display will show
timings are displayed ‘0.000’. Press ‘Time’ key. Further press-
one by one with a ing of ‘Time’ key will increment the data,
delay of 5 seconds like 0.000, 1.000, 2.000, and thereafter
between tow consecu- it will repeat 0.000, etc. To select the
tive timings. digit, press ‘Digit Advance’. This stores
Fig. 5: Component layout for the PCB the present digit and the next digit is


selected as indicated by the decimal will not accept any new bell timings
pointer. Data is stored in 24-hour for- until one of the previously stored timings Programming
mat. The time to be stored is 17.35, of is deleted. There are two ways to program the
which the first digit will be 1.000. The Deletion of bell operating timings. EPROM/OTPROM (one-time program-
second, third, and fourth digits can For deleting a particular timing, first store mable ROM):
be stored in similar fashion. After the this timing using the steps given above. 1. Manipulate the control bits in the
fourthdigit, press ‘Digit Advance’ key Then press ‘Delete’ key to delete the spe- EPROM programming register to pro-
once more. The display will show 1735 cific data from the memory. gram the EPROM/OTPROM on a byte-
(with no decimal). Now press ‘Store’ to Display of real time. If ‘Run’/’Set’ by-byte basis.
store the data. key is taken to run mode, real time will 2. Program the EPROM/OTPROM
Storing of bell timings. The pro- be displayed. with Motorola’s MC68HC705J in-circuit
cedure to store bell operating timings is Checking of bell operating times. simulator.
similar to that of setting real time. The For checking the bell operating times, The author has used the second
only difference is that here data is changed press bell key in ‘Run’ mode only. The method for programming the OTPROM.
by ‘Bell’ key in place of ‘Time’ key. Any stored bell operating timings will be An actual-size, single-sided PCB for
number of bell timings (<20) can be stored displayed one by one with a delay of the circuits in Figs 2 and 3 is shown in
in the same fashion. If the number of bell 5 seconds between two consecutive Fig. 4, with its component layout shown
operating timings exceeds 20, the timer timings. in Fig. 5. ❏

Readers’ comments:

Q1. I have assembled this circuit and
found that pins D0 and D1 of IC 4532
are not properly terminated. Will
this affect the keyboard data? Could
you please tell me from where I can
get the programmed controller?
Deep Saraf
Q2. Does the circuit work by just
assembling it with the IC (MC68H-
C705J1A) bought from the market,
or do we have to install a software
in it? From where can we get the
software? Give a detailed procedure
about how to install the software in
the IC. Fig. 1: Modification of display circuit to operate 2.5cm/5cm display
A. Rajasekaran
Chennai present circuit after omitting resistor R1. ment kit and IDE (integrated development
Q3. The circuit can be modified as shown Somnath Bera environment) software available through
in Fig. 1 for using a brighter and bigger Through e-mail Motorola distributors/Internet. The same
display. You can use this modification for A1 and 2. EFY: Leaving two of the un- can be purchased through our associate
one set of 2.5cm (1-inch) or 5cm (2-inch) used input pins open will not affect the Kits‘n’Spares.
display. For 5V supply, use 7805 regu- circuit performance. The microcontroller A3. EFY: The circuit sent by the reader
lator in place of the zener diode in the has to be programmed using a develop- had anomalies, which have been corrected.


Digital Capacitance-cum-
Frequency Meter
pratap chandra sahu

re is an inexpensive circuit of and external frequency = 1 kHz, we can Parts List
a digital capacitance-cum-fre- read the value of the capacitor under test Semiconductors:
quency meter that can meas- (CUT) directly in nanofarads. With R = IC1 - NE555 timer
ure capacitance in the range of 1 pF to 1 kilo-ohm and frequency = 1 kHz, we IC2, IC3 - CA3140 high-input imped-
10,000 µF and frequency in the range of can read the value of the CUT directly in ance op-amp
microfarads. IC4 (A-D) - 7408 AND gate
0 to 100 kHz. With a slight modification, IC5 - MM74C925 4-digit counter/7-
this circuit can be used as an article coun- Frequency measurement. This segment driver
ter or a time meter. involves passing the unknown frequency IC6 - 74LS121 monostable MV
The principle. In a frequency coun- signal for a known time base period IC7-IC9 - 74LS90 decade counter
through the counter. In a 4-digit counter (divide-by-10)
ter, the unknown input is ANDed with a
IC10 - 7476 JK flip-flop
known time-base period, so that the num- with a time base of one second, the maxi-
IC11 - 7805 regulator +5V
bers of cycles passed over the time-base mum display will be 9999, which means D1-D5 - 1N4007 rectifier diode
period are counted. The time period can be that we cannot read a frequency of more D6 - 1N4148 switching diode
measured similarly if a known frequency than 9999 Hz (≈10 kHz). However, if we LED1 - Red LED
reduce the time base to 0.1 second, the T1-T5 - BC547B npn transistor
is gated with the unknown time period. T6 - BS107 FET
The same instrument can also determine frequency reading can go up by a factor of Resistors (all ¼ watt, ±5% carbon, unless
the time period of a periodic waveform or ten to 99.99 kHz (≈100 kHz) as the time stated otherwise)
the time elapsed between two events. base virtually divides the input frequency R1 - 2.2-kilo-ohm
by 10. For low-frequency measurement, R2, R5 - 1-mega-ohm
In this circuit, the capacitance meas-
R3, R8, R24 - 4.7-kilo-ohm
urement is nothing but the measurement we can increase the resolution by a factor
R4, R20 - 10-kilo-ohm
of the time between two events in a charg- of ten by increasing the time base period R6, R7, R18
ing capacitor. An R-C (resistor-capacitor) to 10 seconds, which is equivalent to the R21 - 1-kilo-ohm
circuit works as a time generator and the multiplication of the input frequency by a R9-R16 - 220-ohm
factor of 10. R17 - 20-kilo-ohm
time is directly proportional to capacitance R19 - 100-kilo-ohm
value under suitable conditions. In the R22, R23 - 560-kilo-ohm
present case the condition being satisfied VR1 - 1-kilo-ohm preset
is that the time period (T) is equal to the
Circuit and operation Capacitors:
The capacitance measurement mode. C1 - 15µF, 25V electrolytic
product RxC, where R is the value of the
C2 - 0.01µF ceramic disk
charging resistor in ohms and C the ca- During the capacitance measurement
C3 - 10nF ceramic disk
pacitance value in farads. mode, switches S1 through S5 are kept C4 - 10µF, 250V electrolytic
Capacitance measurement. One slided towards position ‘C’. The unknown C5 - 1000 µF, 25V electrolytic
RxC time (seconds) is required to charge capacitor is placed across CUT terminals. C6 - 100µF, 25V electrolytic
Ganged switches SR1 and SR2 are used C7, C8 - 22 pF ceramic
a capacitor to 63 per cent (approximately C9 - 0.01µF ceramic
two-third) of its final value (applied volt- for capacitance measurement. Position 1 Miscellaneous:
age). is used for capacitance range of 1 pF to X1 - 230 AC primary to 9-0-9 volt,
Consider the following example: 9999 pF (≈10 nF), position 2 for capaci- 500mA secondary trans-
tance range of 1 nF to 9999 nF (≈10 µF), former
If C = 470 pF and R = 1 mega-ohm,
XTL - 1MHz quartz crystal
then one RC time period T = 470x10–6 and position 3 for capacitance range of 1
S1-S5 - Slide switch
seconds = 470 microseconds. µF to 9999 µF. S6, S7 - Push-to-on switch
If we select the external frequency for Switch SR1 selects 1 mega-ohm charg- SR1-SR2 - Ganged 3-way, 2-pole rotary
the counter as 1 MHz (time period = 1 mi- ing resistor in its positions 1 and 2, while switch
switch SR2 selects a frequency of 1 MHz SR3-SR4 - Ganged 3-way, 2-pole rotary
crosecond), the counter progresses by one switch
count every microsecond and the counter in position 1 and a frequency of 1 kHz in DIS1-DIS4 - LT543 common-cathode,
reading is 470, as the gate will be open for position 2 for the counter operation. In po- 7-segment display
470 microseconds for the above-mentioned sition 3, 1-kilo-ohm charging resistor R6 is
R and C under testing. We get the capaci- selected by SR1, while SR2 selects 1 kHz only. (EFY note. As decimal indication
tance value directly from the readout of as the frequency for counter operation. is not required during capacitance meas-
the counter in picofarads. Ganged rotary switches SR3 and SR4 urement, one might have an additional
Similarly, if we take R = 1 mega-ohm are used for frequency measurement mode ‘off’ position for SR3/SR4 ganged rotary



Fig. 1: Circuit diagram for digital capacitance-cum-frequency meter
IC1 is a monostable multivibrator of 15-second duration. As soon as its out- input of IC3 is biased at 0.63Vcc, which is
based on timer NE555 and is meant for put goes high, it switches off FET switch. set accurately by 1-kilo-ohm preset VR1.
capacitance measurement only. In normal Simultaneously, it takes pin 5 of AND Now the capacitor begins to charge. As
condition, the low output of the monostable gate IC4A high. soon as the voltage across the capacitor
turns on the FET (BS107) switch. So the Now let us examine the conditions at crosses 0.63Vcc (i.e. 3.15 volts with Vcc
capacitor under test gets shorted via the IC2 and IC3 (both CA3140 op-amps). The = 5 volts), the output of IC3 goes low.
FET switch. As and when triggered by the voltage across CUT, after being buffered Thus the output of IC3 and also that of
momentary push-to-on operation of start by IC2, is fed to the inverting input of IC3 AND gate IC4A remains high until the
switch S6, the monostable provides a pulse wired as a comparator. The non-inverting capacitor charges to 63 per cent of Vcc in
one RC time.
Latch-enable (LE) pin 5 of counter
IC5 (74C925) connected to pin 6 of IC4A
remains high to pass the clock selected
via rotary switch SR2 and coupled to
CL (clock) pin 11 of IC5 via AND gate
IC4B. It goes low after one CR time to
latch its count as the output of IC3 goes
low. Thus the number of cycles from the
frequency source passed over one CR
time is recorded in the counter and gets
For precise generation of 1MHz fre-
quency, a 1MHz crystal oscillator is wired
around Schmitt inverter gates N3 and N4.
The oscillator output is routed via AND
gate IC4C to slide switch S2 and rotary
switch SR2 position 1. In capacitance (C)
position of switch S2, this signal, after
Fig. 2: Internal block diagram and functional description for IC 74C925 division by three decade counters IC7, IC8,
and IC9 (7490), which are common to both
frequency and capacitance meter modes,
provides 1kHz signal at pin 12 of IC9,
which, in turn, is extended to positions 2
and 3 of switch SR2. (Note. The outputs
of IC10 are not used during capacitance
measurement. IC10 comes into play only
during the frequency measurement as
explained later.)
The NE555 timer used as a monoshot
ensures the capacitance measurement in
an easy and automatic manner. The LED
connected to AND gate IC4D glows during
the charging of the capacitor. During the
measurement of high-value capacitances,
it may take several seconds to charge to
0.63Vcc. For low-value capacitances, the
LED glows for just a moment after press-
ing start switch S6. If the LED goes off af-
ter the start button is pressed, it indicates
that the measurement is over.
You can reset NE555 timer using
switch S7 if you want to make another
measurement. If this switch is not pro-
vided/operated, you would have to wait
for at least 15 seconds until NE555 timer
becomes normal. Alternatively, you will
have to switch off the complete circuit and
then switch it on again.
Frequency counting. In place of
1MHz oscillator, a 100Hz full-wave recti-
Fig. 3: Actual-size, single-sided PCB layout for digital capacitance-cum-frequency meter fied (pulsating DC) after being shaped by


SR3. Q output of IC10 is used to enable
counter IC5.
The resetting of counter-cum-display
IC5 is accomplished by the narrow output
pulse from IC6 (74121), which is generated
by the leading (rising) edge of Q output of
IC10 connected to its B input (pin 5) via
switch S5. Thus at the beginning of each
counting period, IC5 is reset.
IC5 (74C925) is TTL-compatible with
a multiplexed 4-digit, 7-segment display
driver. Its internal block diagram and
functions are described in Fig. 2. The
maximum frequency display in positions
1, 2, and 3 of ganged switches SR3 and
SR4 is limited to 99.99 kHz, 9.999 kHz,
and 999.9 Hz. The decimal point position
is fixed by switch SR4.
Calibration and testing. Connect a
multimeter to the non-inverting terminal

of IC3 and set the point at 0.63Vcc = 3.15
volts using 1-kilo-ohm preset VR1. To
test the capacitance meter, use a 470pF
polystyrene capacitor with one per cent
Precaution. Try to screen the mains
transformer from the input. Place the
transformer at a place where the chances
of its interference with the input are mini-
mal or nil. While measuring the frequency,
Fig. 4: Component layout for the PCB the frequency source under test should not
be touched or loaded to avoid affecting its
Schmitt inverter N2, is used as the master of gate N2. This 100Hz signal is divided frequency due to stray capacitance associ-
clock to provide the required time bases. by decade counters IC7, IC8, and IC9 to ated with the test leads.
The voltage divider network of resistors obtain 10Hz, 1Hz, and 0.1Hz frequencies. An actual-size, single-sided PCB
R20 and R21 protects gate N2 against The frequency selected via rotary switch for the circuit of Fig. 1 is shown in Fig.
high voltage. SR3 is then divided by 2 by JK flip-flop 3, with its component layout shown in
R21 is test selected to get proper 100 7476 (IC10) so as to provide a gate time of Fig. 4. ❏
Hz rectangular wave form at the output 0.1 second, 1 second, or 10 seconds in po-
sitions 1, 2, and 3, respectively, of switch
Readers’ comments: Praveen Shankar frequency meter after suitably calibrating
Q1. A provision to include inductance Haridwar its scale.
measurement by using an FET-based Q2. I have the following queries: A2. EFY: 1. Yes, ICs DM74LS121 and
tank oscillator circuit (as shown in 1. Are ICs DM74LS121 and SN74LS121 SN74LS121 are similar and you may use
Fig. 1) would enhance the utility of the the same? Can I use DM74LS121 or either of these two ICs as IC6.
circuit. The tank circuit could be tuned by SN74LS121 as IC6? 2. You can replace 15µF, 25V ca-
trimmer CT for a frequency of, say, 1 MHz 2. Can I replace 15µF, 25V capacitor pacitor C1 with a 22µF, 25V capacitor
with a standard inductor of 1 µH. Decade C1 with a 22µF, 25V capacitor? by changing the value of resistor R2
dividers can be used for other ranges for Chang Heen Loong (1 mega-ohm) such that R2 x C1 product
direct readout. Through e-mail remains the same, in order to retain
The author, Pratap Chan- the same output pulsewidth. Since IC1
dra Sahu, replies: (NE555) is a timer IC, configured as
A1. Such a tank oscillator is a monostable, the output at pin 3 is
not suitable for this circuit as approximately 16 seconds as per the
the frequency in such a circuit following relationship:
is inversely proportional to the Pulsewidth = 1.1(R2 x C1) seconds
value of inductance and there So, if the capacitor value is changed
is an offset frequency. The from 15 µF to 22 µF, the resistor value
circuit proposed by the reader needs be changed from 1 mega-ohm to 680
could, however, be used in con- kilo-ohms so that R2 x C1 product remains
Fig. 1: FET-based tank oscillator circuit junction with moving coil type almost the same.


Fluid-Level Controller
with Indicator
bhaskar banerjee

he fluid-level controller circuit pre- from ground level (0V) to supply voltage.
sented here allows you to set the The circuit Thus the reference voltage source should
lower and upper fluid levels at The main part of the circuit as shown in be externally preset, which is feasible with
the desired specific positions between Fig. 1 is dot/bar graph driver LM3914 the help of IC1. This IC can also display
two extreme levels. The total fluid level (IC1). This IC is linearly scaled and is the input voltage on a linear scale using
is divided into ten equal parts. Any two intended for use in LED voltmeter appli- ten LEDs in the bar graph or the dot mode.
of these ten positions may be defined as cation where the number of illuminated Here we have used the bar graph mode.
‘low’ and ‘high’ level, respectively. The LEDs indicates the value of input voltage. The outputs of IC1 are active-
system shows the preset levels on the It contains a floating 1.2V reference source ‘low’ and hence they sink current to
two 7-segment displays and the current between pins 7 and 8 that may be used as illuminate LEDs. Inverters are used
fluid level at any instant on a 10-LED bar the reference input for the IC. The voltage between the outputs of IC1 and the
graph indicator. The same circuit could from the sensor is fed to the input of IC1 inputs of IC3 and IC4 to invert the
also be used for controlling temperature at pin 5. active-‘low’ outputs of IC1. There
in a similar fashion. The output of the sensor may vary are ten outputs available from IC1,

Fig. 1: Schematic diagram of fluid-level controller with indicator


of which only 1, 2, and 3. All switched on. This power-on-reset function
five are used other unused is realised using capacitors C1 and C2,
here. One may input pins of and resistors R12 and R13. The part of
use up to eight IC3 and IC4 are IC6 connected to high-level selector also
outputs of IC1 grounded. gets reset when the count is 5 (101 binary).
since IC3 and The selec- This reset pulse is generated using AND
IC4 (4051) are tion takes place gates of IC CD4081.
1-of-8 data se- according to the The selected minimum and maximum
lectors. (Note. binary word pre- levels are displayed by two 7-segment dis-
If 4067 were Fig. 3: Sensor us- set at the select plays DIS1 and DIS2 that are controlled
used in place of ing float operated input pins (pin by two BCD-to-7-segment decoders 4511
4051, all the ten potmeter 9, 10, and 11) (IC9 and IC10, respectively).
outputs could be of IC3 and IC4. The outputs of IC3 and IC4 are fed
used. It is also Fig. 2: Optical sensor The required binary word is generated to the select input pins of IC5 (4051).
possible to get more than ten outputs by by a dual divide-by-16 counter IC6 (4520). The output of IC5 is fed back to one of
cascading LM3941 ICs.) (IC6 can be replaced by a divide-by-10 its select inputs through an inverter. IC5
Using this circuit, the maximum counter 4518, if desired.) Half of IC6 is determines the control logic. The pump
fluid level can be divided into four equal used for high level and the other half for (or the heater in temperature controller)
parts giving five different level readings low level. IC6 gets its counting pulse from should be ‘on’ when the fluid (or tempera-
from ‘0’ (empty/low level) to ‘4’ (full/high a 555 timer (IC7) used for generation of ture) level is below the minimum level and

level). Thus the five levels are empty, one- approximately 1Hz pulse train. should remain ‘on’ until the maximum
fourth, half, three-fourth, and full. This The high level is set by pressing switch level is reached. It must not start if the
division is meant only for controlling the S1, while the low level is set by pressing fluid level falls below the maximum level
level, while all levels including the inter- switch S2. IC6 is reset when the power is but remains above the minimum level.
mediate levels are constantly displayed
on LED bar graph.
The lower level can be set anywhere
between 0 and 3 in steps of 1 and high
level can be set between 1 and 4. The
fluid level can be maintained between
any two levels by using IC3 and IC4.
IC3 selects the high level and gets inputs
of levels 1, 2, 3, and 4, while IC4 selects
the low level and gets inputs of levels 0,

Parts List
IC1 - LM3914 bar/dot display
IC2 - 4069 hex inverter
IC3, IC4, IC5 - 4051 8-channel analogue
IC6 - 4520 dual binary counter
IC7 - 555 timer
IC8 - 4081 quad 2-input AND
IC9, IC10 - 4511 BCD-to-7-segment
LED1, 3, 5, 7, 9 - Green LED
LED2, 4, 6, 8,
10, 11 - Red LED
Resistors (all ¼-watt, ±5% carbon unless
stated otherwise):
R16-R31 - 470-ohm
R11-R15 - 10-kilo-ohm
R32-R33 - 47-kilo-ohm
R34 - 1-kilo-ohm
VR1 - 10-kilo-ohm preset
C1, C2 - 22µF, 25V electrolytic
C3, C4 - 10µF, 25V electrolytic
C5 - 1µF ceramic disk
DIS1, DIS2 - Common-cathode
7-segment display
S1, S2 - Push-to-on switch
Fig. 4: Actual-size, single-sided PCB layout for fluid-level controller with indicator


transformer that is used to power the cir-
cuit. Alternatively, a separate step-down
transformer may be used for the purpose,
but taking into account the voltage and
current ratings of the lamp.
One may also use the sensor described
in ‘Digital Water Level Meter’ in Circuit
Ideas section of the February 2000 issue of
EFY (also in Electronics Projects Vol. 21).
Use that sensor (VR4) as part of a voltage
divider network as shown in Fig. 3. If the
circuit is used as a temperature controller,
a temperature sensor using the popular
LM35 IC may be built (refer Circuit Ideas
published in March 1993 issue of EFY or
Electronics Projects Vol. 14).
Operation. The lower or the mini-
mum level is set by pressing switch S2 and
the upper or the maximum level by press-
ing switch S1. The two switches should
be kept pressed until the required level is
displayed. For example, if the lower level
is selected 1 and the upper level 3, the
pump (or heater or a flow valve) will start
when the fluid falls below level 1 and will
stop when the fluid reaches level 3.
Assembly and testing. The circuit
may be built on a veroboard. However,
an actual-size, single-sided PCB and its
component layout are shown in Figs 4 and
5, respectively. Switches used, should be of
good quality. After assembling, the circuit
may be tested using a voltage divider (po-
tentiometer) that could be varied between
ground and positive supply.
While testing, set preset VR1 to in-
Fig. 5: Component layout of PCB
crease or decrease the reference voltage
taking into account the maximum output
This function is realised by IC5 that can water level in a tank), an optical sensor as available from the actual sensor. In case
operate a pump (or an alarm, or a flow shown in Fig. 2 may be used. This optical of power failure, there should be proper
valve, or a heater, as required) according sensor consists of a small filament lamp battery back-up. Otherwise, the system
to this control logic. For this, the input (generally used in torch or an IR LED as will not behave as desired. Red and green
lines of IC5 are set to appropriate logic light source) and an LDR or a photodiode LEDs are arranged in alternate fashion to
levels, which must not be disturbed. as the sensor. The filament lamp may make the bar display look attractive. ❏
Sensor. To control the fluid level (say, be powered using the same step-down

Readers’ comments: bottom side of the tank cover. The work- reflected light intensity received by
Q1. Please explain the detailed working ing of the LDR to control the water level is the LDR will be low when the water level
of the circuit. Also elaborate as to how to explained below. is low and it will increase as the water
arrange the LDR and filament lamp in the The light rays from the lamp are re- level in the tank rises. (The intensity at
tank? Please give details, how water level flected from the water surface and fall on the LDR depends on the total length of
will be controlled by LDR? Is there any LDR1. The orientation and the intensity the path travelled by light.) Thus the re-
reflection of light from water surface? of light source are the deciding factors for sistance of LDR is high when the level of
Ajit incidence of adequate reflected light on the water is low and its resistance decreases
Through email LDR for proper control of water level control. as the water level increases. The intensity
A1. EFY: The optical sensor section (LDR No direct light should be allowed to fall of light is indicated by the LEDs and
and filament lamp) can be fixed rigidly on on the LDR. Fix a suitable opaque screen 7-segment display in Fig. 1. of the article.
the bottom side of the tank lid/cover using closer to LDR, between the light source and VR2 (preset) is used to vary the sensitivity
M-seal or Fevi Quick or similar compound. the LDR. of LDR1 so as to obtain a predetermined
Alternatively, you may mount them on a For any given orientation of the light LED/7-segment display when a specified
wooden strip and secure the strip to the source and the position of the LDR, the level is reached.


MGMA—A Mighty Gadget
with Multiple Applications
a. jeyabal

GMA, pronounced as migma, is Fig. 1 shows the block diagram of tor C1, and potmeter VR1 form the oscillator
a versatile and multi-purpose the MGMA circuit. Block 1 is an oscil- circuit. Let us presume that capacitor C1 is in
gadget. It can be used for a lator that is controlled by block 2. Block discharged state and pin 2 of gate N1 is in high
range of applications, from a simple toy 2 contains another oscillator whose fre- state. As the input pin is low, output pin 3 is
to domestic and workbench applications. quency is much lower than that of the high and capacitor C1 starts charging through

It measures time, compares light output, former. The differentiator circuit in block potmeter VR1.
temperature, resistance and capacitance, 3 resets the decade counters periodically. When the voltage across capacitor
etc. You can use this gadget in a number Blocks 4 and 5 count the pulses, which, C1 reaches above half of the supply
of ways, depending on your imagination in turn, are displayed by blocks 6 and voltage, input pin 1 of gate N1 goes high
and creativity. 7. Digit 9 in tens counter is decoded and output pin 3 goes low. Now capaci-
Basically, MGMA is a resistance- by block 8, and its output disables the
capacitance-controlled oscillator that counting process and triggers the aural
counts the pulses for a specific period. If indicator in block 9. Block 10 comprises Parts List
any transducer, such as light-dependent the regulated power supply to run the Semiconductors:
resistor (LDR) or heat-dependent resis- gadget. IC1 - CD4093 quad 2-input Sch-
tor (thermistor), is connected to it, the mitt trigger NAND gate
IC2, IC3 - CD4033 decade counter/
display shows the value corresponding to
its resistance. Contact or break (normally Circuit IC4
7-segment decoder
- 7805 +5V regulator
open or closed) type transducers can also Oscillator. In Fig. 2, Schmitt trigger input T1 - BC557 pnp transistor
be used with MGMA. NAND gate N1 of IC1 (CD4093), capaci- T2 - SL100 npn transistor
D1-D7 - 1N4148 switching diode
D8, D9 - 1N4001 rectifier diode
LED1 - Red LED
Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise)
R1, R6-R9 - 100-kilo-ohm
R2 - 220-kilo-ohm
R3 - 470-kilo-ohm
R4 - 3.3-kilo-ohm
R5, R10, R11 - 330-ohm
VR1 - 1mega-ohm pot., linear
VR2 - 47-kilo-ohm pot., linear
C1, C3 - 0.001µF ceramic disk
C2 - 4.7µF, 10V tantalum
C4 - 1000µF, 25V electrolytic
C5, C6 - 0.1µF ceramic disk
X1 - 230V AC primary to 9-0-9V
AC, 100mA secondary trans-
S1, S2 - Push-to-on switch
S3 - SPST switch, 230V AC
DIS1, DIS2 - LT543 7-segment, common-
cathode type LED display
SOC1 - SOC4 - Earphone socket
SOC5 - DC IN socket
PZ1 - Piezo-buzzer
- IC bases, knobs, mains
chord, cabinet
- Banana-type earphone plugs
Fig. 1: Block diagram of the MGMA circuit


Fig. 2: Schematic diagram of MGMA

tor C1 discharges through potmeter pulses through R1 when switch S1 is held low. So on reset, only DIS1 (unit
VR1. When the voltage across capacitor pressed. digit) will show zero as RBI pin 3 of
C1 falls below half of the supply voltage, Counter and display. The output of IC3 is grounded.
pin 1 of gate N1 goes low and the output the oscillator is connected to clock input Switch S2 is provided to reset the
pin goes high. Now capacitor C1 starts pin 1 of IC2 (CD4033, a decade counter counter manually. Current-limiting
charging again and the cycle repeats for unit digits). The carry-out pin 5 of IC2 resistors R5 and R10 provided with
DIS2 and DIS1, respectively, are used
itself. is connected to the clock input of decade
to reduce the component count and
The pulses from the output of gate counter IC3 that is meant for ten’s digits. ensure the proper operation of digit-9
N1 reach counter IC2 through resistor The segment outputs of both IC2 and decoder circuit.
R1. Switch S1 is provided to stop the IC3 go to the respective seven segments Display controller and differ-
counting manually by grounding the of DIS1 and DIS2 (LT543) for displaying en-tiator. For accurate reading of the
the number of pulses. counter, it must be reset periodically
Table Lamp-test (LT) pin 14 of and the pulses must be counted
Count Decoded output of IC CD4033 both IC2 and IC3 is grounded for a specific period. For this an
a b c d e f g CO through 100-kilo-ohm resistor oscillator circuit comprising gate
0 1 1 1 1 1 1 0 1 R8. The test-point (TP) may N2, diodes D1 and D2, resistor R2,
1 0 1 1 0 0 0 0 1
potmeter VR2, and capacitor C2 is
be used to check the display.
2 1 1 0 1 1 0 1 1
used. This oscillator also works like
When a high-level voltage (5V) the previous one, but its charging
3 1 1 1 1 0 0 1 1 is applied to the test-point, all and discharging paths are separated
4 0 1 1 0 0 1 1 1 segment outputs go high and by diodes D1 and D2. Its ‘on’ time
5 1 0 1 1 0 1 1 0 the display shows 88. (high-level output) can be controlled
6 1 0 1 1 1 1 1 0 by potmeter VR2.
The display is blanked out
7 1 1 1 0 0 0 0 0 When output pin 4 of gate N2 goes
when the number to be dis-
8 1 1 1 1 1 1 1 0
played is 0, provided the ripple from low to high state, the differentiator
9 1 1 1 1 0 1 1 0
blanking input (RBI) pin 3 is circuit comprising capacitor C3 and resis-


tor R9 produces a sharp pulse that resets and it outputs clock pulses. These gate and bring the CE pin to ground for
counters IC2 and IC3. At the same time, pulses are counted by IC2 and IC3 numbers 0 through 8. When the number
gate N1 is enabled as output pin 4 of gate and displayed on DIS1 and DIS2, is 9, the segment outputs a, b, and e are
N2 is connected to input pin 2 of gate N1, respectively. So the oscillator around high, except the segment output e, which
gate N1 is enabled and is inverted by transistor T2. As a result,
disabled during the high CE pin of IC2 goes high and the counters
and low states, respec- are disabled.
tively, of the output of Simultaneously, this high-level out-
gate N2. put is inverted by gates N3 and N4. The
The counters retain inverted output from gate N4 forward
their last count for read- biases transistor T1 to drive the piezo-
ing until the output goes buzzer, while the inverted output from
high once again. This gate N3 grounds the resetting pulses.
reading time is about 2 Diode D4 prevents the high output of
to 3 seconds, which is N3 from reaching the reset pins of IC2
set by resistor R2. Any and IC3.
increase in the value of Power supply. In 5V DC power sup-
R2 will increase the read- ply shown at the bottom in Fig. 2, IC 7805
ing time and vice versa. (IC4) is employed for better regulation. DC
Resistor R3 connected in input/output socket (SOC5) is provided to

parallel across capacitor operate the gadget with external 9V bat-
C3 is used to discharge tery. LED1 acts as a power-on indicator.
it quickly and diode D3
is used to block the DC
voltage (when switch S2 is Construction
pressed) going to gates N1 Figs 3 and 4 show suggested actual-size,
and N3, and other parts of single-sided PCB layout and component
the circuit. layout, respectively, for the circuit in Fig.
Digit 9 decoder and 2. Solder the components in the order of IC
aural indicator. It is sockets, jumpers, resistors, capacitors, di-
very useful to sound an odes, LED, and transistors. Then connect
alarm for a certain read- the rest of the components through wires.
Fig. 3: Actual-size, single-sided PCB pattern suggested for ing or otherwise, say, for a Fig. 5 shows the proposed front-panel
the circuit in Fig. 2 layout of MGMA.
particular temperature or
light output or resistance Before connecting VR1 and VR2 to
value, etc. A permanent the PCB, mark the dials using a digital
number 90 is chosen for multimeter. Both dial 1 and dial 2 (refer
simplicity of the decoding Fig. 5) are calibrated in terms of resist-
circuit. When the display ance for the variable resistance values of
shows 90, the counter must 1 mega-ohm in case of VR1 and 47 kilo-
be disabled and the buzzer ohm in case of VR2, respectively, using a
enabled. digital multimeter. (Note. There may be
From the table of de- dead-ends on both ends of the potmeter,
coded outputs of IC 4033 it and it may vary in construction from
is found that for number 9, manufacturer to manufacturer.) Mark the
at least one of the segment dials for every ten units for easy reading
outputs is low (a, b and f and setting.
are high, while e is low).
For number 8, segment e
is inverted by transistor Applications
T2. As RBI pin 3 of IC3 is For high-resistance and low-resistance
grounded, all the segment transducers, use earphone-type sock-
outputs go low for 0. The ets SOC1 and SOC3, respectively. For
clock-enable (CE) pin 2 of low-capacitance and high-capacitance
IC3 is pulled up by resis- testing, use earphone-type sockets SOC2
tor R7. and SOC4, respectively. For SOC1 and
Pin 2 is also connected to SOC2, the reading will decrease for
a, b, f and e segment outputs of the increasing value of resistance and
IC3 through diodes D5, D6, D7, capacitance, and vice versa for SOC3
and transistor T2, respectively, and SOC4.
Fig. 4: Component layout for the PCB that altogether act as AND Strength-0-meter. This game re-


Game of quick hands. This game 0, and shorted if you’re unable to set the
requires an earphone plug with its two reading near 90.
terminals shorted. Inserting this plug into Remove the unknown resistor. With-
SOC4 grounds input pins 5 and 6 of Sch- out disturbing dial 2, slowly rotate dial 1
mitt NAND gate N2 via the shorted plug to get the same reading. Now dial 1 shows
in SOC4. Since output pin 4 is always in the value of unknown resistor.
high state, its periodic action of disabling If the resistor value is less than 40k,
gate N1 is no longer there. use SOC3 and repeat the same procedure
Connect a 0.1µF capacitor to SOC2 us- with dial 2 instead of dial 1 for accurate
ing an earphone plug. Since its capacitance measurement. The resistance value can be
value is higher than that of capacitor C1, read from dial 2.
Fig. 5: Proposed front-panel layout of MGMA the frequency of the oscillator decreases. Checking and measuing capaci-
The display shows a reading on momen- tance. Using MGMA you can measure
tarily pressing start/reset button capacitances from 0.001 µF to 5 µF. First
S2 and then quickly depressing stop check for the usability of the unknown
button S1. Adjust the dial to read 50 capacitor. Adjust dials 1 and 2 to read 50
in the display. Now tell your friends in the display. Now check the unknown ca-
to press button S2 momentarily and pacitor using SOC2 for unipolar or SOC4
then S1. One who scores less is more for electrolytic/tantalum capacitors with
quicker than the others, and hence the inner and the outer terminals of the
the winner. socket for positive and negative terminals
Water-level monitoring. Five of the capacitor. If there is no change
resistors R12 through R16 are con- in the reading it means the capacitor is
nected in series and the junctions of shorted and a higher reading implies it
the resistors are extended to the five is good.
levels of the water tank using wires To find the value of an unknown non-
(refer Fig. 6). A reference rod is also electrolytic (unipolar) capacitor, connect
fitted with its lower end just below the same to SOC2. Adjust dials 1 and 2 to
Fig. 6: Connections for water level monitor level 1. read a number around 80 in the display.
Plug-in a dummy resistor of Now, without disturbing the dials insert
quires two small rods or prods. Connect 100k into SOC1 and rotate dial 1 to the known capacitors one by one in SOC2.
them to an earphone plug using a pair of the zero-resistance position. Adjust dial 2 The unknown capacitor value is equal to
wires half a metre long. Then insert the to read 55 in the display. Cover the unit the value of the known capacitor for which
plug into SOC1. Hold the rods in each digit with an opaque tape, so that only the display shows the same reading or
hand between forefinger and thumb. the ten’s digit is visible. Now remove the near the number 80.
Adjust dials 1 and 2 such that the buzzer dummy resistor. Connect the other end The procedure is same for electro-
beeps. Then rotate dial 1 slightly in the of five-resistor ladder and the reference lytic and tantalum capacitors, except
anti-clockwise direction to read around 70, probe to SOC1. The display will show the that SOC4 is to be used in place of SOC2,
a point where the buzzer is silent. Now ask water levels from one-fifth to five-fifth of ensuring that the inner and the outer ter-
your friends one by one to grip the rods the tank, depending on the actual level minals of the socket are used for positive
firmly. The winner is the one who sounds at that time. and negative terminals of the capacitor,
the buzzer or scores higher on the meter. Measuring resistance. The idea is respectively.
This depends on how hard one holds the simple. First, VR1 (dial 1) is excluded from Testing a diode. Rotate dial 1 to
rod, the internal resistance of the body, the circuit by rotating it to zero reading. high-resistance position and adjust dial
and dampness of the fingers. Then an unknown resistor is connected 2 such that the display shows a flickering
Plant tender. You can use MGMA to SOC1 and dial 2 is adjusted to read a 45. Test the diode in SOC3 using an ear-
to indicate the time of watering in order number just below 90. Now VR1 (dial 1) is phone plug in the same manner as men-
to avoid excessive watering of plants. For reinstated and rotated to display the same tioned earlier. Interchange the leads and
this, insert two metal strips on both sides reading. As dial 1 is marked for resistance test again. A shorted diode will not make
of the plant. Connect them to an earphone values, the position of dial 1 indicates the any change in the reading, while a good
plug using wires and insert the plug into value of unknown resistor. one gives a reading of around 60 and 90 in
socket SOC3. Since soil-resistance in- With MGMA, up to 2-mega-ohm both the tests. And for the open diode, the
creases with loss of water, the alarm can resistor can be measured. Connect display shows 90 in both the tests.
be set/activated for a specific moisture the unknown resistor to SOC1 us- While checking the diodes, a parallel
level. Adjust dials 1 and 2 such that the ing crocodile clips. Rotate dial 1 to resistance of 100k is required across the
buzzer sounds when the plant needs to be the zero-resistance position without diode. Our body resistance may also do.
watered. The buzzer stops in a short while touching the resistor, otherwise your Other utilities. Heat alarm, fire
on sprinkling water over the soil support- body resistance will get included in alarm, security alarm, strain gauge, in-
ing the plant. The next time the buzzer the measurement. Adjust dial 2 such truder alarm, rain alarm, number game,
will sound automatically when the plant that the display reads around 90. The timer, and many other circuits can be real-
needs to be watered. resistor is open if the display shows ised using this MGMA circuit. ❏


rajesh gupta

his circuit of an adjustable traffic signal for streetlight operation. Its opera- light modes (Part I) controls the switch-
and street light controller can con- tion does not require any software and ing time of streetlights in evenings and
trol the timings of four sides of hardware knowledge. mornings and the time to changeover from
traffic lights separately. It can also control This circuit can also be adopted for
the changeover from continuous traffic synchronisation with the signals of ad- PARTS LIST

light mode to blinking yellow light mode jacent traffic lights by introduction of Semiconductors:
(at night), and from blinking yellow light appropriate delay in traffic light signals’ IC1 - LM358 op-amp
mode to continuous traffic light mode timings. IC2 - 7404 Hex inverters
IC3, IC6, IC12 - NE555 timer
(during day). In addition, this circuit also IC4 - 74LS93 4-bit binary coun-
controls the automatic switching off/on ter
of the streetlights in the mornings and The circuit IC5 - 74LS164 8-bit serial shift
evenings with flexible settings—defining The circuit has two parts—the first for register
IC7-IC9 - 7476 dual JK master-slave
the morning and evening time. In order generation of control signals for streetlight flip-flop
to prevent false triggering of streetlight and traffic light modes and the second IC10 - 7400 Quad 2-input NAND
circuitry due to some shadow or light on for generation of four sides of traffic light gates
IC11 - 7410 Triple 3-input NAND
the sensor, some time delay is taken into signals. gates
consideration before sending the control The circuit for streetlight and traffic IC13 - 7408 Quad 2-input AND
IC14-IC17 - 7402 Quad 2-input NOR
T1-T6 - SL100 npn transistor
D1-D14 - 1N4007 rectifier diode
LED12 - 3mm red LED
LED8, LED11 - 3mm green LED
LED10, LED13 - 3mm yellow LED
Resistors (all ¼-watt, 5% carbon, unless
stated otherwise):
R1, R2,
R18-R21 - 2.2-kilo-ohm
R3-R5, R8,
R22-R25 - 100-kilo-ohm
R6 - 47-kilo-ohm
R7, R9, R11 - 10-kilo-ohm
R10 - 100-ohm
R26 - 47-ohm
R27 - 22-kilo-ohm
R28 - 6.8-kilo-ohm
VR1, VR2,
VR4-VR7 - 1-mega-ohm preset
VR3 - 100-kilo-ohm preset
VR8 - 10-kilo-ohm preset
C1 - 220µ, 10V electrolytic
C2, C4, C6 - 0.01µ ceramic
C3, C5 - 6.8µ, 10V electrolytic
Fig. 1: Block diagram of traffic and street light controller S1 - Push-to-on switch


Fig. 2: Schematic diagram for the traffic and street light controller


continuous traffic light mode to blinking multivibrator mode) via resistor combi- The evening data (high) from comparator
yellow light mode (at night), and from nation RA1 (=R2+R3+VR1), while in the IC1(a) passes to the streetlight after eight
blinking yellow light mode to continuous morning T2 is cut off and Vcc is applied clock cycles of clock-1. This delay is taken
traffic light mode (in daytime). Thus it to pin 7 of IC3 via RA2 (=R1+R8+VR2). into consideration in order to prevent
decides the mode of operation. In other words, the time period of IC3 is false signals to the streetlight due to some
The circuit for four sides of traffic dependent on RA1 from the evening and shadow or light on the sensor.
lights (Part II) also controls the time al- RA2 from the morning. The delayed high QH output provides
lowed for each side of traffic. It is further The diode pair of D1 and D2 or D4 the control signal for night to the second
classified into continuous traffic light and D5 is used to effectively isolate pin 7 part of circuit and changes continuous
mode (for day) and blinking yellow light of IC3 from being pulled towards ground traffic light mode to blinking yellow light
mode (for night). via the conducting transistor (T2 in the mode. In this way the time at which night
Part I Circuit. The block diagram of evening and T1 in the morning). Time functioning of traffic light starts can be
the circuit for signal generation for street- period of 555 clock in astable mode can adjusted by choosing appropriate time
light and traffic light modes is shown be determined from the following rela- period for clock-1 by adjusting the value
above the dotted line in Fig. 1. A natural tionship: of RA1. Similarly, the time at which day
light-dependent voltage and a reference T = RA (C/1.44) + 2 RB (C/1.44) functioning of traffic light starts (stop
voltage, which determines the evening and where RA = RA1 from the evening and blinking yellow light mode and start
morning times are connected individually RA = RA2 from the morning, while RB continuous traffic light mode) can be
to the two inputs of a comparator. Low = R9 = 10 kilo-ohm and C = C1 = 220 adjusted by RA2.
and high states of the comparator output µF. Clock-1 output of IC3 is connected Low (delayed morning signal) and

decide morning and evening timings, to 4-bit negative-edge-triggered counter high (delayed evening signal) QH outputs
respectively. The output of comparator is 74LS93 (IC4). go to the second part of circuit for se-
properly delayed for obtaining the signals Period of output QD of IC4 is 16 times lecting the mode of traffic light. Table I
for streetlight and traffic light modes. the clock-1 time period. This QD output summarises the functioning of the circuit
In the detailed circuit diagram shown (low for first eight clock-1 cycles and high for signal generation for streetlight and
above the dotted line in Fig. 2, a natural for the next eight clock-1 cycles, and re- traffic light modes.
light-dependent voltage is obtained at the peating thereafter) of IC4 is connected to Part II Circuit. The block diagram
junction of light-dependent resistor LDR1 the clock input of an 8-bit (positive-edge- of the circuit for signal generation for
and resistor R7. Resistor R6 is used in triggered) serial shift register 74LS164 four sides of traffic lights is given below
parallel with LDR1 to limit the variation (IC5). the dotted line in Fig. 1. Here, the 4-bit
of the LDR. Light-dependent voltage and The output of IC1(a) forms the data and 2-bit counters are joined together to
variable reference voltage are connected to (D) input for the shift register. The data form a 6-bit counter. Outputs of the 2-bit
the inverting and non-inverting terminals (D) at QA output is available after eight counter, representing two MSB digits, are
respectively of comparator IC1(a). clock-1 cycles, while that at QH is avail- connected to a decoder that has two con-
In the evening, voltage at the invert- able after 120 clock-1 cycles. Thus morn- trol inputs and four outputs. The decoder
ing terminal of the comparator decreases ing/evening (low/high) data is available at activates one of the four outputs depend-
with time due to the increasing resist- QA and QH outputs after 8 and 120 clock-1 ing upon the input (00 or 01 or 10 or 11)
ance of LDR1. At a particular natural cycles, respectively. Note that the clock-1 of 2-bit counter.
light intensity (determined by variable period itself differs for morning data and Each output of the decoder can drive
reference voltage, which can be adjusted evening data. clock-2 at a different frequency. These four
with the help of preset VR8), it becomes Streetlight indicator (LED1) is con- outputs are connected to the four sides of
less than the voltage at the non-inverting nected to QA output of shift register IC5. traffic lights and select each side one after
terminal. This drives the comparator into
positive saturation region. Similarly, in Table I
the morning the comparator goes into Functional Summary of Part I Circuit
negative saturation region at the same Time Output Output at Output at Activated RA Street Traffic
natural light intensity. In this way, the of IC1(a) QA of IC5 QH of IC5 Resistance Light Light
comparator gives high voltage (logic 1) (LED1) Mode
for evening and low voltage (logic 0) for Evening HIGH LOW LOW RA1 OFF A
morning. After 8 cycles of clock-1 HIGH HIGH LOW RA1 ON A
IC1(b), with the non-inverting ter- (Delay time for streetlight)
minal biased at about 1/3rd Vcc, is simply After 120 cycles of clock-1 HIGH HIGH HIGH RA1 ON B
used as an inverter (though wired as (Delay time for night)
comparator). The inverted output of Morning LOW HIGH HIGH RA2 ON B
comparator IC1(a) is coupled to transistor After 8 cycles of clock-1 LOW LOW HIGH RA2 OFF B
T1 through resistor R4, while its direct (Delay time for streetlight)
output is coupled to transistor T2 via After 120 cycles of clock-1 LOW LOW LOW RA2 OFF A
(Delay time for day)
resistor R5.
It is observed that transistor T1 is Evening HIGH LOW LOW RA1 OFF A
cut off in the evening and Vcc is applied Delay times and evening/morning times are adjustable.
A: Continuous traffic light mode B: Blinking yellow light mode
to pin 7 of timer IC3 (wired in astable


Fig. 3: Actual-size, single-sided PCB for the circuit in Fig. 2

Fig. 4: Component layout for the PCB


another. The time in which the preceding not selected by the decoder, red light will active-‘low’, clear input signal for the 6-bit
4-bit counter counts from 0000 to 1111 be ‘on’. Similar operation will repeat for counter (formed by dual J-K flip-flops
(16 counts) is the time allowed for each each of the selected side in its turn. inside IC7 through IC9) is provided
side of traffic lights. Reset pin of clock-3 and clear pins of from the output of NOR gate E1, whose
First, when the 4-bit counter counts the 6-bit counter are controlled by output one input is connected to QH output
from 0000 to 0001 (two counts), yellow QH from IC5 of Part I. At night, QH will go of shift register IC5 of Part I and the
light of the selected side will turn ‘on’. high and the 6-bit counter will clear, while other input is connected to the output of
From count 0010 to 1101 (12 counts), clock-3 becomes active. As a result, yellow inverter gate N3. The input of inverter
green light will turn ‘on’. Again from lights of the four sides of traffic light will gate N3 is connected to push-to-on reset
1110 to 1111 count (two counts), yellow blink simultaneously. switch S1.
light will turn ‘on’. Meanwhile, in the The detailed circuit diagram is Thus the 6-bit counter will clear when
other three sides of traffic lights that are given below the dotted line in Fig. 2. The QH output is high or the reset button is
pressed. The reset key, when pressed, also
causes counter IC4 and shift register IC5
of Part I to be cleared. QH output of IC5 is
connected to reset pin 4 of clock-3 (IC12).
The output of this clock is connected to
inverter gate N4. Low QH (during day)
activates the 6-bit counter and deactivates
clock-3. Due to this, the output of inverter

gate N4 will be high during the day. This
output is connected to one of the inputs of
four AND gates H1 through H4. Each of
these AND gates is a part of one side of
traffic light circuit.
NAND gates B1, B2, and B3 are con-
nected to the outputs of flip-flops F2, F3,
and F4 of the 6-bit counter. The final
output of this circuit (the output of gate
B2) will be high whenever the first four
bits of the counter are 1110 or 1111 or
0000 or 0001 (14 or 15 or 0 or 1), otherwise
it will be low. Accordingly, inverter N5
output will be low for the above contents
of the counter and high for the remaining
contents (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
or 13).
The output of NAND gate B2 and its
complement (the output of inverter N5)
are connected to NOR gates X2 (=E2,
J2, K2, and M2) and X3 (=E3, J3, K3,
and M3) of the each side of traffic light,
respectively. Other inputs of X2 and X3
Fig. 5: Connections for vehicular traffic lights and pedestrians’ signals NOR gates are common.
The last two flip-flops (F5 and F6) of
the 6-bit counter are connected to four
NAND gates G1 through G4 in such a way
that the output of G1, G2, G3, and G4 will
be low when last two counter bits are 00
(0), 01 (1), 10 (2) and 11 (3), respectively.
For example, when last two bits of counter
contents are 01 (1), only output of NAND
gate G2 will be low and others (G1, G3 and
G4) will be high.
The complements of these four NAND
gate outputs (obtained from collectors of
transistors T3 through T6) are connected
to the four RA resistors of 555 clock-2.
Other terminals of these four resistors
are connected to the anodes of diodes D8,
Fig. 6: The traffic and street light controller D10, D12, and D14, while their cathode


of first side will depend on the output of
Table II
the three-NAND gate circuit (comprising
Daytime Functions of Part II Circuit
gates B1, B2, and B3).
Counter Decoder output Activated RA Glowing LEDs When the 6-bit counter counts from
contents G1 G2 G3 G4 resistance
000000 to 000001, the output of the three-
000000 - 0 1 1 1 RA3 4,6,9,12 (Yellow light of 1st side and
000001 red light of other sides)
NAND gate circuit will be high, which is
000010 - 0 1 1 1 RA3 2,6,9,12 (Green light of 1st side and connected to NOR gate X2 of each side
001101 red light of other sides) and its complement is connected to NOR
001110 - 0 1 1 1 RA3 4,6,9,12 (Yellow light of 1st side and gate X3 of all sides. Due to this, the output
001111 red light of other sides) of NOR gate E3 will be high and those of
010000 - 1 0 1 1 RA4 3,7,9,12 (Yellow light of 2nd side and NOR gates E2 and E4 low. In short, dur-
010001 red light of other sides) ing the count period 000000 to 000001
010010 - 1 0 1 1 RA4 3,5,9,12 (Green light of 2nd side and yellow light of the first side of traffic light
011101 red light of other sides)
and red light of the other three sides will
011110 - 1 0 1 1 RA4 3,7,9,12 (Yellow light of 2nd side and
011111 red light of other sides) be ‘on’.
100000 - 1 1 0 1 RA5 3,6,10,12 (Yellow light of 3rd side and When the counter counts up further
100001 red light of other sides) from 000010 to 001101, the output of the
100010 - 1 1 0 1 RA5 3,6,8,12 (Green light of 3rd side and three-NAND gate circuit will be low and
101101 red light of other sides) its complement will be high. Due to this
101110 - 1 1 0 1 RA5 3,6,10,12 (Yellow light of 3rd side and reason, the output of NOR gate E2 will
101111 red light of other sides) go high and that of NOR gates E3 and
110000 - 1 1 1 0 RA6 3,6,9,13 (Yellow light of 4th side and E4 low. Therefore, when counter contents
110001 red light of other sides)
increment from 000010 to 001101, green
110010 - 1 1 1 0 RA6 3,6,9,11 (Green light of 4th side and
111101 red light of other sides) light of first side and red light of all the
111110 - 1 1 1 0 RA6 3,6,9,13 (Yellow light of 4th side and other sides will be ‘on’.
111111 red light of other sides) Again from 001110 to 001111, the
Note. The two MSB digits determine the side, while the next four digits determine the time for output of three-NAND gate circuit will
which the mentioned LEDs are ‘on’. go high, due to which yellow light of first
side and red light of the other sides will
terminals are all connected to pin 7 of of NOR gates X3(=E3, J3, K3 and M3) turn ‘on’. The time in which the counter
555 clock-2 (IC6). This is analogous to the of each side, because one of the inputs counts from 000000 to 001111 can be
fashion in which RA1 and RA2 have been of AND gates is high in daytime. Low adjusted by RA3. The functioning of the
connected in Part I in the clock-1 circuit. QH (during daytime) forces NOR gates other three sides of the traffic light is
When last 2-bit counter contents are J1, K1, and M1 to work as the inverter similar.
00, RA3 (=R21+R25+VR7) will become gate for the other inputs. Therefore the Daytime functional summary of the
active and other three resistors RA4, RA5, common input of NOR gates X2 and X3 circuit for signal generation for four sides
and RA6 will become inactive. Therefore of sides 1, 2, 3, and 4 will be the same as of traffic light is given in Table II. Change
the time period of clock-2 of the 6-bit coun- the output of NAND gates G1, G2, G3, in RB resistance (VR3+R11) of clock-2,
ter will be dependent upon RA3. and G4, respectively. being common for all sides, will change
Similarly, when last 2-bit counter con- Let us suppose that initially the the time allowed for each side of traffic
tents are 01 or 10 or 11, the time period contents of the 6-bit counter are 000000. light by an equal amount.
of clock-2 will be dependent upon RA4 When the counter counts up from 000000 At night, QH output of IC5 will be
(=R20+R24+VR6), RA5 (=R19+R13+VR5), to 001111, the output of NAND gate high, due to which the 6-bit counter will
and RA6 (=R18+R12+VR4), respectively. G1 will be low and that of other NAND clear and clock-3 will start working. The
The output of NAND gate G1 is con- gates G2, G3, and G4 high. Due to this, output of NOR gates J1, K1, and M1 and
nected to the common input of NOR gates RA3 will be active and the time period of NAND gate G1, and the complement of
E2 and E3 of the first side of traffic light clock-2 of the counter will be according the output of the three-NAND gate cir-
and complements of the outputs of other to RA3. cuit will be low. This forces the output of
three NAND gates G2, G3, and G4 are The high output of NAND gates G2, NOR gate X3 of each side to high state.
connected to one of the inputs of NOR G3, and G4 forces the output from NOR This high output will turn off all the red
gates J1, K1, and M1, respectively. The gates J2, K2, M2 and J3, K3, M3 to low lights and give high signal to one of the
other inputs of these NOR gates are con- state. These low outputs are input to inputs of AND gates H1 through H4. The
nected to QH output of IC5. Red and green NOR gates J4, K4, and M4, due to which other input of these AND gates is con-
lights are connected to the outputs of NOR the output of these gates will be high. It nected to the complement of clock-3, due
gates X4 (=E4, J4, K4, and M4) and X2 means yellow and green lights will be ‘off’ to which all the four sides of yellow light
(=E2, J2, K2, and M2), and yellow light is and red light will be ‘on’ in the remaining will blink.
connected to AND gate of each side of the three sides of the traffic light. The four sides of traffic light signals
traffic light. Due to the low output of NAND gate can be used for driving vehicular traffic
During daytime, the outputs of AND G1 (which is connected to the common signals for straight, right, and left turns
gates (which are connected to yellow input of NOR gates E2 and E3 of first and pedestrian’s signals. Fig. 5 shows
lights) will be the same as the outputs side), the output of NOR gates E2 and E3 one of such possible connections of vehicu-


lar and pedestrian’s signals. The complete where TDay and TNight are delay times in obtained from the shift register.
circuit in model form is shown in Fig. 6. seconds (time interval between switching Also, time-controlling variable resis-
Actual-size, single side PCB for the circuit of comparator IC1(a) and when the traffic tors VR4 through VR7 of Part II can
shown in Fig. 2 is given in Fig. 3 with its light switches its mode) corresponding to be replaced by LDRs with a small light
component layout in Fig. 4. day and night, respectively. source whose light intensity varies accord-
Variable resistors VR4 through VR7 ing to the strength of traffic on each side.
can be calibrated on a time scale by the Implementation of this system requires
Calibration following relationship: traffic-sensing sensors. This system will
Set preset VR8 in such a position that the VR (4,5,6,7) = (1/16)(1.44 T/6.8) 106 – change the time of each side of traffic
output of comparator IC1(a) switches from (122.2) 103 – 2 VR3 light according to the strength of traffic.
one state to the other at a particular in- where T is the time allowed (in seconds) Further, the present circuit being
tensity of natural light. Variable resistors for the side of traffic light in which the only a demonstration model uses LEDs
VR1 and VR2 can be calibrated on a time corresponding variable resistance is con- for lights. To drive high-wattage lights,
scale using the following relationships: nected. one can easily boost the signals used for
VR1 = (1/120) (1.44 TNight/220) 106 – Possible enhancements. Stepper driving the LEDs to operate solidstate or
(122.2) 103 motor-driven wiper can be used for clean- electomechanical relays.
VR2 = (1/120) (1.44 TDay/220) 106 – ing the dust over the light sensor during ❏
(122.2) 103 night time. Control signal for this can be



Lead-Acid Battery
Charger with Active
Power Control
m.k. chandra mouleeswaran

igh-power lead-acid battery char- Constant voltage at a constant current to vary the charging current in accordance
gers usually employ constant results in a very large initial current in with the existing terminal voltage of the
voltage charging method. In a ‘flat’ battery and a very low current in battery.
such chargers the charging is monitored a partially charged battery. To overcome In the circuit presented here the
against the battery terminal voltage. this problem, the charger should be made charging current is adjusted against the

Fig. 1: Schematic diagram of lead-acid battery charger


terminal voltage in such a way following sections:
that any battery with any level 1. The DC power supply section.
of charge can be connected to the 2. The series DC voltage regulation
charger without requiring any section.
manual adjustment. The charg- 3. The battery status indication-cum-
ing voltage is held constant, while charge current regulation section.
an appropriate charging current The DC power supply section. The
range is automatically selected 230V AC mains supply is connected to
at successive different battery a step-down transformer with a second-
terminal voltages. And when the ary rating of 24V AC, 5A through DPDT
battery gets fully charged, the toggle switch S1. When switch S1 is
charger switches over to trickle- in ‘off’ position, the availability of
charge mode. mains supply is indicated by green
Fig. 2: Charging current versus battery terminal voltage The circuit consists of the LED1. When switch S1 is toggled to ‘on’
position, red LED2 glows to indicate
that the charger is ‘on’. The four
15-kilo-ohm resistors R1, R2 and
R3, R4 in the path of LED1 and
LED2, respectively, are rated at
1 watt each.

The output from the secondary
of transformer X1 is rectified by the
bridge rectifier comprising 1N5408
diodes D3 through D6, rated at 800V,
3A. The rectified output is smoothed
by three capacitors C1, C2, and C3
before being applied to the rest of the
circuit. The 4.7-kilo-ohm resistor R6
acts as a bleeder resistance. LED7
indicates that DC is available at the
output of this section.
The series DC voltage regu-
lation section. This section is
configured around power Darlington
transistor TIP142 (T1) that functions
in conjunction with transistor T3
(BC549) and preset VR2 to regulate
Fig. 3: Actual-size, single-sided PCB for battery charger
the output voltage from the DC volt-
age regulator section.
Since zener diode ZD1 conducts
only after the output voltage reaches
15 volts, the output voltage needs to
be adjusted in the vicinity of 15 volts
with the help of preset VR2. When
transistor T3 conducts fully, the base
of transistor T1 is pulled towards
ground via resistor R8 and it stops
conducting after the output voltage
exceeds a specific value.
Transistor T2 (also a BC549)
helps in current limit adjustments.
Low-value, high-wattage resistors
R15 (shunted by R14) through R19
connected in series form a current-
limiting resistor network at the
output of transistor T1. This resistor
network limits the charging cur-
rent depending on the energisation/
de-energisation state of relays RL1
through RL4 that select the cur-
Fig. 4: Component layout for the PCB rent range. The resistors are either


Parts List Table
Semiconductors: LED/Relay Operation and Charging Resistance
IC1 - LM324 quad op-amp Battery LED/Relay status Charging Preset
T1 - TIP142 power Darlington
transistor voltage LED3 LED4 LED5 LED resistance current
T2, T3 - BC549 npn transistor /RL1 /RL2 /RL3 /RL4
T4-T7 - 2N2222A npn transistor <10.5V Off Off Off Off 1 ohm 1A
D1, D2, 10.5V On Off Off Off 0.33 ohm 3A
D7-D11 - 1N4007 rectifier diodes 11.5V On On Off Off 0.53 ohm 2A
D3-D6, D12 - 1N5408 rectifier diodes 12.5V On On On Off 1 ohm 1A
LED1 - Green LED 13.5V On On On On 2 ohms 0.5A*
LED2 - Red LED
LED3 - Bright yellow LED * 0.5A is taken as the trickle charging current.
LED4, LED5 - Bright green LED
LED6, LED7 - Bright red LED
ZD1 - 15V, 1W zener diode
shorted or added by respective relay edand left unattended under the control of
ZD2 - 6.8V, 1W zener diode contacts RY1 through RY4 depending on this charger circuit.
Capacitors: the charging current requirement from
C1, C2 - 2200µF, 40V electrolytic the regulator.
C3 - 1000µF, 40V electrolytic
C4 - 470µF, 25V electrolytic The battery status indication-cum- When the battery is flat with termi-
C5 - 100nF ceramic charge current regulation section. In nal voltage below 10.5 volts, the initial
Resistors (all ¼-watt, ±5% carbon unless this circuit, a quad op-amp LM324 (IC1) charging current is selected at just one
stated otherwise) ampere because a higher initial charging
R1-R4 - 15-kilo-ohm, 1W is wired as a four-stage comparator to
R5 - 2.2-kilo-ohm indicate the battery voltage with the help current may cripple both the battery and
R6 - 4.7-kilo-ohm, 0.5W of four LEDs (LED3 through LED6), while the charger. A higher charging current is
R7, R10, R12 - 1-kilo-ohm at the same time selecting and driving selected only when the battery has reached
R8 - 100-ohm
R9 - 470-ohm corresponding relays to set the charging a safe level of terminal voltage.
R11 - 4.7-kilo-ohm current range. Later, as the battery starts charging
R13 - 47-ohm The 6.8V reference voltage developed and its terminal voltage starts rising, the
R14-R15 - 0.66-ohm, 3W wirewound or charging current is decreased in proper
fusible across zener diode ZD2 is proportion-
R16 - 0.67-ohm, 3W wirewound or ately applied to the inverting terminals steps. Upon reaching the full voltage of 13.5
fusible of comparators A1 through A4, while the volts, the charger switches to the trickle
R17 - 0.20-ohm, 3W wirewound or charge mode with resistor R19 coming into
sampled battery voltage is proportionately
R18 - 0.47-ohm, 3W wirewound or applied to the non-inverting terminals of the charging path. Optionally, one can
fusible all the comparators. switch off the charger on energisation of re-
R19 - 1.0-ohm, 1W wirewound Preset VR3 may be adjusted to obtain lay RL4 by just removing resistor R19 from
R20-R23 - 470-ohm, MFR 0.5% or 0.1%
R24 - 820-ohm, MFR 0.5% or 0.1% the reference voltages as shown in Fig. 1. the circuit. Whenever the terminal voltage
R25 - 10-kilo-ohm, MFR 0.5% or Preset VR4 may be adjusted by applying level of the battery goes low, the charger
0.1% an external fixed voltage of 10.5V, 11.5V, automatically resumes charging.
R26-R28 - 1.2-kilo-ohm Figs 3 and 4 show the actual-size, sin-
R29 - 1.5-kilo-ohm 12.5V, or 13.5V across the battery’s screw
VR1-VR2 - 2.2-kilo-ohm preset terminals, ensuring that the correspond- gle-sided PCB and the component layout,
VR3 - 10-kilo-ohm preset ing LEDs (and relays) light up (energise) respectively, of the charger circuit.
VR4 - 15-kilo-ohm preset in accordance with the table. Note. To ensure proper functioning
RL1-RL4 - 24V DC, 500-ohm relay In the charge characteristic curve of of the circuit, use good-quality relays and
contacts at 10A DC Fig. 2, it can be seen that the terminal precise-value resistors (R14 through R24)
X1 - 230V AC primary to 0-24V, voltage is compared by the comparators with tolerance as mentioned in the Parts
5A secondary transformer List. Connect the metal housing of the
S1 - DPDT toggle switch against the preset values and the charg-
F1 - 750mA cartridge glass fuse ing current is selected accordingly. Thus a charger circuit to the earth line of the AC
battery of any charge level can be connect- mains supply for personal safety. ❏


Amplitude Measurement of
Sub-Microsecond Pulses
anil kumar maini

pulse or a repetitive train of
pulses is one of the most fre-
quently encountered electronic
signals, and the conventional way to
determine its peak amplitude is to have
an oscilloscope display of the waveform.
An oscilloscope that has the required

bandwidth to correctly display sub-
microsecond-wide pulses is an expensive
instrument, and is often beyond the reach
of most electronics enthusiasts, hobby-
ists, and small-scale units. The circuit
presented here allows you to measure the
peak amplitude of a single pulse as well
as of a repetitive train of pulses with a
conventional multimeter.
The circuit is capable of measuring
peak amplitude of pulses as narrow as
100 nanoseconds (ns) up to a maximum of
100V amplitude. There is practically no
limit on the maximum value of the pulse
width. It can also be used to measure the
peak amplitude of a repetitive pulsed
waveform as long as the time interval
between two successive pulses is greater
than 100 microseconds (µs).

The circuit
The pulse under measurement is fed to
the input of a cascaded arrangement of
two unity-gain peak detection stages built
around IC1 and IC2 using high-speed
op-amps AD829, as shown in Fig. 1. The
op-amp has a guaranteed unity-gain band-
width of 120 MHz and a slew rate of 230
V/µs, and it is capable of driving highly
capacitive loads. This makes it ideal for
receiving input pulses as narrow as 100
ns. D1 and D2 (1N914) are high-speed
switching diodes having a response time
of the order of 2 ns to 3 ns.
The input pulse gets stretched to
about 10 µs at the output of the first peak-
detection stage built around IC1 and to
about 100 µs at the output of the second
peak-detection stage built around IC2.
With switch S1 open, the circuit can Fig. 1: Circuit for measuring sub-microsecond pulses


Photograph of author’s prototype

switch causes mum input pulse amplitude of 100 volts,

division of the the ADC analogue input is limited to 5
input voltage
Parts List
by a factor of
10 due to the
IC1, IC2 - AD829 op-amp
arrangement IC3 - LM329 comparator
of resistors R1 IC4 - 74121 monostable multivi-
through R3. brator
Fig. 2: Waveforms at various points of the circuit The peak IC5 - AD0808 analogue-to-digital
amplitude of IC6 - DAC0808 digital-to-ana-
receive input pulses greater than 100 mV the stretched pulse at the output of the logue converter
(which is the same as the reference voltage second peak detector is the same as IC7 - LF356 op-amp
set for comparator IC3, LM319) but less the input pulse peak amplitude. This IC8 (N1-N3) - 74HCT04 hex inverter
IC9 (N4-N7) - 7400 NAND gate
than or equal to 10 volts. output amplitude is halved by resistors
D1, D2 - 1N914 high-speed switching
With switch S1 closed, the input pulse R9 and R10 before feeding the same to diode
amplitude may be anywhere between the analogue input of IC5 (ADC-type ZD1 - 2.5V zener diode
1 volt and 100 volts. The closure of the AD0808). This ensures that for the maxi- Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise):
R1, R2 - 18-kilo-ohm
R3, R16 - 1-kilo-ohm
R4 - 12-kilo-ohm
R5, R6 - 22-kilo-ohm
R7, R8 - 15-kilo-ohm
R9-R12 - 100-kilo-ohm
R13 - 470-ohm
R14 - 220-kilo-ohm
R15, R18, R19,
R24, R25 - 10-kilo-ohm
R17 - 2.2-kilo-ohm
R20, R21 - 2.7-kilo-ohm
R22 - 4.7-kilo-ohm
R23 - 33-kilo-ohm
VR1 - 50-kilo-ohm preset
C1, C2, C4, C5,
C7-C9, C11-C17
C19 - 0.1µF ceramic disk
C3, C10 - 0.001µF ceramic disk
C6 - 0.01µF ceramic disk
C18 - 56 pF ceramic disk
S1, S2 - On/off switch (SPST)
Meter - Multimeter
Fig. 3: Actual-size, single-side PCB layout for the circuit


Every time there is a pulse at the input,
there is a stretched pulse appearing at the
analogue input of the ADC, with its lead-
ing edge coinciding with the leading edge
of the input pulse. Fig. 2 shows waveforms
available at various test points marked A,
B, C, D, and E in the circuit shown in Fig.
1. Also, there is a start-of-conversion pulse
appearing at the relevant input of the
ADC. The conversion starts at the trailing
edge (test point E) of this pulse 1 µs after
the leading edge of the input pulse.
Since the stretched pulse is about
100µs wide, the peak amplitude of the
pulse 1 µs later is almost the same as the
actual peak amplitude. At the same time,
this small delay ensures that the analogue
input is already present on the relevant

input at the start of conversion.
Fig. 4: Component layout for the PCB The latched digital output from the
ADC feeds the corresponding inputs of
volts, which is the maximum amplitude it acts as the start-of-conversion pulse the DAC0808 (IC6) as stated earlier. The
it can accept. for analogue-to-digital converter IC5 output of the DAC, after conversion into
The output of the first peak detector (ADC0808). The NAND logic is used here the proportional voltage by LF356 (IC7),
stage after a division by a factor of 2 by to incorporate the reset feature. is fed to the multimeter (set to appropri-
the arrangement of resistors R11 and The clock generator circuit for IC5 ate DC voltage scale) for measurement of
R12 feeds comparator LM319 (IC3). The is built around 74HCT04 (IC8) to pro- peak pulse amplitude. Potentiometer VR1
leading edge of the pulse output from the vide 1MHz clock. The clock frequency is used for calibration.
comparator coincides with the leading is decided by R24, R25, and C18. The The display holds the peak amplitude
edge of the input pulse. The leading-edge latched digital output from IC5 feeds the of the last pulse until it is reset using
comparator output triggers monoshot corresponding inputs of DAC0808 (IC6). switch S2 or it is updated by another
74121 (IC4) to produce a 1µs pulse (as The DAC output, which is a latched DC pulse at the input. The accompanying
determined by timing components R1 current, is converted into a proportional photograph shows the assembled circuit
7-C10) at its Q-output, with its leading voltage in the current-to-voltage circuit that the author used for performance
edge coinciding with the leading edge of built around op-amp LF356 (IC7). This DC evaluation.
the input pulse. voltage is connected to the multimeter for An actual-size, single-side PCB for the
The monoshot output is passed indication of peak amplitude of the input circuit is shown in Fig. 3 and its component
through an appropriate NAND gate pulse to the circuit. Potentiometer VR1 is layout in Fig. 4. ❏
logic circuit built around 7400 (IC9) and meant for calibration.


Automatic Submersible
Pump controller k.c. bhasin

number of construction projects as 2850 rpm typically. the run capacitor value can be calculated
well as circuit ideas for water-/ The ESP body is made of cast iron using the simple thumb rule (70 µF per
fluid-level control have appeared or stainless steel. For low and medium HP), while the start capacitor value may
in EFY over the years, but so far no dedi- range, one can use 3-phase or split-phase be determined from Table I.
cated project has appeared for automating (also referred to as 2-phase) supply. ESPs Manual operation of ESP motor
the control of submersible water pumps. of 3 HP or higher rating invariably use (Fig. 1). The control panel comprises an
Looking into the demand for such a project 3-phase supply. isolator switch, push-to-on single-/dual-
from readers, we present here a circuit for Let us consider a typical case of 1.5HP section ‘start’ button, push-to-off ‘stop’
button, a triple-pole moulded case circuit
breaker (MCCB) for motor protection with
magnetic trip and resetting facility (with
an adjustable current range of 12 to 25 am-
peres), start and run capacitors, ampere-
meter, voltmeter, neon indicators, etc.
(Note. The MCCBs used for motor con-
trol are termed as motor circuit protectors
(MCPs). These are classified/catalogued
by number of poles, continuous ampere rat-
ing, and magnetic trip range (current). For
details, you may visit Cutler-Hammer’s
Website or contact Bhartia Cuttler-Ham-
mer dealers.)
Fig. 1 shows a simplified control panel
diagram, along with ESP motor wiring.
Fig. 1: Line diagram of control panel for manual operation of ESP motor The ‘start’ pushbutton (green), which is
automating the operation of an electrical ESP with 100mm bore diameter, using normally open, and the ‘stop’ pushbutton
submersible pump (ESP) based on the a split-phase motor. The motor draws a (red), which is normally closed, are in
minimum and the maximum levels in the running current of 10 to 11 amp, while
Motor rating Start capacitor value (µF)
overhead tank (OHT). This circuit can be the starting current is around 2.5 to three in HP 230V AC (working)
interfaced to the existing manual control times the running current value. 275V AC (surge)
panel of an ESP and can also be used as a To obtain a higher initial torque, the 1/6 20-25
standalone system after minor additions. run winding is connected in series with a 1/5 30-40
parallel combination of 120-150µF, 230V 1/4 40-60
AC bipolar paper electrolytic capacitor 1/3 60-80
ESP basics and 72µF, 440V AC run-mode capacitor.
Electrical submersible pumps are single- After two or three seconds of running, 1 120-150
or multiple-stage radial-flow pressure se- when the motor has picked up sufficient 1½ 150-200
ries impeller pumps that are close coupled speed, the start capacitor goes out of the 2 200-250
to the motor for low and medium heads. circuit because of the opening
These find applications in domestic, in- of the centrifugal switch in- Truth Table for relay operation
dustrial, irrigation, air-conditioning, and side the motor, while the run Water level Relay operation (2.5 – 3 sec.) Pump motor
various other systems. capacitor stays in the circuit in tank RL1 (stop) RL2 (Start) operation
The ESPs are classified by the bore permanently. For ESPs that Below
diameter (which generally varies from don’t have an integral cen- low level No Yes Starts
100 mm to 200 mm), horse-power (from trifugal switch arrangement, Above
about 0.5 HP to 40 HP), and discharge rate a dual-section start switch low level
(typically 120 litres per minute for 0.5 HP (explained later) can be used but below
high level No No Remains on
to about 2000 litres per minute for 40 HP). to perform the function of the
These are run at a fixed speed, which is centrifugal switch.
high level Yes No Stops
For the split-phase motor,


Fig. 2: Circuit diagram for automatic control of ESP motor via control panel (Fig. 1)

series with the live or phase line. centrifugal switch opens to take the start ‘off’ button, which interrupts the supply to
The isolator switch is normally in ‘on’ capacitor out of the circuit and only the run the contactor coil.
position. When ‘start’ button is momentar- capacitors (2x36 µF) permanently stay in To interface the control circuit shown
ily pressed, the contactor energises via the series with one of the two stator windings in Fig. 2, we use circled points A and B
closed contacts of ‘off’ button. One of the of the ESP motor. (in parallel with ‘on’ button) and C and D
contact pairs of the contactor is used as In case the ESP is not provided with (formed by disconnecting one of the wires
the hold contact to shunt ‘on’ button and an integral centrifugal switch, a second going to ‘off’ button terminal, i.e. in series
provide a parallel path to the contactor section in ‘start’ button (shown in light with ‘off’ button). Points E and F will be
coil, which thus latches. shade in Fig. 1) can be used to shunt used if the ESP does not have an integral
The supply to the motor gets completed points ‘E’ and ‘F’. Since this switch sec- centrifugal switch.
via the other N/O contacts of the contac- tion has no hold on contacts, the start It may be recalled, by referring to Fig.
tor and the pump motor starts. When the capacitor will go out of circuit as soon as 1 of the project ‘Auto Control for 3-phase
motor gains sufficient speed (around 80 ‘start’ button is released. The motor can be Motor’ published in EFY’s June issue
per cent of the normal running speed), the switched off by momentarily depression of (same EP Vol. 22), that wiring of ‘on’ and
‘off’ buttons of 3-phase (4-wire system)
and split-phase motors are identical.
Hence the control circuit described here
can equally be used for 3-phase motors of
up to about 10 HP. For motors of higher
HP, one must use star-delta type starter

The circuit
As shown in Fig. 2, the 230V AC mains
(tapped from the same points from which
it is fed to the control panel of Fig. 1) is
stepped down to 12V-0-12V by trans-
former X1. The rectified output smoothed
Fig. 3: Actual-size, single-sided PCB layout for Fig. 2 by capacitor C1 is used for operation of


Parts List
IC1, IC2 - NE555 timer
IC3 - CD4049 hex inverter/buffer
T1, T2 - BC548 npn transistor
T3, T4 - BD139/SL100 npn transis-
D1-D4, D7-D9 - 1N4007 rectifier diode
D5, D6 - 1N4001 rectifier diode
ZD1 - 12V, 1W zener diode
Resistors (all ¼-watt ±5% carbon unless stated
R1, R3, R5,
R7, R9, R12,
R14 - 10-kilo-ohm
R2, R6, R11,
R15-R17 - 1-kilo-ohm
Fig. 4: Component layout for the PCB R4, R13 - 220-kilo-ohm
R8, R10 - 330-kilo-ohm
heavy-duty 24V, 250-ohm relays RL1 relay contacts, and also that the two relays R18 - 330-ohm
and RL2 having contact rating of 30 amp. never operate simultaneously. Capacitors:
The relay contacts identified by letters ‘A’ In the case of mains failure, the pump C1 - 470µF, 63V electrolytic
through ‘F’ in Fig. 2 are to be connected to stops if it was already running. When the capacitors
identically marked points in Fig. 1. mains supply resumes, the pump starts C2 - 470µF, 25V electrolytic
Note that point C in Fig. 1 is created only when the water goes below the low capacitors
C3, C7 - 47µ, 25V electrolytic capaci-
by breaking the connection going to point level. In such a situation, you can restart
D on the ‘stop’ switch. We have used relay the motor by manual operation of ‘start’ C4, C6 - 0.01µF ceramic disk
RL1 with single changeover contacts. If button on the control panel. C5, C8 - 10µF, 25V electrolytic
you need higher current rating, use re- The connections for the ammeter and capacitors
lays with double changeover contacts by the voltmeter, not shown in Fig. 1, can be Miscellaneous:
interconnecting N/C, N/O, and pole of one made easily. Connect the voltmeter across X1 - 230V AC primary to 12V-0-
set to the corresponding terminals of the the incoming live and neutral lines, and 12V, 1amp
Secondary transformer
other set. The circuit, except for the relay insert the ammeter in series with the stop L1 - NE2 (neon bulb with inbuilt
drivers, is operated with regulated +12V switch by breaking the live line connection resistor)
supply developed across capacitor C2. after the stop switch. S1 - On/off switch
The +12V supply is fed to the common Transformer, relays, switches, fuse, F1 - 3amp fuse
and neon indicator (with integral resistor) RL1 - 24V, 250-ohm, 1 c/o relay,
probe in the overhead tank/storage tank
30A contact rating
via 10-kilo-ohm resistor R1 and diode are to be mounted on the cabinet.
D9. Low-level and high-level probes are of ESP motor as possible and extend
connected to the input of CMOS inverter connections from tag blocks for relay and
gates N3 and N1, respectively, via 10-kilo- Precautions power supply to the corresponding points,
ohm resistors. The following are the vital points to be borne as explained earlier, using cables of cor-
The final low-level output at pin 10 of in mind during wiring, assembly, and instal- rect ratings.
gate N5 goes high when the water level lation: 5. For probes, use stainless steel
in the overhead/storage tank is below the 1. One-watt resistor R18 should be rods of about 10cm length and 5 to 8 mm
low-level probe. The final high-level output mounted leaving some space below it. diameter with arrangement for screwing
at pin 4 of gate N2 goes high as soon as the 2. Use multistrand insulated copper wires the telephone-type 25/26 SWG wire to be
water touches the high-level probe. of 15-amp rating for taking connections from used for extending the probes’ connections
Both IC1 and IC2 have been config- relay terminals and terminate them on a tag to the circuit. Teflon-insulated wires are,
ured as monostables with a pulse width of block, marking each terminal properly. Simi- however better as they would last longer.
about 2.5 to 3 seconds. This period is found larly, terminate the points to be extended to The joint may be covered by epoxy.
to work optimally for ‘start’ and ‘stop’ the OHT/storage tank on a tag block (TB) us- 6. The probes can be hung from the
switch operation of the manual control ing 25-28SWG wire, marking them suitably. lid of the tank to appropriate levels using
panel. The respective monostables for low 3. Mount the relays inside the body of a the same wire. Make sure that the com-
level (IC2) and high level (IC1) get trig- suitable metallic enclosure. The enclosure mon probe goes up to the bottom of the
gered via transistors T2 and T1 when the should be properly earthed via the earth lead tank/storage tank.
final output at pin 10 of gate N5 or pin 4 of of the mains. Also mount the step-down trans- 7. All the wires from tank to the TBs
gate N2, respectively, goes high. former inside the same enclosure/cabinet. Use in the cabinet should be routed in such a
The connection of reset pins of IC2 and a TB for incoming live, neutral, and earth con- way that they do not interfere with any
IC1 to the outputs of gates N1 and N2, nections from the mains (to be taken from the mains wiring. The length of the wires
respectively, ensures that no false trig- manual control panel of ESP motor). hardly matters as the CMOS gates used
gering of monostables takes place due to 4. After assembly, position the cabi- for terminating the wires from probes
the noise generated during changeover of net as close to the manual control panel have very high input impedance.


Transistor Curve Tracer
a. saravanan

ransistor is the basic component circuit designed may need to be operated single control terminal unlike op-amps.
of all electronic equipment. A good at different conditions (for example, at an
design of electronic circuitry re- ambient temperature of 40°C and collec-
quires proper knowledge of the character- tor current of 10 mA), the manufacturer’s Block diagram
istics and parameters of transistors. Due data is no longer adequate. The manual The transistor curve tracer is built around
to such factors as changes in doping level procedure to draw the characteristics of the ramp generator and the current-to-
of impurities and physical dimensions, a transistor is tedious and cumbersome. voltage converter. The ramp generator
production imperfections, and environ- Further, using the manual procedure, it produces a linear ramp that is applied
mental (ambient temperature, humidity, is not feasible to draw the dynamic char- to the transistor under test either as

etc) changes, no two transistors can have acteristics of a transistor. the collector-emitter voltage (VCE) or the
the same characteristics. The transistor curve tracer circuit base-emitter voltage (VBE). The ramp is
Transistor is an active device and presented here enables one to draw the also used to deflect the electron beam
even a very small change in its param- input and output characteristics of npn horizontally (along x-axis) on the screen of
eters causes a large drift in its operation. transistors in common-emitter configura- the CRO. Similarly, the current-to-voltage
This affects the overall efficiency and the tion on a cathode ray oscilloscope (CRO). converter converts either the collector
reliability of an equipment. Hence for an It can be constructed and calibrated by the current (IC) or the base current (IB) into a
efficient, reliable, and trouble-free design/ designer himself. proportional voltage that is used to deflect
operation of the electronic equipment, the The circuit can be upgraded to the electron beam vertically (along y-axis)
designer must know the characteristics draw the characteristics of both npn on the screen.
and parameters of each transistor used in and pnp transistors, field effect tran- The signal conditioning and switching
the equipment. sistors (FETs), metal-oxide semicon- circuits, along with the ramp generator
The manufacturer provides general- ductor field effect transistors (MOS- and current-to-voltage converter, make
ised family characteristics of transistors FETs), unijunction transistors (UJTs), a complete curve tracer for the input and
bearing specific part numbers. These silicon-controlled rectifiers (SCRs), output characteristics of an npn transis-
characteristics are drawn under specific TRIACs, etc. In general, it can be up- tor.
test conditions such as 25oC temperature graded for any two- or three-terminal Output characteristics (Fig. 1).
and 10mA collector current IC. But as the analogue electronic device that has a The ramp and clock generator generates
a linear ramp and 1 kHz clock pulses. The
ramp is amplified by the ramp buffer am-
plifier to 0 to 5 volts. This amplified ramp
is applied to the collector of the transistor
under test as the collector-emitter volt-
age (VCE) through the current-to-voltage
The current-to-voltage converter gives
an output voltage proportional to collector
current IC that is applied to the CRO to
Fig. 1: Block diagram for tracing transistor output characteristics
deflect the beam in y-axis. The 0-5V ramp
output is applied to the CRO to deflect the
beam in x-axis. Hence we can trace the
output characteristics of the transistor
with the collector-emitter voltage (VCE) on
x-axis and IC on y-axis.
To trace the output characteristic
graph for various base current (IB) val-
ues, the generator’s clock output fed to
the counter is incremented for each clock
pulse. The count sequence is 000, 001,
010, 011, 100, 101, 110, and 111 (0 to
Fig. 2: Block diagram for tracing transistor input characteristics 7 decimal). After 111, the counter resets


Fig. 3: Circuit diagram of transistor curve tracer

automatically to 000 and the sequence input characteristics of the transistor with 35V capacitors act as filters to eliminate
repeats. The lower three bits of the coun- VBE on x-axis and IB on y-axis. ripples and provide unregulated DC out-
ter are applied to the base-current control To trace the input characteristics put voltage.
circuit. graph for various VCE values, the clock The unregulated dual DC voltage is
The base-current control circuit sets output of the generator is fed to the coun- converted by three-terminal ICs AN7812
IB in eight discrete 100µA steps, i.e. 0 µA, ter and switching circuit. The counter and AN7912 into ±12V regulated power
100 µA, 200 µA, 300 µA, 400 µA, 500 µA, counts the number of pulses in the binary supply. (Note. Connect 0.1µF decoupling
600 µA, and 700 µA. Adjust the step width form. Q0 output of the counter is used as capacitors between the supply terminals
(100 µA) using a potentiometer such that the collector-emitter voltage control that and ground of every IC in order to sup-
the output characteristics of various npn toggles VCE with 0 volt and 10 volts for press unwanted noise signals in the sup-
transistors with various current gains (β) every clock pulse. Thus we can trace the ply voltage.)
are traced/accommodated. input characteristics for VCE = 0 volt and 2. The ramp and clock generator
Input characteristics (Fig. 2). VCE = 10 volts. section. The ramp and clock generator
Here again, the ramp and clock generator uses a constant current source (LM334)
generates a linear ramp and 1kHz clock and a capacitor, in conjunction with timer
pulses. The ramp is amplified by the ramp The circuit NE555 (IC3) wired as an astable multi-
buffer amplifier to 0-5V. This amplified The transistor curve tracer circuit (Fig. 3) vibrator, to generate a linear ramp. The
ramp is attenuated and amplified as re- comprises power supply, ramp and clock control terminal of timer 555 (pin 5) is
quired to get 0-1V ramp and applied to generator, ramp buffer and offset null, held at a reference voltage of 5 volts by a
the base of the transistor under test as current-to-voltage converter, counter, base zener diode so that the upper threshold
the base-emitter voltage (VBE) through the current control, and switching sections. (VUTP) is at 5 volts and the lower threshold
current-to-voltage converter. 1. The power supply section. The (VLTP) at 2.5 volts.
The current-to-voltage converter gives circuit operates on ±12V regulated power The output current from IC LM334
an output voltage proportional to base supply. The input AC mains supply is can be controlled with the help of poten-
current IB that is applied to the CRO to stepped down by transformer X1 to deliver tiometer VR1. This current charges the
deflect the beam in y-axis. The 0-1V ramp a secondary supply of 15-0-15V AC at 1 capacitor linearly in the form of a linear
output is applied to the CRO to deflect the ampere. The output of the transformer is ramp. As soon as the voltage across the
beam in x-axis. Hence we can trace the rectified by a bridge rectifier. The 1000µF, capacitor exceeds the upper threshold volt-


age (VUTP), the output of timer 555 changes
its state and goes low. This activates the
discharge terminal (pin 7) of timer 555
and hence the capacitor quickly discharges
through the timer.
As the voltage across the capacitor
drops below the lower threshold voltage
(VLTP), the output of timer 555 changes
its state and goes high to disable the dis-
charge terminal and further discharging of
capacitor stops. Once again the capacitor
gets charged linearly through the constant
current source and the sequence repeats.
Thus the potential across the capacitor is
a positive linear ramp between 2.5 volts
and 5 volts. The ramp frequency can be
controlled by varying the charging current
using potentiometer VR1. (EFY Lab note.
During lab testing, we used AD590 tem-
perature transducer in place of LM334H

as the constant current source, and the
method of using the same is shown in Fig.
3 within dotted lines.)
3. The ramp buffer and offset null
section. Since the output impedance of
the ramp source is very high, we cannot
load it. Also, a DC offset voltage equal to
the lower threshold voltage (VLPT = 2.5V)
is present in the ramp output. In order
Fig. 4: Actual-size, single-side PCB layout for transistor curver tracer to nullify the offset voltage of the ramp
and to source the current from the ramp,
use a buffer amplifier. An op-amp in non-
inverting amplifier configuration is used
to achieve this function.
As the input impedance of the non-
inverting amplifier is very high, it will not
load the ramp source. Also, it is possible to
nullify the DC offset voltage present in the
ramp output with the help of ramp offset
adjustment preset VR2.
By adjusting feedback preset VR3, the
output of ramp buffer can be set to deliver
a linear 0-5V ramp. This output is used as
VCE for the transistor under test to source
the collector current (IC).
To draw the input characteristics of
the transistor, the base-emitter voltage
(VBE) should be varied linearly. For this we
require a linear 0-1V ramp with sufficient
current sourcing capability. In order to
achieve this, a ramp attenuator (voltage
divider) and an amplifier are used.
The 0-5V ramp output of ramp buffer
is attenuated by the potential divider
network (comprising resistors R4 and R5)
followed by an op-amp (IC5) connected in
non-inverting configuration. The gain of
the op-amp can be adjusted using preset
VR5 connected in the feedback path.
In order to nullify the offset voltage of
Fig. 5: Component layout for the PCB


the op-amp, balancing preset VR4 is con- the transistor output characteristics and where Vout = 10xI
nected between the offset null terminals base current IB in the transistor input Hence, there is a potential drop of 10 mV
of the op-amp. The output of the op-amp characteristics), the current component per mA of the current through the circuit.
is 0-1V linear ramp, which is used as the is to be converted into a proportional We cannot apply this small floating potential
base-emitter voltage (VBE) for sourcing voltage. directly to the CRO for a significant deflection.
the base current (IB) of the transistor The current to be measured is passed Therefore we use a differential amplifier to
under test. through series resistor R7 of 10-ohm, have an output voltage with respect to the
4. The current-to-voltage convert- ±1% MFR (metal film resistor). Potential ground that is proportional to the current
er section. The spot on the CRO screen drop Vout across the resistor, according to though the circuit. The differential amplifier
is deflected in proportion to the potential the Ohm’s law, is proportional to current has a gain of 100 that can be fine-tuned with
applied to its input. Hence in order to I through it and is given by the following the help of gain adjust preset VR7 in the feed-
deflect the beam along y-axis, which is relationship: back path.
the current axis (collector current IC in V = IR The current-to-voltage converter converts
the current of 1 mA into a potential difference
of 1 volt that can be applied to the CRO to
deflect the beam in vertical axis. In order to
nullify the offset voltage of the op-amp, connect
a balancing preset to the offset null terminals
of the op-amp.
5. The counter section. The base cur-
rent (IB) is to be changed in discrete steps
for every ramp to enable the transistor’s
output characteristics for various IB values
simultaneously on the CRO screen.
In the counter circuit, the output of
timer 555 (IC3) from pin 3 is a square wave
that intimates the end of ramp. This output
is used as clock pulse for the counter wired
around CMOS binary/decade, up/down IC
MC14029B or CD4029B (IC7).
IC7 is wired as a 3-bit binary up-
counter so that the output of the counter
(Q2, Q1, and Q0) is incremented by bi-
nary 1 for every clock pulse. The count
sequence is 000, 010, 011, 100, 101, 110,
and 111, i.e. 0 through 7 decimal. After
111, the counter is automatically reset to
000, and once again the count sequence
repeats. Hence we get eight discrete logic
levels, and accordingly we can set the
base current (IB) using a base current
control circuit.
Similarly, to draw the input charac-
teristics of the transistor under test for
various collector-emitter voltage (VCE)
values, the collector-emitter voltage (VCE)
is to be changed for each ramp. The least
significant bit (Q0) of the counter is used
to toggle the collector-emitter voltage (VCE)
from 0 volt to 10 volts. Thus we can view
the input characteristics of the transistor
for VCE= 0 volt to VCE= 10 volts simultane-
ously on the screen of the CRO.
6. The base current control
section. This section receives the
input from the counter circuit and
varies the base current (I B ) of the
transistor. The output of counter IC7
in series with a high-value resistor
acts as the constant current source.
Fig. 6: Waveforms at various points in the circuit


resistors in parallel to have 25-kilo-ohm and 6 of timer 555 (ramp output). A lin-
resistor. This method has been shown in ear ramp with positive slope is observed
Fig 3.) on the screen of the CRO. By adjusting
7. The switching section. Certain frequency control potentiometer VR1, set
circuits are common in tracing both the the frequency of the ramp at 1 kHz (refer
output characteristics and input charac- waveform 1 in Fig. 6).
teristics. The ramp and clock generator, 3. Connect the CRO to the output of
ramp buffer and amplifier, and counter ramp buffer. Adjust preset VR2 to nul-
circuits are retained at their places for lify the DC offset voltage in the output of
both output and input characteristics. But ramp buffer. Adjust preset VR3 to set the
to trace the output characteristics the cur- amplitude of ramp output to 0 to 5 volts
Fig. 7: Actual output curves on CRO (shown rent-to-voltage converter is to be connected (refer waveform 2 in Fig. 6).
without retrace) in the collector of the transistor under test 4. Connect CRO at the output of ramp
and to trace the input characteristics it is attenuator and amplifier. Adjust preset
to the connected in the base of the transis- VR4 to nullify the DC offset voltage in the
tor (refer Figs 1 and 2 for output and input output of ramp buffer. Adjust preset VR5
characteristics, respectively). to set the amplitude of ramp output to 0 to
To have minimum complexity, the 1 volt (refer waveform 3 in Fig. 6).
collector and the base circuits of the 5. Calibrate the current-to-voltage
transistor are switched suitably using a converter by connecting a 1-kilo-ohm. 1%

changeover switch on the front panel. The metal film resistor between the collector
switching details are obvious from the and emitter terminals of the transistor
circuit diagram in Fig. 3. under test. Connect the output of the
current-to-voltage converter to a CRO.
By observing the ramp waveform on
Fig. 8: Actual input curves on CRO (shown
Construction the screen of the CRO, nullify DC offset
without retrace) Wire the circuit on a 2.5mm, IC-type gen- voltage using preset VR6 and adjust the
eral-purpose printed circuit board (PCB) amplitude of the observed ramp wave-
as shown in Fig. 3. The use of glass-epoxy form to 0-5 volts with the help of preset
The high-level outputs of the counter PCB is recommended. An actual-size, VR7. Calibrate the current-to-voltage
are fairly constant at 10 volts. single-side PCB for the circuit is shown in converter to convert 1 mA of current into
When we connect a resistor of 100 Fig. 4, with its component layout shown 1 volt (refer waveform 4 in Fig. 6). Then
kilo-ohms in series with Q0 output of the in Fig. 5. check the clock output by connecting the
counter, it supplies a constant current of Carefully solder all the components CRO to pin 3 of timer 555 (refer waveform
100 µA during its logic 1 state. Similarly, and use sockets for ICs. All range resis- 5 in Fig. 6).
when we connect a resistor of 50 kilo-ohms tors used should be stable, close-tolerance 6. Verify the outputs of the counter by
(two 100 kilo-ohm resistors in parallel) type (preferably MFRs). Preferably use using a dual-trace oscilloscope. Connect
in series with Q1 output of the counter, linear-type IB SET potentiometer and one input channel of the CRO with clock
it supplies a constant current of 200 µA mount it on the front panel of the instru- pulses at pin 3 of IC3 and the outputs at
during its logic 1 state. Using 25-kilo-ohm ment. Enclose the circuit board, power pins 6, 11, and 14 of counter IC7 to the
resistor in series with Q2 output we can transformer, and other circuit compo- other input of the CRO sequentially (refer
get a constant current source of 400 µA. nents in a metal box having approximate waveforms 5, 6, 7, and 8 in Fig. 6).
When more than one current source dimensions of 22x17x7.5 cm. Extend 7. Short-circuit the base-emitter ter-
are connected in parallel, the result is input and output leads to the correspond- minals of the transistor under test. Select
similar to having a current source equal to ing points in the circuit. Terminate the input/output characteristics switch S2 to
the sum of individual source currents. outputs for connection to the CRO in output characteristics position and con-
If we use the base current (IB) setting BNC(F) connectors. nect the CRO to the output of the current-
as it is for a transistor with large current to-voltage converter. By adjusting IB SET
amplification factor (α), its collector cur- potentiometer VR8 on the front panel of
rent (IC) gets saturated for much smaller Calibration the instrument, check proper operation
values of IB and only two or three traces After construction, check the circuit of the base-current section by observing
appear on the screen of the CRO. To get thoroughly for short circuits, breaks, stair-case ramp of varying amplitude on
the maximum number of traces, reduce and open circuits on the PCB. After the screen of the CRO (refer waveform 9
the base current by increasing the series switching on the instrument, let it in Fig. 6).
resistor values through IB SET potentiom- warm up for a few minutes before
eter VR8. With the help of VR8, we can commencing with the calibration.
adjust the base current in incremental Calibration procedure of the circuit is Operation
steps from 10 µA to 100 µA. as follows: After calibration, the instrument is ready
(Note. Connect two 100-kilo-ohm re- 1. Check and ensure ±12V regu- for use to trace the input and output
sistors in parallel to get 50-kilo-ohm resis- lated voltage with respect to ground. characteristics of npn transistors. Follow
tor. Similarly, connect four 100-kilo-ohm 2. Connect a CRO to shorted pins 2 the operating procedure given below every


Parts List corresponding inputs of the CRO. characteristics position.
2. Plug in the AC cord of both the CRO 16. Set the volts/div control of x-axis to
IC1 - 7812, +12V regulator and the transistor curve tracer and switch 0.1 volt/div and observe the input charac-
IC2 - 7912, –12V regulator them on. teristics likewise.
IC3 - NE555 timer 3. Set the CRO inputs to ground. Figs 7 and 8 show a typical transis-
IC4, IC6 - µA741 op-amp (IC OP-07 4. Allow warm-up time of at least 10 tor’s output and input characteristics,
op-amps can be used
in place of µA741 with minutes for the circuit components to get respectively, on the CRO screen (without
advantage) stabilised. retrace).
IC7 - MC14029B/CD4039 binary/ 5. Set the CRO for X-Y mode of opera-
decade up-/down-counter tion.
IC8 - LM334H/AD590 tempera-
ture sensor
6. Adjust intensity and focus controls Conclusion
D1-D4 - 1N4007 rectifier diode to get a sharp spot on the screen of the To draw the characteristics of pnp tran-
ZD1 - 5V zener diode CRO. sistors, insert an inverter circuit in the
Resistors (all ¼-watt, ±1% MFR, unless stated 7. Set the volts/div control of x-axis to ramp path of collector-emitter voltage
otherwise): 0.5 volt/div. VCE and base-emitter voltage VBE, and
R1, R5, R6, 8. Set the volts/div scale of y-axis to invert the output of the current-to-voltage
R8, R9 - 1-kilo-ohm 2 volts/div. converter.
R2, R4 - 22-kilo-ohm
R7 - 10-ohm 9. Adjust the position controls of the By using a potential divider and
R3, R10, R11 CRO to position the spot on the left bot- buffer amplifier circuit in place of the
(A,B), R12(A-D) - 100-kilo-ohm tom of the screen ((0,0) position in the base-current control circuit you can
VR1 - 1-kilo-ohm preset graph). draw the characteristics of FETs and
VR2 - 2.2-kilo-ohm preset
VR3, VR4,
10. Set the inputs for DC coupling to MOSFETs.
VR5, VR6 - 10-kilo-ohm preset the CRO. To trace the forward characteristics
VR7 - 150-kilo-ohm preset 11. Connect the transistor whose of diodes, connect the anode of the diode
VR8 - 1-mega-ohm potmeter characteristics are to be traced to the to the base terminal and the cathode to
Capacitors: transistor curve tracer, ensuring correct the emitter terminal. Set the transistor
C1-C4, C9 - 0.1µF ceramic disk pin configuration. curve tracer to draw input characteristics,
C5, C6 - 1000µF, 35V electrolytic 12. Set the selector switch for input/ and the CRO screen displays the forward
C7, C8 - 100µF, 25V electrolytic
C10 - 0.01µF ceramic disk output characteristics to the output char- characteristics of the diode.
acteristics position. Similarly, with simple add-on circuits
X1 - 230V AC primary to 13. Release the CRO inputs from to the motherboard, you can draw the
15V-0-15V AC, 500mA ground and switch them over to connect characteristics of UJTs, SCRs, TRIACs,
secondary transformer inputs. etc.
S1 - On/off switch 14. Now view the output characteris- Thin and faint retrace lines visible
S2 - DPDT switch
tics of the transistor. Fine-tune the IB set along with the characteristic traces can
potentiometer to get eight traces on the be removed by connecting a retrace blank-
time to get correct traces of input and out- screen of the CRO. ing circuit to the Z-mod input of the CRO.
put characteristics of the transistor: 15. To trace input characteristics of Almost all CROs exceeding 30MHz band-
1. Connect the x-axis and y-axis BNC the transistor, change the input/output width have the Z-mod input facility.
pins of the transistor curve tracer to the characteristics selector switch to the input ❏


Tripping Sequence
r.g. thiagraj kumar and s. ramaswamy

n applications like power stations and events that might have occurred during
continuous process control plants, a the period when the clock was low. Hence The circuit
protection system is used to trip the events themselves are used as clock IC1 and IC2 (CD4043) Quad NOR RS
faulty systems to prevent damages and signals in this circuit. flip-flops in Fig. 2 are used to capture and
ensure the overall safety of the personnel Fig. 1 shows the block diagram of the store the information pertaining to the

and machinery. But this often results in tripping sequence recorder-cum-indicator. tripping of individual units. Reset pins of
multiple or cascade tripping of a number The inputs derived from auxiliary relay all the eight flip-flops and sub-parallel en-
of subunits. contacts (N/O) of subunits or push-to-on able (PE) pin 1 of BCD up-/down-counter
Looking at all the tripped units doesn’t switches are latched by RS flip-flops when CD4510 (IC3) are returned to ground via
reveal the cause of failure. It is therefore the corresponding subunits trip, causing 10-kilo-ohm resistor R22, while set pins
very important to determine the sequence the following four actions: of all RS flip-flops are returned to ground
of events that have occurred in order to 1. The latch outputs are ORed to acti- via individual 10-kilo-ohm resistors R14
exactly trace out the cause of failure and vate audio alarm. through R21.
revive the system with minimal loss of 2. The latch outputs are differentiated Initially, all the eight Q outputs of
time. individually and then ORed to provide IC1 and IC2 are at logic 0. The auxiliary
The circuit presented here stores the clock pulses to the counter to increment relay contacts of the subunits, which are
tripping sequence in a system with up to the output of the counter that is initially depicted here by push-to-on switches S1
eight units/blocks. It uses an auxiliary relay preset at 1 (decimal). through S8, connect the set terminal of the
contact point in each unit that closes when- 3. Each individual latch output acti- corresponding stage of RS flip-flop to +12V
ever tripping of the corresponding unit oc- vates the associated latch/decoder/driver whenever tripping of a specific subunit
curs. Such contact points can be identified and 7-segment display set to display the occurs. This makes the output of the as-
easily, especially in systems using program- number held at the output of the counter, sociated flip-flop go high. Thus whenever
mable logic controllers (PLCs). which, in fact, indicates the total number
This circuit records tripping of up to of trips that have taken place since the Parts List
eight units and displays the order in which last presetting. Semiconductors:
they tripped. A clock circuit, however fast, 4. LEDs associated with each of the IC1, IC2 - CD4043 quad NOR RS latch
IC3 - CD4510 BCD up-/down-
cannot be employed in this circuit because latch, decoder, and driver sets remain lit counter
the clock period itself will be a limiting to indicate the readiness of the sets to re- IC4-IC11 - CD4511 BCD-to-7-segment
factor for sensing the incidence of fault. ceive the tripping input. LEDs associated latch/decoder/driver
Besides, it may also mask a number of with the tripped unit go off. T1-T11 - BC547 npn transistor
T12-T19 - BC557 pnp transistor
D1-D16 - 1N4007 rectifier diode
DIS1-DIS8 - LT543 common-cathode
7-segment display
Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise):
R13-R38 - 10-kilo-ohm
R12, R39-R46 - 1-kilo-ohm
R47-R102 - 470-ohm
C1-C8 - 0.01µF ceramic disk
S1-S8 - Push-to-on switch or relay
contacts (N/O)
S9 - Push-to-on switch
PZ1 - Piezobuzzer
- 12V, 500mA power supply
Fig. 1: Block diagram of tripping sequence recorder-cum-indicator


Fig. 2: Schematic diagram of tripping sequence recorder-cum-indicator

a sequence of tripping of subunits

occurs, the corresponding outputs
(1Q to 8Q) go high in the order
of the tripping of the associated
All the eight Q outputs are
connected to the correspond-
ing latch-enable inputs of BCD
latch-cum-decoder-driver ICs
(CD4511). These Q outputs
are also ORed using diodes D1
through D8 to activate an audible
alarm and also routed to a set of
differentiator networks (compris-
ing capacitors C1 through C8 and
resistors R2 through R9).
A differentiator provides a
sharp pulse corresponding to the
tripping of a subunit. All such
differentiated pulses are ORed
via diodes D9 through D16 and
coupled to the counter stage Fig. 3: Actual-size, single-side PCB of the main control portion of tripping sequence controller-cum-
formed by IC3 (CD4510, a syn- indicator circuit


data input. Simultaneously, the
buzzer goes on to sound an audible
alarm, indicating the emergency
situation at the plant.
The differentiator formed
by C5 and R6 responds to the
low-to-high transition of 5Q and
generates a short pulse. This pulse
passes through diode D13 and
transistors T2 and T3 and reaches
clock pin of counter IC3. The
counter counts up and its output
becomes 0010 (decimal 2).
As mentioned earlier, all the
display units other than E have
the drive signal on segments a, b,
g, e, and c now but are off because
of the missing common-cathode
drive. When the next subunit H
trips, output 8Q experiences a

low-to-high transition and the cor-
Fig. 4: Component layout for Fig. 3
responding display (DIS8) shows
digit ‘2’. The above sequence of
operation holds true for any further
subunit tripping—with the displayed
digit incrementing by one for each se-
quential tripping.
In the prototype, LEDs D17 through
D24 were fixed below the corresponding
7-segment displays pertaining to subunits
A through H to provide a visual indication
that these units are ready to respond to
a tripping.
The circuit works satisfactorily with
twisted-pair wires of length up to 5 me-
tres. In electrically noisy environments,
the length of the cable has to be reduced
Fig. 5: Actual-size, single-side PCB for Fig. 6: Component layout for Fig. 5 or a shielded twisted-pair cable can be
latch decoder/driver and display circuit of used.
one subunit
outputs go high. An actual-size, single-side PCB layout
chronous up-/down-counter with preset) However, the common-cathode drive for the main control portion of the tripping
after amplification and pulse shaping by is absent in all the 7-segment displays sequence recorder-cum-indicator circuit is
transistor amplifier stages built around because driver transistors T4 through T11 shown in Fig. 3 and its component layout
transistors T2 and T3. These pulses serve are cut off due to the low outputs of all RS in Fig. 4. The PCB layout for the indica-
as clock to count the number of trippings flip-flops and hence the displays are blank. tor set comprising IC4, DIS1, transistors
that occurred after a reset. At the same time, the low outputs of all T4 and T12, LED1, etc is shown in Fig. 5
RS flip-flops (1Q through 8Q) forward bias and its component layout in Fig. 6. The
pnp transistors T12 through T19 associ- indicator set of Fig. 5 can be connected
Operation ated with LED1 through LED8 of each of to the main PCB of Fig. 3 using Bergstrip
Let us assume that three units, say, E, H, the displays. As a result, all these LEDs type SIP (single-inline-pin) connectors as
and A (fifth, eighth, and first), tripped in glow, indicating no tripping. per requirements.
that order following a fault. Now when unit E trips, output 5Q This tripping sequence recorder-cum-
When the system is reset (before of RS flip-flop IC2 goes high to provide indicator circuit can also be used in quiz
any tripping), the outputs of all RS flip- the base drive to common-cathode drive games to decide the order in which the
flops (1Q through 8Q) are low. This LE* transistor T8. This, in turn, activates DIS5 teams responded to a common question.
active-low makes latches IC4 through (fifth from left in Fig. 2) to display ‘1’, indi- For this, provide push-to-on switches on
IC11 transparent and as the counter is cating that unit E tripped first. The corre- the tables of individual teams and a mas-
preset to 1 (since P1 input is high while sponding LED5 goes off as transistor T16 ter reset to the quiz master. Modify the
P2, P3, and P4 are low) with the help is cut off. Also, latch IC8 is disabled due alarm circuit suitably with a retriggerable
of switch S9, all the latches hold that to logic 1 on its pin 5 and therefore it does monostable stage so that the audible alarm
‘1’ and their decoded ‘b’ and ‘c’ segment not respond to further changes in its BCD stops after a short interval. ❏


Electronic Starter
for Single-Phase motors
sarat chandra das

novel single-phase electronic hence relay RL2 latches even if switch The contact rating for relays RL1 and
starter circuit meant for 0.5HP S1 is subsequently opened. The other N/O RL2 should be 5 amperes, while contact
and 1HP motors is presented here. contacts RL2(b) of relay RL2, on energisa- ratings of relay RL3 should be 10 to 15
It incorporates both overload and short- tion, connect the voltage developed across amperes.
circuit protections. A special current- capacitor C2 to relay RL3, which thus Transformer X1 can be wound using
sensing device has been added in this energises and completes the supply to the any suitable size CRGO core. (One can
starter to sense the current being drawn motor, as long as current passing through use a burntout transformer core as well.)

by the motor. primary of transformer X1 is within limits The primary comprises 30 to 31 turns for
If the motor jams due to bearing fail- (for a 1hp motor). use with 1HP motor and additional eight
ure or defect in the pump or any other When the current drawn by motor turns, if you are using a 0.5HP motor.
reason, it would draw much higher current exceeds the limit (approx. 5A), the volt- Fuses F1 and F2 are kit-kat type. The ‘on’
than its normal rated current. This will age developed across the secondary of pushbutton is normally-‘off’ type, while
be sensed by the current-sensing device, transformer X1 is sufficient to energise ‘off’ pushbutton S2 is of normally-‘on’
which will trip the circuit and protect the relay RL1 and trip the supply to relays type. Capacitors C1 and C2, apart from
motor. Some other reasons for the motor RL2 and RL3, which was passing via the smoothing the rectified output, provide
drawing higher current are as follows: N/C contact of relay RL1. As a result, the necessary delay during energisation and
(a) Windings damaged or short-circuit supply to the motor also trips. de-energisation of relays. Diodes across
between them.
(b) Shorting of motor terminals by
(c) Under voltage or single phasing
occuring in the mains supply source (nor-
mally, a 440V AC, 3-phase with neutral
four-wire system).
The main components used in the
circuit comprise a specially wound sensing
transformer X1, another locally available
step-down transformer X2, single-change-
over relay RL1, two double-changeover
relays (RL2 and RL3), and other discrete
components shown in the figure. The
mains supply to the motor is routed in
series with the primary of transformer
X1 via normally-open contacts of relay
RL3. The primary of transformer X1 is
connected in the neutral line.
To switch on the supply to the mo-
tor, switch S1 is to be pressed momen-
tarily, which causes the supply path
to the primary of transformer X2 to
be completed via N/C contacts of relay
RL1. Relay RL2 gets energised due to
the DC voltage developed across capac-
itor C2 via the bridge rectifier. Once
the relay energises, its N/O contacts
RL2(a) provide a short across switch
S1 and supply to the primary of trans-
former X2 becomes continuous, and


relays are used for protection as free- Users are therefore compelled to use circuit given here, which works very reli-
wheeling diodes. 10-amp rated circuit breaker for such mo- ably. Parts used in this circuit are easily
Starters for 0.5HP and 1HP motors tors. A mechanical starter or auto starter available in most of the local markets.
are not easily available in the market. would turn out to be costlier than the

Readers’ comments: tral and ground are shorted together and

 I would like to have some doubts thus the body of the gadget becomes ‘live’
cleared: and one could get a shock on touching the
1. In the circuit, AC supply was in- gadget. One must use a 3-pin plug and
dicated by phase and neutral. If phase socket system in which live and neutral
and neutral are changed, what will be conventions are adhered to as per ISI speci-
the result? fications/Electricity Act and rules.)
2. What is the suggested core size of 2. The suggested core size is shown in
transformer X1 tested by the author? Fig. 1. I suggest the use of a 220V/6V-0-
3. Can we use ferrite core transformer Fig. 1: Suggested ‘El’ core dimensions 6V, 500mA to 1A rating step-down trans-
instead of CRGO core? former core used in battery eliminators
J.V.K. Naidu do not make sure as to which is phase and (new or burnt), which is available in the
Eluru neutral in the socket (when using a 2-pin local market.
The author, Sarat Chandra Das, plug top). Nothing happens when phase 3. Ferrite core is better than CRGO,
replies: and neutral are interchanged. but it is costlier and not easily available
1. The mains supply is taken from 3-phase, (EFY: Nothing untoward happens as in the local market, while CRGO core is
4-wire system. When you are using any do- long as supply in the gadget is first routed easily available. Technically, turns ratio
mestic appliance such as fan, TV, etc, you to a transformer. In some appliances neu- in winding will change.

Modem ‘On’/‘Off’ Indicator

t.k. Hareendran

ere is an interesting, low com-
ponent-count, and easy-to-build
electronic circuit for the Internet
surfers. This circuit, using two LEDs,
indicates the modem status, i.e. whether
it is in use or not.
The incoming telephone line termi-
nating on a master phone is shunted by a
metal oxide varistor.
The circuit is configured around the
popular timer chip NE555, which is wired
as an astable multivibrator. When power
is applied to the circuit, the astable starts
working as usual. However, LEDs D2 and
D3 connected to its output pin 3 would not
glow as transistor T1 is in off condition and D1 and D2 start blinking at the bist- wiper of preset VR1 very slowly until the
hence resistor R4’s bottom end is hanging able IC1’s frequency determined by the LEDs start blinking. Memorise the wiper
in high impedance state. values of resistors R1 and R2 and capaci- position and fix it in this position using a
However, when the modem is work- tor C1. good-quality glue/compound.
ing, voltage drop across preset VR1 A 9V, 0.5A AC adapter can be used After construction, fix the complete
illuminates the LED inside the opto- to power the circuit. Finally, one minor circuit in a suitable and attractive cabinet
coupler (IC2). As a result, transistor adjustment is required for successful op- with one LED in its front panel. Keep
T1 gets sufficient base-bias through eration of the gadget. For this, first switch the whole unit near the modem and fit
activated transistor inside opto-coupler on the supply to the gadget and then another LED near the master telephone
via resistor R3. Consequently, LEDs switch ‘on’ the modem. Now adjust the with the label ‘Modem in Use’.


Touch-Select Audio source
saravanan j.

ften you need to connect out- pact that it can be fixed within the audio causes selection of CD outputs being con-
put from more than one source power amplifier cabinet and can use the nected to the power amplifier input, which
(preamplifier) such as tape same power supply source. is indicated by lighting of LED1.
recorder/player and CD (compact The circuit uses just two CMOS ICs When touch-plate S2 is touched, the
disc) player to audio power amplifier. and a few other componenets. The ICs outputs of gates N1 and N2 toggle. That
This needs disconnecting/connecting used are MC14551/CD4551 (quad 2-chan- is, IC2 pin 3 is pulled ‘low’ while its pin 4
wires when you want to change the nel analogue multiplexer) and CD4011 goes ‘high’. This results in selection of tape
source, which is quite cumbersome (quad 2-input NAND gate). When touch- recorder outputs being connected to the
and irritating. plate S1 is touched (its two plates are input of power amplifier. This is indicated
Here is a circuit that helps you choose to be bridged using a fingertip), gate N1 by lighting of LED2.

between two stereo sources by simple output (IC1, pin 3) goes high while the Pin 9 is the control pin of IC2. In the
touch of your hand. This circuit is so com- output of gate N2 at pin 4 goes low. This circuit, the state of multiplexer switches
is shown with pin 9 ‘high’
(CD source selected). When
pin 9 is pulled ‘low’, all the
switches within the multi-
plexer change over to the
alternate position to select
tape player as source.
EFY Lab note. Al-
though one can connect pin
7 (VEE) of IC2 to ground,
but for operation with
preamplifier signals going
above and below ground
level, one must connect it
to a negative voltage (say,
–1V to –1.5V) to avoid

Precision attenuator
with digital control
anantha narayan

hen instruments are designed, ator with digital control is described here, lar OP07 op-amp with ultra-low offset
an analogue front-end is es- where digital control can be a remote dip in the inverting configuration. A dual,
sential. Further, as most equip- switch, or CMOS logic outputs of a decade 4-channel CMOS analogue multiplexer
ment have digital or microcontroller in- counter (having binary equivalent weight switch CD4052 enables the change in
terface, the analogue circuit needs to have of 1, 2, 4, and 8, respectively), or I/O port gain. An innovative feature of the circuit
digital control/access. of a microcontroller like 80C31. is that the ‘on’ resistance (around 100
The circuit of a programmable attenu- The heart of this circuit is the popu- ohms) of CD4052 switch is bypassed so


(b) Output
The output can be connected to a
7107/7135-based DPM or any other ana-
logue-to-digital converter or op-amp stage.
Use a buffer at the output if the output has to
be loaded by a load less than 1 meg-ohm.
Use an inverting buffer if input leads
have to have polarity where ground is the
inverting terminal. (For details, see next
(c) CD4052 CMOS switch
The on-resistance (100-ohm approx.)
comes in series with the op-amp output
source resistance, which produces no er

Truth Table (Control input VS attenuation)

X,Y (ON-switch (2) (1) Gain
Pair) B A (Attenuation)
that no error is introduced by its use. have to add some stages (IC4 and IC5 X0,Y0 0 0 1/1000
X1,Y1 0 1 1/100
Resistors R1 to R6 used in the cir- circuitry shown in precision amplifier
X2,Y2 1 0 1/10
cuit should be of 0.1 per cent tolerance, circuit described later). X3,Y3 1 1 1
50 ppm (parts per million) if you use The OP07 pinout is based on stand-
3½-digit DPM, i.e. ±1999 counts (approx. ard single op-amp 741. Any other ror at output.
11 bits). But for 4½-digit DPM (approx. op-amp like CA3140, TLO71, or LF351 can Caution. The circuit does not isolate,
14 bits), you may need to have trimpots be used but with offset errors in excess of 1 it only attenuates. When high voltage is
(e.g. replace 1k-ohm resistor R6 by a fixed per cent, which is not tolerable in precision present at its input, do not touch any part
900-ohm resistor in series with a 200-ohm instrumentation. of the circuit.
trimpot) to replace R3, R4, R5, and R6 The OP07 has equivalent ICs like (d) Digital control options
gain selection resistors for proper calibra- µA741 and LM607 having ultra-low (i) A and B can be controlled by I/O
tion to required accuracy. However, for offset voltage (<100µV), low input bias port of a microcontroller like 80C31 so that
testing or trials, use 1 per cent 100ppm current (<10nA), and high input imped- the controller can control gain.
MFR resistors. The expected errors will ance (>100M), which are the key require- (ii) A and B can be given to counters
be around 1 per cent. ments for a good instrumentation op-amp like 4029/4518 to scroll gain digitally.
To keep parts count (hence cost) to for use with DC inputs. (iii) A and B can be connected to DIP
a minimum, the common or ground is The following design considerations switch.
used as the positive input terminal and should be kept in mind: (iv) A and B can be connected to a
one end of resistor R1 as the negative. (a) Input: 500V max thumbwheel switch.
This is so because the op-amp inverts Since ¼W resistors can withstand Notes. 1. Digital input logic 0 is 0V and
the polarity as it is used in inverting up to 250V, resistors R1 and R2 in series logic 1 is 5V.
configuration. This does not matter as are used for 1 meg-ohm with 500V (max) 2. All resistors are metal film resistors
the equipment will be isolated by the input limit. These resistors additionally (MFR) with 1% tolerance, unless specified
power supply transformer and all po- limit the input current as well. Diodes D1 otherwise.
larities are relative. In case you want and D2 clamp the voltage across input of 3. C2 and C3 are ceramic disk capaci-
the common to be the negative, you will op-amp to ±0.5V, thereby protecting the tors of 0.1µF = 100nF value.

Precision Amplifier
with Digital Control
anantha narayan

his circuit is similar to the pre- in this configuration, which is useful for The gain selection resistors R3
ceding circuit of the attenuator. signal conditioning of low output of trans- to R6 can be selected by the user and
Gain of up to 100 can be achieved ducers in millivolt range. can be anywhere from 1 kilo-ohm to 1


meg-ohm. Trimpots can be used for obtain- resistance of value less than 1 meg- pin-compatible) in place of OP07 and use ±7.5V
ing any value of gain required by the user. ohm will cause an error. An alterna- instead of ±5V supply.
The resistor values shown in the circuit tive is to make R9=R10=1 meg-ohm Eight steps for gain or attenuation can
are for decade gains suitable for an autor- and do away with IC4, though this be added by using two CD4051 and pin
anging DPM. may not be an ideal method. 6 inhibit on CD4051/52. More steps can
Resistor R1 and capacitor C1 reduce be added by cascading many CD4051, or
ripple in the input and also snub tran- Truth Table (Control Input vs Gain) CD4052, or CD4053 ICs, as pin 6 works
sients. Zeners Z1 and Z2 limit the input to X,Y (On-switch (2) (1) Gain like a chip select.
±4.7V, while the input current is limited Pair) B A (Av.) Some extended applications of this
by resistor R1. Capacitors C2 and C3 are X0,Y0 0 0 1/10 circuit are given below.
X1,Y1 0 1 1
the power supply decoupling capacitors. 1. Error correction in transducer am-
X2,Y2 1 0 10
Op-amp IC1 is used to increase the X3,Y3 1 1 100 plifiers by correcting gain.
input impedance so that very low inputs 2. Autoranging in DMM.
are not loaded on measurement. The user 3. Sensor selection or input type selec-
can terminate the inputs with resistance Gains greater than 100 may not be practi- tion in process control.
of his choice (such as 10 meg-ohm or 1 cal because even at gain value of 100 itself, 4. Digitally preset power supplies or
meg-ohm) to avoid floating of the inputs a 100µV offset will work out to be around 10 electronic loads.
when no measurement is being made. mV at the output (100µV x 100). This can be 5. Programmable precision mV or mA
IC5 is used as an inverting buffer trimmed using the offset null option in the sources.
to restore polarity of the input while OP07, connecting a trimpot between pins 1 6. PC or microcontroller or microproc-
IC4 is used as buffer at the output and 8, and connecting wiper to +5V supply essor based instruments.
of CD4052, because loading it by rails. For better performance, use ICL7650 (not 7. Data loggers and scanners.

Random Number Generator

Based Game
k. udhaya kumaran

his electronic game is simulation ‘run’ position, all segments of 7-segment tinue advancing and the final display
of one-arm bandit game. Elec- displays (DIS1 through DIS3) will light is unpredictable. Thus the final number
tronics hobbyists will find it very up. On turning toggle switch S1 from ‘run’ displayed in DIS1 through DIS3 is of
interesting. When toggle switch S1 is in to ‘stop’ position, displayed digits will con- random nature. The speed with which


the number in 7-segment display keeps
changing on flipping switch S1 from ‘run’
to ‘stop’ condition slowly decays before
stopping with a random number display.
To play this game, one has to obtain
three identical numbers in displays DIS1
through DIS3. The contestant would
score 1 (one) point if he manages to get a
final display of ‘000’, 2 points for getting
‘111’ display, 3 points for ‘222’,… and so
on—up to ten points for ‘999’. He should
try to score maximum possible points in
fixed numbers of attempts (say, 20 to 25
Apart from using this circuit as
a game for entertainment, one can use
it as random number generator for
any other application as well. The
decay time with the given component
values is around 15 seconds before the
display could stop at a final random
The circuit comprises clock oscillator
built around NE555 timer IC4, three- timing capacitor C3 to change the op- by 1 for every positive clock transition.
stage clock pulse counter built using three erating frequency of the astable from Reset pin 15 of all counter ICs is held low
CD4033 ICs (IC1 to IC3), and three 7-seg- around 35 kHz to around 65 Hz. Now through resistor R25. Thus reset facility
ment LED displays (DIS1 to DIS3). capacitor C1 slowly starts charging as is not used in this circuit.
In clock oscillator circuit, NE555 it is connected in the discharge path Due to persistence of vision, one can-
timer IC4 is used in a similar way as a of the timing capacitors C3 and C4. not distinguish 0-9 counting in DIS1 to
free-running astable multivibrator, the The clock frequency of IC4 gradually DIS3 when the clock frequency is high.
only difference being the additional ca- reduces and after 15 seconds, when All 7-segment displays appear to show
pacitor C1 introduced between pin No. 7 capacitor C1 is sufficiently charged, digit 8, while the red LED1 remains lit
of IC4 and junction of resistors R22 and the oscillating frequency gradually continuously, indicating clock counter is
R24. When toggle switch S1 is in ‘run’ po- drops and finally it stops oscillating. in running condition.
sition, both terminals of capacitor C1 are Thus, pin 3 of IC4 becomes low. On sliding toggle switch S1 from
shorted by switch S1 and timer IC4 works Second part of the circuit comprises ‘run’ to ‘stop’ position, the counting
as a free-running astable multivibrator. three cascaded ICs, IC1 through IC3 speed of individual digits falls immedi-
The operating frequency is in the vicin- (CD4033 decade upcounter cum 7-seg- ately due to the clock frequency chang-
ity of 35 kHz, determined by the value of ment decoder). In conjunction with three ing to around 65 Hz. Now, the counting
timing components. 7-segment displays (DIS1 to DIS3), these speed will be 65 Hz for DIS3, 6.5 Hz for
When toggle switch S1 is flipped form a 3-digit clock counter. The clock DIS2, and 0.6 Hz for DIS1. This speed of
from ‘run’ to ‘stop’ position, capacitor counting speed is dependant upon the individual digit counting slowly decays,
C1 is introduced in the discharge path clock pulse frequency of IC4. It is con- until the counter stops and LED1 stops
of pin No. 7 of IC4 and junction of re- nected to clock input pin 1 of IC1 while blinking, and the final count (random
sistors R22 and R24. At the same time, chip enable pin 2 of IC1 to IC3 are held numbers) are displayed in DIS1, DIS2,
capacitor C4 comes in parallel with low. Thus all clock counter ICs advance and DIS3.

9-Line Telephone Sharer

Dhurjati Sinha

his circuit is able to handle nine distance of 100m from each other, for re- line is to be shared by more members re-
independent telephones (using a ceiving and making outgoing calls, while siding in different rooms/apartments.
single telephone line pair) located maintaining conversation secrecy. This Normally, if one connects nine phones
at nine different locations, say, up to a circuit is useful when a single telephone in parallel, ring signals are heard in all


ceiver CM8870 (IC3) outputs
code ‘0001’, which is fed to the
4-bit BCD-to-10 line decimal
decoder IC4 (CD4028). The
output of IC4 at its output
pin 14 (Q1) goes high and
switches on the SCR (TH-1)
and associated relay RL1.
Relay RL1, in turn, connects,
via its N/O contacts, the 50Hz
extension ring signal, derived
from the 230V AC mains, to
the line of telephone ‘1’. This
ring signal is available to tele-
phone ‘1’ only, because half of
the signal is blocked by diode
D1 and DIAC1 (which do not
conduct below 35 volts).
As soon as phone ‘1’ is
lifted, the ring current in-

creases and voltage drop
across R28 (220-ohm, 1/2W
resistor) increases and oper-
ates opto-coupler IC5 (MCT-
2E). This in turn resets timer
IC2 causing:
(a) interruption of the
power supply for processing
circuitry as well as the ring
signal relays RL1 through
RL9, and
(b) removal of loop re-
sistance R16, via the second
contact of relay RL10.
As a result, the telephone
line voltage shoots up to 48V,
DIAC1 and diode D1 con-
nected in series with phone
1 conduct within a few mil-
liseconds, and phone 1 comes
into operation. The telephone
exchange does not interpret
the nine telephones (it is also possible that extension number, say, ‘1’, within 10 sec-
this as break in off-hook condition, since
the phones will not work due to higher onds. (In case the calling subscriber fails
some delay margin is set at exchange.
load), and out of nine persons eight will to dial the required extension number
When phone ‘1’ is busy, the other
find that the call is not for them. Further, within 10 seconds, the line will be discon-
eight phones will not work, since line
one can overhear others’ conversation, nected automatically.) Also, if the dialed
voltage will again drop to 10V and the
which is not desirable. To overcome these extension phone is not lifted within 10
other diacs will not conduct. Thus conver-
problems, the circuit given here proves seconds, the ring-back tone will cease.
sation secrecy will be maintained.
beneficial, as the ring is heard only in the The ring signal on the main phone
The other extensions also work in a
desired extension, say, extension number line is detected by opto-coupler MCT-
similar manner when another extension
‘1’. 2E (IC1), which in turn activates the
number is dialed and its corresponding
For making use of this facility, the 10-second ‘on timer’, formed by IC2 (555),
relay energises to extend the 50Hz ring
calling subscriber is required to ini- and energises relay RL10 (6V, 100-ohm,
to another extension.
tially dial the normal phone number 2 C/O). One of the ‘N/O’ contacts of the
The 24V, 50Hz ring signal derived
of the called subscriber. When the call relay has been used to connect +6V rail
from transformer X1 is sufficient for
is established, no ring-back tone is to the processing circuitry and the other
working with phones of Beetel and ITI
heard by the calling party. The call- has been used to provide 220-ohm loop re-
make, but for Pretel and some other
ing subscriber has then to press the sistance to de-energise the ringer relay in
makes, it may be necessary to increase
asterik (*) button on the telephone to telephone exchange, to cut off the ring.
the ring voltage to about 30 volts or even
activate the tone mode (if the phone When the caller dials the extension
normally works in dial mode) and dial number (say, ‘1’) in tone mode, tone re-


Electronic Card Lock System
priyank mudgal

his circuit of electronic card lock 3, 21, and 22 (address pins A0 through result, transistor T1 conducts and ex-
system is much simpler and A3), makes corresponding output go logic tends positive supply to the collectors of
cheaper than other similar circuits high, thus turning on the appliance transistors T2 through T5. Then, depend-
that have appeared in earlier issues of through relay contacts. Up to 15 appli- ing upon the holes blocked/punched in
EFY. ances can be switched on/off (one at a the inserted card, any combination of
The circuit is configured around time). Output Q0 (pin 11) can be used emitters of transistors T2 through T5
an addressable 1 of 16 demultiplexer for visual indication, to show that circuit turns logic ‘high’ (transistors’ output
CD4514B (IC1). Any number in binary is active. corresponding to blocked LDRs only goes
form, when available at input pins 2, A 40W bulb illuminates LDR1 ‘high’). These outputs connected to address
input pins A0 through A3 of IC1

Table I
Appliance LDR2 LDR3 LDR4 LDR5
1 - * * *
2 * - * *
3 - - * *
4 * * - *
5 - * - *
6 * - - *
7 - - - *
8 * * * -
9 - * * -
10 * - * -
11 - - * -
12 * * - -
13 - * - -
14 * - - -
15 - - - -
- Blocked hole corresponding to selected
binary address.
* Punched holes corresponding to LDR posi-
tion on card

switch on the corresponding appliance

to LDR5 (one out of 15).
constantly. The card used should be of opaque
This pulls plastic. It should be able to withstand
down bases some heat from the bulb, even though the
of transis- appliance remains ‘on’ only for the period
tors T1 for which the card is in the slot.
through T5 The card has a triangular notch that
to ground. shows correct orientation/direction of
LDR1 en- insertion of card and prevents false op-
sures that card is prop- eration. LDRs can be placed in a line, or
erly inserted into the randomly, to increase security.
card slot. The order in which holes should be
When the card is punched for each appliance is given in
correctly inserted, it Table I. Two illustrations, one each for
covers the hole/open- card-2 and card-5, are shown in the ac-
ing for LDR1 and thus companying figures. An elevation and
blocks the light from plan/top view of the gadget is also shown
falling on LDR1. As a in the figures.


Pulsed Operation
of a CW Laser Diode
dr. alika khare

ere a simple low-cost technique pulsed discharges, optical communication, digital storage oscilloscope and it is also
for converting a CW laser di- fibre-optic sensors, image processing, connected to the PC for getting a hard
ode at 670 nm wavelength to etc—where one is required to check the copy.
pulsed laser up to a frequency of 500 kHz frequency response of the detection system Up to a frequency of around 20 kHz,
is presented. or optical simulation of an optical source the threshold voltage for laser oscillations
A low-power pulsed radiation source or local networking using optical fibre is around 2.4V. For frequencies greater
is very important for any laboratory in- cable. Fast-speed LED offers the solu- than 20 kHz, the threshold for laser

volved in optical pulsed systems—laser, tion for such requirements, but because oscillations depends on the operating
of very low power and large frequency and is higher than 2.4V. The
divergence, its use remains behaviour of laser pulses up to 10 kHz is
limited. On the other hand, nearly similar. Laser output at a typical
a pulsed diode laser offers frequency of 2 kHz is shown in Fig. 3, at
a very good solution for this various voltages (2.6V, 3.4V, and 4V). The
problem. input waveform ‘A’ is shown at the bottom
Commercial systems are of the figure.
usually expensive. However, For a driving pulse of about 3V (which
a CW diode laser operating is the normal operating voltage for CW
at 670 nm can easily be operation), the laser pulse becomes flat
pulsed up to a frequency of after a delay of approximately 40 µs (time
500kHz with low-cost technique, using taken to build up the laser oscillations
a function generator and an inexpensive to its maximum amplitude). Above 3V,
push-pull amplifier interface circuit. The probably population inversion is devel-
block diagram of the system is shown in oped much above threshold, before the
Fig. 1. laser oscillations build up into the cavity,
A 3mW CW diode laser at 670 nm and so we observe the sharp peak in laser
with voltage and current rating of 3V output (for more details, refer Laser Fun-
at 100mA, respectively, is used. The damentals book by W. T. Silfvast, pub-
source (a function generator) is capable of lished by Cambridge University Press),
delivering square pulses of 3V amplitude, exponentially decaying to a steadystate
which are amplified by a complementary value with a time constant depending on
symmetry push-pull circuit shown in Fig. the initial peak intensity and the carrier
2. life time in the excited state. After the
The output of the
amplifier is
connected to
the diode la-
ser for pulsed
The laser is
focused onto
a photodiode
with 50-ohm
resistor (Fig.
1). The out-
put of pho-
todiode is
displayed on


input pulse is over, the oscillations die shows the laser waveforms at 50 kHz, with the DC component in it. Beyond
down within 5 µs. 100 kHz, 200 kHz, 300 kHz, and 500 500 kHz, it is difficult to observe laser
Therefore above 3V, up to a fre- kHz, respectively. oscillations even at voltages higher
quency of 10 kHz, the laser is operated All these pulses were recorded at than 4V.
in quasi CW mode. In the frequency around 4V. In this range of frequencies, Lab note. Tests conducted at EFY
range of 10 kHz to 50 kHz, the laser the duration for which voltage is on/off using laser diode of laser torch (rated for
output keeps on increasing, even dur- is of the order of less than 5 µs, and so <5mW) with identical inputs at 2 kHz did
ing the flat portion of the input current the driving pulses switch off before the not show any marked departure of output
pulse, and falls down to zero during the termination of laser oscillations. There- waveform (square wave) from the input
off period of the driving pulse. Fig. 4 fore the laser output shows a modulation square wave.

Generation of 1-sec. pulses

spaced 5-Sec. Apart
Praveen shanker

his circuit using a dual-timer timer 1 in NE556 triggers by itself. C6. This action results in momentar-
NE556 can produce 1Hz pulses The output of the first timer is con- ily pulling down of pin 8 towards the
spaced 5 seconds apart, either nected to trigger pin 8 of second timer, ground potential, i.e. ‘low’. (Otherwise
manually or automatically. IC NE556 which, in turn, is connected to a potential pin 8 is at 1/2 Vcc and triggers at/below
comprises two independent NE555 timers divider comprising resistors R4 and R5. 1/3 Vcc level.) When the second timer is
in a single package. It is used to produce Resistor R1, preset VR1, resistor R2, triggered at the trailing edge of 5-second
pulse, it generates a 1-second
wide pulse.
When switch S2 is on posi-
tion ‘b’, switch S1 is discon-
nected, while pin 6 is connected
to pin 2. When capacitor C2
is charged, it is discharged
through pin 2 until it reaches
1/3Vcc potential, at which it is
retriggered since trigger pin 6 is
also connected here. Thus timer
1 is retriggered after every
5-second period (corresponding
to 0.2Hz frequency). The second
timer is triggered as before to
produce a 1-second pulse in
synchronism with the trailing
edge of 5-second pulse.
two separate pulses of different pulse preset VR2, and capacitors C2 and C5 are This circuit is important wherever a
widths, where one pulse initiates the acti- the components determining time period. pulse is needed at regular intervals; for
vation of the second pulse. Presets VR1 and VR2 permit trimming of instance, in ‘Versatile Digital Frequency
The first half of the NE556 is wired the 5-second and 1-second pulse width of Counter Cum Clock’ construction project
for 5-second pulse output. When slide respective sections. published in EFY Oct. ’97 (or Electronics
switch S2 is in position ‘a’, the first When switch S2 is in position ‘a’ Projects Vol. 18), one may use this circuit
timer is set for manual operation, i.e. and switch S1 is pressed momentarily, in place of CD4060-based circuit. For
by pressing switch S1 momentarily the output at pin 5 goes high for about the digital clock function, however, pin 8
you can generate a single pulse of 5-sec- 5 seconds. The trailing (falling) edge of and 12 are to be shorted after removal of
ond duration. When switch S2 is kept in this 5-second pulse is used to trigger 0.1µF capacitor and 10-kilo-ohm resistors
‘b’ position, i.e. pins 6 and 2 are shorted, the second timer via 0.1µF capacitor R4 and R5.


Cutout with Timer
dr d.k. kaushik

his inexpensive circuit can be rupted for another one minute, and so tor T3 remains cut off (with its collector
connected to an air-conditioner/ on, until the mains supply comes within remaining high) until the mains supply
fridge or to any other sophisticated limits (>180V AC). The AC mains supply falls below the lower limit, causing its
electrical appliance for its protection. is resumed to appliance only when it is collector voltage to fall. The collector of
Generally, costly voltage stabilisers are above the lower limit. transistor T3 is connected to the trigger
used with such appliances for maintain- When the input AC mains increases point (pin 2) of IC1.

ing constant AC voltage. However, due to beyond 270 volts, preset VR1 is adjusted When the input is more than the lower
fluctuations in AC mains supply, a regular such that transistor T1 conducts and limit, pin 2 of IC1 is nearly at +Vcc. In
‘click’ sound in the relays is heard. The relay RL1 energises and resistance this condition the output of IC1 is low,
frequent energisation/de-energisation of R8 gets connected in series with the relay RL2 is de-energised and power is
the relays leads to electrical noise and electrical appliance. This 10-kilo-ohm, supplied to the appliance through the N/C
shortening of the life of electrical appli- 20W resistor produces a voltage drop terminals of relay RL2.
ances and the relay/stabiliser itself. The of approximately 200V, with the fridge If the mains supply is less than the
costly yet fault-prone stabiliser may be as load. lower limit, pin 2 of IC1 becomes momen-
replaced by this inexpensive high-low The value and wattage of resistor R8 tarily low (nearly ground potential) and
cutout circuit with timer. may be suitably chosen according to the thus the output of IC1 changes state from
The circuit is so designed that relay electrical appliance to be used. It is ‘low’ to ‘high’, resulting in energisation

of relay RL2.
As a result, power
to the load/appli-
ance is cut off.
Now, capacitor
C2 starts charg-
ing through resis-
tor R6 and preset
VR3. When the
capacitor charges
to (2/3)Vcc, IC1
changes state
from ‘high’ to
‘low’. The value
RL1 gets energised when the mains practically observed that after con- of preset VR3 may be so adjusted that it
voltage is above 270V. This causes re- tinuous use, the value of resistor R8 takes about one minute (or as desired) to
sistor R8 to be inserted in series with changes with time, due to heating. So charge capacitor C1 to (2/3)Vcc. Relay is
the load and thereby dropping most of adjustment of preset VR1 is needed two now de-energised and the power is sup-
the voltage across it and limiting the to three times in the beginning. But once plied to the appliance if the mains supply
current through the appliance to a very it attains a constant value, no further voltage has risen above the lower cut-off
low value. adjustment is required. This is the only limit, otherwise the next cycle repeats
If the input AC mains is less than 180 adjustment required in the beginning, automatically.
volts or so, the low-voltage cut-off circuit which is done using a variac. One additional advantage of this
interrupts the supply to the electrical ap- Further, the base voltage of transis- circuit is that both relays are de-
pliance due to energisation of relay RL2. tor T2 is adjusted with the help of pre-set energised when the input AC mains
After a preset time delay of one minute VR2 so that it conducts up to the lower voltage lies within the specified limit
(adjustable), it automatically tries again. limit of the input supply and cuts off and the normal supply is extended to
If the input AC mains supply is still low, when the input supply is less than this the appliance via the N/C contacts of
the power to the appliance is again inter- limit (say, 180V). As a result, transis- both relays.


heat detector
Sukant Kumar Behara

his circuit uses a complementary To test the working of the circuit, bring conducting. Simultaneously, transistor
pair comprising npn metallic tran- a burning matchstick close to transistor T2 also conducts because its base is con-
sistor T1 (BC109) and pnp germa- T1 (BC109), which causes the resistance nected to the collector of transistor T1. As
nium transistor T2 (AC188) to detect heat of its emitter-collector junction to go low a result, relay RL1 energises and switches
(due to outbreak of fire, etc) in the vicinity due to a rise in temperature and it starts on the siren circuit to produce loud sound
and energise a siren. The collector of tran- of a firebrigade siren.
Pin Designation Sound Effect
sistor T1 is connected to the base of tran- Lab note. We have added a
sistor T2, while the collector of transistor table to enable readers to obtain
No Connection No Connection Police Siren
T2 is connected to relay RL1. +3V