Hi3520D V200 H.

264 CODEC Processor

Brief Data Sheet

Issue 01

Date 2014-09-21
Copyright © HiSilicon Technologies Co., Ltd. 2014. All rights reserved.
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 Hi3520D V200
Hi3520D V200 H.264 CODEC Processor
Key Specifications
Processor Core video inputs in total)
z ARM Cortex A9@max. 660 MHz − 144 MHz BT.656 2-channel byte-interleaved mode for
− 32 KB L1 I-cache and 32 KB L1 D-cache each 8-bit interface (4x720p@30 fps real-time video
− 128 KB L2 cache inputs in total)
− 148.5 MHz BT.1120 Y/C interleaved mode for each 8-
Video Encoding and Decoding Protocols
bit interface (2x720p@30 fps or 2x1080p@30 fps real-
z H.264 baseline/main/high profile level 4.2 time video inputs in total)
z MJPEG/JPEG baseline encoding/decoding − 148.5 MHz BT.1120 standard mode for the 16-bit
Video Encoding and Decoding interface (1x1080p@60 fps real-time video inputs in
z H.264&JPEG multi-stream encoding and decoding: total)
− 8xD1@6 fps+8xCIF@6 fps encoding+8xD1@6 fps z Video output interfaces
decoding+JPEG snapshot D1@16 fps − HDMI 1.3+VGA+CVBSx2 outputs. The HDMI and
− 8xCIF@30 fps +8xQCIF@30 fps VGA outputs share the same source
encoding+8xCIF@30 fps decoding +JPEG snapshot − Maximum resolution 1080p@60 fps for HDMI or
D1@16 fps VGA
− 4xD1@30 fps+4xCIF@30 fps encoding+4xD1@30 fps − Three graphics layers in RGB1555 or RGB8888 format,
decoding+ JPEG snapshot D1@8 fps with the maximum resolution of 1920x1080
− 4x960H@30 fps+4xCIF@30 fps − One hardware cursor layer in RGB1555 or RGB8888
encoding+1x960H@30 fps decoding+ JPEG snapshot format, with the maximum resolution of 128x128
960H@8 fps − CVBS0 video layer can be used as the HD PIP layer
− 8xD1@30 fps H.264 decoding Audio Interfaces
− 4x720p@30 fps H.264 decoding z Two I2S interfaces
z CBR or VBR ranging from 16 kbit/s to 40 Mbit/s − One input interface
z Encoding frame rate ranging from 1 fps to 60 fps − One output interface
z ROI encoding
Ethernet Port
z Generating and encoding gray-scale video from color
video z One Ethernet port
− Integrated FE PHY
Intelligent Video Analysis
− MDI at the PHY layer or RMII at the MAC layer
z Integrated intelligent analysis acceleration engine, − 10/100 Mbit/s
supporting motion detection, boundary security, and video − full-duplex or half-duplex mode
diagnosis z Integrated FE PHY
Video and Graphic Processing Peripheral Interfaces
z Video pre- and post-processing, including de-interlacing, z Two SATA 2.5 interfaces
image enhancement, edge enhancement, and 3D denoising − PM
z Anti-flicker processing on output videos and graphics − eSATA
z 1/8x to 16x video scaling z Four UART interfaces
z 1/2x to 2x graphic scaling z One SPI, supporting two CSs
z Up to eight OSDs for video before encoding z One IR interface, one I2C interface, and multiple GPIO
z Alpha blending of video layers and graphics layers for interfaces
video displaying z Two USB 2.0 host ports, supporting hub
Audio Encoding and Decoding Memory Interfaces
z Hard-wired audio encoder, supporting ADPCM, G.711, z One 16-bit DDR2/DDR3 SDRAM controller interface
and G.726 encoding − Maximum frequency of 660 MHz
z Software encoding and decoding complying with various − ODT
standards − Maximum capacity of 512 MB
Security Engine − Automatic power consumption control
z AES, DES, and 3DES encryption and decryption z SPI NOR flash interfaces
− 1-, 2-, or 4-bit SPI NOR flash interfaces
Video Interfaces
− Two CSs
z Video input interfaces
− Maximum capacity of 32 MB for each CS
− Two 8-bit interfaces or one 16-bit interface
z Built-in 4 KB BOOTROM and 10 KB SRAM
− 108 MHz/144 MHz BT.656 4-channel byte-interleaved
mode for each 8-bit interface (8xD1/8x960H real-time

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 Hi3520D V200 H.264 CODEC Processor
RTC with Separated Power Supply Physical Specifications
z Independent power supply for the RTC by using batteries z Power consumption
z Built-in temperature sensor − 2.5 W typical power consumption
z Automatic correction of RTC counting frequency based − Multi-level power-saving control
on the temperature z Operating voltage
Boot Modes − 1.25 V core voltage
− 3.3 V I/O voltage
z Boots from the BOOTROM.
− 1.5 V or 1.8 V DDR2/DDR3 SDRAM interface voltage
z Boots from the SPI NOR flash.
z Package
SDK − RoHS, Epad-LQFP256
z Linux 3.0-based SDK − Lead pitch: 0.4 mm (0.016 in.)
z High-performance H.264 decoding PC library − Body size: 28 mm x 28 mm (1.1 in. x 1.1 in.)

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 Hi3520D V200 H.264 CODEC Processor

Functional Block Diagram

ARM subsystem Image subsystem

A9 @660
A9 dual MHz
core@930Mhz IVS engine HDMI/
DDRC x 1 32 KB/32 KBL1
32KB/32KB L1Cache
cache VGA/
128 KBL2
256KB L2Cache
cache 2 x CVBS
VPSS
BT.1120/
BT.656
SATA x 2 TDE
input

Flash I/F
AMBA 3.0 bus
I2C

SSP x 2 RTC
Video CODEC
MAC x 1 I 2C
H.264/MJPEG/
JPEG SRAM
FE PHY
GPIOs
USB 2.0 AES/DES/3DES
host x 2 IR
AENC
I 2S x 2 UART x 4

BOOTROM

Hi3520D V200 is a professional SoC designed for multi-channel D1, HD DVRs, and HD NVRs. With a high-performance A9
processor and an engine supporting up to 8-channel D1 encoding and decoding, Hi3520D V200 meets the rising demand for HD
applications. Hi3520D V200 also integrates an outstanding video processing engine, various encoding/decoding algorithms, and
multi-channel HD output capability. These features provide users with high-quality image experience. In addition, Hi3520D V200
integrates various peripheral interfaces to meet customer requirements for functionality, features, and image quality, while reducing
the EBOM cost.

DVRs (Each with a Hi3520D V200)

4xD1 DVR
z 4xD1+4xCIF dual-stream real-time encoding+JPEG snapshot D1@8 fps +4xD1 real-time decoding
z HDMI+VGA 1080p@60 fps outputs from the same source+2-channel CVBS outputs

4x960H DVR
z 4x960H+4xCIF encoding+1x960H real-time decoding
z HDMI+VGA 1080p@60 fps outputs from the same source+2-channel CVBS outputs

4x720p DVR
z 4x720p@25 fps+4xCIF@25 fps encoding+1x720p@25 fps decoding

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 Hi3520D V200 H.264 CODEC Processor
z HDMI+VGA 1080p@50 fps outputs from the same source
8xCIF DVR
z 8xCIF+8xQCIF encoding+JPEG snapshot D1@16 fps +8xCIF real-time decoding
z HDMI+VGA 1080p@60 fps outputs from the same source+2-channel CVBS outputs

8xD1 DVR
z 8xD1@6 fps+8xCIF@6 fps dual-stream encoding +1xD1@6 fps decoding
z HDMI+VGA 1080p@60 fps outputs from the same source+2-channel CVBS outputs

SATA SATA SATA

HDD HDD HDD

SATA-to-SATA SATA-to-SATA

HDMI VGA CVBS0 CVBS1 SATA SATA

Flash

DDR3

GMAC USB2.0 host

Transformer FE PHY VI0 VI1

8-/4-channel audio/video
decoder

... ...
LAN/WAN

NVRs (Each with a Hi3520D V200)

8xD1 NVR
z 8xD1 real-time decoding
z HDMI+VGA 1080p@60 fps outputs from the same source+2-channel CVBS outputs

4x720p NVR
z 4x720p real-time decoding
z HDMI+VGA 1080p@60 fps outputs from the same source+2-channel CVBS outputs

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 Hi3520D V200 H.264 CODEC Processor
SATA SATA SATA
HDD HDD HDD

SATA-to-SATA SATA-to-SATA

HDMI VGA CVBS0 CVBS1 SATA SATA

Flash

DDR3

GMAC USB2.0 host

MAC

Hub

LAN/WAN ...
IP camera

Acronyms and Abbreviations

3DES triple data encryption standard
AES advanced encryption standard
CBR constant bit rate
CS chip select
CVBS composite video broadcast signal
DES data encryption standard
DVR digital video recorder
eSATA external serial advanced technology attachment
FE fast Ethernet
GPIO general purpose input/output
HD high definition
HDMI high-definition multimedia interface
I2C inter-integrated circuit
IR infrared
I2S Inter-IC sound
JPEG Joint Photographic Experts Group
LAN local area network
LQFP low-profile quad flat package

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 Hi3520D V200 H.264 CODEC Processor
MAC media access control
MJPEG Motion Joint Photographic Experts Group
NVR network video recorder
ODT on-die termination
OSD on-screen display
PHY physical layer
PIP picture-in-picture
PM port multiplexer
RMII reduced media independent interface
RoHS restriction of the use of certain hazardous substances
ROI region of interest
RTC real-time clock
SATA serial advanced technology attachment
SDK software development kit
SDRAM synchronous dynamic random access memory
SoC system-on-chip
SRAM static random access memory
SPI serial peripheral interface
UART universal asynchronous receiver transmitter
VBR variable bit rate
VGA video graphics array
WAN wide area network

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