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T1040RDB

Page Description Version Control


A A
1 SCHEMATIC PAGE LISTING
Version Date Modifications
2 SYSTEM BLOCK DIAGRAM
3 T1040 DDR3L MEMORY INTERFACE V0.1 2013/06 First release of Schematics
4 T1040 IFC INTERFACE
5 T1040 NOR and NAND FLASH INTERFACE V1.0 2013/10 Released to Manufacturing
6 T1040 SPI FLASH and SDHC INTERFACE
7 T1040 SYSTEM LOGIC INTERFACE V2.0 2014/01 Add SD_REFCLK1_SEL to select SerDes PLL1 input clock frequency
Change the direction of the battery holder
8 T1040 ETHERNET and SERDES INTERFACE
9 SERDES MUX/DEMUX SWITCHs
10 T1040 QE INTERFACE
11 T1040 USB INTERFACE
12 T1040 POWER SUPPLY
B B
13 T1040 PLL FILTERs and GROUND
14 T1040 DUART INTERFACE
15 RGMII ETHERNET PORT 1
16 RGMII ETHERNET PORT 2 Variants Description
17 SGMII ETHERNET PORT
INTERPOSER INTERPOSER version (normal + VIT)
18 QSGMII PHY 1
T1040/T2081 RDB T1040RDB version (normal + VNIT)
19 QSGMII PHY 2
20 QSGMII ETHERNET PORTs
21 10G EDC PHY and SFP+ CONNECTOR
22 PCIe X1/X4 SLOT, MINI PCIe and SATA CONNECTORs
23 POTS 1&2 INTERFACE
C
24 POTS 3&4 INTERFACE C
25 POTS VBAT POWER SUPPLY
26 CPLD
27 SYSTEM CLOCK GENERATORs
28 SYSTEM CLOCK GENERATORs (cont.)
29 T1040 CORE POWER CONVERTOR
30 SYSTEM POWER CONVERTORs
31 SYSTEM POWER SWITCHs
All information is subject to change without notice.
32 SYSTEM POWER INPUT No warranty, expressed or applied, is made as to the
33 MECHANICALs accuracy of the information contained herein. This
schematic is provided for reference purposes only.
34 CHANGE LIST Contact your Freescale representative to obtain the
latest information on this product.

D D

Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 1 of 34


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1 2 3 4 5

SYSTEM BLOCK DIAGRAM

A A

RS232 UART1 DDR3L


RJ45 RS232 XCVR DDR3L UDIMM ATX Power

RJ45 2x1
I2C1
72bit, 4GB
12V
5V
RS232 UART2
RJ45 RS232 XCVR IFC NOR FLASH
16bit, 128MB VCORE
1.0V
USB1 I2C EEPROM 1.35V
USB1
USB Conn. USB Protect & USB2 AT24C256 1.5V Power
USB2 Power Switch Regulators
TypeA x2 USB CTL NAND FLASH 1.8V
8bit, 1GB 2.5V
Thermal Monitor 3.3V
SGMII ADT7461
MDI MDI SGMII PHY 5V
RJ45 Magnetics
RTL8211DN EMI1 ALTERA CPLD 12V
EPM570G
SPI SPI FLASH
B B
RGMII 64MB
MDI MDI RGMII PHY
RJ45 Magnetics
RTL8211E-VB
RJ45 2x1

SDHC SDHC SD Card


Protect T1040 ONLY!
RGMII SDHC/SDXC
MDI MDI RGMII PHY
RJ45 Magnetics
RTL8211E-VB T1040
JTAG JTAG
OVDD<->3.3V COP Conn.

FXS
TIP/RING
Protect
Tip/Ring TDM /T2081
Dual SLAC&SLIC
Tip/Ring
PCIe
TIP/RING Le88266 SPI
FXS Protect I2C2CH4 PEX x1/4 SLOT x1 For T1040; x4 For T2081
T1040 ONLY!

RJ11 x4

TIP/RING Tip/Ring
FXS Protect Dual SLAC&SLIC
PCIe
Tip/Ring
I2C2CH1 Mini PCIe Conn. T1040 ONLY!
TIP/RING Le88266
FXS Protect

PCIe
FXO Conn. Relay VBAT I2C2CH2 Mini PCIe Conn. T1040 ONLY!

C C
MDI MDI SATA
SATA Conn. T1040 ONLY!
MDI MDI QSGMII
QSGMII
MDI MDI PHY
MAGNETICS
T1040 ONLY!

MDI MDI F104S8A EMI1


RJ45 x8

MDI MDI

T1040 ONLY!
MDI MDI QSGMII
QSGMII QE
MDI MDI PHY
SPI TDM Riser Card Conn.
MDI MDI F104S8A
T2081 ONLY!

XFI XFI
10G PHY
SFP+ EMI2
CS4315
I2C2CH3

D D

Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 2 of 34


1 2 3 4 5
1 2 3 4 5

U1A
DDR_ECC[0..7]
DDR_ECC0 L24
DDR CONTROLLER
T27 DDR_MCK0_P
T1040 DDR3L MEMORY INTERFACE 1V35_SLP VTT MVREF
DDR_ECC1 D1_MECC0 1 of 15 D1_MCK0 DDR_MCK0_N
N23 T28 1.35V DDR3L SDRAM UDIMM
DDR_ECC2 T23 D1_MECC1 D1_MCK0_B R27 DDR_MCK1_P Micron MPN(4GB,1600): MT18KSF51272AZ-1G6
DDR_ECC3 U23 D1_MECC2 D1_MCK1 R28 DDR_MCK1_N
4GB
J1A
(x72, ECC, DR) Micron MPN(2GB,2133): MT9JSF25672AZ-2G1
DDR_ECC4 L23 D1_MECC3 D1_MCK1_B K22 DDR_MA[0..15] DDR_DQ[0..63] C1 C2 C15 C16 C17 C18 C19
DDR_ECC5 M23 D1_MECC4 TEST_OUT4 M22 DDR_MA0 188 3 DDR_DQ0
DDR_ECC6 R24 D1_MECC5 TEST_OUT5 U22 DDR_MA1 181 A0 DQ0 4 DDR_DQ1 22uF 22uF 22uF 0.1uF 0.1uF 0.1uF 0.1uF
DDR_ECC7 T24 D1_MECC6 TEST_OUT6 P22 DDR_MA2 61 A1 DQ1 9 DDR_DQ2
DDR_DQ[0..63] D1_MECC7 TEST_OUT7 DDR_MA3 180 A2 DQ2 10 DDR_DQ3 1V35_SLP
A DDR_DQ0 C21 A24 DDR_MDQS0_P DDR_MA4 59 A3 DQ3 122 DDR_DQ4 A
DDR_DQ1 A22 D1_MDQ00 D1_MDQS0 D26 DDR_MDQS1_P DDR_MA5 58 A4 DQ4 123 DDR_DQ5
DDR_DQ2 A26 D1_MDQ01 D1_MDQS1 G24 DDR_MDQS2_P DDR_MA6 178 A5 DQ5 128 DDR_DQ6
DDR_DQ3 B26 D1_MDQ02 D1_MDQS2 L25 DDR_MDQS3_P DDR_MA7 56 A6 DQ6 129 DDR_DQ7 C998 C999 C3 C4 C5 C6 C7
DDR_DQ4 B21 D1_MDQ03 D1_MDQS3 W25 DDR_MDQS4_P DDR_MA8 177 A7 DQ7 12 DDR_DQ8
DDR_DQ5 A21 D1_MDQ04 D1_MDQS4 AA23 DDR_MDQS5_P DDR_MA9 175 A8 DQ8 13 DDR_DQ9 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
DDR_DQ6 B24 D1_MDQ05 D1_MDQS5 AE25 DDR_MDQS6_P DDR_MA10 70 A9 DQ9 18 DDR_DQ10
DDR_DQ7 A25 D1_MDQ06 D1_MDQS6 AG24 DDR_MDQS7_P DDR_MA11 55 A10/AP DQ10 19 DDR_DQ11
DDR_DQ8 C23 D1_MDQ07 D1_MDQS7 R23 DDR_MDQS8_P DDR_MA12 174 A11 DQ11 131 DDR_DQ12
DDR_DQ9 C24 D1_MDQ08 D1_MDQS8 DDR_MA13 196 A12/BC DQ12 132 DDR_DQ13 C8 C9 C10 C11 C12 C13 C14
DDR_DQ10 F25 D1_MDQ09 A23 DDR_MDQS0_N DDR_MA14 172 A13 DQ13 137 DDR_DQ14
DDR_DQ11 F26 D1_MDQ10 D1_MDQS0_B D25 DDR_MDQS1_N DDR_MA15 171 A14 DQ14 138 DDR_DQ15 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
DDR_DQ12 D22 D1_MDQ11 D1_MDQS1_B G23 DDR_MDQS2_N DDR_MBA[0..2] A15 DQ15 21 DDR_DQ16
DDR_DQ13 D23 D1_MDQ12 D1_MDQS2_B K25 DDR_MDQS3_N DDR_MBA0 71 DQ16 22 DDR_DQ17
DDR_DQ14 B27 D1_MDQ13 D1_MDQS3_B V25 DDR_MDQS4_N DDR_MBA1 190 BA0 DQ17 27 DDR_DQ18
DDR_DQ15 E25 D1_MDQ14 D1_MDQS4_B Y23 DDR_MDQS5_N DDR_MBA2 52 BA1 DQ18 28 DDR_DQ19
DDR_DQ16 E23 D1_MDQ15 D1_MDQS5_B AF25 DDR_MDQS6_N BA2 DQ19 140 DDR_DQ20 1V35_SLP J1B
DDR_DQ17 E24 D1_MDQ16 D1_MDQS6_B AH24 DDR_MDQS7_N DDR_MCK0_P 184 DQ20 141 DDR_DQ21
DDR_DQ18 J23 D1_MDQ17 D1_MDQS7_B P23 DDR_MDQS8_N DDR_MCK0_N 185 CK0 DQ21 146 DDR_DQ22 51 2
DDR_DQ19 K23 D1_MDQ18 D1_MDQS8_B DDR_MDM[0..8] CK0 DQ22 147 DDR_DQ23 54 VDD VSS 5
DDR_DQ20 F22 D1_MDQ19 B22 DDR_MDM0 DDR_MCK1_P 63 DQ23 30 DDR_DQ24 57 VDD VSS 8
DDR_DQ21 H22 D1_MDQ20 D1_MDM0 C25 DDR_MDM1 DDR_MCK1_N 64 CK1 DQ24 31 DDR_DQ25 60 VDD VSS 11
DDR_DQ22 H23 D1_MDQ21 D1_MDM1 F23 DDR_MDM2 CK1 DQ25 36 DDR_DQ26 62 VDD VSS 14
DDR_DQ23 J24 D1_MDQ22 D1_MDM2 K26 DDR_MDM3 DDR_MDQS0_P 7 DQ26 37 DDR_DQ27 65 VDD VSS 17
B D1_MDQ23 D1_MDM3 DQS0 DQ27 VDD VSS B
DDR_DQ24 H26 U26 DDR_MDM4 DDR_MDQS0_N 6 149 DDR_DQ28 66 20
DDR_DQ25 J25 D1_MDQ24 D1_MDM4 Y24 DDR_MDM5 DDR_MDQS1_P 16 DQS0 DQ28 150 DDR_DQ29 69 VDD VSS 23
DDR_DQ26 P26 D1_MDQ25 D1_MDM5 AD24 DDR_MDM6 DDR_MDQS1_N 15 DQS1 DQ29 155 DDR_DQ30 72 VDD VSS 26
DDR_DQ27 N25 D1_MDQ26 D1_MDM6 AF24 DDR_MDM7 DDR_MDQS2_P 25 DQS1 DQ30 156 DDR_DQ31 75 VDD VSS 29
DDR_DQ28 G25 D1_MDQ27 D1_MDM7 N24 DDR_MDM8 DDR_MDQS2_N 24 DQS2 DQ31 81 DDR_DQ32 78 VDD VSS 32
DDR_DQ29 H25 D1_MDQ28 D1_MDM8 DDR_MDQS3_P 34 DQS2 DQ32 82 DDR_DQ33 170 VDD VSS 35
DDR_DQ30 M26 D1_MDQ29 DDR_MDQS3_N 33 DQS3 DQ33 87 DDR_DQ34 173 VDD VSS 38
DDR_DQ31 M25 D1_MDQ30 DDR_MDQS4_P 85 DQS3 DQ34 88 DDR_DQ35 176 VDD VSS 41
DDR_DQ32 T25 D1_MDQ31 DDR_MDQS4_N 84 DQS4 DQ35 200 DDR_DQ36 179 VDD VSS 44
DDR_DQ33 U25 D1_MDQ32 DDR_MDQS5_P 94 DQS4 DQ36 201 DDR_DQ37 182 VDD VSS 47
DDR_DQ34 AA26 D1_MDQ33 Y21 DDR_MDQS5_N 93 DQS5 DQ37 206 DDR_DQ38 183 VDD VSS 80
DDR_DQ35 AA25 D1_MDQ34 TEST_OUT8 DDR_MDQS6_P 103 DQS5 DQ38 207 DDR_DQ39 186 VDD VSS 83
D1_MDQ35 (DDR4 ONLY) DQS6 DQ39 VDD VSS
DDR_DQ36 P25 DDR_MDQS6_N 102 90 DDR_DQ40 189 86
DDR_DQ37 R25 D1_MDQ36 DDR_MDQS7_P 112 DQS6 DQ40 91 DDR_DQ41 191 VDD VSS 89
DDR_DQ38 W26 D1_MDQ37 DDR_MDQS7_N 111 DQS7 DQ41 96 DDR_DQ42 194 VDD VSS 92
DDR_DQ39 Y25 D1_MDQ38 DDR_MBA[0..2] DDR_MDQS8_P 43 DQS7 DQ42 97 DDR_DQ43 VTT 197 VDD VSS 95
DDR_DQ40 V24 D1_MDQ39 Y28 DDR_MBA0 DDR_MDQS8_N 42 DQS8 DQ43 209 DDR_DQ44 VDD VSS 98
D1_MDQ40 DDR4 D1_MBA0 DQS8 DQ44 VSS
DDR_DQ41 W23 NAMES W28 DDR_MBA1 210 DDR_DQ45 MVREF 120 101
DDR_DQ42 AA22 D1_MDQ41 D1_MBA1 E28 DDR_MBA2 DDR_MCS0_N 193 DQ45 215 DDR_DQ46 240 VTT VSS 104
D1_MDQ42 BG0 D1_MBA2 S0 DQ46 VTT VSS
DDR_DQ43 AC22 DDR_MA[0..15] DDR_MCS1_N 76 216 DDR_DQ47 48 107
DDR_DQ44 W22 D1_MDQ43 V28 DDR_MA0 DDR_MCS2_N 79 S1 DQ47 99 DDR_DQ48 49 VTT/NC VSS 110
DDR_DQ45 V23 D1_MDQ44 D1_MA00 N28 DDR_MA1 DDR_MCS3_N 198 S2/NC DQ48 100 DDR_DQ49 VTT/NC VSS 113
DDR_DQ46 AB24 D1_MDQ45 D1_MA01 N27 DDR_MA2 DDR_MCAS_N 74 S3/NC DQ49 105 DDR_DQ50 67 VSS 116
DDR_DQ47 AB23 D1_MDQ46 D1_MA02 M28 DDR_MA3 DDR_MRAS_N 192 CAS DQ50 106 DDR_DQ51 3V3 1 VREFCA VSS 121
C C
DDR_DQ48 AD26 D1_MDQ47 D1_MA03 L27 DDR_MA4 DDR_MWE_N 73 RAS DQ51 218 DDR_DQ52 VREFDQ VSS 124
DDR_DQ49 AD25 D1_MDQ48 D1_MA04 L28 DDR_MA5 DDR_MDM[0..8] WE DQ52 219 DDR_DQ53 236 VSS 127
DDR_DQ50 AD23 D1_MDQ49 D1_MA05 K28 DDR_MA6 DDR_MDM0 125 DQ53 224 DDR_DQ54 VDDSPD VSS 130
DDR_DQ51 AE22 D1_MDQ50 D1_MA06 J28 DDR_MA7 126 DM0/DQS9 DQ54 225 DDR_DQ55 C20 202 VSS 133
DDR_DQ52 AB25 D1_MDQ51 D1_MA07 J27 DDR_MA8 DDR_MDM1 134 NC/DQS9 DQ55 108 DDR_DQ56 205 VSS VSS 136
DDR_DQ53 AC25 D1_MDQ52 D1_MA08 G27 DDR_MA9 135 DM1/DQS10 DQ56 109 DDR_DQ57 0.1uF 208 VSS VSS 139
DDR_DQ54 AC23 D1_MDQ53 D1_MA09 Y27 DDR_MA10 DDR_MDM2 143 NC/DQS10 DQ57 114 DDR_DQ58 211 VSS VSS 142
DDR_DQ55 AE23 D1_MDQ54 D1_MA10 H28 DDR_MA11 144 DM2/DQS11 DQ58 115 DDR_DQ59 214 VSS VSS 145
DDR_DQ56 AG25 D1_MDQ55 D1_MA11 G28 DDR_MA12 DDR_MDM3 152 NC/DQS11 DQ59 227 DDR_DQ60 217 VSS VSS 148
DDR_DQ57 AH25 D1_MDQ56 D1_MA12 AE28 DDR_MA13 153 DM3/DQS12 DQ60 228 DDR_DQ61 220 VSS VSS 151
DDR_DQ58 AH22 D1_MDQ57 D1_MA13 E27 DDR_MA14 DDR_MDM4 203 NC/DQS12 DQ61 233 DDR_DQ62 223 VSS VSS 154
D1_MDQ58 BG1 D1_MA14 DM4/DQS13 DQ62 VSS VSS
DDR_DQ59 AF22 D28 DDR_MA15 204 234 DDR_DQ63 226 157
D1_MDQ59 ACT_B D1_MA15 NC/DQS13 DQ63 VSS VSS
DDR_DQ60 AF26 DDR_MDM5 212 DDR_ECC[0..7] 229 160
DDR_DQ61 AH26 D1_MDQ60 AA28 DDR_MRAS_N 213 DM5/DQS14 39 DDR_ECC0 232 VSS VSS 163
D1_MDQ61 A16 D1_MRAS_B NC/DQS14 CB0 VSS VSS
DDR_DQ62 AH23 AC28 DDR_MCAS_N DDR_MDM6 221 40 DDR_ECC1 235 166
D1_MDQ62 A15 D1_MCAS_B DM6/DQS15 CB1 VSS VSS
DDR_DQ63 AF23 AB27 DDR_MWE_N 222 45 DDR_ECC2 239 199
D1_MDQ63 A14 D1_MWE_B NC/DQS15 CB2 VSS VSS
DDR_MDM7 230 46 DDR_ECC3
1V35_SLP T1040 REV 1.0: 162 ohm AB28 DDR_MCS0_N 231 DM7/DQS16 CB3 158 DDR_ECC4 167 187
T2081 REV 1.0: 187 ohm D1_MCS0_B AC27 DDR_MCS1_N DDR_MDM8 161 NC/DQS16 CB4 159 DDR_ECC5 DDR_MAPAR_OUT 68 TEST/NC EVENT/NC 53
R1 162 1% U28 D1_MCS1_B AG27 DDR_MCS2_N 162 DM8/DQS17 CB5 164 DDR_ECC6 PARIN/NC ERROUT/NC
D1_MDIC1 M1_C0 D1_MCS2_B NC/DQS17 CB6
AF28 DDR_MCS3_N 165 DDR_ECC7
M1_C1 D1_MCS3_B CB7
R3 162 1% P28 DDR_MCKE0 50 DDR_MAPAR_ERR DDR3_DIMM
D1_MDIC0 DDR_MCKE0 31 DDR_MCKE0 DDR_MCKE1 CKE0
C27 169
D1_MCKE0 31 DDR_MCKE1 CKE1
D R4 10K C28 DDR_MCKE1 DDR_MODT0 195 D
DDR_MAPAR_ERR F28 ALERT_B D1_MCKE1 H21 DDR_MODT1 77 ODT0
MVREF DDR_MAPAR_OUT V27 D1_MAPAR_ERR_B TEST_OUT0 F21 ODT1
D1_MAPAR_OUT TEST_OUT1 168
DDR_MODT0 26 DDR_RST_N RESET
F20 AD28 3V3
D1_MVREF D1_MODT0 AE27 DDR_MODT1 R2 1K 117 118 Title
M1_C2 D1_MODT1 1V35_SLP SA0 SCL I2C1_SCL 7,14,29
C21 C22 W21 237 238 T1040RDB
TEST_OUT2 SA1 SDA I2C1_SDA 7,14,29
J20 V21 119
0.1uF 0.01uF D1_TPA TEST_OUT3 SPD ADDR = 0x51 SA2 Size Document Number Design Engineer Rev
B <Doc> MICETEK A
T1040 DDR3_DIMM
Date: Thursday, January 16, 2014 Sheet 3 of 34
1 2 3 4 5
1 2 3 4 5

T1040 IFC INTERFACE


OVDD OVDD OVDD OVDD OVDD OVDD OVDD

R797 20K FOR T1040/T2081, OVDD = 1.8V


R798 20K FOR INTERPOSER, OVDD = 3.3V
R799 20K R5 R6 R7 R9 R10 R11
R800 20K CS0: NOR or NAND
R864 20K U1D 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K CS1: NAND or NOR
CS2: CPLD
A 5,26 IFC_AD[0..15] IFC_AD0 IFC INTERFACE A
A4 C13
IFC_AD1 B5 IFC_AD00 4 of 15 IFC_CS0_B E15
IFC_CS0_N 26
IFC_AD01 IFC_CS1_B IFC_CS1_N 26
IFC_AD2 A5 D16
IFC_AD02 IFC_CS2_B IFC_CS2_N 26
IFC_AD3 B6 C16
IFC_AD4 A6 IFC_AD03 IFC_CS3_B E17
IFC_AD5 A7 IFC_AD04 IFC_CS4_B C17 R801 20K
IFC_AD6 B8 IFC_AD05 IFC_CS5_B D18 R802 20K OVDD
IFC_AD7 A8 IFC_AD06 IFC_CS6_B C19 R803 20K
IFC_AD8 B9 IFC_AD07 IFC_CS7_B R804 20K
IFC_AD9 A9 IFC_AD08 D13
IFC_AD09 IFC_WE0_B IFC_WE_N 5,26
IFC_AD10 A10
IFC_AD11 B11 IFC_AD10
IFC_AD12 A11 IFC_AD11
IFC_AD13 B12 IFC_AD12 Interposer por cfg
IFC_AD14 A12 IFC_AD13 F16 cfg_rcw_src0
IFC_AD14 (WE1_B) IFC_CLE IFC_CLE 5,26
IFC_AD15 A13
IFC_AD15 D15 cfg_rcw_src2
IFC_OE_B IFC_OE_N 5,26
B15
4,5,26 IFC_A[5..31] IFC_A16 IFC_RB0_B IFC_RB0_N 26
C5 A15
IFC_A16 IFC_RB1_B IFC_RB1_N 26
IFC_A17 C6 F17 cfg_rcw_src3
IFC_A17 IFC_WP0_B IFC_WP_N 5,26
IFC_A18 D7
IFC_A19 C7 IFC_A18 D17
IFC_A19 IFC_AVD IFC_AVD 5
IFC_A20 cfg_test_port_dis D8 A14
B IFC_A20 IFC_BCTL B
IFC_A21 C8 B14 IFC_TE
IFC_A22 D9 IFC_A21 IFC_TE
IFC_A23 cfg_elbc_ecc C9 IFC_A22 A17 R12 10
IFC_A23 IFC_CLK0 IFC_CLK 26
IFC_A24 cfg_dram_type D10 A19
IFC_A25 C10 IFC_A24 IFC_CLK1
IFC_A26 cfg_xvdd_sel 1 for 1.5V E11 IFC_A25
IFC_A27 C11 IFC_A26 D14
IFC_A28 IFC_A27 IFC_NDDDR_CLK IFC_NDWE_N 5
D11 A16
IFC_A29 C12 IFC_A28 IFC_NDDQS
IFC_A30 D12 IFC_A29 E14
IFC_A31 E12 IFC_A30 IFC_PERR_B
IFC_A31 C15 cfg_rcw_src4
R809 4.7K IFC_PAR0 C14 cfg_rcw_src1
IFC_PAR1 IFC_PAR1 5
R810 4.7K R13
DNP R811 4.7K DNP
4.7K T1040 R812 4.7K DNP

U2

IFC_AD5 IFC_A5 IFC_A[5..31] 4,5,26


47 2 R14 33
IFC_AD6 46 1D1 1Q1 3 R15 33 IFC_A6
IFC_AD7 44 1D2 1Q2 5 R16 33 IFC_A7
T1040 RESET CONFIGURATION IFC_AD8 43 1D3 1Q3 6 R18 33 IFC_A8
C C
cfg_rcw_src[0:8] IFC_AD9 41 1D4 1Q4 8 R20 33 IFC_A9
0_0010_0111: NOR FLASH BOOT IFC_AD10 40 1D5 1Q5 9 R22 33 IFC_A10
0_0100_0000: SD CARD BOOT IFC_AD11 38 1D6 1Q6 11 R24 33 IFC_A11
0_0100_0101: SPI BOOT IFC_AD12 37 1D7 1Q7 12 R26 33 IFC_A12
1_0001_1001: NAND FLASH BOOT 1D8 1Q8
48
SW1 1 LE1
OE1
IFC_AD8 ON IFC_AD13 IFC_A13
cfg_rcw_src0 1 16 R17 4.7K 36 13 R28 33
IFC_AD9 cfg_rcw_src1 2 1 16 15 R19 4.7K IFC_AD14 35 2D1 2Q1 14 R30 33 IFC_A14
IFC_AD10 cfg_rcw_src2 3 2 15 14 R21 4.7K IFC_AD15 33 2D2 2Q2 16 R32 33 IFC_A15
IFC_AD11 cfg_rcw_src3 4 3 14 13 R23 4.7K 32 2D3 2Q3 17
IFC_AD12 cfg_rcw_src4 5 4 13 12 R25 4.7K 30 2D4 2Q4 19
IFC_AD13 cfg_rcw_src5 6 5 12 11 R27 4.7K 29 2D5 2Q5 20
IFC_AD14 cfg_rcw_src6 7 6 11 10 R29 4.7K 27 2D6 2Q6 22
IFC_AD15 cfg_rcw_src7 8 7 10 9 R31 4.7K 26 2D7 2Q7 23
8 9 2D8 2Q8
25
SWITCH_DIP_8 24 LE2
SW2 OE2
4
IFC_CLE ON GND
cfg_rcw_src8 1 16 R33 4.7K 10
IFC_TE cfg_ifc_te 2 1 16 15 R34 4.7K 1: TE logic 0 OVDD OVDD GND 15
D IFC_A18 cfg_pll_config_sel_b 3 2 15 14 R35 4.7K GND 21 D
IFC_A19 cfg_por_ainit 4 3 14 13 R36 4.7K 7 GND 28
IFC_A16 cfg_svr0 5 4 13 12 R37 4.7K 18 VCC GND 34
IFC_A17 cfg_svr1 6 5 12 11 R39 4.7K cfg_dram_type C23 C24 C25 C26 31 VCC GND 39
IFC_A21 cfg_dram_type 7 6 11 10 R38 4.7K For T1040: 0: DDR3L 42 VCC GND 45
IFC_AVD cfg_rsp_dis 8 7 10 9 R40 4.7K For T2081 1: DDR3L 0.1uF 0.1uF 0.1uF 0.1uF VCC GND Title
8 9 T1040RDB
74LVC16373
SWITCH_DIP_8 Size Document Number Design Engineer Rev
B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 4 of 34


1 2 3 4 5
1 2 3 4 5

T1040 NOR and NAND FLASH INTERFACE


OVDD OVDD OVDD OVDD U98 3V3

FOR T1040/T2081, OVDD = 1.8V 16 13


FOR INTERPOSER, OVDD = 3.3V VCCA VCCB
R43 R41 R42
128MB 16-BIT NOR FLASH 4,5,26 IFC_AD[0..15] IFC_AD7 1 12 NAND_IO0
IFC_AD6 2 A1 B1 11 NAND_IO1
4.7K 4.7K 4.7K U4 IFC_AD5 3 A2 B2 10 NAND_IO2
A IFC_AD4 4 A3 B3 9 NAND_IO3 A
4,26 IFC_A[5..31] IFC_A30 IFC_AD15 IFC_AD[0..15] 4,5,26 A4 B4
31 35
IFC_A29 26 A0 DQ0 37 IFC_AD14 8 5
A1 DQ1 5,26 IFC_LATCH_N OE NC1
IFC_A28 25 39 IFC_AD13 6 14
IFC_A27 24 A2 DQ2 41 IFC_AD12 7 GND NC2 15
IFC_A26 23 A3 DQ3 44 IFC_AD11 GND NC3
IFC_A25 22 A4 DQ4 46 IFC_AD10
IFC_A24 21 A5 DQ5 48 IFC_AD9 TXBN0304RSV
IFC_A23 20 A6 DQ6 50 IFC_AD8
IFC_A22 10 A7 DQ7 36 IFC_AD7 OVDD U99 3V3
IFC_A21 9 A8 DQ8 38 IFC_AD6
IFC_A20 8 A9 DQ9 40 IFC_AD5 16 13
IFC_A19 7 A10 DQ10 42 IFC_AD4 VCCA VCCB
IFC_A18 6 A11 DQ11 45 IFC_AD3 IFC_AD3 1 12 NAND_IO4
IFC_A17 5 A12 DQ12 47 IFC_AD2 IFC_AD2 2 A1 B1 11 NAND_IO5
IFC_A16 4 A13 DQ13 49 IFC_AD1 IFC_AD1 3 A2 B2 10 NAND_IO6
IFC_A15 3 A14 DQ14 51 IFC_AD0 IFC_AD0 4 A3 B3 9 NAND_IO7
IFC_A14 54 A15 DQ15/A-1 A4 B4
IFC_A13 19 A16 8 5
IFC_A12 18 A17 6 OE NC1 14
IFC_A11 11 A18 OVDD 7 GND NC2 15
IFC_A10 12 A19 GND NC3
IFC_A9 15 A20
IFC_A8 2 A21 TXBN0304RSV
B A22 B
1 R44 3V3 3V3
56 A23 OVDD 3V3 OVDD 3V3
55 A24 4.7K
A25
32 17 C1071 C1072 C1073 C1074 R45 R46
1GB 8-BIT NAND FLASH
26 NOR_CS_N CE RDY/BUSY
34
4,5,26 IFC_OE_N OE
13 0.1uF 0.1uF 0.1uF 0.1uF 4.7K 4.7K U6
4,26 IFC_WE_N WE
14 9 29 NAND_IO0
26 NOR_RST_N RESET CE1 IO0 NAND_IO1
27 10 30
OVDD 53 NC1 28 CE2 IO1 31 NAND_IO2
16 BYTE NC2 30 OVDD 3V3 OVDD 3V3 16 IO2 32 NAND_IO3
WP/ACC NC3 17 CLE IO3 41 NAND_IO4
OVDD 3V3 43 33 ALE IO4 42 NAND_IO5
R47 29 VCC GND 52 C1059 C1060 C1061 C1062 8 IO5 43 NAND_IO6
VIO GND 18 RE IO6 44 NAND_IO7
4.7K 0.1uF 0.1uF 0.1uF 0.1uF WE IO7
JS28F00AM29EWHA 7
R/B1 NAND_RB_N 26
19 6
IFC_VA5 WP R/B2 3V3
IFC_VA6 1 24
IFC_VA7 2 NC1 NC24 27
OVDD U7 3V3 3 NC2 NC27 28
OVDD 4 NC3 NC28 33 R48
C C
U8 16 13 5 NC4 NC33 40
IFC_A7 1 5 On Interposer ONLY, NAND AVD is routed on PAR1 VCCA VCCB 3V3 11 NC5 NC40 45 1K
I0 VCC 4 1 12 14 NC11 NC45 46
26 CFG_VBANK[0..2] CFG_VBANK2 O 4,5,26 IFC_OE_N A1 B1 NC14 NC46
2 3 2 11 15 47
I1 GND 26 NAND_CS_N A2 B2 NC15 NC47
3 10 20
4,26 IFC_CLE A3 B3 NC20
74LVC1G86 R49 0 VNIT 4 9 R51 21 26
4 IFC_AVD A4 B4 NC21 DNU26
R50 0 VIT 22 35
4 IFC_PAR1 NC22 DNU35
OVDD 8 5 0 23 38
5,26 IFC_LATCH_N OE NC1 NC23 DNU38
U9 6 14
IFC_A6 1 5 7 GND NC2 15 34 25
I0 VCC 4 GND NC3 39 DNU34/VCCQ DNU25/VSSQ 48 R52 0
CFG_VBANK1 2 O 3 12 DNU39/VCCQ DNU48/VSSQ 13
I1 GND TXBN0304RSV 3V3 37 VCC GND 36
74LVC1G86 VCC GND
OVDD U11 3V3
OVDD MT29F8G08ABABAWP-ITX:B
U10 16 13
IFC_A5 1 5 VCCA VCCB On Interposer, NAND MPN: K9F5608U0D
I0 VCC 4 1 12
CFG_VBANK0 O 4 IFC_NDWE_N A1 B1
2 3 2 11
I1 GND 4,26 IFC_WP_N A2 B2
3 10 3V3
74LVC1G86 4 A3 B3 9
A4 B4
D OVDD 3V3 OVDD R808 4.7K 8 5 D
OVDD 6 OE NC1 14 C27 C28 C29
7 GND NC2 15
GND NC3 1uF 0.1uF 0.1uF
C30 C31 C32 C33 C34 C35
TXBN0304RSV Title
0.1uF 0.1uF 0.1uF 1uF 0.1uF 0.1uF T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 5 of 34


1 2 3 4 5
1 2 3 4 5

T1040 SPI FLASH and SDHC INTERFACE

3V3 3V3 3V3 3V3

A A
R55 R54 R57 R56

4.7K 4.7K 4.7K 4.7K 64MB SERIAL FLASH


R58 33
OVDD U12 3V3
SPI OPERATES AT 1.8V FOR T1040/T2081
U1C 3.3V FOR INTERPOSER 16 13 U13 3V3
VCCA VCCB
SPI / SDHC Interfaces
P2 PROC_SPI_MOSI 1 12 R866 51 15 8
3 of 15 SPI_MOSI PROC_SPI_MISO A1 B1 SI SO
P1 2 11 16
SPI_MISO N1 R59 10 PROC_SPI_CLK 3 A2 B2 10 R865 51 7 SCK C36 C37
SPI_CLK PROC_SPI_CS0_N 4 A3 B3 9 CS
M1 A4 B4 9 3 1uF 0.1uF
(SD_DAT4) SPI_CS0_B WP NC1
M2 PROC_SPI_CS1_N 8 5 1 4
(SD_DAT5) SPI_CS1_B OE NC1 SPI_CLK 10,23,24 HOLD NC2
M3 PROC_SPI_CS2_N 6 14 5
(SD_DAT6) SPI_CS2_B GND NC2 SPI_MISO 10,23,24 NC3
N3 PROC_SPI_CS3_N 7 15 3V3 6
(SD_DAT7) SPI_CS3_B GND NC3 SPI_MOSI 10,23,24 NC4 11
2 NC5 12
TXBN0304RSV VCC NC6 13
10 NC7 14
L2 SDHC_DAT0 GND NC8
SDHC_DAT0 K4 SDHC_DAT1
B SDHC_DAT1 B
L3 SDHC_DAT2 N25Q512A13GSF40F
SDHC_DAT2 L1 SDHC_DAT3 CO-LAYOUT
SDHC_DAT3 EVDD CAN BE 3.3V or 1.8V EVDD 3V3 U15 DNP
K1 R61 0 SDHC_CLK
SDHC_CLK K3 SDHC_CMD R60 10K 8
SDHC_CMD R62 10K VCC
R63 10K 5 2
L5 SDHC_CD_N R64 10K 6 SI SO
SDHC_CD_B M5 SDHC_WP 1 SCK
SDHC_WP R68 10K 3 CS
R67 10K 7 WP
T1040 OVDD HOLD
4
R66 10K 9 GND 3V3
R65 10K EPAD

N25Q512A13GF840F
C38 C39

U93 1uF 0.1uF


1 8
OVDD 3V3 OVDD 3V3
2 7 SD CARD FOR T1040 ONLY!
C 3V3 C
C40 C41 C42 C43 9 J2
9
0.1uF 0.1uF 0.1uF 0.1uF 3 6 1 D2/RSV
2 D3/CS
4 5 3 CMD/DIN
4 VSS 10
RClamp0524J.TCT 5 VDD INSERT 11
U94 6 CLK/SCLK PROTECT
OVDD U18 3V3 1 8 7 VSS 12
8 D0/DOUT COM1 13
16 13 2 7 D1/RSV COM2
VCCA VCCB SD_CARD_SKT
PROC_SPI_CS3_N 1 12 9
A1 B1 SPI_CS3_N 10
PROC_SPI_CS2_N 2 11
PROC_SPI_CS1_N A2 B2 POTSB_SPI_CS_N 24
3 10 3 6
A3 B3 POTSA_SPI_CS_N 23
4 9
A4 B4 4 5
8 5
6 OE NC1 14 RClamp0524J.TCT
7 GND NC2 15
GND NC3

TXBN0304RSV
D D

Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 6 of 34


1 2 3 4 5
1 2 3 4 5

T1040 SYSTEM LOGIC INTERFACE


OVDD_SLP 2V5_SLP DVDD OVDD OVDD_SLP

OVDD_SLP OVDD_SLP

1K
1K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
R85 R813
A TEMP_DIODE_P 14 A
TEST_SEL_B
TEMP_DIODE_N 14
FOR T1040, PULL-DOWN U1F 4.7K 4.7K
EVT_PWR_EN 26
FOR T1020/T2081, PULL-UP
System Logic EVT_PWR_OK 26

R69
R70
R71
R72
R73
R74
R75
R76
R77
R78
R79
R80
R81
R82
R83
R84
F9 E21
G8 SCAN_MODE_B 6 of 15 TD1_ANODE G21 DVDD
26 TEST_SEL_N TEST_SEL_B TD1_CATHODE

F7 FOR INTERPOSER/T1040, DVDD = 3.3V


26 CPLD_INT1_N IRQ00

1
D3 FOR T2081, DVDD = 2.5V
26 CPLD_INT2_N IRQ01
E9 DVDD DVDD DVDD DVDD Q1 3V3 3V3
D1 IRQ02 IRLML6346
26 SDHC_VS IRQ03
D4 D6 2 3
D5 IRQ04 EVT0_B C4
AB4 IRQ05 EVT1_B C1 R86 R87 R88 R89 R90 R91
15 EC1_INT_N IRQ06 EVT2_B
AD5 C2
15 EC1_PME_N IRQ07 EVT3_B

1
AB1 C3 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
AC5 IRQ08 EVT4_B Q2
26 GPIO_CKE_ISO IRQ09
L4 W1 IRLML6346
16 EC2_INT_N IRQ10 IIC1_SCL I2C1_SCL 3,14,29
U3 V1 2 3
16 EC2_PME_N IRQ11 IIC1_SDA I2C1_SDA 3,14,29
26 EVT_BRD_ISO
A3 V3
32 LP_TMPDET_N IRQ_OUT_B IIC2_SCL Y3 U19
23,24 POTS_TDM_TXD IIC2_SDA
F19
23,24 POTS_TDM_FS TMP_DETECT_B
R6 V2 R92 4.7K 14 5
B 23,24 POTS_TDM_CLK LP_TMP_DETECT_B (T2081 only)
IIC3_SCL SCL SC0 I2C2_MPEX1_SCL 22 B
FOR T2081, KEEP SLAC RESET W3 R93 4.7K 15 4
23,24 POTS_TDM_RXD IIC3_SDA SDA SD0 I2C2_MPEX1_SDA 22
DVDD
OVDD_SLP R94 4.7K F13 AA3 R95 4.7K 7
PORESET_B IIC4_SCL SC1 I2C2_MPEX2_SCL 22
R96 4.7K E8 AB3 R97 4.7K 3V3 6
HRESET_B IIC4_SDA SD1 I2C2_MPEX2_SDA 22
R98 4.7K B3
RESET_REQ_B R99 4.7K 3 10
RESET SC2 I2C2_SFPP_SCL 21
AA1 9
26 PORESET_N UART1_SIN PROC_UART1_RXD 14 SD2 I2C2_SFPP_SDA 21
P5 AA2 1
26 HRESET_N DMA1_DREQ0_B UART1_SOUT PROC_UART1_TXD 14 A0
cfg_test_port_mux_sel U5 Y2 2 12
26 RESET_REQ_N DMA1_DACK0_B UART1_CTS_B PROC_UART1_CTS_N 14 A1 SC3 I2C2_PEX_SCL 22
R100 10 R5 Y1 3V3 13 11
DMA1_DDONE0_B UART1_RTS_B PROC_UART1_RTS_N 14 A2 SD3 I2C2_PEX_SDA 22
V5
3V3 U20 OVDD AA5 DMA2_DREQ0_B 16 8
Y5 DMA2_DACK0_B W4 VDD VSS
DMA2_DDONE0_B UART2_SIN PROC_UART2_RXD 14
16 13 AA4 C48
VCCA VCCB UART2_SOUT PROC_UART2_TXD 14
Y4 PCA9546APW
JTAG_TDI UART2_CTS_B PROC_UART2_CTS_N 14
1 12 A18 V4 0.1uF
A1 B1 TDI UART2_RTS_B PROC_UART2_RTS_N 14
2 11 JTAG_TDO C18
3 A2 B2 10 JTAG_TCK E18 TDO XVDD use 1.35V I2C ADDR = 0x77
4 A3 B3 9 JTAG_TMS B18 TCK B2 ASLEEP cfg_xvdd_sel R101 4.7K
A4 B4 TMS ASLEEP OVDD_SLP
D19 F18 CKSTP_OUT_N R102 4.7K
26 JTAG_TRST_N TRST_B CKSTP_OUT_B OVDD
8 5
6 OE NC1 14
7 GND NC2 15 G15 E6 TP1 OVDD_SLP 3V3_SLP
GND NC3 27 SYS_REFCLK SYSCLK CLK_OUT
C J21 B20 U21 C
27 DDR_REFCLK DDRCLK FA_ANALOG_PIN C20 1 5 LABEL = ASLEEP
TXBN0304RSV G14 FA_ANALOG_G_V 2 VCC1 VCC D1
27 SYS_REFCLK_P DIFF_SYSCLK A
F14 3 4 R103 510 2 1
27 SYS_REFCLK_N DIFF_SYSCLK_B GND O
3V3 OVDD R104 R105
TP2 B17 1% 1% FXLP34P5X GRN
3V3 3V3 RTC 698 698
C49 C50 OVDD 3V3
R106 T1040 U22
3V3 0.1uF 0.1uF 1 5 OVDD_SLP OVDD 3V3_SLP 3V3
R108 R109 10K 2 VCC1 VCC
R107 10K 3 A 4
R110 10K J3 10 10K GND O C52 C53 C54 C51
COP_TDO FXLP34P5X
R111 10K COP_TDI 1 2 0.1uF 0.1uF 0.1uF 0.1uF
3 4 COP_TRST_N 26
R112 10K
R113 10K COP_TCK 5 6
R114 10K COP_TMS 7 8
9 10
26 COP_SRESET_N 11 12
26 COP_HRESET_N COP_CKSTP_OUT_N 13 14
15 16
HTST-108-01-L-DV

D D

Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 7 of 34


1 2 3 4 5
1 2 3 4 5

T1040 ETHERNET and SERDES INTERFACE

U1E
15 EC1_TXD[0..3] EC1_TXD0 ETHERNET EC2_TXD0 EC2_TXD[0..3] 16
R115 10 AE3 AE7 R117 10
A EC1_TXD1 EC1_TXD0 5 of 15 EC2_TXD0 EC2_TXD1 A
R116 10 AE4 AF7 R118 10
EC1_TXD2 R119 10 AD3 EC1_TXD1 EC2_TXD1 AF6 R120 10 EC2_TXD2
EC1_TXD3 R121 10 AC3 EC1_TXD2 EC2_TXD2 AG5 R122 10 EC2_TXD3
R123 4.7K EC1_TXD3 EC2_TXD3 R124 4.7K
R125 10 AF4 AF8 R126 10
15 EC1_TXCTL EC1_TX_CTL EC2_TX_CTL EC2_TXCTL 16
R127 10 AF3 AE8 R128 10
15 EC1_GTXCLK EC1_GTX_CLK EC2_GTX_CLK EC2_GTXCLK 16
C55 10pF AC4 C56 10pF
DNP EC1_TX_ER DNP
15 EC1_RXD[0..3] EC2_RXD[0..3] 16
EC1_RXD0 AF2 AH8 EC2_RXD0
EC1_RXD1 AF1 EC1_RXD0 EC2_RXD0 AG7 EC2_RXD1
EC1_RXD2 AE1 EC1_RXD1 EC2_RXD1 AH7 EC2_RXD2
EC1_RXD3 AD2 EC1_RXD2 EC2_RXD2 AH6 EC2_RXD3
EC1_RXD3 EC2_RXD3
AG2 AG8
15 EC1_RXCTL EC1_RX_CTL EC2_RX_CTL EC2_RXCTL 16
AD1 AH5
15 EC1_RXCLK EC1_RX_CLK EC2_RX_CLK EC2_RXCLK 16
AG3 AC6
15 EC1_REFCLK EC1_GTX_CLK125 EC2_GTX_CLK125 EC2_REFCLK 16
AC2
AC1 EC1_RX_ER EC1&EC2 OPERATE AT 2.5V EXCEPT EMI2 OPERATES AT 1.8V
EC1_COL
R129 10 AH3 L6 R130 10
15 EMI1_MDC_SLP EMI1_MDC EMI2_MDC EMI2_MDC 21
15 EMI1_MDIO_SLP
AH4
EMI1_MDIO T2081 only { EMI2_MDIO
M6
EMI2_MDIO 21
AC8 AD7 TP3
R131 R132 AB6 TSEC_1588_CLK_IN TSEC_1588_CLK_OUT AF5 TP4 R133 R134
B TSEC_1588_TRIG_IN1 TSEC_1588_ALARM_OUT1 B
AE5 AC7 TP5
2V5_SLP 2V5_SLP 1.5K 4.7K TSEC_1588_TRIG_IN2 TSEC_1588_ALARM_OUT2 AE6 TP8 1V8 510 270
U23 TP6 TP7 TP9 TSEC_1588_PULSE_OUT1 AD8 TP10
1 5 2V5 TSEC_1588_PULSE_OUT2
A VCC 4
2 C 3 2V5_SLP 2V5_SLP T1040
16,17,18,19 EMI1_MDC B GND
74LVC1G66 R138 R135 R136 R137
2V5_SLP C57 C58
U24 1K 4.7K 4.7K 4.7K
1 5 0.1uF 0.1uF
A VCC 4
2 C 3
16,17,18,19 EMI1_MDIO B GND
74LVC1G66
U1B
SerDes
C59 0.1uF AH10 AD10
21 XFI_RX_P SD1_RX0_P 2 of 15 SD1_TX0_P XFI_TX_P 21
C60 0.1uF AG10 AE10
21 XFI_RX_N SD1_RX0_N SD1_TX0_N XFI_TX_N 21
C63 0.1uF AH11 AD11
9 SD_RX1_P SD1_RX1_P SD1_TX1_P SD_TX1_P 9
C64 0.1uF AG11 AE11
9 SD_RX1_N SD1_RX1_N SD1_TX1_N SD_TX1_N 9
C65 0.1uF AH13 AD13
9 SD_RX2_P SD1_RX2_P SD1_TX2_P SD_TX2_P 9
C61 0.1uF AG13 AE13
9 SD_RX2_N SD1_RX2_N SD1_TX2_N SD_TX2_N 9
C C62 0.1uF AH14 AD14 C
19 QSGMII2_RX_P SD1_RX3_P SD1_TX3_P QSGMII2_TX_P 19
C66 0.1uF AG14 AE14
19 QSGMII2_RX_N SD1_RX3_N SD1_TX3_N QSGMII2_TX_N 19
AH16 AD16
22 PEX_RX0_P SD1_RX4_P SD1_TX4_P PEX_TX0_P 22
AG16 AE16
22 PEX_RX0_N SD1_RX4_N SD1_TX4_N PEX_TX0_N 22
AH17 AD17
9 SD_RX5_P SD1_RX5_P SD1_TX5_P SD_TX5_P 9
AG17 AE17
9 SD_RX5_N SD1_RX5_N SD1_TX5_N SD_TX5_N 9
AH19 AD19
9 SD_RX6_P SD1_RX6_P SD1_TX6_P SD_TX6_P 9
AG19 AE19
9 SD_RX6_N SD1_RX6_N SD1_TX6_N SD_TX6_N 9
AH20 AD20
9 SD_RX7_P SD1_RX7_P SD1_TX7_P SD_TX7_P 9
AG20 AE20
9 SD_RX7_N SD1_RX7_N SD1_TX7_N SD_TX7_N 9
C67 0.1uF AB14 AB18
28 SD_REFCLK1_P SD1_REF_CLK1_P SD1_REF_CLK2_P SD_REFCLK2_P 27
C68 0.1uF AA14 AA18
28 SD_REFCLK1_N SD1_REF_CLK1_N SD1_REF_CLK2_N SD_REFCLK2_N 27
TP11 Y15 Y20
TP12 AB15 SD1_PLL1_TPA SD1_IMP_CAL_TX AA12
SD1_PLL1_TPD SD1_IMP_CAL_RX
TP13 Y19
TP14 AB19 SD1_PLL2_TPA R139 R140
SD1_PLL2_TPD 1% 1%
SVDD 200 XVDD 698
T1040

D D

Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 8 of 34


1 2 3 4 5
1 2 3 4 5

SERDES MUX/DEMUX SWITCHs

U25 U26
A A
3 19 3 19
8 SD_TX1_P A0+ B0+ SGMII_TX_P 9,17 8 SD_RX5_N A0+ B0+ PEX_RX1_N 22
4 18 4 18
8 SD_TX1_N A0- B0- SGMII_TX_N 9,17 8 SD_RX5_P A0- B0- PEX_RX1_P 22
15 15
C0+ C0+ MPEX1_RX_N 22
14 14
C0- C0- MPEX1_RX_P 22
7 17 7 17
8 SD_RX1_P A1+ B1+ SGMII_RX_P 9,17 8 SD_TX5_N A1+ B1+ PEX_TX1_N 22
8 16 8 16
8 SD_RX1_N A1- B1- SGMII_RX_N 9,17 8 SD_TX5_P A1- B1- PEX_TX1_P 22
13 13
C1+ C1+ MPEX1_TX_N 22
12 3V3 R142 4.7K 12
C1- C1- MPEX1_TX_P 22
9 2 9 2
SEL PD T2081_EN 9,26,31 26 PEX2_SEL_N SEL PD
3V3 1 5 3V3 1 5
6 VDD GND 11 6 VDD GND 11
10 VDD GND 20 10 VDD GND 20
VDD GND 21 VDD GND 21
C69 C70 C71 EPAD C72 C73 C74 EPAD

0.01uF 0.01uF 0.01uF PI3PCIE3212 0.01uF 0.01uF 0.01uF PI3PCIE3212

B B
U27 U28

3 19 3 19
8 SD_RX2_N A0+ B0+ QSGMII1_RX_N 18 8 SD_RX6_N A0+ B0+ PEX_RX2_N 22
4 18 4 18
8 SD_RX2_P A0- B0- QSGMII1_RX_P 18 8 SD_RX6_P A0- B0- PEX_RX2_P 22
15 15
C0+ SGMII_RX_N 9,17 C0+ MPEX2_RX_N 22
14 14
C0- SGMII_RX_P 9,17 C0- MPEX2_RX_P 22
7 17 7 17
8 SD_TX2_N A1+ B1+ QSGMII1_TX_N 18 8 SD_TX6_N A1+ B1+ PEX_TX2_N 22
8 16 8 16
8 SD_TX2_P A1- B1- QSGMII1_TX_P 18 8 SD_TX6_P A1- B1- PEX_TX2_P 22
13 13
C1+ SGMII_TX_N 9,17 C1+ MPEX2_TX_N 22
R141 4.7K 12 3V3 R143 4.7K 12
C1- SGMII_TX_P 9,17 C1- MPEX2_TX_P 22
9 2 9 2
9,26,31 T2081_EN SEL PD 9,26 PEX4_SEL_N SEL PD
3V3 1 5 3V3 1 5
6 VDD GND 11 6 VDD GND 11
10 VDD GND 20 10 VDD GND 20
VDD GND 21 VDD GND 21
C75 C76 C77 EPAD C78 C79 C80 EPAD

0.01uF 0.01uF 0.01uF PI3PCIE3212 0.01uF 0.01uF 0.01uF PI3PCIE3212


C C

U29

3 19
8 SD_RX7_N A0+ B0+ PEX_RX3_N 22
4 18
8 SD_RX7_P A0- B0- PEX_RX3_P 22
15
C0+ SATA_RX_N 22
14
C0- SATA_RX_P 22
7 17
8 SD_TX7_N A1+ B1+ PEX_TX3_N 22
8 16
8 SD_TX7_P A1- B1- PEX_TX3_P 22
13
C1+ SATA_TX_N 22
12
C1- SATA_TX_P 22
9 2
9,26 PEX4_SEL_N SEL PD
3V3 1 5
6 VDD GND 11
10 VDD GND 20
VDD GND 21
C81 C82 C83 EPAD

D 0.01uF 0.01uF 0.01uF PI3PCIE3212 D

Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 9 of 34


1 2 3 4 5
1 2 3 4 5

T1040 QE INTERFACE

A A

U1N
MISC.
U2 TDMA_RXD
14 of 15 TDMA_RXD TDMA_RSYNC
U1
TDMA_RSYNC T1 TDMA_TXD
TDMA_TXD R1 TDMA_TSYNC
TDMA_TSYNC R2 TDMA_RQ
TDMA_RQ
U4 TDMB_RXD
TDMB_RXD T3 TDMB_RSYNC
TDMB_RSYNC T4 TDMB_TXD
TDMB_TXD R3 TDMB_TSYNC
TDMB_TSYNC R4 TDMB_RQ
TDMB_RQ
P4 TDMA_TCK_CLK9
CLK09 P3 TDMB_RCK_CLK10
CLK10 N4 TDMB_TCK_CLK11
CLK11 M4 TDMA_RCK_CLK8_12
B CLK12 TDM RISER CARD CONNECTOR B

T1040 ONLY!
T1040 12V
J43
TDMB_RXD
TDMA_RQ 1 2
12V 3 4 3V3
TDMA_TXD 5 6
TDMA_TSYNC 7 8
3V3 TDMA_RSYNC 9 10
C1080 C84 C85 TDMA_RXD 11 12
R849 4.7K 13 14 T1040 DVDD: 3.3V
220uF 0.1uF 0.01uF R850 4.7K TDMA_TCK_CLK9 15 16 TDMB_RSYNC
25V R851 4.7K 17 18 TDMB_TXD
R852 4.7K TDMA_RCK_CLK8_12 19 20 TDMB_TSYNC
21 22 TDMB_RQ
3V3 23 24
26 TDMR_SLP_N 25 26 R867 51
26 TDMR_PRS_N TDMB_RCK_CLK10 27 28 SPI_CLK 6,23,24
29 30
26 TDMR1_INT_N 31 32
C92 C93 C94 C1081
26 TDMR2_INT_N 33 34 R868 33
26 TDMR_RST_N 35 36 SPI_MISO 6,23,24
10uF 0.1uF 0.1uF 0.1uF R869 51
TDMB_TCK_CLK11 37 38 SPI_MOSI 6,23,24
C C
39 40
CONN_2X20

3V3
U100
1 5
6 SPI_CS3_N I0 VCC TDMR_SPI_CS0_N
4
2 O 3
26 SPI_CS3_SEL I1 GND
74LVC1G32

3V3
U101
3V3 1 5
I0 VCC 4 TDMR_SPI_CS1_N
R859 4.7K 2 O 3
I1 GND
3

74LVC1G32

Q41
R860 1K 1 IRLML6346

D D
2

Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 10 of 34


1 2 3 4 5
1 2 3 4 5

T1040 USB INTERFACE


3V3_SLP 3V3_SLP

R155 R156 3V3_SLP 3V3_SLP

10K 10K
A R157 0 R158 R159 5V0_SLP U37 A
DNP

3
10K 10K 7
Q3 IN
IRLML6346 USB1_PWREN 1 8 5V0_USB1
1 USB1_FLG_N 2 CTLA OUTA
FLGA
USB2_PWREN 4 5 5V0_USB2

2
USB2_FLG_N 3 CTLB OUTB
FLGB C124 C125 C126 C127 C128 C129
6 R163 D3 R164 D4
R160 0 R161 R162 GND 100uF 10uF 1000pF 1% 100uF 10uF 1000pF 1%
DNP 10V 51.1K CMHD3595 10V 51.1K CMHD3595
3

1K 1K MIC2506YM
Q4
IRLML6346 5V0_SLP 5V0_SLP
1
R165 R166
C130 C131 1% 1%
2

18.2K 18.2K
10uF 0.1uF

B B

R167 0 USB1_VBUS
DNP J41
1 L1 2 USB1_DP 7 5 FB6
U1L BLM21PG121SN1
4 3 USB1_DM 6 5 6 7 8 8 FB7
USB INTERFACES 90ohm BLM21PG121SN1
F5 12 of 15 F6 R168 0 3 1 FB8
USB1_PWRFAULT USB1_DRVVBUS DNP BLM21PG121SN1
F1 R169 0 2 1 2 3 4 4 FB9
USB1_UDP F2 DNP BLM21PG121SN1
USB1_UDM 1 L2 2 USB2_DP USB_A_2

9
10
11
12
E4 USB1_VBUSCLMP
USB1_VBUSCLMP 4 3 USB2_DM USB2_VBUS
F4 90ohm
USB1_UID R170 0
DNP

U38 USB1_VBUS
H5 J5
USB2_PWRFAULT USB2_DRVVBUS 1 6 USB1_DP
C H1 C
USB2_UDP H2 2 5
G4 USB2_UDM
USB_IBIAS_REXT J4 USB2_VBUSCLMP 3 4 USB1_DM
USB2_VBUSCLMP
USB_REFCLK F8 H4
USBCLK USB2_UID VBUS054B-HSF
C1022
DNP R171 T1040 R172 R173
0.1uF 1% 1% 1% USB1&2 FOR HOST MODE U96 USB2_VBUS
10K 49.9 49.9
1 6 USB2_DP
R814
1% 2 5
49.9
DNP 3 4 USB2_DM

VBUS054B-HSF

X1

R174 1K 1 3 R175 33 USB_REFCLK


OVDD_SLP OE OUT
D FB10 C132 USBCLK BELONGS TO O1VDD D
OVDD_OSC_USB 4 2 DNP R176 FOR T1040/T2081, USBCLK OPERATES AT 1.8V
BLM18BD601SN1 VDD GND 10pF DNP FOR INTERPOSER, USBCLK OPERATES AT 3.3V
C133 C134 C135 C136 1K
24MHz,+/-50ppm
0.1uF 0.01uF 1uF 0.1uF Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 11 of 34


1 2 3 4 5
1 2 3 4 5

T1040 POWER SUPPLY


USB_SVDD supply must ramp before or after the
1V35_SLP U1G OVDD 1V35_SLP VCORE U1H USB_HVDD and USB_OVDD supplies have ramped. VCORE_SLP
FB11
POWER #1 POWER #2
D27 J14 K15 K9 1V0_USB_SVDD
F27 G1VDD01 7 of 15 OVDD1 J15 K17 VDD01 8 of 15 USB_SVDD1 K10 BLM18PG121SN1
H27 G1VDD02 OVDD2 J16 C140 C141 C142 C143 C137 C144 C145 C146 K19 VDD02 USB_SVDD2 C147 C148 C138 C149
K21 G1VDD03 OVDD3 J17 L12 VDD03 J8
K27 G1VDD04 OVDD4 J18 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF L14 VDD04 USB_HVDD1 K8 0.1uF 0.1uF 2.2uF 2.2uF
A L21 G1VDD05 OVDD5 J19 L16 VDD05 USB_HVDD2 A
M21 G1VDD06 OVDD6 L18 VDD06 3V3_SLP
M27 G1VDD07 J11 OVDD_SLP L20 VDD07 J9 FB12
N21 G1VDD08 O1VDD1 J12 C150 C151 C152 C153 C154 C155 C156 C157 M9 VDD08 USB_OVDD1 J10 3V3_USB_HVDD
P21 G1VDD09 O1VDD2 J13 M13 VDD09 USB_OVDD2 BLM18PG121SN1
P27 G1VDD10 O1VDD3 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF M15 VDD10 C158 C159 C160 C161 C162
R21 G1VDD11 M17 VDD11
T21 G1VDD12 M19 VDD12 0.1uF 0.1uF 3000pF 2.2uF 2.2uF
U21 G1VDD13 N12 VDD13 USB_OVDD ONLY ON T1040/T2081
U27 G1VDD14 C163 C164 C139 C165 C166 C167 C168 C169 N14 VDD14 OVDD_SLP
W27 G1VDD15 N16 VDD15 FB13
AA27 G1VDD16 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF N18 VDD16 1V8_USB_OVDD
AD27 G1VDD17 N20 VDD17 BLM18PG121SN1
AF27 G1VDD18 P9 VDD18 AB9 C170 C171 C172 C173 C174
2V5 G1VDD19 P11 VDD19 SENSEVDDC
V8 2V5 2V5_SLP DVDD P13 VDD20 AB10 0.1uF 0.1uF 3000pF 2.2uF 2.2uF
W8 LVDD1 DVDD OVDD EVDD P15 VDD21 SENSEGNDC
LVDD2 P17 VDD22
N8 P19 VDD23
DVDD1 P8 C175 C176 C177 C178 C179 C180 C181 C182 C183 C1028 C184 C185 R12 VDD24
DVDD2 VDD25 SENSEVDDC 29
R8 OVDD R14 G19
DVDD3 VDD26 SENSEVDD SENSEGNDC 29
10uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R16
VDD27 SENSEVDD 29
M8 R18 G20 C1106 C1107 C1108
CVDD1 VDD28 SENSEGND SENSEGND 29
2V5_SLP R20
B VDD29 B
T8 EVDD T9 VCORE 22uF 22uF 22uF
U8 L1VDD1 L8 THESE PINs ONLY ON T1040/T2081 T13 VDD30
L1VDD2 EVDD1 LABEL = PROG_SFP OVDD_SLP OVDD T15 VDD31
J9 T17 VDD32
F12 1V8_SFP T19 VDD33 C1109 C186 C187 C188 C189 C904 C905 C906 C907
PROG_SFP U14 VDD34
F11 C192 R177 JMP2 C195 C196 C197 C198 C199 C1011 C1012 U16 VDD35 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
PROG_MTR U18 VDD36
G18 0.1uF 330 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF U20 VDD37
FA_VL V9 VDD38
G9 J10 V13 VDD39 C1110 C908 C909 C910 C911 C912 C913 C914 C915
TH_VDD 1V8_MTR OVDD_SLP V15 VDD40 DNP DNP DNP DNP
P6 1V0_LP V17 VDD41 22uF 22uF 22uF 22uF 22uF 1uF 1uF 1uF 1uF
(T2080 only)
VDD_LP VDD42
C208 R178 JMP2 1V0_LP V19
LABEL = PROG_MTR W14 VDD43
T1040 0.1uF 330 C209 C210 C211 C220 Y8 VDD44
VCORE C256 Y9 VDD45 C1111 C200 C201 C202 C203 C204 C205 C206 C207
J11 10uF 0.1uF 0.1uF 0.1uF Y11 VDD46
SVDD U1I XVDD 1V0_FA_VL 0.1uF VDD47 22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

W15 POWER #3: SerDes AC9 C222 R179 JMP2


S1VDD1 9 of 15 X1VDD1
W16 AC12 LABEL = FA_VDD
W17 S1VDD2 X1VDD2 AC15 0.1uF 330 VCORE_SLP C212 C213 C214 C215 C216 C217 C218 C219
W18 S1VDD3 X1VDD3 AC18 OVDD
C C
W19 S1VDD4 X1VDD4 AC21 K11 T11 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
W20 S1VDD5 X1VDD5 K13 VDDC01 VDDC07 U10
Y13 S1VDD6 L10 VDDC02 VDDC08 U12
S1VDD7 C232 THVDD ONLY ON T1040/T2081 M11 VDDC03 VDDC09 V11
N10 VDDC04 VDDC10 W10 C1029 C1030 C1031 C1032 C1033 C1034 C1035 C1036
T1040 0.1uF R10 VDDC05 VDDC11 W12
VDDC06 VDDC12 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
1V0S 1V35
C1013 C1014 T1040

C223 C224 C225 C226 C227 C228 C229 C230


NFM21PC225B0J3 NFM21PC225B0J3
0.1uF 0.1uF 0.1uF 0.1uF 1500pF 1500pF 1500pF 1500pF

1V8 3V3 OVDD


SVDD VCORE_SLP
R180 0 VIT C1003 C1004 C1005 C1006 C1007 C1008 C1009 C1010
R182 0 VNIT DNP
1500pF 1500pF 1500pF 1500pF 1500pF 1500pF 1500pF 1500pF
C242 C243 C244 C245 C246 C247 C1027 C248 1V8_SLP 3V3_SLP OVDD_SLP C234 C235 C236 C237 C238 C239 C240 C241
DNP DNP DNP DNP
2.2uF 2.2uF 3000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R183 0 VIT 22uF 22uF 22uF 22uF 1uF 1uF 1uF 1uF
R184 0 VNIT
D D
XVDD
C1037 C1038 C1039 C916 C917 C918 C919 C920 C921 C922 C923
DNP DNP DNP
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1500pF 1500pF 1500pF 1500pF
C249 C250 C251 C252 C253 C254 C1026 C255 Title
T1040RDB
2.2uF 2.2uF 3000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
Size Document Number Design Engineer Rev
B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 12 of 34


1 2 3 4 5
1 2 3 4 5

T1040 PLL FILTERs and GROUND


U1J
GROUNDS #1
A2 N15
GND001 10 of 15 GND086
A20 N17
A27 GND002 GND087 N19
B1 GND003 GND088 N22
B4 GND004 GND089 N26
B7 GND005 GND090 P7
A 3V3_SLP B10 GND006 GND091 P10 A
B13 GND007 GND092 P12
B16 GND008 GND093 P14
B19 GND009 GND094 P16
R185 B23 GND010 GND095 P18
B25 GND011 GND096 P20
U1O 4.7K B28 GND012 GND097 P24
C22 GND013 GND098 R7
NC/SPECIAL GND014 GND099
AG28 AH27 C26 R9
NC_DET15 of 15 DEV_DET T2081_DET_N 26
D2 GND015 GND100 R11
G17 (T2081 detect) D20 GND016 GND101 R13
N6 NC01 D21 GND017 GND102 R15
T6 NC02 D24 GND018 GND103 R17
U6 NC03 E5 GND019 GND104 R19
V6 NC04 G6 E7 GND020 GND105 R22
W6 NC05 SPARE1 H6 E10 GND021 GND106 R26
Y6 NC06 SPARE2 J6 E13 GND022 GND107 T2
AA6 NC07 SPARE3 E16 GND023 GND108 T5
AA7 NC08 E19 GND024 GND109 T7
AA8 NC09 E22 GND025 GND110 T10
AA9 NC10 F10 E26 GND026 GND111 T12
AA10 NC11 TH_TPA F15 GND027 GND112 T14
AB8 NC12 F24 GND028 GND113 T16
AB11 NC13 G7 GND029 GND114 T18
B NC14 GND030 GND115 B
AB12 G13 T20
NC15 G16 GND031 GND116 T22
G22 GND032 GND117 T26
T1040 G26 GND033 GND118 U7
H7 GND034 GND119 U9
H8 GND035 GND120 U11 U1K
H9 GND036 GND121 U13
GND037 GND122 GROUNDS #2
LABEL = T1040/T1020 3V3_SLP H10 U15 Y14 E1
D5 H11 GND038 GND123 U17 Y16 S1GND0111 of 15USB_AGND01 E2
R186 510 1 2 H12 GND039 GND124 U19 Y17 S1GND02 USB_AGND02 E3
26 LED_T1040_DET GND040 GND125 S1GND03 USB_AGND03
H13 U24 Y18 F3
GRN H14 GND041 GND126 V7 AA13 S1GND04 USB_AGND04 G1
D6 H15 GND042 GND127 V10 AA15 S1GND05 USB_AGND05 G2
R187 510 1 2 H16 GND043 GND128 V12 AA17 S1GND06 USB_AGND06 G3
26 LED_T2081_DET GND044 GND129 S1GND07 USB_AGND07
H17 V14 AA19 G5
GRN H18 GND045 GND130 V16 AA21 S1GND08 USB_AGND08 H3
LABEL = T2081 H19 GND046 GND131 V18 AB13 S1GND09 USB_AGND09 J1
H20 GND047 GND132 V20 AB17 S1GND10 USB_AGND10 J2
H24 GND048 GND133 V22 AB21 S1GND11 USB_AGND11 J3
J7 GND049 GND134 V26 AF10 S1GND12 USB_AGND12
J22 GND050 GND135 W2 AF11 S1GND13
J26 GND051 GND136 W5 AF12 S1GND14
K2 GND052 GND137 W7 AF13 S1GND15 AC10
THESE PINs ONLY ON T1040/T2081 U1M K5 GND053 GND138 W9 AF14 S1GND16 X1GND01 AC11
C C
OVDD 1V35 K6 GND054 GND139 W11 AF15 S1GND17 X1GND02 AC13
PLL FILTERS GND055 GND140 S1GND18 X1GND03
K7 W13 AF16 AC14
AVDD_CGA1 13 of 15 AVDD_SD1_PLL1 GND056 GND141 S1GND19 X1GND04
R188 5.1 G11 AB16 R189 0.33 K12 W24 AF17 AC16
AVDD_CGA1 AVDD_SD1_PLL1 1% K14 GND057 GND142 Y7 AF18 S1GND20 X1GND05 AC17
C257 C258 C259 C260 C261 K16 GND058 GND143 Y10 AF19 S1GND21 X1GND06 AC19
K18 GND059 GND144 Y12 AF20 S1GND22 X1GND07 AC20
10uF 1uF 3000pF 4.7uF 47uF K20 GND060 GND145 Y22 AG9 S1GND23 X1GND08 AD9
AA16 AGND_SD1_PLL1 R190 0 K24 GND061 GND146 Y26 AG12 S1GND24 X1GND09 AD12
AGND_SD1_PLL1 L7 GND062 GND147 AA11 AG15 S1GND25 X1GND10 AD15
R191 5.1 AVDD_CGA2 G12 AB20 AVDD_SD1_PLL2 R192 0.33 L9 GND063 GND148 AA24 AG18 S1GND26 X1GND11 AD18
AVDD_CGA2 AVDD_SD1_PLL2 1% L11 GND064 GND149 AB2 AG21 S1GND27 X1GND12 AD21
C262 C263 C264 C265 C266 L13 GND065 GND150 AB5 AH9 S1GND28 X1GND13 AE9
L15 GND066 GND151 AB7 AH12 S1GND29 X1GND14 AE12
10uF 1uF 3000pF 4.7uF 47uF L17 GND067 GND152 AB22 AH15 S1GND30 X1GND15 AE15
OVDD_SLP AA20 AGND_SD1_PLL2 R193 0 L19 GND068 GND153 AB26 AH18 S1GND31 X1GND16 AE18
AGND_SD1_PLL2 L22 GND069 GND154 AC24 AH21 S1GND32 X1GND17 AE21
R194 5.1 AVDD_PLAT G10 L26 GND070 GND155 AC26 S1GND33 X1GND18
AVDD_PLAT M7 GND071 GND156 AD4
C267 C268 M10 GND072 GND157 AD6 T1040
M12 GND073 GND158 AD22
10uF 1uF M14 GND074 GND159 AE2
M16 GND075 GND160 AE24
M18 GND076 GND161 AE26
D R195 5.1 AVDD_DDR1 E20 M20 GND077 GND162 AF9 D
AVDD_D1 M24 GND078 GND163 AF21
C269 C270 N2 GND079 GND164 AG1
T1040 N5 GND080 GND165 AG4
10uF 1uF N7 GND081 GND166 AG6
N9 GND082 GND167 AG22 Title
N11 GND083 GND168 AG23 T1040RDB
N13 GND084 GND169 AG26
GND085 GND170 AH2 Size Document Number Design Engineer Rev
GND171 B <Doc> MICETEK A

T1040 Date: Thursday, January 16, 2014 Sheet 13 of 34


1 2 3 4 5
1 2 3 4 5

T1040 DUART and I2C DEVICE INTERFACE


U39 3V3

C271 0.1uF 1 16 C272 0.1uF


C1+ VCC
3 2 C273 0.1uF
C1- V+
A
RS-232 XCVR A
C274 0.1uF 4 6 C275 0.1uF
C2+ V-
5 15
DVDD U40 3V3 C2- GND

17
18
19
J13A
16 13 11 14 R196 100 FB18 RS232_TXD1 A1
VCCA VCCB T1-IN T1-OUT BLM18BD601SN1 A2
1 12 UART1_TXD 12 13 R197 100 FB19 RS232_RXD1 A3
7 PROC_UART1_CTS_N A1 B1 R1-OUT R1-IN
2 11 UART1_RXD BLM18BD601SN1 A4
7 PROC_UART1_RTS_N A2 B2 UART1_RTS_N
3 10 A5
7 PROC_UART1_TXD A3 B3
4 9 UART1_CTS_N 10 7 R198 100 FB20 RS232_RTS1 A6
7 PROC_UART1_RXD A4 B4 T2-IN T2-OUT BLM18BD601SN1 A7
8 5 9 8 R199 100 FB21 RS232_CTS1 A8
6 OE NC1 14 R2-OUT R2-IN BLM18BD601SN1
7 GND NC2 15 C276 C277 C278 C279 RJ45_2X1
GND NC3 MAX3232
100pF 100pF 100pF 100pF
TXBN0304RSV

DVDD 3V3 DVDD 3V3


U41 3V3

C280 C281 C282 C283 C285 0.1uF 1 16 C286 0.1uF


B C1+ VCC B

0.1uF 0.1uF 0.1uF 0.1uF 3 2 C287 0.1uF


C1- V+
RS-232 XCVR
C284 0.1uF 4 6 C288 0.1uF
C2+ V-
5 15
DVDD U42 3V3 C2- GND
J13B
16 13 11 14 R200 100 FB22 RS232_TXD2 B1
VCCA VCCB T1-IN T1-OUT BLM18BD601SN1 B2
1 12 UART2_TXD 12 13 R201 100 FB23 RS232_RXD2 B3
7 PROC_UART2_CTS_N A1 B1 R1-OUT R1-IN
2 11 UART2_RXD BLM18BD601SN1 B4
7 PROC_UART2_RTS_N A2 B2
3 10 UART2_RTS_N B5
7 PROC_UART2_TXD A3 B3 UART2_CTS_N RS232_RTS2
4 9 10 7 R202 100 FB24 B6
7 PROC_UART2_RXD A4 B4 T2-IN T2-OUT BLM18BD601SN1 B7
8 5 9 8 R203 100 FB25 RS232_CTS2 B8
6 OE NC1 14 R2-OUT R2-IN BLM18BD601SN1
7 GND NC2 15 C289 C290 C291 C292 RJ45_2X1

20
21
22
GND NC3 MAX3232
100pF 100pF 100pF 100pF
TXBN0304RSV

C C
For RS232 ESD protection, place close to RJ45 connector
I2C EEPROM U43 DNP
RS232_TXD1 1 16

I2C ADDR = 0x50 RS232_RTS1 2 15

RS232_RXD1 3 14
3V3 U44
RS232_CTS1 4 13
6 7 3V3
3,7,14,29 I2C1_SCL SCL WP RS232_CTS2
5 5 12
3,7,14,29 I2C1_SDA SDA 1
8 A0 2 C293 RS232_RXD2 6 11
4 VCC A1 3
GND A2 0.1uF
I2C THERMAL MONITOR RS232_TXD2 7 10

AT24C256 3V3 3V3 RS232_RTS2 8 9


I2C ADDR = 0x4C
LCDA15C-8
C294
U45 3V3 R853 R204
1000pF
D R205 100 2 1 4.7K 4.7K D
7 TEMP_DIODE_P D+ VDD
R206 100 3
7 TEMP_DIODE_N D- 4
THERM THERM_FAULT_N 26,32
6
ALERT/THERM2 THERM_ALERT_N 26
8
3,7,14,29 I2C1_SCL SCLK
7 5 C295 Title
3,7,14,29 I2C1_SDA SDATA GND T1040RDB
0.1uF
ADT7461 Size Document Number Design Engineer Rev
B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 14 of 34


1 2 3 4 5
1 2 3 4 5

RGMII ETHERNET PORT 1

T2 3V3_SLP
FB29
EC1_MDI0_P 12 13 EC1_MDX0_P
A BLM18BD601SN1 A
C328 0.01uF 10 15 R236 75 C329

EC1_MDI0_N 11 14 EC1_MDX0_N 0.1uF

EC1_MDI1_P 9 16 EC1_MDX1_P
100 ohms
U49 DIFF PAIRs C330 0.01uF 7 18 R237 75 J14B
B1 B9
22 EC1_MDI1_N 8 17 EC1_MDX1_N B2
8 EC1_GTXCLK TXC B3 B10
8 EC1_TXD[0..3] EC1_TXD0 EC1_MDI2_P EC1_MDX2_P
23 1 6 19 B4
EC1_TXD1 24 TXD0 MDI+[0] 2 B5
EC1_TXD2 25 TXD1 MDI-[0] C332 0.01uF 4 21 R240 75 B6 B11
EC1_TXD3 26 TXD2 4 B7
27 TXD3 MDI+[1] 5 EC1_MDI2_N 5 20 EC1_MDX2_N B8 B12
8 EC1_TXCTL TXCTL MDI-[1]
R238 33 19 7 EC1_MDI3_P 3 22 EC1_MDX3_P RJ45_LED_2X1
8 EC1_RXCLK

27
28
C331 10pF DNP RXC MDI+[2] 8
8 EC1_RXD[0..3] EC1_RXD0 MDI-[2]
R239 33 14 C333 0.01uF 1 24 R241 75
EC1_RXD1 R242 33 16 RXD0/SELRGV 10
EC1_RXD2 R243 33 17 RXD1/TXDLY MDI+[3] 11 EC1_MDI3_N 2 23 EC1_MDX3_N
EC1_RXD3 R244 33 18 RXD2/AN0 MDI-[3]
R245 33 13 RXD3/AN1 C334
B 8 EC1_RXCTL RXCTL/PHY_AD2 B
GST5009LF 1000pF
30 34 EC1_LED0 2KV
8 EMI1_MDC_SLP MDC LED0/PHY_AD0
31 35 EC1_LED1
8 EMI1_MDIO_SLP MDIO LED1/PHY_AD1 32 EC1_RXDLY
LED2/RXDLY
26 EC1_RST_N
42 46 R246 33
CKXTAL1 CLK125 EC1_REFCLK 8
43 C335 10pF R247 510
Y2 CKXTAL2 DNP R248 510
R249 100 29 20 R250 0
PHYRST INT EC1_INT_N 7
1 3 C337 C338
R825 0 38 33 R251 0 C336 0.1uF
ENSWREG PME EC1_PME_N 7
C339 C340 R252 470pF 470pF
25MHz 39 12 R253 15 C341 1000pF C342 0.01uF
2

27pF 27pF 4.7K RSET NC DNP DNP


44 48 L4
45 VDDREG REG_OUT 2.2uH
2V5_SLP VDDREG C343 C344
15 28 R826
21 DVDD33 DVDD10 36 4.7uF 0.1uF
37 DVDD33 DVDD10 0 For Gigabit Ethernet protection, place close to magnetics
C346 C347 DVDD33 3
6 AVDD10 9 1V05_EC1_DVDD U50 DNP
0.1uF 0.1uF 41 AVDD33 AVDD10 40
3V3_SLP AVDD33 AVDD10 C348 C349 EC1_MDI0_N 1 6 EC1_MDI1_N
C C
47 49
GND EPAD 0.1uF 0.1uF 2 5

C350 C351 RTL8211E-VB EC1_MDI0_P 3 4 EC1_MDI1_P


R256 1V05_EC1_AVDD
0.1uF 0.1uF 1%
2.49K C353 C354 C355 SRV05-4

0.1uF 0.1uF 0.1uF U51 DNP

3V3_SLP EC1_MDI2_N 1 6 EC1_MDI3_N

2 5

C356 C357 C358 EC1_MDI2_P 3 4 EC1_MDI3_P

4.7uF 0.1uF 0.1uF


SRV05-4
RGMII PHY POWER-ON STRAPPINGs

2V5_SLP 3V3_SLP

EC1_RXD0 R257 4.7K SELRGV 2.5V


D EC1_RXD1 R258 4.7K TXDLY D
EC1_RXD2 R259 4.7K AN0 NWay, advertize all capability
EC1_RXD3 R260 4.7K AN1
EC1_RXCTL R261 4.7K PHY_AD2
EC1_LED0 R262 4.7K PHY_AD0 PHY ADDR = 0x01
EC1_LED1 R263 4.7K PHY_AD1 Title
EC1_RXDLY R264 4.7K RXDLY T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 15 of 34


1 2 3 4 5
1 2 3 4 5

RGMII ETHERNET PORT 2

T1 3V3
FB26
EC2_MDI0_P 12 13 EC2_MDX0_P
A BLM18BD601SN1 A
C296 0.01uF 10 15 R207 75 C297

EC2_MDI0_N 11 14 EC2_MDX0_N 0.1uF

EC2_MDI1_P 9 16 EC2_MDX1_P
100 ohms

25
26
U46 DIFF PAIRs C298 0.01uF 7 18 R208 75 J14A
A1 A9
22 EC2_MDI1_N 8 17 EC2_MDX1_N A2
8 EC2_GTXCLK TXC A3 A10
8 EC2_TXD[0..3] EC2_TXD0 EC2_MDI2_P EC2_MDX2_P
23 1 6 19 A4
EC2_TXD1 24 TXD0 MDI+[0] 2 A5
EC2_TXD2 25 TXD1 MDI-[0] C299 0.01uF 4 21 R210 75 A6 A11
EC2_TXD3 26 TXD2 4 A7
27 TXD3 MDI+[1] 5 EC2_MDI2_N 5 20 EC2_MDX2_N A8 A12
8 EC2_TXCTL TXCTL MDI-[1]
R211 33 19 7 EC2_MDI3_P 3 22 EC2_MDX3_P RJ45_LED_2X1
8 EC2_RXCLK RXC MDI+[2]
C300 10pF DNP 8
8 EC2_RXD[0..3] EC2_RXD0 MDI-[2]
R209 33 14 C301 0.01uF 1 24 R212 75
EC2_RXD1 R213 33 16 RXD0/SELRGV 10
EC2_RXD2 R214 33 17 RXD1/TXDLY MDI+[3] 11 EC2_MDI3_N 2 23 EC2_MDX3_N
EC2_RXD3 R215 33 18 RXD2/AN0 MDI-[3]
R216 33 13 RXD3/AN1 C302
B 8 EC2_RXCTL RXCTL/PHY_AD2 B
GST5009LF 1000pF
30 34 EC2_LED0 2KV
8,17,18,19 EMI1_MDC MDC LED0/PHY_AD0
31 35 EC2_LED1
8,17,18,19 EMI1_MDIO MDIO LED1/PHY_AD1 32 EC2_RXDLY
LED2/RXDLY
26 EC2_RST_N
42 46 R217 33
CKXTAL1 CLK125 EC2_REFCLK 8
43 C303 10pF R218 510
Y1 CKXTAL2 DNP R219 510
R220 100 29 20 R221 0
PHYRST INT EC2_INT_N 7
1 3 C307 C308
R822 0 38 33 R222 0 C306 0.1uF
ENSWREG PME EC2_PME_N 7
C304 C305 R823 470pF 470pF
25MHz 39 12 R224 15 C309 1000pF C310 0.01uF
2

27pF 27pF 4.7K RSET NC DNP DNP


44 48 L3
45 VDDREG REG_OUT 2.2uH
2V5 VDDREG C312 C313
15 28 R824
21 DVDD33 DVDD10 36 4.7uF 0.1uF
37 DVDD33 DVDD10 0 For Gigabit Ethernet protection, place close to magnetics
C314 C315 DVDD33 3
6 AVDD10 9 1V05_EC2_DVDD U47 DNP
0.1uF 0.1uF 41 AVDD33 AVDD10 40
3V3 AVDD33 AVDD10 C316 C317 EC2_MDI0_N 1 6 EC2_MDI1_N
C C
47 49
GND EPAD 0.1uF 0.1uF 2 5

C319 C320 RTL8211E-VB EC2_MDI0_P 3 4 EC2_MDI1_P


R227 1V05_EC2_AVDD
0.1uF 0.1uF 1%
2.49K C321 C322 C323 SRV05-4

0.1uF 0.1uF 0.1uF U48 DNP

3V3 EC2_MDI2_N 1 6 EC2_MDI3_N

2 5

C324 C325 C326 EC2_MDI2_P 3 4 EC2_MDI3_P

4.7uF 0.1uF 0.1uF


SRV05-4
RGMII PHY POWER-ON STRAPPINGs

2V5 3V3

EC2_RXD0 R228 4.7K SELRGV 2.5V


D EC2_RXD1 R229 4.7K TXDLY D
EC2_RXD2 R230 4.7K AN0 NWay, advertize all capability
EC2_RXD3 R231 4.7K AN1
EC2_RXCTL R232 4.7K PHY_AD2
EC2_LED0 R233 4.7K PHY_AD0 PHY ADDR = 0x02
EC2_LED1 R234 4.7K PHY_AD1 Title
EC2_RXDLY R235 4.7K RXDLY T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 16 of 34


1 2 3 4 5
1 2 3 4 5

SGMII ETHERNET PORT


U52

48
GTX_CLK 17
HSOP SGMII_RX_P 9
50 18 100 ohms DIFF PAIR
TXD0 HSON SGMII_RX_N 9
53
A 54 TXD1 22 T3 3V3 A
55 TXD2 HSOP_CK 21 100 ohms FB32
57 TXD3 HSON_CK DIFF PAIRs SG_MDI0_P 12 13 SG_MDX0_P
58 TXD4 BLM18BD601SN1
59 TXD5 C360 0.01uF 10 15 R265 75 C361
60 TXD6 1
49 TXD7 MDIP0 2 SG_MDI0_N 11 14 SG_MDX0_N 0.1uF
61 TXEN/TXCTL MDIN0
TXER 4 SG_MDI1_P 9 16 SG_MDX1_P
56 MDIP1 5

13
TXCLK MDIN1 C362 0.01uF 7 18 R266 75 J42
38 7 1 9
RXC MDIP2 8 SG_MDI1_N 8 17 SG_MDX1_N 2
33 MDIN2 3 10
35 RXD0 10 SG_MDI2_P 6 19 SG_MDX2_P 4
36 RXD1 MDIP3 11 5
2V5 37 RXD2 MDIN3 C363 0.01uF 4 21 R267 75 6 11
2.5V GMII/RGMII R268 4.7K 39 RXD3 7
41 RXD4/SELRGV SG_MDI2_N 5 20 SG_MDX2_N 8 12
42 RXD5/TXDLY 13
R269 4.7K 43 RXD6/RXDLY HSIP 14 SG_MDI3_P 3 22 SG_MDX3_P RJ45_LED

14
NWay, advertize all capability 32 RXD7/AN0 HSIN
R270 4.7K 44 RXDV/RXCTL C364 0.01uF 1 24 R271 75
RXER/AN1
B B
SGMII to Coper R272 4.7K 46 SG_MDI3_N 2 23 SG_MDX3_N
R273 4.7K 45 CRS/MII1
COL/MII0 C365
72 68 GST5009LF 1000pF
8,16,18,19 EMI1_MDC MDC LED0/PHY_AD0
73 69 C366 0.1uF 2KV
8,16,18,19 EMI1_MDIO MDIO LED1/PHY_AD1 SGMII_TX_P 9
70 C367 0.1uF 100 ohms DIFF PAIR
LED2/MDI0 SGMII_TX_N 9
71
LED3/MDI1 3V3
65 64
62 TDI TDO SG_LED0 R274 510
63 TMS SG_LED1 R275 510
TCK R276 4.7K R277 4.7K
26 SG_RST_N
81 86 R278 4.7K R279 4.7K C369 C370
82 CKXTAL1 CLK125 PHY ADDR = 0x03 C368 0.1uF
CKXTAL2 SGMII to Coper R854 4.7K 470pF 470pF
Y3 R280 100 52 75 R281 0 C371 0.01uF
PHYRST INT SG_INT_N 26
1 3 R827 0 77 74
R282 ENSWREG PME
C372 C373 78 28
25MHz 4.7K RSET NC1 29
2

27pF 27pF 26 NC2 30 For Gigabit Ethernet protection, place close to magnetics
REXT NC3 31
NC4 76 R284 15 C374 1000pF U53 DNP
C C
NC5 DNP DNP
84 88 L5 SG_MDI0_N 1 6 SG_MDI1_N
R285 R286 85 VDDREG REG_OUT 4.7uH
1% 1% 2V5 VDDREG 47 C375 C376 2 5
2.49K 12.1K DVDD10 66 R828
34 DVDD10 22uF 0.1uF SG_MDI0_P 3 4 SG_MDI1_P
40 DVDD33 24 0
51 DVDD33 REGV15
3V3 67 DVDD33 3 1V05_SG_DVDD SRV05-4
DVDD33 AVDD10 9
6 AVDD10 12 C377 C378 U54 DNP
25 AVDD33 AVDD10 16
C381 C382 C383 80 AVDD33 AVDD10 23 0.1uF 0.1uF SG_MDI2_N 1 6 SG_MDI3_N
AVDD33 AVDD10 79
0.1uF 0.1uF 0.1uF 15 AVDD10 2 5
19 AGND 83 1V05_SG_AVDD
20 AGND GND 87 SG_MDI2_P 3 4 SG_MDI3_P
27 AGND GND 89 C384 C385 C386 C388 C389 C390
AGND EPAD
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF SRV05-4
RTL8211DN

D 3V3 2V5 D

C391 C392 C393 C1025 C398 C399


Title
22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 17 of 34


1 2 3 4 5
1 2 3 4 5

QSGMII PHY 1
T1040 ONLY!

U55A

D31 B18
A 20 QSG2_MDI0_P P0_D0P P1_D0P QSG1_MDI0_P 20 A
D30 B17
20 QSG2_MDI0_N P0_D0N P1_D0N QSG1_MDI0_N 20
C25 C29 1V0 U55B 2V5
20 QSG2_MDI1_P P0_D1P P1_D1P QSG1_MDI1_P 20
C24 C28
20 QSG2_MDI1_N P0_D1N P1_D1N QSG1_MDI1_N 20
E5 E3
D29 B16 E7 VDD1 VDD25 E4
20 QSG2_MDI2_P P0_D2P P1_D2P QSG1_MDI2_P 20 VDD1 VDD25
C23 B15 E10 E6
20 QSG2_MDI2_N P0_D2N P1_D2N QSG1_MDI2_N 20 VDD1 VDD25
E13 E8
C22 C27 E15 VDD1 VDD25 E12
20 QSG2_MDI3_P P0_D3P P1_D3P QSG1_MDI3_P 20 VDD1 VDD25
C21 C26 E17 E18
20 QSG2_MDI3_N P0_D3N P1_D3N QSG1_MDI3_N 20 VDD1 VDD25
E19 E20
E2 C3 E21 VDD1 VDD25 E22
20 QSG2_LED0 LED0_PHY0 LED0_PHY1 QSG1_LED0 20 VDD1 VDD25
D1 B2 E23 E24
20 QSG2_LED1 LED1_PHY0 LED1_PHY1 QSG1_LED1 20 VDD1 VDD25
D2 C4 1V0 E25 E26 2V5
C2 LED2_PHY0 LED2_PHY1 D4 FB35 VDD1 VDD25 FB36
LED3_PHY0 LED3_PHY1 E1 E27
C33 C1 BLM18PG121SN1 E11 VDD1A VDD25A E29 BLM18PG121SN1
20 QSG4_MDI0_P P2_D0P P3_D0P QSG3_MDI0_P 20 VDD1A VDD25A
C32 C36 E14 E31
20 QSG4_MDI0_N P2_D0N P3_D0N QSG3_MDI0_N 20 VDD1A VDD25A
E16 E33
B20 D35 E28 VDD1A VDD25A E35
20 QSG4_MDI1_P P2_D1P P3_D1P QSG3_MDI1_P 20 VDD1A VDD25A
B19 D34 E30 E37 2V5A_QSG1
20 QSG4_MDI1_N P2_D1N P3_D1N QSG3_MDI1_N 20 VDD1A VDD25A
E32 2V5
A10 C35 E34 VDD1A
20 QSG4_MDI2_P P2_D2P P3_D2P QSG3_MDI2_P 20 VDD1A
A9 C34 E36 E9
B 20 QSG4_MDI2_N P2_D2N P3_D2N QSG3_MDI2_N 20 VDD1A VDDMDIO B

C31 D33 B1 D9
20 QSG4_MDI3_P P2_D3P P3_D3P QSG3_MDI3_P 20 THERMDA VSS/EFUSE
C30 D32 D3 139
20 QSG4_MDI3_N P2_D3N P3_D3N QSG3_MDI3_N 20 THERMDC_VSS VSS_CASE
C5 B4
20 QSG4_LED0 LED0_PHY2 LED0_PHY3 QSG3_LED0 20
D5 C6 F104S8A
20 QSG4_LED1 LED1_PHY2 LED1_PHY3 QSG3_LED1 20
B3 A2
D6 LED2_PHY2 LED2_PHY3 D7
LED3_PHY2 LED3_PHY3 1V0A_QSG1
C400 0.1uF D16 D14
9 QSGMII1_TX_P QSGMII0_TXP QSGMII0_RXP QSGMII1_RX_P 9
C405 0.1uF D15 D13 C401 C402 C403 C404 C406 C407 C1082
9 QSGMII1_TX_N QSGMII0_TXN QSGMII0_RXN QSGMII1_RX_N 9
C410 0.1uF D11 B13 2V5 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
28 QSG1_REFCLK_P REFCLK_P RCVRD_CLK0
C411 0.1uF D12 C20
28 QSG1_REFCLK_N REFCLK_N RCVRD_CLK1
D27
CLK_SQUELCH_IN R855
B8 2V5A_QSG1
REFCLK_SEL[1:0] = 00 for 125MHz clock B7 REFCLK_SEL0 2V5 4.7K
REFCLK_SEL1 C412 C413 C414 C415 C416
C11 C10 R291 0
8,16,17,19 EMI1_MDC MDC MDINT QSG1_INT_N 26
D10 10uF 1uF 0.1uF 0.1uF 0.1uF
8,16,17,19 EMI1_MDIO MDIO
C R292 100 B5 C19 R293 4.7K C
26 QSG1_RST_N RESET PHYADD2 B12 R294 4.7K DNP PHY ADDR = 0x04~07 1V0
D8 PHYADD3 D26 R295 4.7K DNP
COMA_MODE PHYADD4
D19 C17
R296 R297 C14 GPIO0 GPIO8 D22 C420 C421 C422 C423 C424 C425 C1083
D20 GPIO1 GPIO9 D24
2V5 4.7K 4.7K C15 GPIO2 GPIO10 D23 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF
B9 GPIO3 GPIO11 C18
C16 GPIO4 GPIO12 B11
D21 GPIO5 GPIO13 D25 2V5
B10 GPIO6 GPIO14
GPIO7
C9 C8
A3 JTAG_DI JTAG_DO C432 C433 C434 C435 C436 C437 C1084
B6 JTAG_TMS
C7 JTAG_CLK 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF
JTAG_TRST
A8 D17 R724 619
A7 REF_REXT SEDES_REXT_0 D18 1%
REF_FILT SEDES_REXT_1
A1 C12
R302 R303 C440 A4 NC1 HSTST_P/NC C13
1% A5 NC2 HSTST_N/NC D28
D 1K 2K 1uF A6 NC3 TANA_0/NC B14 D
NC4 TANA_1/NC

F104S8A

Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 18 of 34


1 2 3 4 5
1 2 3 4 5

QSGMII PHY 2
T1040 ONLY!

U56A

D31 B18
A 20 QSG6_MDI0_P P0_D0P P1_D0P QSG5_MDI0_P 20 A
D30 B17
20 QSG6_MDI0_N P0_D0N P1_D0N QSG5_MDI0_N 20
C25 C29 1V0 U56B 2V5
20 QSG6_MDI1_P P0_D1P P1_D1P QSG5_MDI1_P 20
C24 C28
20 QSG6_MDI1_N P0_D1N P1_D1N QSG5_MDI1_N 20
E5 E3
D29 B16 E7 VDD1 VDD25 E4
20 QSG6_MDI2_P P0_D2P P1_D2P QSG5_MDI2_P 20 VDD1 VDD25
C23 B15 E10 E6
20 QSG6_MDI2_N P0_D2N P1_D2N QSG5_MDI2_N 20 VDD1 VDD25
E13 E8
C22 C27 E15 VDD1 VDD25 E12
20 QSG6_MDI3_P P0_D3P P1_D3P QSG5_MDI3_P 20 VDD1 VDD25
C21 C26 E17 E18
20 QSG6_MDI3_N P0_D3N P1_D3N QSG5_MDI3_N 20 VDD1 VDD25
E19 E20
E2 C3 E21 VDD1 VDD25 E22
20 QSG6_LED0 LED0_PHY0 LED0_PHY1 QSG5_LED0 20 VDD1 VDD25
D1 B2 E23 E24
20 QSG6_LED1 LED1_PHY0 LED1_PHY1 QSG5_LED1 20 VDD1 VDD25
D2 C4 1V0 E25 E26 2V5
C2 LED2_PHY0 LED2_PHY1 D4 FB37 VDD1 VDD25 FB38
LED3_PHY0 LED3_PHY1 E1 E27
C33 C1 BLM18PG121SN1 E11 VDD1A VDD25A E29 BLM18PG121SN1
20 QSG8_MDI0_P P2_D0P P3_D0P QSG7_MDI0_P 20 VDD1A VDD25A
C32 C36 E14 E31
20 QSG8_MDI0_N P2_D0N P3_D0N QSG7_MDI0_N 20 VDD1A VDD25A
E16 E33
B20 D35 E28 VDD1A VDD25A E35
20 QSG8_MDI1_P P2_D1P P3_D1P QSG7_MDI1_P 20 VDD1A VDD25A
B19 D34 E30 E37 2V5A_QSG2
20 QSG8_MDI1_N P2_D1N P3_D1N QSG7_MDI1_N 20 VDD1A VDD25A
E32 2V5
A10 C35 E34 VDD1A
20 QSG8_MDI2_P P2_D2P P3_D2P QSG7_MDI2_P 20 VDD1A
A9 C34 E36 E9
B 20 QSG8_MDI2_N P2_D2N P3_D2N QSG7_MDI2_N 20 VDD1A VDDMDIO B

C31 D33 B1 D9
20 QSG8_MDI3_P P2_D3P P3_D3P QSG7_MDI3_P 20 THERMDA VSS/EFUSE
C30 D32 D3 139
20 QSG8_MDI3_N P2_D3N P3_D3N QSG7_MDI3_N 20 THERMDC_VSS VSS_CASE
C5 B4
20 QSG8_LED0 LED0_PHY2 LED0_PHY3 QSG7_LED0 20
D5 C6 F104S8A
20 QSG8_LED1 LED1_PHY2 LED1_PHY3 QSG7_LED1 20
B3 A2
D6 LED2_PHY2 LED2_PHY3 D7
LED3_PHY2 LED3_PHY3 1V0A_QSG2
C445 0.1uF D16 D14
8 QSGMII2_TX_P QSGMII0_TXP QSGMII0_RXP QSGMII2_RX_P 8
C454 0.1uF D15 D13 C446 C447 C448 C449 C450 C451 C1085
8 QSGMII2_TX_N QSGMII0_TXN QSGMII0_RXN QSGMII2_RX_N 8
C455 0.1uF D11 B13 2V5 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
28 QSG2_REFCLK_P REFCLK_P RCVRD_CLK0
C456 0.1uF D12 C20
28 QSG2_REFCLK_N REFCLK_N RCVRD_CLK1
D27
CLK_SQUELCH_IN R856
B8 2V5A_QSG2
REFCLK_SEL[1:0] = 00 for 125MHz clock B7 REFCLK_SEL0 2V5 4.7K
REFCLK_SEL1 C457 C458 C459 C461 C462
C11 C10 R312 0
8,16,17,18 EMI1_MDC MDC MDINT QSG2_INT_N 26
D10 10uF 1uF 0.1uF 0.1uF 0.1uF
8,16,17,18 EMI1_MDIO MDIO
C R313 100 B5 C19 R314 4.7K DNP C
26 QSG2_RST_N RESET PHYADD2 B12 R315 4.7K PHY ADDR = 0x08~0B 1V0
D8 PHYADD3 D26 R316 4.7K DNP
COMA_MODE PHYADD4
D19 C17
R317 R320 C14 GPIO0 GPIO8 D22 C465 C466 C467 C468 C469 C470 C1086
D20 GPIO1 GPIO9 D24
2V5 4.7K 4.7K C15 GPIO2 GPIO10 D23 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF
B9 GPIO3 GPIO11 C18
C16 GPIO4 GPIO12 B11
D21 GPIO5 GPIO13 D25 2V5
B10 GPIO6 GPIO14
GPIO7
C9 C8
A3 JTAG_DI JTAG_DO C477 C478 C479 C480 C481 C482 C1087
B6 JTAG_TMS
C7 JTAG_CLK 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF
JTAG_TRST
A8 D17 R725 619
A7 REF_REXT SEDES_REXT_0 D18 1%
REF_FILT SEDES_REXT_1
A1 C12
R323 R324 C485 A4 NC1 HSTST_P/NC C13
1% A5 NC2 HSTST_N/NC D28
D 1K 2K 1uF A6 NC3 TANA_0/NC B14 D
NC4 TANA_1/NC

F104S8A

Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 19 of 34


1 2 3 4 5
1 2 3 4 5

QSGMII ETHERNET PORTs


T1040 ONLY!
T4 2V5_LED T5 2V5_LED

97
98
2 23 QSG5_MDX0_P J15E 2 23 QSG1_MDX0_P J15A
19 QSG5_MDI0_P 18 QSG1_MDI0_P
C491 0.1uF 1 24 R331 75 E1 E9 C490 0.1uF 1 24 R332 75 A1 A9
3 22 QSG5_MDX0_N E2 3 22 QSG1_MDX0_N A2
19 QSG5_MDI0_N QSG5_MDX1_P 18 QSG1_MDI0_N QSG1_MDX1_P
5 20 E3 E10 5 20 A3 A10
19 QSG5_MDI1_P 18 QSG1_MDI1_P
C492 0.1uF 4 21 R333 75 E4 C493 0.1uF 4 21 R334 75 A4
A 6 19 QSG5_MDX1_N E5 6 19 QSG1_MDX1_N A5 A
19 QSG5_MDI1_N QSG5_MDX2_P 18 QSG1_MDI1_N QSG1_MDX2_P
8 17 E6 E11 8 17 A6 A11
19 QSG5_MDI2_P 18 QSG1_MDI2_P
C494 0.1uF 7 18 R335 75 E7 C495 0.1uF 7 18 R336 75 A7
9 16 QSG5_MDX2_N E8 E12 9 16 QSG1_MDX2_N A8 A12
19 QSG5_MDI2_N QSG5_MDX3_P 18 QSG1_MDI2_N QSG1_MDX3_P
11 14 11 14
19 QSG5_MDI3_P 18 QSG1_MDI3_P
C496 0.1uF 10 15 R337 75 RJ45_LED_8 C497 0.1uF 10 15 R338 75 RJ45_LED_8
12 13 QSG5_MDX3_N 12 13 QSG1_MDX3_N
19 QSG5_MDI3_N 18 QSG1_MDI3_N
R339 510 R340 510
19 QSG5_LED0 18 QSG1_LED0
GST5009LF C498 1000pF R341 510 GST5009LF C499 1000pF R342 510
19 QSG5_LED1 18 QSG1_LED1
2KV 2KV
C500 470pF C501 470pF
C502 470pF C503 470pF

T6 2V5_LED T7 2V5_LED
2 23 QSG6_MDX0_P J15F 2 23 QSG2_MDX0_P J15B
19 QSG6_MDI0_P 18 QSG2_MDI0_P
C504 0.1uF 1 24 R343 75 F1 F9 C505 0.1uF 1 24 R344 75 B1 B9
3 22 QSG6_MDX0_N F2 3 22 QSG2_MDX0_N B2
19 QSG6_MDI0_N 18 QSG2_MDI0_N
5 20 QSG6_MDX1_P F3 F10 5 20 QSG2_MDX1_P B3 B10
19 QSG6_MDI1_P 18 QSG2_MDI1_P
C506 0.1uF 4 21 R345 75 F4 C507 0.1uF 4 21 R346 75 B4
6 19 QSG6_MDX1_N F5 6 19 QSG2_MDX1_N B5
19 QSG6_MDI1_N 18 QSG2_MDI1_N
8 17 QSG6_MDX2_P F6 F11 8 17 QSG2_MDX2_P B6 B11
19 QSG6_MDI2_P 18 QSG2_MDI2_P
C508 0.1uF 7 18 R347 75 F7 C509 0.1uF 7 18 R348 75 B7
9 16 QSG6_MDX2_N F8 F12 9 16 QSG2_MDX2_N B8 B12
B 19 QSG6_MDI2_N QSG6_MDX3_P 18 QSG2_MDI2_N QSG2_MDX3_P
B
11 14 11 14
19 QSG6_MDI3_P 18 QSG2_MDI3_P
C510 0.1uF 10 15 R349 75 RJ45_LED_8 C511 0.1uF 10 15 R350 75 RJ45_LED_8
12 13 QSG6_MDX3_N 12 13 QSG2_MDX3_N
19 QSG6_MDI3_N 18 QSG2_MDI3_N
R351 510 R352 510
19 QSG6_LED0 18 QSG2_LED0
GST5009LF C512 1000pF R353 510 GST5009LF C513 1000pF R354 510
19 QSG6_LED1 18 QSG2_LED1
2KV 2KV
C514 470pF C515 470pF
C516 470pF C517 470pF

T8 2V5_LED T9 2V5_LED
2 23 QSG7_MDX0_P J15G 2 23 QSG3_MDX0_P J15C
19 QSG7_MDI0_P 18 QSG3_MDI0_P
C518 0.1uF 1 24 R355 75 G1 G9 C519 0.1uF 1 24 R356 75 C1 C9
3 22 QSG7_MDX0_N G2 3 22 QSG3_MDX0_N C2
19 QSG7_MDI0_N QSG7_MDX1_P 18 QSG3_MDI0_N QSG3_MDX1_P
5 20 G3 G10 5 20 C3 C10
19 QSG7_MDI1_P 18 QSG3_MDI1_P
C520 0.1uF 4 21 R357 75 G4 C521 0.1uF 4 21 R358 75 C4
6 19 QSG7_MDX1_N G5 6 19 QSG3_MDX1_N C5
19 QSG7_MDI1_N QSG7_MDX2_P 18 QSG3_MDI1_N QSG3_MDX2_P
8 17 G6 G11 8 17 C6 C11
19 QSG7_MDI2_P 18 QSG3_MDI2_P
C522 0.1uF 7 18 R359 75 G7 C523 0.1uF 7 18 R360 75 C7
9 16 QSG7_MDX2_N G8 G12 9 16 QSG3_MDX2_N C8 C12
19 QSG7_MDI2_N QSG7_MDX3_P 18 QSG3_MDI2_N QSG3_MDX3_P
11 14 11 14
19 QSG7_MDI3_P 18 QSG3_MDI3_P
C524 0.1uF 10 15 R361 75 RJ45_LED_8 C525 0.1uF 10 15 R362 75 RJ45_LED_8
12 13 QSG7_MDX3_N 12 13 QSG3_MDX3_N
19 QSG7_MDI3_N 18 QSG3_MDI3_N
C R363 510 R364 510 C
19 QSG7_LED0 18 QSG3_LED0
GST5009LF C526 1000pF R365 510 GST5009LF C527 1000pF R366 510
19 QSG7_LED1 18 QSG3_LED1
2KV 2KV
C528 470pF C529 470pF
C530 470pF C531 470pF

T10 2V5_LED T11 2V5_LED


2 23 QSG8_MDX0_P J15H 2 23 QSG4_MDX0_P J15D
19 QSG8_MDI0_P 18 QSG4_MDI0_P
C532 0.1uF 1 24 R367 75 H1 H9 C533 0.1uF 1 24 R368 75 D1 D9
3 22 QSG8_MDX0_N H2 3 22 QSG4_MDX0_N D2
19 QSG8_MDI0_N QSG8_MDX1_P 18 QSG4_MDI0_N QSG4_MDX1_P
5 20 H3 H10 5 20 D3 D10
19 QSG8_MDI1_P 18 QSG4_MDI1_P
C534 0.1uF 4 21 R369 75 H4 C535 0.1uF 4 21 R370 75 D4
6 19 QSG8_MDX1_N H5 6 19 QSG4_MDX1_N D5
19 QSG8_MDI1_N 18 QSG4_MDI1_N
8 17 QSG8_MDX2_P H6 H11 8 17 QSG4_MDX2_P D6 D11
19 QSG8_MDI2_P 18 QSG4_MDI2_P
C536 0.1uF 7 18 R371 75 H7 C537 0.1uF 7 18 R372 75 D7
9 16 QSG8_MDX2_N H8 H12 9 16 QSG4_MDX2_N D8 D12
19 QSG8_MDI2_N QSG8_MDX3_P 18 QSG4_MDI2_N QSG4_MDX3_P
11 14 11 14
19 QSG8_MDI3_P 18 QSG4_MDI3_P
C538 0.1uF 10 15 R373 75 RJ45_LED_8 C539 0.1uF 10 15 R374 75 RJ45_LED_8
99
100

12 13 QSG8_MDX3_N 12 13 QSG4_MDX3_N C540 470pF


19 QSG8_MDI3_N 18 QSG4_MDI3_N
R375 510
18 QSG4_LED0
GST5009LF C541 1000pF GST5009LF C542 1000pF R376 510
18 QSG4_LED1
2KV 2KV C543 470pF
R377 510 C544 0.01uF
19 QSG8_LED0
D R378 510 D
19 QSG8_LED1
2V5 2V5_LED C545 0.01uF
FB39 C546 470pF
C547 470pF C548 0.01uF
BLM18BD601SN1
C549 C551 C552 C550 0.01uF Title
T1040RDB
0.1uF 4.7uF 0.01uF C553 0.01uF
Size Document Number Design Engineer Rev
B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 20 of 34


1 2 3 4 5
1 2 3 4 5

10G EDC PHY and SFP+ CONNECTOR


T2081 ONLY!
1V0
100 ohms U57A 100 ohms
DIFF PAIRs DIFF PAIRs
C554 0.1uF A7 L8 SFPP_TX_P
8 XFI_TX_P XTX1_DINP TX1_DOUTP SFPP_TX_N
C555 0.1uF A8 L7 C556 C557 C558 C559 C560 C561 C562 C563 C903 C1088 C1089 C1090 C1091
8 XFI_TX_N XTX1_DINN TX1_DOUTN
A C6 22uF 22uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF A
TX_CLKOUT1
A10 L10 SFPP_RX_P
8 XFI_RX_P XRX1_DOUTP RX1_DINP
A11 L11 SFPP_RX_N 1V8
8 XFI_RX_N XRX1_DOUTN RX1_DINN
NO VIAs G10 D11 NO VIAs
USE SFP+ RX LOS SIGNAL RX1_LOS RX_CLKOUT1 1V0 U57B
C7 C566 C567 C568 C569 C570 C571 C1092 C1093 C1094
E11 GPIO1_1 D6 A3
GPIO2_1 22uF 22uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF F6 DIGVDD DIGVSS A6
C564 0.1uF A1 L2 1V8 F7 DIGVDD DIGVSS A9
C565 0.1uF A2 XTX2_DINP TX2_DOUTP L1 DIGVDD DIGVSS E6
XTX2_DINN TX2_DOUTN D7 DIGVSS E7
J2 G2 V2P5 DIGVSS
TX_CLKOUT2 1V8 USE 1.8V IO H11 V2P5 B7
PHY #2 UNUSED! A4 L4 C572 0.1uF FB40 V2P5 TX1VSS B8
A5 XRX2_DOUTP RX2_DINP L5 C573 0.1uF 1V8_XG_AV J8 TX1VSS G7
XRX2_DOUTN RX2_DINN BLM18PG121SN1 J9 AV1P8 TX1VSS H8
H1 J3 C1018 C576 C577 C899 AV1P8 TX1VSS K6
RX2_LOS RX_CLKOUT2 C8 TX1VSS K7
D3 0.1uF 22uF 1uF 1uF C9 AV1P8RX TX1VSS K8
J11 GPIO1_2 1V8 AV1P8RX TX1VSS L6
GPIO2_2 FB41 TX1VSS
C574 0.1uF C1 C2 1V8_XG_RX J4 B1
B 28 XG_REFCLK_P REFCLKP NC1 BV1P8 TX2VSS B
C575 0.1uF D1 E3 1V8 BLM18PG121SN1 J5 B2
28 XG_REFCLK_N REFCLKN NC2 BV1P8 TX2VSS
C1019 C578 C579 C900 D2
G1 F2 R379 4.7K C4 TX2VSS E1
8 EMI2_MDC MDC MADDR1 BV1P8RX TX2VSS
F1 E2 R380 4.7K 0.1uF 22uF 1uF 1uF C5 H4
8 EMI2_MDIO MDIO MADDR2 BV1P8RX TX2VSS
H2 R381 4.7K PHY ADDR = 0x0C 1V0 H5
R382 4.7K H3 MADDR3 F3 R383 4.7K FB42 TX2VSS K1
1V8 SCL MADDR4 TX2VSS
R385 4.7K G3 1V0_XG_TX E8 K2
SDA B6 R384 4.7K BLM18PG121SN1 E9 TX1VDD TX2VSS
R386 100 H10 MICROSEL E10 R387 4.7K MDIO INTERFACE C1020 C580 C901 C581 C582 J7 TX1VDD B9
26 XG_RST_N RESET MDIOSEL TX1VDD RX1VSS
1V0 B10
J6 R389 4.7K 1.8/2.5V IO 0.1uF 22uF 1uF 1uF 1uF RX1VSS B11
R388 IO_VDD_SEL 1V0 E4 RX1VSS D8
D10 G11 FB43 E5 TX2VDD RX1VSS D9
1V8 4.7K C10 TDI TDO 1V0_XG_RX J1 TX2VDD RX1VSS F8
F11 TMS BLM18PG121SN1 TX2VDD RX1VSS F9
F10 TCK C1021 C583 C902 C584 C585 RX1VSS H9
TRST C11 RX1VSS K10
0.1uF 22uF 1uF 1uF 1uF G5 RX1VDD RX1VSS K11
CS4315 G9 RX1VDD RX1VSS L9
U58 DNP H7 RX1VDD RX1VSS
J10 RX1VDD B3
7 6 3V3 3V3 3V3 3V3 K9 RX1VDD RX2VSS B4
WP SCL 5 1V8 C587 C588 C589 RX1VDD RX2VSS B5
1 SDA RX2VSS D4
C C
2 A0 8 I2C ADDR = 0x50,51 1uF 1uF 1uF C3 RX2VSS D5
3 A1 VCC 4 R390 R391 R392 R393 G4 RX2VDD RX2VSS F4
A2 GND C586 G8 RX2VDD RX2VSS F5
J16 4.7K 4.7K 4.7K 4.7K H6 RX2VDD RX2VSS G6
AT24C64 0.1uF 3V3 3V3 K3 RX2VDD RX2VSS K4
6 RX2VDD RX2VSS K5
MOD_DEF(0)/DET SFPP_DET_N 26 RX2VSS
FOR DEBUG ONLY! 5 L3
MOD_DEF(1)/SCL I2C2_SFPP_SCL 7 RX2VSS

2
4
MOD_DEF(2)/SDA I2C2_SFPP_SDA 7
D36 D37
3V3 8 GRN GRN CS4315
RX_LOS SFPP_RXLOS 26
FB44
3V3_SFPP_VDDR 15 13 SFPP_RX_P
BLM21PG121SN1 VDDR RX_DAT+

1
C590 C591 C592 C593 12 SFPP_RX_N
10 RX_DAT- R394 510
RGND 26 XG_LED0
0.1uF 0.01uF 22uF 0.1uF 11 RX+/- AC COUPLING INSIDE THE MODULE R395 510
RGND 26 XG_LED1
14 TX+/- AC COUPLING INSIDE THE MODULE
RGND 3V3 3V3
1 J17
17 TGND
20 TGND 1 20
3V3 TGND 18 SFPP_TX_P R396 R397 2 MH1 MH20 19
FB45 TX_DAT+ 3 MH2 MH19 18
D 3V3_SFPP_VDDT 16 19 SFPP_TX_N 4.7K 4.7K 4 MH3 MH18 17 D
BLM21PG121SN1 VDDT TX_DAT- 5 MH4 MH17 16
C594 C595 C596 C597 7 2 6 MH5 MH16 15
RS0 TX_FAULT SFPP_TXFAIL 26 MH6 MH15
9 3 7 14
RS1 TX_DIS SFPP_TXDIS 26 MH7 MH14
0.1uF 0.01uF 22uF 0.1uF 8 13
9 MH8 MH13 12 Title
3V3 SFP+_CONN 10 MH9 MH12 11 T1040RDB
MH10 MH11
R845 4.7K R846 4.7K DNP Size Document Number Design Engineer Rev
R847 4.7K R848 4.7K DNP SFP_CAGE B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 21 of 34


1 2 3 4 5
1 2 3 4 5

PCIe X1/X4 SLOT, MINI PCIe and SATA CONNECTORs

MINI PCIe CONNECTOR 3V3


PCIe x1/x4 SLOT
3V3 J19 R398 4.7K
T1040: PCIe x1 R404 4.7K
T2081: PCIe x4 2 30
3.3V SMB_CLK I2C2_MPEX1_SCL 7
52 32
A 3.3V SMB_DATA I2C2_MPEX1_SDA 7 A
12V J18 3V3
1V5 24 1 R399 4.7K
B1 B9 R400 4.7K 3.3VAUX WAKE
B2 +12V JTAG1_TRST A5 R401 4.7K 6 22
+12V JTAG2_TCK 1.5V PERST MPEX1_RST_N 26
A2 A6 R402 4.7K 28
A3 +12V JTAG3_TDI A7 48 1.5V 7
3V3 3V3 B3 +12V JTAG4_TDO A8 R403 4.7K 1.5V CLKREQ
+12V JTAG5_TMS 13
REFCLK+ MPEX1_REFCLK_N 27
B8 11
+3V3 REFCLK- MPEX1_REFCLK_P 27
A9
R405 A10 +3V3 3V3 4 25
+3V3 GND PERP0 MPEX1_RX_P 9
9 23
GND PERN0 MPEX1_RX_N 9
4.7K B10 R406 4.7K 15
+3V3AUX R407 4.7K 18 GND 33 C598 0.1uF
GND PETP0 MPEX1_TX_P 9
A1 B5 21 31 C599 0.1uF
PRSNT1 SMCLK I2C2_PEX_SCL 7 GND PETN0 MPEX1_TX_N 9
B17 B6 26
26 PEX_PRS_N PRSNT2_X1 SMDAT I2C2_PEX_SDA 7 GND
27 38 100 ohms
B12 B11 R408 4.7K 29 GND USB_D+ 36 DIFF PAIRs
RSVD1 WAKE 34 GND USB_D-
B4 A11 35 GND 42 3V3
GND PERST PEX_RST_N 26 GND LED_WWAN
A4 40 44
B7 GND A13 50 GND LED_WLAN 46
GND REFCLK+ PEX_REFCLK_P 27 GND LED_WPAN
A12 A14
GND REFCLK- PEX_REFCLK_N 27
B13 3 20 C600 C601 C602 C603 C604 C605
B GND RSVD1 RSVD10 B
A15 A16 5 37
GND PERP0 PEX_RX0_P 8 RSVD2 RSVD11
B16 A17 8 39 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF
GND PERN0 PEX_RX0_N 8 RSVD3 RSVD12
B18 10 41
A18 GND B14 C606 0.1uF 12 RSVD4 RSVD13 43
GND PETP0 PEX_TX0_P 8 RSVD5 RSVD14
B15 C607 0.1uF 14 45 1V5
PETN0 PEX_TX0_N 8 RSVD6 RSVD15
END OF X1 16 47
B31 A21 17 RSVD7 RSVD16 49
PRSNT2_X4 PERP1 PEX_RX1_P 9 RSVD8 RSVD17
A19 A22 19 51
RSVD2 PERN1 PEX_RX1_N 9 RSVD9 RSVD18
B30 C609 C610 C611 C612 C613 C614
A32 RSVD3 B19 C608 0.1uF 53 54
RSVD4 PETP1 PEX_TX1_P 9 MS1 MS2
B20 C615 0.1uF 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF
PETN1 PEX_TX1_N 9
A20
B21 GND A25 MINIPCIE_CONN
GND PERP2 PEX_RX2_P 9
B22 A26
GND PERN2 PEX_RX2_N 9
A23 MINI PCIe CONNECTOR 3V3
A24 GND B23 C616 0.1uF
GND PETP2 PEX_TX2_P 9
B25 B24 C617 0.1uF 3V3 J20 R409 4.7K
GND PETN2 PEX_TX2_N 9
B26 R410 4.7K
A27 GND A29 2 30
GND PERP3 PEX_RX3_P 9 3.3V SMB_CLK I2C2_MPEX2_SCL 7
A28 A30 52 32
GND PERN3 PEX_RX3_N 9 3.3V SMB_DATA I2C2_MPEX2_SDA 7
B29
A31 GND B27 C618 0.1uF 1V5 24 1 R411 4.7K
GND PETP3 PEX_TX3_P 9 3.3VAUX WAKE
B32 B28 C619 0.1uF
GND PETN3 PEX_TX3_N 9
C END OF X4 6 22 C
1.5V PERST MPEX2_RST_N 26
100 ohms 28
PCIE_X4 DIFF PAIRs 48 1.5V 7
1.5V CLKREQ
12V 3V3 13
REFCLK+ MPEX2_REFCLK_N 27
11
REFCLK- MPEX2_REFCLK_P 27
4 25
GND PERP0 MPEX2_RX_P 9
C620 C621 C622 C623 C624 C625 C626 C627 C628 C629 9 23
GND PERN0 MPEX2_RX_N 9
15
100uF 10uF 10uF 0.1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 18 GND 33 C630 0.1uF
GND PETP0 MPEX2_TX_P 9
25V M3 M4 M5 M6 21 31 C631 0.1uF
GND PETN0 MPEX2_TX_N 9
26
27 GND 38 100 ohms
29 GND USB_D+ 36 DIFF PAIRs
34 GND USB_D-
35 GND 42
ON-BOARD SATA CONNECTOR M7 M9 M10 M8 40 GND LED_WWAN 44
J21 50 GND LED_WLAN 46
T1040 ONLY! GND LED_WPAN
3 20
1 5 RSVD1 RSVD10 37
C632 0.01uF 2 GND 8 RSVD2 RSVD11 39
9 SATA_TX_P TX_P RSVD3 RSVD12
C633 0.01uF 3 M13 M11 M14 M12 10 41
9 SATA_TX_N TX_N RSVD4 RSVD13
D 4 12 43 D
C634 0.01uF 5 GND 14 RSVD5 RSVD14 45
9 SATA_RX_N RX_N RSVD6 RSVD15
C635 0.01uF 6 16 47
9 SATA_RX_P RX_P RSVD7 RSVD16
7 17 49
100 ohms GND 19 RSVD8 RSVD17 51
DIFF PAIRs 8 M15 M16 M17 M18 RSVD9 RSVD18 Title
9 MH1 53 54 T1040RDB
MH2 MS1 MS2
Size Document Number Design Engineer Rev
SATA_CONN MINIPCIE_CONN B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 22 of 34


1 2 3 4 5
1 2 3 4 5

POTS 1&2 INTERFACE


T1040 ONLY!

25 POTS_SWOUT
25 POTS_SWIS
25 POTSA_SWVSY
U59
A 25 POTS_SWCMP A
21 13 R716 200K R412 200K
3V3 3V3 3V3 19 SWOUTY TDC1 14 R717 200K R413 200K
18 SWISY RDC1
20 SWVSY C636 0.1uF
SWCMPY 200V F1
R857 R428 R420 11 C637 0.068uF R414 3.01K 3A/60V
TAC1 100V 1% J22A
4.7K 4.7K 4.7K 12 C638 0.068uF R416 3.01K C639 U60
RAC1 100V 1% 1 8 A6
R417 51 30 0.022uF A5
7,24 POTS_TDM_CLK PCLK/DCL POTS1_TIP
R418 51 26 100V 2 7 A4
7,24 POTS_TDM_FS FS/FSC
R421 51 29 3 6 POTS1_RING A3
7,24 POTS_TDM_TXD DRA/DD
R422 33 28 77 A2
7,24 POTS_TDM_RXD DXA/DU TIPD1
27 C640 4 5 A1
TSCA
R423 51 34 0.022uF TISP61089B F2
6,10,24 SPI_MOSI DIN/S1
R419 33 35 71 100V 3A/60V RJ11_6P_2
6,10,24 SPI_MISO DOUT RINGD1
R425 51 33
6,10,24 SPI_CLK DCLK/S0
36 VBATH
6 POTSA_SPI_CS_N CS/PG
31 F3
26 POTSA_INT_N INT/S2
R426 100 32 67 3A/60V
24 POTS_RST_N RST TIPD2 J22B
24 C641 U61
B I/O11 B
22 1 8 B6
I/O21 61 0.022uF B5
38 RINGD2 100V 2 7 POTS2_TIP B4
40 I/O12 3 6 POTS2_RING B3
I/O22 B2
VBATH C643 4 5 B1
50 C642 0.068uF R429 3.01K
VBATL R430 402K 45 TAC2 100V 1% 0.022uF TISP61089B F4
1% XB 49 C644 0.068uF R431 3.01K 100V 3A/60V RJ11_6P_2
R433 402K RAC2 100V 1%
1% DNP 41 C645 0.1uF
43 SWOUTZ 200V
44 SWISZ 47 R718 200K R434 200K
25 POTSA_SWVSZ SWVSZ RDC2
42 48 R719 200K R435 200K
SWCMPZ TDC2
R436 47.5K 9 52 R437 47.5K
1% RTV1 RTV2 1%
6 55
RSN1 RSN2
C646 10uF 17 16
VREF IREF
C647 4.7uF 10 15 3V3 3V3
IHL1 LFC1
C C648 4.7uF 51 46 C
IHL2 LFC2

2
R438
2 70 C649 D38 D39
4 RSVD1 RSVD10 72 DNP 75K GRN GRN
59 RSVD2 RSVD11 73 0.1uF 1%
62 RSVD3 RSVD12 74
63 RSVD4 RSVD13 75

1
64 RSVD5 RSVD14 76
65 RSVD6 RSVD15 78 R439 510
RSVD7 RSVD16 26 FXS1_LED
66 80 R440 510
RSVD8 RSVD17 26 FXS2_LED
VBATL VBATH 68
RSVD9
3
VBH
C650 C651 1
60 VBM1 81
0.1uF 0.1uF VBM2 EPAD
100V 200V 79 5
69 VBL1 BGND1 58
VBL2 BGND2
3V3 25 23
37 DVDD DGND 39
DVDD DGND
7 8
D C652 C653 C654 C655 C656 C657 54 AVDD AGND 53 D
57 AVDD AGND 56
4.7uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF AVDD AGND

Le88266DLC
Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 23 of 34


1 2 3 4 5
1 2 3 4 5

POTS 3&4 INTERFACE


T1040 ONLY!

U63
A 25 POTSB_SWVSY A
21 13 R720 200K R441 200K
3V3 3V3 19 SWOUTY TDC1 14 R721 200K R451 200K J23A
18 SWISY RDC1
20 SWVSY C658 0.1uF A6
SWCMPY 200V F5 A5
R858 R442 11 C659 0.068uF R452 3.01K 3A/60V FXS_TIP A4
TAC1 100V 1% FXS_RING A3
4.7K 4.7K 12 C660 0.068uF R444 3.01K C661 U62 A2
RAC1 100V 1% 1 8 A1
R445 51 30 0.022uF
7,23 POTS_TDM_CLK PCLK/DCL POTS3_TIP
R446 51 26 100V 2 7
7,23 POTS_TDM_FS FS/FSC
R447 51 29 3 6 POTS3_RING RJ11_6P_2
7,23 POTS_TDM_TXD DRA/DD
R448 33 28 77
7,23 POTS_TDM_RXD DXA/DU TIPD1
27 C662 4 5
TSCA
R453 51 34 0.022uF TISP61089B F6
6,10,23 SPI_MOSI DIN/S1
R449 33 35 71 100V 3A/60V
6,10,23 SPI_MISO DOUT RINGD1
R450 51 33
6,10,23 SPI_CLK DCLK/S0
36 VBATH
6 POTSB_SPI_CS_N CS/PG
31 F7
26 POTSB_INT_N INT/S2
R455 100 32 67 3A/60V
23 POTS_RST_N RST TIPD2 J23B
LIFELINE 24 C664 U64
B I/O11 B
22 1 8 B6
I/O21 61 0.022uF B5
38 RINGD2 100V 2 7 POTS4_TIP B4
40 I/O12 3 6 POTS4_RING B3
I/O22 B2
VBATH C667 4 5 B1
50 C666 0.068uF R459 3.01K
VBATL R460 402K 45 TAC2 100V 1% 0.022uF TISP61089B F8
1% XB 49 C668 0.068uF R461 3.01K 100V 3A/60V RJ11_6P_2
R463 402K RAC2 100V 1%
1% DNP 41 C669 0.1uF
43 SWOUTZ 200V
44 SWISZ 47 R722 200K R464 200K
25 POTSB_SWVSZ SWVSZ RDC2
42 48 R723 200K R465 200K
SWCMPZ TDC2 J24
R466 47.5K 9 52 R467 47.5K
1% RTV1 RTV2 1% 3V3
6 55 J25 4
RSN1 RSN2 9 FXO_TIP FXO_TIP 3
C670 10uF 17 16 FXS_TIP 8 FXO_RING 2
VREF IREF R468 7 POTS3_TIP 1
C671 4.7uF 10 15 2 FXO_RING
IHL1 LFC1 10 FXS_RING 3
C C672 4.7uF 51 46 4 POTS3_RING C
IHL2 LFC2 R469 1 5 RJ11_4P
2 70 C673 10 6
4 RSVD1 RSVD10 72 DNP 75K D22 RB521
59 RSVD2 RSVD11 73 0.1uF 1% TQ2-3V
62 RSVD3 RSVD12 74 LIFELINE
63 RSVD4 RSVD13 75
64 RSVD5 RSVD14 76
65 RSVD6 RSVD15 78 3V3 3V3 3V3
66 RSVD7 RSVD16 80
VBATL VBATH 68 RSVD8 RSVD17
RSVD9

2
3 D40 D41 D42
VBH GRN GRN GRN
C674 C675 1
60 VBM1 81
0.1uF 0.1uF VBM2 EPAD

1
100V 200V 79 5 R470 510
VBL1 BGND1 26 FXO_LED
69 58 R471 510
VBL2 BGND2 26 FXS3_LED
R472 510
26 FXS4_LED
3V3 25 23
37 DVDD DGND 39
DVDD DGND
7 8
D C676 C677 C678 C679 C680 C681 54 AVDD AGND 53 D
57 AVDD AGND 56
4.7uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF AVDD AGND

Le88266DLC
Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 24 of 34


1 2 3 4 5
1 2 3 4 5

POTS VBAT POWER SUPPLY


T1040 ONLY!

A A

R473 402K 1% C682 4700pF

C683 4.7pF
23 POTS_SWCMP
DNP
C684

330pF R474 402K 1%


23 POTSA_SWVSY
R475 402K 1% DNP
R476 402K 1%
24 POTSB_SWVSY
R477 402K 1% DNP VBH VBATH
R478 402K 1% L6 D25
23 POTSA_SWVSZ
R479 402K 1%
24 POTSB_SWVSZ
220uH
12V C685 R480 R481ES1D-13-F
FB46 D26
12V_POTS 1 T12 10 VBH1 VBH2 0.1uF 200K 200K
BLM21PG121SN1 200V
B B
C686 C687 C688 D27 MURS120-13-F C689
R482 R484 R483 BAW56-7-F 2 9
0.1uF 470uF 0.1uF 1 2 3 100uF VBATL
25V 1.8K 1.8K 1.8K D28 100V L7
8 VBL1 VBL2

3
C690 1000pF 4 100uH
100V 5 MURS120-13-F C691 C692 C693 C694
6 7
C695 C8140 82uF 82uF 1uF 0.1uF
R485 50V 50V 50V 100V
0.1uF
1.8K

3
1 Q5
MMBT2907A
Q6

3
C696 R486 10 1 IRLZ24NSPBF

470pF 3

2
R487 R488 1K
POTS_SWIS 23
R490 Q7
R489 0 10 1 FDV301N 13K
23 POTS_SWOUT
R491 C697
C C
2

R493 0.02 220pF


2%
13K

D D

Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 25 of 34


1 2 3 4 5
1 2 3 4 5

CPLD
CPLD_TDO 3.3V BANK1 IO 1.8V/3.3V BANK2 IO
IO_E4 IO_B9 IFC_AD15 IFC_AD[0..15] 4,5
U65A U65B cfg
NAND_RB_N 5
IO_H1 IO_A9 cfg IFC_AD14
IO_C2 IO_A2 CPLD_REFCLK IO_G1 COP_SRESET_N 7 IO_C8 IFC_AD13
C2 A2 H5 M8 cfg
IO_C3 IO_B1_C2 IO_B2_A2 IO_A4 GCLK0p DEV_OE IO_J1 COP_HRESET_N 7 IO_A8 IFC_AD12
C3 A4 J5 M9 cfg
IO_D1 IO_B1_C3 IO_B2_A4 IO_A5 GCLK1p DEV_CLRn IO_P13 COP_TRST_N 7 IO_B8 IFC_AD11
D1 A5 J12 cfg
A IO_D2 IO_B1_D1 IO_B2_A5 IO_A6 4 IFC_CLK GCLK2p IO_R13 GPIO_CKE_ISO 7 IO_A7 IFC_AD10 A
D2 A6 H12 cfg
IO_D3 IO_B1_D2 IO_B2_A6 IO_A7 GCLK3p IO_P12 TDMR_SLP_N 10 IO_B7 IFC_AD9
D3 A7 cfg
IO_B1_D3 IO_B2_A7 TDMR_PRS_N 10
IO_E1 E1 A8 IO_A8 CPLD_TDI L6 M5 IO_P4 IO_A6 cfg IFC_AD8
IO_B1_E1 IO_B2_A8 TDI TDO T2081_DET_N 13
IO_E2 E2 A9 IO_A9 CPLD_TMS N4 IO_H3 IO_A10 IFC_AD7
IO_E3 IO_B1_E2 IO_B2_A9 IO_A10 CPLD_TCK TMS IO_J2 EC1_RST_N 15 IO_B10 IFC_AD6
E3 A10 P3
IO_B1_E3 IO_B2_A10 TCK EC2_RST_N 16
IO_E4 E4 A11 IO_A11 IO_R7 IO_B11 IFC_AD5
IO_B1_E4 IO_B2_A11 SG_RST_N 17
IO_F1 F1 A12 IO_A12 H8 H7 IO_M3 OD OUTPUT IO_A11 IFC_AD4
IO_F2 IO_B1_F1 IO_B2_A12 IO_A13 VCCINT GNDINT IO_N3 QSG1_RST_N 18 IO_A12 IFC_AD3
F2 A13 1V8_SLP H10 H9 OD OUTPUT
IO_B1_F2 IO_B2_A13 VCCINT GNDINT QSG2_RST_N 19
IO_F3 F3 A15 IO_A15 J7 J8 IO_R11 IO_B12 IFC_AD2
IO_G1 IO_B1_F3 IO_B2_A15 IO_B1 VCCINT GNDINT IO_R5 TDMR_RST_N 10 IO_B13 IFC_AD1
G1 B1 J9 J10
IO_B1_G1 IO_B2_B1 VCCINT GNDINT PEX_RST_N 22
IO_G2 G2 B3 IO_B3 IO_T2 IO_A13 IFC_AD0
IO_G3 IO_B1_G2 IO_B2_B3 IO_B4 IO_R3 MPEX1_RST_N 22 IO_A5 IFC_A31 IFC_A[27..31] 4,5
G3 B4 C1 A1
IO_B1_G3 IO_B2_B4 VCCIO1 GNDIO MPEX2_RST_N 22
IO_H1 H1 B5 IO_B5 H6 A16 IO_C3 IO_D12 IFC_A30
IO_H2 IO_B1_H1 IO_B2_B5 IO_B6 VCCIO1 GNDIO IO_L2 PWR_RST_N 32 IO_C11 IFC_A29
H2 B6 J6 B2
IO_H3 IO_B1_H2 IO_B2_B6 IO_B7 VCCIO1 GNDIO IO_K2 SFPP_DET_N 21 IO_C12 IFC_A28
H3 B7 L8 B15
IO_J1 IO_B1_H3 IO_B2_B7 IO_B8 VCCIO1 GNDIO IO_L3 SFPP_TXDIS 21 IO_C13 IFC_A27
J1 B8 L9 G7
IO_B1_J1 IO_B2_B8 VCCIO1 GNDIO SFPP_RXLOS 21
IO_J2 J2 B9 IO_B9 3V3_SLP P1 G8 IO_J3 IO_D16 cfg
IO_B1_J2 IO_B2_B9 VCCIO1 GNDIO SFPP_TXFAIL 21 IFC_A16 4,5
IO_J3 J3 B10 IO_B10 T3 G9 IO_D1 IO_E15 cfg
IO_B1_J3 IO_B2_B10 VCCIO1 GNDIO THERM_FAULT_N 14,32 IFC_A17 4,5
IO_K1 K1 B11 IO_B11 T14 G10 IO_M4 IO_B6
IO_K2 IO_B1_K1 IO_B2_B11 IO_B12 VCCIO1 GNDIO IO_E1 THERM_ALERT_N 14 IO_B5 IFC_CS0_N 4
K2 B12 A3 K7
IO_B1_K2 IO_B2_B12 VCCIO2 GNDIO FAN_PWM 32 IFC_CS1_N 4
IO_K3 K3 B13 IO_B13 A14 K8 IO_P5 IO_A4
IO_B1_K3 IO_B2_B13 VCCIO2 GNDIO PEX_PRS_N 22 IFC_CS2_N 4
IO_L1 L1 B14 IO_B14 C16 K9 IO_N5 IO_H15 cfg
IO_B1_L1 IO_B2_B14 VCCIO2 GNDIO VDD_EN 31 IFC_WE_N 4,5
IO_L2 L2 B16 IO_B16 F8 K10 IO_R14 IO_G15 cfg
IO_B1_L2 IO_B2_B16 VCCIO2 GNDIO VCORE_EN 29 IFC_OE_N 4,5
IO_L3 L3 C4 IO_C4 F9 R2 IO_R10 IO_A15
B
IO_L4 IO_B1_L3 IO_B2_C4 IO_C5 VCCIO2 GNDIO IO_P8 VCORE_PGOOD 29 IO_B16 IFC_RB0_N 4 B
L4 C5 OVDD_SLP H11 R15
IO_B1_L4 IO_B2_C5 VCCIO2 GNDIO VCORE_HOT_N 29 IFC_RB1_N 4
IO_M1 M1 C6 IO_C6 J11 T1 IO_P7 IO_D13
IO_B1_M1 IO_B2_C6 VCCIO2 GNDIO SENSEVDD_EN 29 NOR_CS_N 5
IO_M2 M2 C7 IO_C7 P16 T16 IO_K1 IO_C14
IO_B1_M2 IO_B2_C7 VCCIO2 GNDIO 3V3_PGOOD 30 NOR_RST_N 5
IO_M3 M3 C8 IO_C8 IO_R8 IO_D15 cfg
IO_B1_M3 IO_B2_C8 IOPWR_EN 30,31 IFC_CLE 4,5
IO_M4 M4 C9 IO_C9 D6 H4 IO_P10 IO_F16 cfg
IO_N1 IO_B1_M4 IO_B2_C9 IO_C10 NC_D6 NC_H4 IO_N12 IOPWR_EN_N 31 IFC_WP_N 4,5
N1 C10 D7 H13
IO_N2 IO_B1_N1 IO_B2_C10 IO_C11 NC_D7 NC_H13 IO_R4 VDD_EN_N 31 IO_J16 CFG_VBANK0 CFG_VBANK[0..2] 5
N2 C11 D8 J4
IO_N3 IO_B1_N2 IO_B2_C11 IO_C12 NC_D8 NC_J4 IO_L4 DDRPWR_EN_N 31 IO_H16 CFG_VBANK1
N3 C12 D9 J13
IO_B1_N3 IO_B2_C12 NC_D9 NC_J13 CKE_ISO_EN 31
IO_N5 N5 C13 IO_C13 D10 K4 IO_F1 IO_J15 CFG_VBANK2
IO_N12 IO_B1_N5 IO_B2_C13 IO_C14 NC_D10 NC_K4 IO_C2 EVDD_SEL 31 IO_G16
N12 C14 E5 K5
IO_P2 IO_B1_N12 IO_B2_C14 IO_C15 NC_E5 NC_K5 IO_R9 PWR_GOOD 32 IO_B14 NAND_CS_N 5
P2 C15 E6 K6
IO_B1_P2 IO_B2_C15 NC_E6 NC_K6 T2081_EN 9,31 IFC_LATCH_N 5
IO_P4 P4 D4 IO_D4 E7 K11 IO_P6
IO_B1_P4 IO_B2_D4 NC_E7 NC_K11 PEX2_SEL_N 9
IO_P5 P5 D5 IO_D5 E8 K12 IO_R6 IO_B4
IO_P6 IO_B1_P5 IO_B2_D5 IO_D11 NC_E8 NC_K12 IO_D2 PEX4_SEL_N 9 IO_A2 JTAG_TRST_N 7
P6 D11 E9 K13 OD OUTPUT
IO_P7 IO_B1_P6 IO_B2_D11 IO_D12 NC_E9 NC_K13 IO_F3 LED_STATUS 32 IO_C15 DDR_RST_N 3
P7 D12 E10 L5
IO_P8 IO_B1_P7 IO_B2_D12 IO_D13 NC_E10 NC_L5 IO_E2 FXO_LED 24 IO_D14 PORESET_N 7
P8 D13 E11 L7 OD OUTPUT
IO_B1_P8 IO_B2_D13 NC_E11 NC_L7 FXS1_LED 23 HRESET_N 7
IO_P9 P9 D14 IO_D14 E12 L10 IO_D3 IO_K15
IO_P10 IO_B1_P9 IO_B2_D14 IO_D15 NC_E12 NC_L10 IO_F2 FXS2_LED 23 IO_P15 RESET_REQ_N 7
P10 D15 F4 L11
IO_P11 IO_B1_P10 IO_B2_D15 IO_D16 NC_F4 NC_L11 IO_E3 FXS3_LED 24 IO_E13 XG_RST_N 21
P11 D16 F5 L12
IO_P12 IO_B1_P11 IO_B2_D16 IO_E13 NC_F5 NC_L12 IO_G3 FXS4_LED 24 IO_E14 CPLD_INT1_N 7
P12 E13 F6 M6
IO_P13 IO_B1_P12 IO_B2_E13 IO_E14 NC_F6 NC_M6 IO_G2 XG_LED0 21 IO_M16 CPLD_INT2_N 7
P13 E14 F7 M7
IO_R1 IO_B1_P13 IO_B2_E14 IO_E15 NC_F7 NC_M7 IO_T4 XG_LED1 21 IO_L15 SDHC_VS 7
R1 E15 F10 M10
IO_B1_R1 IO_B2_E15 NC_F10 NC_M10 LED_T1040_DET 13 EVT_PWR_EN 7
IO_R3 R3 E16 IO_E16 F11 M11 IO_T5 IO_L16
IO_R4 IO_B1_R3 IO_B2_E16 IO_F13 NC_F11 NC_M11 IO_M2 LED_T2081_DET 13 IO_K16 EVT_PWR_OK 7
C R4 F13 F12 M12 C
IO_R5 IO_B1_R4 IO_B2_F13 IO_F14 NC_F12 NC_M12 IO_N2 SG_INT_N 17 IO_N16 EVT_BRD_ISO 7
R5 F14 G4 N6 OD OUTPUT(INTERPOSER)
IO_R6 IO_B1_R5 IO_B2_F14 IO_F15 NC_G4 NC_N6 IO_P2 QSG1_INT_N 18 IO_N15 PEXCLK_OE_N 27
R6 F15 G5 N7 OD OUTPUT(INTERPOSER)
IO_R7 IO_B1_R6 IO_B2_F15 IO_F16 NC_G5 NC_N7 IO_H2 QSG2_INT_N 19 IO_M15 DIFSYSCLK_OE_N 27
R7 F16 G6 N8
IO_R8 IO_B1_R7 IO_B2_F16 IO_G14 NC_G6 NC_N8 IO_K3 POTSA_INT_N 23 IO_E16 SYSCLK_OE 27
R8 G14 G11 N9 cfg
IO_B1_R8 IO_B2_G14 NC_G11 NC_N9 POTSB_INT_N 24 TEST_SEL_N 7
IO_R9 R9 G15 IO_G15 G12 N10 IO_R12 IO_F15 BOOT_FLASH_SEL
IO_B1_R9 IO_B2_G15 NC_G12 NC_N10 TDMR1_INT_N 10
IO_R10 R10 G16 IO_G16 1V8_SLP G13 N11 IO_P11
IO_R11 IO_B1_R10 IO_B2_G16 IO_H14 NC_G13 NC_N11 IO_P9 TDMR2_INT_N 10
R11 H14
IO_R12 IO_B1_R11 IO_B2_H14 IO_H15 IO_M1 SPI_CS3_SEL 10
R12 H15
IO_R13 IO_B1_R12 IO_B2_H15 IO_H16 SD_REFCLK1_SEL 28
R13 H16 EPM570GF256
IO_R14 R14 IO_B1_R13 IO_B2_H16 J14 IO_J14 C698 C699 C700 C1101 X2
IO_R16 R16 IO_B1_R14 IO_B2_J14 J15 IO_J15
IO_T2 T2 IO_B1_R16 IO_B2_J15 J16 IO_J16 1uF 0.1uF 0.1uF 0.1uF R494 1K 1 3 R495 33 CPLD_REFCLK CPLD JTAG CONNECTOR
IO_T4 T4 IO_B1_T2 IO_B2_J16 K14 IO_K14 3V3_SLP OE OUT
IO_T5 T5 IO_B1_T4 IO_B2_K14 K15 IO_K15 FB47 3V3_SLP J26 3V3_SLP
IO_T6 T6 IO_B1_T5 IO_B2_K15 K16 IO_K16 3V3_SLP 3V3_OSC_CPLD 4 2 R496 4.7K CPLD_TCK
IO_T7 T7 IO_B1_T6 IO_B2_K16 L13 IO_L13 BLM18BD601SN1 VDD GND CPLD_TDO 1 2
IO_T8 T8 IO_B1_T7 IO_B2_L13 L14 IO_L14 C701 C702 C703 C704 R497 10K CPLD_TMS 3 4
IO_T9 T9 IO_B1_T8 IO_B2_L14 L15 IO_L15 32.768KHz 5 6
IO_T10 T10 IO_B1_T9 IO_B2_L15 L16 IO_L16 C705 C706 C707 C708 C709 C710 C1102 C1103 0.1uF 0.01uF 1uF 0.1uF R498 10K CPLD_TDI 7 8
IO_T11 T11 IO_B1_T10 IO_B2_L16 M13 IO_M13 9 10
IO_T12 T12 IO_B1_T11 IO_B2_M13 M14 IO_M14 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF SW3 HDR_2X5
IO_T13 T13 IO_B1_T12 IO_B2_M14 M15 IO_M15
IO_T15 IO_B1_T13 IO_B2_M15 IO_M16 IFC_WE_N ON
T15 M16 cfg_eng_use0 1 16 R499 4.7K
D
IO_B1_T15 IO_B2_M16 N13 IO_N13 OVDD_SLP OVDD cfg_eng_use1 IFC_OE_N 2 1 16 15 R500 4.7K D
IO_B2_N13 N14 IO_N14 cfg_eng_use2 IFC_WP_N 3 2 15 14 R501 4.7K
IO_B2_N14 N15 IO_N15 R502 10K BOOT_FLASH_SEL 4 3 14 13 R503 1K
IO_B2_N15 N16 IO_N16 R504 10K CFG_VBANK0 5 4 13 12 R505 1K
IO_B2_N16 P14 IO_P14 C711 C712 C713 C714 C715 C716 C1104 C1105 R506 10K CFG_VBANK1 6 5 12 11 R507 1K
IO_B2_P14 P15 IO_P15 R508 10K CFG_VBANK2 7 6 11 10 R509 1K Title
IO_B2_P15 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF TEST_SEL_N 8 7 10 9 T1040RDB
8 9
EPM570GF256 Size Document Number Design Engineer Rev
SWITCH_DIP_8 B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 26 of 34


1 2 3 4 5
1 2 3 4 5

SYSTEM CLOCK GENERATORs

X3

1 3 R511 33
A 26 SYSCLK_OE OE OUT SYS_REFCLK 7 A
OVDD_SLP
FB48 C718
OVDD_OSC_SYS 4 2 DNP R513
BLM18BD601SN1 VDD GND 10pF DNP
C720 C721 C722 C723 1K
100MHz,+/-50ppm
0.1uF 0.01uF 1uF 0.1uF

X5

R516 1K 1 3 R517 33
OE OUT DDR_REFCLK 7
OVDD
FB50 C728
OVDD_OSC_DDR 4 2 DNP R518
BLM18BD601SN1 VDD GND 10pF DNP
C729 C730 C731 C732 1K
66.66MHz,+/-50ppm
0.1uF 0.01uF 1uF 0.1uF

B B

I2C ADDR = 0x6A


1V8_SLP

U97 Integrated output terminations providing Zo=100


26 PEXCLK_OE_N
R519 49.9
26 DIFSYSCLK_OE_N
2 14 R520 0 DNP 1%
X1_25 DIF0 PEX_REFCLK_P 22
3 15 R521 0
X2 DIF0 PEX_REFCLK_N 22
Y4 R523 49.9
13 18 DNP 1%
1 3 R533 1K 21 OE0 DIF1 19
24 OE1 DIF1 R524 49.9
C733 C734 30 OE2 22 R525 0 DNP 1%
OE3 DIF2 MPEX1_REFCLK_P 22
25MHz R843 1K 35 23 R526 0
MPEX1_REFCLK_N 22
2

2pF 2pF R844 1K 38 OE4 DIF2 R527 49.9 R528 49.9


DEFAULT NO SPREAD OE5 28 R530 0 DNP 1% DNP 1%
DIF3 MPEX2_REFCLK_P 22
R829 1K DNP 1 29 R532 0
SS_EN_TRI DIF3 MPEX2_REFCLK_N 22
R834 1K 6 R534 49.9 R535 49.9
R842 1K SADR/REF1.8 33 R536 0 DNP 1% DNP 1%
DIF4 SD_REFCLK2_P 8
40 34 R537 0
CKPWRGD_PD DIF4 SD_REFCLK2_N 8
R835 49.9 R538 49.9
9 36 R836 0 DNP 1% DNP 1%
29 I2C1_SCL_SLP SCLK_3.3 DIF5 SYS_REFCLK_P 7
10 37 R837 0
29 I2C1_SDA_SLP SDATA_3.3 DIF5 SYS_REFCLK_N 7
C R838 49.9 C
7 12 DNP 1%
20 NC1 VDDIO 17
25 NC2 VDDIO 27
NC3 VDDIO 32
R839 10 1V8_0641_VDDXTAL 4 VDDIO 39 1V8_SLP
VDDXTAL1.8 VDDIO FB54
C1040 C1041 26 5 1V8_0641_VDDIO
VDDA1.8 VDDREF1.8 BLM18PG221SN1
10uF 0.01uF 16 C1044 C1045 C1046 C1047 C1048 C1052
1V8_SLP 31 VDD1.8 8
VDD1.8 GNDDIG 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
11 41
R841 10 1V8_0641_VDDA VDDDIG1.8 EPAD

C736 C737 IDT9FGV0641

10uF 0.01uF
1V8_SLP
1V8_SLP
FB55
1V8_0641_VDD C735
BLM18PG221SN1
C1049 C1050 C1051 0.1uF
D D
10uF 0.1uF 0.1uF

Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 27 of 34


1 2 3 4 5
1 2 3 4 5

SYSTEM CLOCK GENERATORs (cont.)

A A

U68

13 3
XTAL_IN Q0 SD_REFCLK1_P 8
12 4
XTAL_OUT Q0 SD_REFCLK1_N 8
Y5
LOW: 156.25MHz FOR T2081 14 19
TEST_CLK Q1 XG_REFCLK_P 21
1 3 HIGH: 125MHz FOR T1040 18
Q1 XG_REFCLK_N 21
9
C739 C738 3V3 11 F_SEL0
25MHz F_SEL1 R541 R542 R543 R544

4
27pF 33pF 15
6 XTAL_SEL 150 150 150 150
C742 C743 PLL_SEL
5
0.1uF 0.1uF MR
26 SD_REFCLK1_SEL
10 1
3V3 16 VCC NC1 7
FB52 VCC NC2
3V3O_843002A 2
BLM18BD601SN1 20 VCCO
C746 C747 VCCO
8 17
B VCCA VEE B
0.1uF 0.1uF

3V3 ICS843002-01

R549 10 3V3A_843002A

C750 C751

10uF 0.01uF

T1040 ONLY!
U67

13 3
XTAL_IN Q0 QSG1_REFCLK_N 18
12 4
XTAL_OUT Q0 QSG1_REFCLK_P 18
C Y6 C
14 19
TEST_CLK Q1 QSG2_REFCLK_N 19
1 3 18
Q1 QSG2_REFCLK_P 19
R540 1K 9
C740 C741 3V3 11 F_SEL0
25MHz 125MHz F_SEL1 R545 R546 R547 R548
2

27pF 33pF 15
6 XTAL_SEL 150 150 150 150
C744 C745 PLL_SEL
5
0.1uF 0.1uF MR
10 1
3V3 16 VCC NC1 7
FB53 VCC NC2
3V3O_843002B 2
BLM18BD601SN1 20 VCCO
C748 C749 VCCO
8 17
0.1uF 0.1uF VCCA VEE

3V3 ICS843002-01

R550 10 3V3A_843002B

D C752 C753 D

10uF 0.01uF

Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 28 of 34


1 2 3 4 5
1 2 3 4 5

T1040 CORE POWER CONVERTOR


U92
To assure sensing is in place with no processor Important! Normal operation, switch is closed,
VCORE_SLP 1 but when going to sleep (and after cores are disabled),
IN1 SENSEVDD_EN 26 switch must be opened BEFORE power FET for VDD is turned off.
R551 100 10 2 R552 0 Then when coming out of sleep, first turn on power FET for VDD,
D1 S1A SENSEVDD 12 then close sense switch, then enable cores.
9
R553 10 S1B This assures that there is no sensing of unstable or zero voltages.
12 SENSEVDDC
5
A IN2 When T2081, sleep mode is not used, A
For the first programming R556 100 6 4 R554 0 may simply keep sense switch closed
of the internal flash: D2 S2A SENSEGND 12 (SENSVDDC/SENSEGNDC pins are open when T2081).
7
VR_HOT, EN S2B 3V3_SLP
need to be connected to GND. via R555 10 3 8 C997 0.1uF
short Jumper and CPLD will drive 12 SENSEGNDC GND VDD
12V_SLP 12VF_SLP 12V_SLP
both enables low. L23
(I2C address in this mode 0Ah) ADG836 7V0_DRV U69
PROGRAMING CONNECTOR 1uH
R557 C756 0.22uF 3 18 C1000 C754 C757 C758 C755 C759 C1077 C1075 C1076 C1078
J27 VCC VIN 20
VCORE_HOT_N 13K 3V3_SLP VIN 21 0.1uF 10uF 10uF 22uF 22uF 220uF 10uF 10uF 0.1uF 0.01uF

VCORE_VRTN1
VCORE_VSEN1
7V0_DRV VIN 22 25V
JMP2 VCORE_VCC R559 0 VIN 23
LABEL = PROG_VCORE R558 10K 25 VIN
J28 C760 C762 PHSFLT 24 R561 0
SM_DIO 1 R560 C761 26 BOOST FP1007R3-R22-R
2 1uF 0.1uF PWM 6 C763 0.22uF Irms = 61A
SM_CLK 3 1K 0.01uF 27 SW 7 Isat@125 = 43A
BBRK SW L8 DCR = 0.29mohm +/-5%
HDR_1X3 5 VCORE_SW1
U70 C764 30 GATEL1 32 215nH
IOUT GATEL2 R562 3.57K C765 0.22uF
3V3_SLP 22 2 3000pF 29 2 1%
B VCC VSEN1 REFIN CSIN+ B
3 1 4 x POSCAP
R563 4.7K 9 VRTN1 CSIN- C766 1000pF VCORE 2R5TPE470M7
R564 10K VINSEN 28 4 DNP R565 R566 ESR = 7mohm
12 31 LGND PGND 16 R567 1
26 VCORE_EN EN1 TGND PGND
7 DNP 301 301
26 VCORE_PGOOD PGOOD1
R568 1K 8 Snubber Circuit 1% 1% C767 C768
1 EN2 17 VCORE_PWM1A IR3550 STUFF IR3553
PGOOD2 PWM1A 29 VCORE_ISEN1A 470uF 470uF
R570 4.7K SM_CLK 16 ISEN1A 30 VCORE_IRTN1A 12VF_SLP 2.5V 2.5V
R569 4.7K SM_DIO 15 SM_CLK IRTN1A
R573 4.7K 14 SM_DIO 7V0_DRV U71
R574 4.7K SM_ALERT
R575 1.78K 13 C769 0.22uF 3 18 C1001 C771 C772 C773 C774 C775 C776 C777
PMBus Address offset to "+2" C770 0.01uF ADDR_PROT 18 VCORE_PWM1B VCC VIN 20
11 PWM1B 27 VCORE_ISEN1B VIN 21 0.1uF 10uF 10uF 22uF 22uF 220uF 470uF 470uF
26 VCORE_HOT_N VRHOT_ICRIT ISEN1B VCORE_IRTN1B VIN
28 22 25V 2.5V 2.5V
R576 2.87K 31 IRTN1B VIN 23
1% RCSP1 25 VIN
PLACE R577 R578 C778 PHSFLT 24 R579 0
THERMISTOR 1% 26 BOOST FP1007R3-R22-R COPPER PLANE
NEAR L8&L9 10K 3.4K 100pF 19 PWM 6 C779 0.22uF Irms = 61A
R580 2.87K 32 PWM2 25 R581 301 1% 27 SW 7 Isat@125 = 43A VCORE_SLP
1% RCSM1 ISEN2 26 R582 301 1% BBRK SW L9 DCR = 0.29mohm +/-5% 12 x 22uF,0805,6.3V
23 IRTN2 5 VCORE_SW2
C C
RCSM2 30 GATEL1 32 215nH
R726 IOUT GATEL2 R586 3.57K C785 0.22uF C781 C782 C783 C784
29 2 1%
10K REFIN CSIN+ 1 22uF 22uF 22uF 22uF
24 21 R588 0 CSIN- C786 1000pF
RCSP2 VSEN2 20 R589 0 28 4 DNP R590 R591
5 VRTN2 31 LGND PGND 16 R592 1
TSEN TGND PGND DNP 301 301
4 10 Snubber Circuit 1% 1% C787 C788 C789 C790
RRES NC IR3550 STUFF IR3553
6 33 22uF 22uF 22uF 22uF
R593 R594 V18A EPAD

10K 7.5K IR36021 5V0_SLP


1% If 5.0V for IR3553 is OK, DNP the 7.0V LDO
R595 75 3V3_SLP R727 0 C791 C792 C793 C794
DNP
3V3 C795 22uF 22uF 22uF 22uF
PowIRstage MOSFET Driver power supply
4.7uF Make sure 7.0V supply is applied
12V_SLP after 3.3V is ready U72 7V0_DRV
1

7.0V supply is ramped down


Q39 before 3.3V supply 2 3
D IRLML6346 IN OUT D
2 3 C796 R597 49.9K 1% 1 4 R598 46.4K C797
R596 20.0K 1% EN ADJ 1%
1uF C798 1uF 5 7 R599 10uF
6 GND GND 8
GND GND
1

10K Title
Q40 1% T1040RDB
IRLML6346 SM_CLK MIC39102YM
3,7,14 I2C1_SCL SM_DIO I2C1_SCL_SLP 27
2 3 Size Document Number Design Engineer Rev
3,7,14 I2C1_SDA I2C1_SDA_SLP 27
B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 29 of 34


1 2 3 4 5
1 2 3 4 5

2.2uH(IHLP2525CZER2R2M01): Irms = 8A, Isat = 14A, DCR = 18mohm


3.3uH(IHLP2525CZER3R3M01): Irms = 6A, Isat = 13.5A, DCR = 28mohm
SYSTEM POWER CONVERTORs
4.7uH(IHLP2525CZER4R7M01): Irms = 5.5A, Isat = 10A, DCR = 37mohm
COPPER ISLAND COPPER ISLAND

5V0_SLP Rff(kohm) = Vout/(1Vx20pFxFsw) U86 COPPER PLANE 5V0_SLP Rff(kohm) = Vout/(1Vx20pFxFsw)


MAX 10A
U87 COPPER PLANE
SWITCHABLE ALWAYS ON
Fsw = 400KHz Rset = 24(mohm)xIoc/19(uA) Fsw = 400KHz Rset = 13(mohm)xIoc/19(uA)
13 14 C924 0.33uF 1V0 13 14 C927 0.47uF 1V35_SLP
C928 1uF 10 VIN BOOT Vout = 0.5x(Rtop/Rbot+1) C929 1uF 10 VIN BOOT Vout = 0.5x(Rtop/Rbot+1)
C930 C925 C1054 1uF VCC 12 L17 C931 C926 C1053 1uF VCC 12 L18
A R730 124K 1% 15 PHASE 2.2uH R728 169K 1% 15 PHASE 2.2uH A
22uF 22uF C938 0.01uF DNP FF 2 R729 10K 1% C937 C939 C933 22uF 22uF C932 1uF FF 2 R731 10K 1% C934 C936 C940
R732 10K DNP 16 ISET R733 1.65K 1% R738 R734 10K 16 ISET R735 2.05K 1% R736
R737 10K 3 EN C935 0.1uF 1% 47uF 47uF 0.1uF R739 10K 3 EN C941 0.1uF 1% 47uF 47uF 0.1uF
PGOOD 10K PGOOD 10K
26,30,31 IOPWR_EN
8 C942 510pF 8 C943 560pF
Enable DCM Mode R740 10K DNP 3VCBP 5 Enable DCM Mode R741 10K DNP 3VCBP 5
R742 0 1 FB 1V0 1V0 R743 0 1 FB
6 FCCM 7 6 FCCM 7
SS NC1 9 R744 SS NC1 9 1V35_SLP 1V35_SLP R745 R787
C944 C945 4 NC2 1% C1063 C1064 C946 C947 4 NC2 1% 1%
17 GND 11 10K 17 GND 11 5.9K 32.4K LABEL = DDR3 VOLTAGE
1uF 0.01uF GND PGND 47uF 47uF 1uF 0.1uF GND PGND C1069 C1070 J39
1
IR3473 IR3475 47uF 47uF 2

Css(nF) = 22xTss(mS) 1V35 POWER ON LAST Css(nF) = 22xTss(mS) JMP2


INSTALL JUMPER FOR
DDR3 1.5V
FOR INTERPOSER MUST INSTALL JUMPER
COPPER ISLAND COPPER ISLAND

5V0_SLP Rff(kohm) = Vout/(1Vx20pFxFsw) U88 SWITCHABLE COPPER PLANE 5V0_SLP Rff(kohm) = Vout/(1Vx20pFxFsw) U89 ALWAYS ON COPPER PLANE
Fsw = 400KHz Rset = 24(mohm)xIoc/19(uA) Fsw = 400KHz Rset = 24(mohm)xIoc/19(uA)
B B
13 14 C948 0.47uF 1V5 13 14 C949 0.47uF 1V8_SLP
C950 1uF 10 VIN BOOT Vout = 0.5x(Rtop/Rbot+1) C951 1uF 10 VIN BOOT Vout = 0.5x(Rtop/Rbot+1)
C952 C953 C1055 1uF VCC 12 L19 C954 C955 C1056 1uF VCC 12 L20
R746 187K 1% 15 PHASE 3.3uH R747 226K 1% 15 PHASE 3.3uH
22uF 22uF C956 0.01uF DNP FF 2 R748 10K 1% C959 C960 C961 22uF 22uF C957 0.01uF DNP FF 2 R749 10K 1% C958 C962 C963
R750 10K DNP 16 ISET R751 2.21K 1% R753 R754 10K 16 ISET R755 2.43K 1% R757
R752 10K 3 EN C964 0.1uF 1% 47uF 47uF 0.1uF R756 10K 3 EN C965 0.1uF 1% 47uF 47uF 0.1uF
PGOOD 10K PGOOD 10K
26,30,31 IOPWR_EN
8 C966 560pF 8 C967 620pF
Enable DCM Mode R758 10K DNP 3VCBP 5 Enable DCM Mode R759 10K DNP 3VCBP 5
R760 0 1 FB 1V5 1V5 R761 0 1 FB 1V8_SLP 1V8_SLP
6 FCCM 7 6 FCCM 7
SS NC1 9 R762 SS NC1 9 R763
C968 C969 4 NC2 1% C1095 C1096 C970 C971 4 NC2 1% C1097 C1098
17 GND 11 4.99K 17 GND 11 3.83K
1uF 0.01uF GND PGND 47uF 47uF 1uF 0.01uF GND PGND 47uF 47uF

IR3473 IR3473

Css(nF) = 22xTss(mS) Css(nF) = 22xTss(mS)

C COPPER ISLAND COPPER ISLAND C

5V0_SLP Rff(kohm) = Vout/(1Vx20pFxFsw) U91 COPPER PLANE 5V0_SLP Rff(kohm) = Vout/(1Vx20pFxFsw)


MAX 10A
U90 COPPER PLANE
Fsw = 400KHz
ALWAYS ON
Rset = 24(mohm)xIoc/19(uA) Fsw = 400KHz
ALWAYS ON
Rset = 13(mohm)xIoc/19(uA)
13 14 C972 1uF 2V5_SLP 13 14 C978 1uF 3V3_SLP
C973 1uF 10 VIN BOOT Vout = 0.5x(Rtop/Rbot+1) C974 1uF 10 VIN BOOT Vout = 0.5x(Rtop/Rbot+1)
C975 C976 C1057 1uF VCC 12 L21 C979 C980 C1058 1uF VCC 12 L22
R764 309K 1% 15 PHASE 4.7uH R765 412K 1% 15 PHASE 2.2uH
22uF 22uF C977 0.01uF DNP FF 2 R766 10K 1% C982 C983 C984 22uF 22uF C981 0.01uF DNP FF 2 R767 10K 1% C985 C986 C987
R768 10K 16 ISET R769 2.55K 1% R774 R770 10K 16 ISET R775 2.32K 1% R772
R773 10K 3 EN C988 0.1uF 1% 47uF 47uF 0.1uF R771 10K 3 EN C989 0.1uF 1% 47uF 47uF 0.1uF
PGOOD 3V3_SLP PGOOD
10K 10K
26 3V3_PGOOD
8 C990 680pF 8 C991 680pF
Enable DCM Mode R776 10K DNP 3VCBP 5 Enable DCM Mode R777 10K DNP 3VCBP 5
R778 0 1 FB 2V5_SLP 2V5_SLP R779 0 1 FB 3V3_SLP 3V3_SLP 3V3_SLP
6 FCCM 7 5V0_SLP 5V0_SLP 6 FCCM 7
SS NC1 9 R780 SS NC1 9 R781
C992 C993 4 NC2 1% C1099 C1100 C994 C995 4 NC2 1% C1066 C1067 C1068
17 GND 11 2.49K C1112 C1113 17 GND 11 1.78K
1uF 0.01uF GND PGND 47uF 47uF 1uF 0.01uF GND PGND 47uF 47uF 47uF
22uF 22uF
IR3473 IR3475

Css(nF) = 22xTss(mS) Css(nF) = 22xTss(mS)


D D

Caution: separate analog and power ground and make connection at GND plane
Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 30 of 34


1 2 3 4 5
1 2 3 4 5

SYSTEM POWER SWITCHs


Q8
VCORE_SLP IRFH6200 VCORE
1
5 2
3
Q9 Q31 Q11 12V_SLP Q12 12V
IRFH6200 1V35_SLP IRFHM4226 1V35 1V8_SLP IRFHM4226 1V8 IRF9321
1 1 1 1 5 DISCHARGE LOAD

4
A 5 2 5 2 5 2 2 6 A
3 3 3 3 7
8 R870
DISCHARGE LOAD R782 DISCHARGE LOAD R656
12V_SLP 4 DISCHARGE LOAD R654 12V_SLP 12V_SLP 4.7K

4
R657 0 R783 0 1K R659 0 1K
R660 10K 1K R784 10K R662 10K R663 10K
C871 0.01uF C996 0.01uF C873 0.01uF C874 0.01uF

3
Q13 Q32 Q15 Q16
R665 1K 1 IRLML6346 R785 1K 1 IRLML6346 R666 1K 1 IRLML6346 R670 1K 1 IRLML6346
26 VDD_EN_N 26 DDRPWR_EN_N 26,31 IOPWR_EN_N 26,30 IOPWR_EN
R667 10K R786 10K R669 10K R671 10K
2

2
FOR INTERPOSER/T1040, DVDD = 3.3V
Q17 Q18 3V3 Q42 Q23 FOR T2081, DVDD = 2.5V Q24 Q43 2V5
2V5_SLP IRFHM4226 2V5 3V3_SLP IRFH6200 3V3 IRFHM4226 IRFHM4226 DVDD IRFHM4226 IRFHM4226
1 1 1 1 1 1
5 2 5 2 2 5 5 2 2 5 5 2
3 3 3 3 3 3
B B

DISCHARGE LOAD R672 DISCHARGE LOAD R673 R687


12V_SLP 12V_SLP
4

4
R675 0 1K R676 0 1K 1K
R678 10K R679 10K 12V_SLP DISCHARGE LOAD 12V_SLP
C875 0.01uF C876 0.01uF R688 0 R689 0
R690 10K R691 10K
3

3
C878 0.01uF C879 0.01uF

3
Q20 Q21
R681 1K 1 IRLML6346 R682 1K 1 IRLML6346
26,31 IOPWR_EN_N 26,31 IOPWR_EN_N
R684 10K R685 10K Q25 Q26
R692 1K 1 IRLML6346 1 IRLML6346
9,26 T2081_EN
2

2
R693 10K

2
Q44 Q33 Q34 Q45
COPPER ISLAND 1V8 IRLML2030 IRLML2030 EVDD IRLML2030 IRLML2030 3V3

1V35_SLP 3V3_SLP U81 MVREF COPPER ISLAND 2 3 3 2 2 3 3 2

C 2 3 VTT C
VLDOIN VO DISCHARGE LOAD R815
C880 C881 10 5 R694 10

1
R695 1 VIN VOSNS 6 1K
10uF 10uF 1% REFIN REFOUT 12V_SLP 12V_SLP
1K C882 7 9 C883 C884 C885 C886 R816 0 R817 0
EN PGOOD R818 10K R819 10K
4.7uF 4 0.1uF 1uF 22uF 22uF C1023 0.01uF C1024 0.01uF
8 PGND 11
GND PAD

3
3V3_SLP
R696 C887
1% TPS51200 R697 100K Q35 Q36
1K 1000pF R820 1K 1 IRLML6346 1 IRLML6346
26 EVDD_SEL
Tracking Startup and Shutdown R821 10K

2
DDR_MCKE0 3

3
1V8_SLP 3V3_SLP U95 1V0S
Vout = 0.7x(Rtop/Rbot+1)
1 7 Q37
2 IN OUT 8 R830 1K 1 IRLML6346
IN OUT 26 CKE_ISO_EN
D D
DDR_MCKE1 3
4 6 R806 4.32K

2
BIAS FB/ADJ

3
1%
C1015 C1016 5 3 R807 C1017 C1079
EN GND 9 Q38
1uF 1uF EPAD 10K 10uF 0.1uF R831 10K 1 IRLML6346 Title
1% T1040RDB
MIC47100YMME

2
Size Document Number Design Engineer Rev
26 VDD_EN
B <Doc> MICETEK A
T1040/T2081 SVDD power on with VDD
Date: Thursday, January 16, 2014 Sheet 31 of 34
1 2 3 4 5
1 2 3 4 5

SYSTEM POWER INPUT

3V3 12V
CHASSIS FAN HEADER
A J30 LABEL = SYS_FAN A
VDD_LP_BAT R700 0 J33
D30 J31 1
2 1 1 D31 T2081 ONLY! F9 500mA 2
2 RB521 LED DNP 3
RB521 U82 1V0_LP
JMP2 CON_3PIN
BAT_SOCKET 1 5 3V3_SLP 3V3_SLP 12V
VIN VOUT LABEL = SYS_FAN
Connected: VDD_LP_BAT EN 3 J32 R861 0 J44
EN

2
Disconnected: VDD_LP_BAT DIS (default) C888 C889 1 1
4 2 2 D43 D44 F11 500mA 2
NC GND LP_TMPDET_N 7
10uF 10uF 3 GRN GRN DNP 3

NCP571 JMP3 CON_3PIN


VDD_LP_DET 12V

1
1->2: VDD_LP_DET ON R702 510 LABEL = SYS_FAN
26 LED_STATUS
2->3: VDD_LP_DET OFF R862 0 J45
R699 1
F12 500mA 2
510 DNP 3

CON_3PIN
CPU FAN HEADER 12V
B B
12V_SLP LABEL = SYS_FAN
LABEL = CPU_FAN R863 0 J46
R701 0 J34 1
1 F13 500mA 2
F10 500mA 2 DNP 3
3V3_SLP 3V3_SLP DNP 3
CON_3PIN
CON_3PIN

R703 R704 D33 C890 C891

10K 10K BAT43WS 10uF 0.1uF LABEL = FULL SPEED


D34 L16 J35
1 INSTALL JUMPER FOR
14,26 THERM_FAULT_N FULL SPEED ON FAN
22uH 2 ATX POWER INPUT CONNECTOR
3

RB521
JMP2
Q27 Q28 Q29 5V0_SLP J37 5V0_SLP
1 IRLML6346 1 IRLML6346 1 IRLML2502
26 FAN_PWM
5V MAX: 10A 1 11
C892 12V MAX: 5A +3.3VDC +3.3VDC
2

2 12
22pF +3.3VDC -12VDC
C 3V3_SLP 3 13 C
COM COM
RESET 5V0_SLP 4 14 PWR_EN_N
+5VDC PS_ON
R705 3V3_SLP U83 5 15
LABEL = RESET COM COM
SW4 4.7K 4 R706 6 16
VCC +5VDC COM
1 2 R707 100 3 2 4.7K 12V_SLP 5V0_SB 7 17
MR RESET PWR_RST_N 26 COM COM
3 4
C893 1 8 18
SWITCH GND R708 5V0_SB PWR_OK -5VDC
0.1uF 9 19
MIC811 4.7K R709 +5VSB +5VDC
10 20
3V3_SLP R710 3.74K +12VDC +5VDC
1%
4.7K ATX_PWR_CONN_20PIN
26 PWR_GOOD
C1002
PWR SWITCH 5V0_SB PWR_EN_N
0.1uF U84 R712 C894
3
R711 100
5V0_SB 2 5 R713 1K 1 Q30 4.7K 0.1uF
D35 D Q MMBT4401
D LABEL = POWER U85 1 3 5V0_SB D
2

SW5 1 5 CLK Q
RB521 NC VCC 4 7 8 5V0_SB 5V0_SB
1 2 R714 100K 2 O 3 R715 100K 6 PRE VCC 4
3 4 I GND CLR GND
C895 74AHC1G14 C896 C897 C898 Title
SWITCH 10mS Debounce Default Power Off 74LVC2G74 T1040RDB
0.1uF 0.1uF 0.1uF 0.1uF
Size Document Number Design Engineer Rev
B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 32 of 34


1 2 3 4 5
1 2 3 4 5

MECHANICALs

A A

Fiducial Marks Layer Detail


Top 1.5OZ
Z97 Z98 Z99 Z100 Z101 Z102 Z103 Z104
L2GND 1OZ

L3SIG 1OZ

L4PWR 1OZ 2.0mm


+/- 10%
Mouting Holes L5PWR 1OZ

L6SIG 1OZ
Z105 Z106 Z109 Z110 Z111 Z112
L7GND 1OZ

Bottom 1.5OZ

B B

Z107 Z108

Heatsink Fan

M2 HEATSINK_FAN

M19

DDR3_ECC_UDIMM
1
2
3
4

Micron MPN(4GB,1600): MT18KSF51272AZ-1G6

C C

D D

Title
T1040RDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Thursday, January 16, 2014 Sheet 33 of 34


1 2 3 4 5
1 2 3 4 5

CHANGE LIST
2013/6/12 2013/7/19
1. Add DDR3 CKE pull down circuit for deep sleep 1. Add 20K pull-up to IFC_A[16-19],AVD,OE,WE,WP
2. Change SYSCLK to 66.66MHz and DDRCLK to 133.33MHz 2. Add IFC_LATCH_N to IFC voltage level translators
3. Change ICS557-05 S0~S2 configuration to support spread, but default no spread 3. Change NAND RB pull-up to 1K
4. Change power switch mosfet to IR 4. Change SD card ESD chip to Rclamp0524J
5. Add dip switch for board configuration form CPLD, but bit definition need to confirm 5. Change NOR MPN to S29GL01GP11TFIV10
A 6. Add 1.0V LDO for S1VDD, use NFM55PC155F1H4B instead of BLM18 bead for SVDD and XVDD A
2013/6/13 7. Change SD card insert and protect signal pull-up to 1.8V and connect to T2080 derectly
1. Add 100MHz diff SYS_CLK to support single source clock input mode
2. Change SD card WP pin ESD protect circuit 2013/7/24
1. Connect EVT2, EVT3, EVT9, IRQ9 to CPLD for sleep mode control
2013/6/14 2. Change I2C MUX address to 0x77
1. Correct JTAG_TRST_N single pin error 3. Add test point for CLK_OUT and RTC, change RTC pull-down to 10K
2. Change 1 MOSFET of VDD switch to 2 for decrease Rds-on 4. Add test point for 1588 signals
5. Change USB protect chip from SRV05-4 to VBUS054B-HSF
2013/6/17 6. Change LED drive resistor from 330ohm to 510ohm
1. Use Mux/Demux for SerDes to switch T1040/T2081 7. Correct VSC8514 QSGMII TX/RX pin out error
2. Change DVDD voltage select by MOSFET 8. Add MCKE pull-down circuit
3. Change 2N7002 MOSFET to IRLML6346 9. Add EVDD select circuit, SDHC support 1.8V or 3.3V, change SDHC_CLK serial resistor to 0 ohm
4. Change CVDD and EVDD connect to OVDD, add voltage translator to SPI and SDHC 10. Add test points for SD_PLL_TPA and SD_PLL_TPD
5. Delete INTERPOER_N signal 11. Add optional filtering for USB_BIAS
6. Change FXO 2PIN connector to RJ11 12. Connect RGMII PHY tap pins together, change crystal caps from 20pF to 27pF,
7. Change DIN power connector to 20PIN ATX power connector remove bead, add 0 ohm to ENSWREG, change RST to pull-up
8. Correct 2V5 power DCDC chip from IR3898 to IR3897 2013/7/30
9. Change low current MOSFET from IRFH6200 to IRLHM620 1. Change the VDD/VDDC sensing strategy
10. Change VCORE DCDC to IR36021 2. Change sleep mode enter or exit power control signals to 3 tiers
11. Add front panel LEDs (general IO power, core power, DDR power)
B 12. Add 3V3_PGOOD to CPLD for power-on reset and CKE isolate control signal, correct IRQ9 and EVT9 signal name B
3. Change GND CKE chip from 74LVC1G125 to MOSFET
2013/6/19
1. Change EMI2 pull-up resistor to 270ohm for MDC and 510ohm for MDIO(pull-up to 1.8V) 2013/8/2
2. Add MOSFET for USB PWRFAULT signal active high 1. Change EVDD switch signal to IRQ3 though CPLD(1.8V<->3.3V), delete SGMII PHY PME interrupt
3. Change ICS557-05 to IDT5V41236 for PCIE GEN2 and GEN3 support 2. Change SVDD and XVDD power enable signal belong to VCORE and GVDD
4. Correct NCP1117 resistor value 3. Change SVDD LDO from MIC49150 to MIC47100
2013/6/21 2013/8/5
1. Update PRO config signals connection 1. Change IDT5V41236 to IDT9FGV0641 to support single source clock
2. Change CPLD from EPM240G to EPM570G 2. Delete differential output OSC of system clock
2013/6/22 2013/8/8
1. Delete unused IFC_AD0~4 to 74LVC16373 1. Add 1uF input cap to IR3473/IR3475
2. Update IR36021 VCORE circuit 2. Change all IR3473 OCP resistor to 10K
2013/8/15
2013/6/23
1. Change SYS_REFCLK to 100MHz
1. Add T1040/T2081 detect LED
2. Update IR3473/IR3475 circuit
2. Add labels for LEDs and connectors
3. Change SVDD and XVDD filter cap from NFM55PC155 to NFM21PC225
3. Add voltage translator for UART signals
2013/8/20
C 2013/7/5 1. Delete backpanel LEDs, LED header and front panel header C
1. Change SD_REFCLK1 to 156.25MHz and SD_REFCLK2 to 100MHz
2. Change IRLHM620 to IRFHM4226 2013/8/23
3. GVDD and USB power do not need to turn off 1. Add SE SYSCLK and DIFF SYSCLK select control from CPLD, OD output for IDT9FGV0641(1.8V)
(GVDD: 1V35_SLP for GVDD, delete MCKE pull-down circuit, delete MVREF_SLP MOSFET, 2. Isolate I2C1 for don't sleep chips
change AVDD_D1 to 1V8_SLP)(USB: change USB_SVDD,USB_HVDD,USB_OVDD power to SLP power) 2013/9/4
4. Change IR3897 and IR3898 to IR3473 or IR3475 1. Change PMC connector to TDM riser card connector
5. Add 5V0_SLP to 7V0_DRV option for LDO cost 2. Change IRQs to CPLD then CPLD to T1040/T2081
6. Change IR36021 programing connector pin order
7. Delete RCSP/RCSM temp sense circuit for loop2 of IR36021 2013/9/11
8. Add more 10uF caps for VDDC and VDD 1. Change DDR3 SODIMM to UDIMM
9. Update VSC8514 circuit refer to reference design 2013/9/12
1. Add notes at page 1
2013/7/7 2. Change DDR REFCLK from 133.33MHz to 66.66MHz
1. Correct SD_TX/RX1 Mux/DeMux control pin connection
2. Change Mux/DeMux chip from PI3PCIE3215 to PI3PCIE3212,delete bead of power supply,change caps to 0.01uF 2013/9/27
3. Add 2pin jumper for DDR3 voltage change to 1.5V surport 1. Update system block diagram
4. Add 2pin 2mm wafer CPU_FAN connector 2. Change DVDD and EVDD power select from 1 MOSFET to 2 MOSFET
5. Add front panel connector and LED connector 2013/10/8
1. Change VCORE caps near T1040 from 10uF to 22uF
2013/7/12
D 1. Add analog switch for sense VDDC or VDD select 2013/10/10 D
1. Add 51ohm resistors for SPI signals
2013/7/13 2. Change VCORE caps near T1040 to follow QDS board
1. Correct IR3473 connection error
2. Change IR36021 programing connector pin order 2013/10/19
1. Add GVDD power-on delay Title
2. Correct 12V enable signal name T1040RDB
3. Add 2x22uF to 3.3V DCDC power input Size Document Number Design Engineer Rev
2013/11/19 B <Doc> MICETEK A
1. Change QSGMII PHY MPN
Date: Thursday, January 16, 2014 Sheet 34 of 34
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