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divisorFRC = OSC_FRC_DIV_2
Internal FRC 8 MHz
Fast RC Oscillator Divider FRCDIV = 4 MHz
Oscillator 8 MHz
÷ 16 FRCDIV16 = 0.5 MHz
OSC1/ 8 MHz
POSC
CLKI
External
Primany POSC POSC
8
Oscillator Enable
Oscillator FRC
OSC2/ POSCMOD = XT
CLKO
POSC Divider
CLK Out 8
PBCLK
Enable
OSCIOFNC = ON UPLLIDIV=
XTPLL, HSPLL,
ECPLL, FRCPLL
Low Power LPRC 31.25 KHz
RC POSC
Oscillator LPRC
Oscillator 32 KHz
FRC
External Crystal Freq = 32.77 KHz 32.768 KHz
SOSC FRC/16
SOSC FRC/16
SOSCI
External SOSC FRCDIV
Secondary SOSC
Oscillator Enable
Oscillator LPRC
FSOSCEN = ON
SOSCO
SOSC
REFCLKI
Enter external
clock frequency
FPLLMUL =
MUL_15 0
MUL_16 0
MUL_17 0
MUL_18 0
MUL_19 0
MUL_20 20
MUL_21 0
MUL_24 0
20
FPLLODIV = DIV_1 0
DIV_2 2
DIV_4 0
DIV_8 0
DIV_16 0
DIV_32 0
DIV_64 0
DIV_256 0
2
FNOSC = FRC 8 0
FRCPLL 26.66667 26.666667
PRI 8 0
PRIPLL 26.66667 0
SOSC 0.032768 0
LPRC 0.031250 0
FRCDIV16 0.5 0
FRCDIV 4 0
26.666667
UPLLIDIV =DIV_1 0
DIV_2 0
DIV_3 3
DIV_4 0
DIV_5 0
DIV_6 0
DIV_10 0
DIV_12 0
3
UPLLEN = ON
OFF
FSOSCEN = ON
OFF
OSCIOFNC = ON
OFF
FPBDIV = DIV_1 0
DIV_2 2
DIV_4 0
DIV_8 0
2
Cell formatting logic to find invalid input (false = no problem):
cell #:
E31 1 Is OSC2 needed for crystal input (can't be used as clock out)?
Notes:
1) Settings that produce red cells are invalid.
2) See device data sheet for details.
3) Password to unprotect = "microchip"
USB PLL
32 MHz
USB PLL Divide 32
Divider
x 24 ÷2
2.6667 64 32
usbClock= SYS_OSC_USBCLK_PRIMARY
Must be
DIV_3 4 MHz UPLLEN= ON
4 MHz
FRCDIV
SYSCLK =26.6667 MHz
31.25 KHz
LPRC
32.768 KHz
SOSC
FNOSC = FRCPLL
8 MHz
FRC
Enter: trimValue (0 to 511)
53.333 MHz refOscDiv (0 to 32767)
PLL Out FREFCLKO =
POSC
8 MHz
REFCLK (
2 refOscDiv +
Out
64 KHz trimValue = 255 Enable
B PLL Out
refOscDiv = 9
31.25 KHz
LPRC REFCLK REFCLKO = 0.4211
32.768 MHz 8 Divider
SOSC
13.333 MHz FREFIN
PBCLK
26.667 MHz
SYSCLK
2 MHz
REFCLKI
refOscBaseClock = OSC_REF_BASECLOCK_FRC
peripheralBusClkDiv
1
2
4
8
newOsc
OSC_FRC
OSC_FRC_WITH_PLL
OSC_PRIMARY
OSC_PRIMARY_WITH_PLL
OSC_SECONDARY
OSC_LPRC
OSC_FRC_DIV_BY_16
OSC_FRC_BY_FRCDIV
selectPLL
OSC_PLL_SYSTEM
OSC_PLL_USB
usbClock
SYS_OSC_USBCLK_PRIMARY
SYS_OSC_USBCLK_FRC
PLLInClockSource
OSC_SYSPLL_IN_CLK_SOURCE_FRC
OSC_SYSPLL_IN_CLK_SOURCE_PRIMARY
PLLInDiv
OSC_SYSPLL_IN_DIV_1
OSC_SYSPLL_IN_DIV_2
OSC_SYSPLL_IN_DIV_3
OSC_SYSPLL_IN_DIV_4
OSC_SYSPLL_IN_DIV_5
OSC_SYSPLL_IN_DIV_6
OSC_SYSPLL_IN_DIV_7
OSC_SYSPLL_IN_DIV_8
pll_multiplier
15
16
17
18
19
20
21
24
PLLOutDiv
OSC_SYSPLL_OUT_DIV_1
OSC_SYSPLL_OUT_DIV_2
OSC_SYSPLL_OUT_DIV_4
OSC_SYSPLL_OUT_DIV_8
OSC_SYSPLL_OUT_DIV_16
OSC_SYSPLL_OUT_DIV_32
OSC_SYSPLL_OUT_DIV_64
OSC_SYSPLL_OUT_DIV_256
refOscBaseClock
OSC_REF_BASECLOCK_FRC 8 8
OSC_REF_BASECLOCK_SYSPLLOUT 53.333 0
OSC_REF_BASECLOCK_PRIMARY 8 0
OSC_REF_BASECLOCK_USBCLK 64 0
OSC_REF_BASECLOCK_LPRC 0.0313 0
OSC_REF_BASECLOCK_SOSC 0.0328 0
OSC_REF_BASECLOCK_PBCLK 13.333 0
OSC_REF_BASECLOCK_SYSCLK 26.667 0
OSC_REF_BASECLOCK_EXT 2 0
8
refOscDiv (this is a 15 bit field that can hold values from 1 to 32768)
OSC_REF_DIV_1 1
OSC_REF_DIV_2 2
OSC_REF_DIV_4 4
OSC_REF_DIV_8 8
OSC_REF_DIV_16 16
OSC_REF_DIV_32 32
OSC_REF_DIV_64 64
OSC_REF_DIV_128 128
OSC_REF_DIV_256 256
OSC_REF_DIV_512 512
OSC_REF_DIV_1024 1024
OSC_REF_DIV_2048 2048
OSC_REF_DIV_4096 4096
OSC_REF_DIV_8192 8192
OSC_REF_DIV_16384 16384
OSC_REF_DIV_32768 32768
trimValue
1 refOscDiv + trimValue = 9.4980
2
…
512
Symbol Name
Symbol Name
Symbol Name
(
2 refOscDiv +
trimValue
512 )
MHz
1, refOscBaseClock);
refOscDiv);
PIC32MZ Oscillator Configuration
Click on highlighted cell
tuningValue = +\- 12.5% select settings per drop-
FRC
Tune
divisorFRC = OSC_FRC_DIV_2
Internal FRC 8 MHz
Fast RC FRC FRCDIV =
Oscillator 4
Oscillator Divider
8 MHz
OSC1/ 24 MHz
POSC
CLKI
External
Primany POSC POSC
UPLLFSEL =
Oscillator Enable
Oscillator
OSC2/ POSCMOD = EC USB PLL
CLKO
REFCLKIx
Enter external
clock frequency
E31 0 Is OSC2 needed for crystal input (can't be used as clock out)?
Is input to PLL outside of this range:?
M19 1 0 0 RANGE_34_64_MHZ
M19 1 0 0 RANGE_21_42_MHZ
M19 1 0 0 RANGE_13_26_MHZ
M19 0 0 0 RANGE_8_16_MHZ
M19 0 1 0 RANGE_5_10_MHZ
M19 0 Bypass
M19 0 Is there a problem?
Notes:
1) Settings that produce red cells are invalid
2) See device data sheet for details.
MHz 3) Password to unprotect = "microchip"
PLL
Range
FPLLRNG = RANGE_5_10_MHZ
Each peripheral clock
(except PBCLK1) can
be disabled.
peripheralBusClkDiv = 2
FREQ_12MHZ Divider PBCLK1 = 100 MHz
peripheralBusClkDiv = 2
4 MHz Divider PBCLK5 = 100 MHz
FRCDIV
200 MHz peripheralBusClkDiv = 1
SPLL
Divider PBCLK7 = 200 MHz
24 MHz
POSC
peripheralBusClkDiv = 2
8 MHz Divider PBCLK8 = 100 MHz
BFRC
BFRC Divider PBCLK8 =
32 KHz
LPRC
SYSCLK = 200 MHz
32.768 KHz
SOSC
FNOSC = SPLL
8 MHz
FRC
Enter: trimValue (0 to 511)
200 MHz refOscDiv (0 to 32767)
SPLL FREFCLKO =
POSC
24 MHz
REFCLK (
2 refOscDiv +
Out
8 MHz trimValue = 218 Enable
BFRC
refOscDiv = 5
32 KHz
LPRC REFCLK REFCLKOx = 18.4305
32.768 KHz 200 Divider
SOSC
3 REFCLK outputs
100 MHz FREFIN SPI (REFCLK1)
PBCLK1 ADC (REFCLK3)
200 MHz SQI (REFCLK2)
SYSCLK
2 MHz
EFCLKIx
x = 1, 3, 4 (REFCLK2 is internal only)
refOscBaseClock = OSC_REF_BASECLOCK_SYSPLLOUT
peripheralBusClkDiv
1
2
…
128
newOsc
OSC_FRC
OSC_FRC_WITH_PLL
OSC_PRIMARY
OSC_PRIMARY_WITH_PLL
OSC_SECONDARY
OSC_LPRC
OSC_FRC_DIV_BY_16
OSC_FRC_BY_FRCDIV
peripheralBusNumber
OSC_PERIPHERAL_BUS_1
OSC_PERIPHERAL_BUS_2
OSC_PERIPHERAL_BUS_3
OSC_PERIPHERAL_BUS_4
OSC_PERIPHERAL_BUS_5
OSC_PERIPHERAL_BUS_7
OSC_PERIPHERAL_BUS_8
selectPLL
OSC_PLL_SYSTEM
OSC_PLL_USB
PLLFrequencyRange
OSC_SYSPLL_FREQ_RANGE_BYPASS,
OSC_SYSPLL_FREQ_RANGE_5M_TO_10M
OSC_SYSPLL_FREQ_RANGE_8M_TO_16M
OSC_SYSPLL_FREQ_RANGE_13M_TO_26M
OSC_SYSPLL_FREQ_RANGE_21M_TO_42M
OSC_SYSPLL_FREQ_RANGE_34M_TO_68M
PLLInClockSource
OSC_SYSPLL_IN_CLK_SOURCE_FRC
OSC_SYSPLL_IN_CLK_SOURCE_PRIMARY
PLLInDiv
OSC_SYSPLL_IN_DIV_1
OSC_SYSPLL_IN_DIV_2
OSC_SYSPLL_IN_DIV_3
OSC_SYSPLL_IN_DIV_4
OSC_SYSPLL_IN_DIV_5
OSC_SYSPLL_IN_DIV_6
OSC_SYSPLL_IN_DIV_7
OSC_SYSPLL_IN_DIV_8
pll_multiplier
1
2
…
128
PLLOutDiv
OSC_SYSPLL_OUT_DIV_1
OSC_SYSPLL_OUT_DIV_2
OSC_SYSPLL_OUT_DIV_4
OSC_SYSPLL_OUT_DIV_8
OSC_SYSPLL_OUT_DIV_16
OSC_SYSPLL_OUT_DIV_32
OSC_SYSPLL_OUT_DIV_64
OSC_SYSPLL_OUT_DIV_256
refOscBaseClock
OSC_REF_BASECLOCK_FRC 4 0
OSC_REF_BASECLOCK_SYSPLLOUT 200 200
OSC_REF_BASECLOCK_PRIMARY 24 0
OSC_REF_BASECLOCK_BFRC 8 0
OSC_REF_BASECLOCK_LPRC 0.032 0
OSC_REF_BASECLOCK_SOSC 0.0328 0
OSC_REF_BASECLOCK_PBCLK 100 0
OSC_REF_BASECLOCK_SYSCLK 200 0
OSC_REF_BASECLOCK_EXT 2 0
200
refOscDiv (this is a 15 bit field that can hold values from 1 to 32768)
OSC_REF_DIV_1 1
OSC_REF_DIV_2 2
OSC_REF_DIV_4 4
OSC_REF_DIV_8 8
OSC_REF_DIV_16 16
OSC_REF_DIV_32 32
OSC_REF_DIV_64 64
OSC_REF_DIV_128 128
OSC_REF_DIV_256 256
OSC_REF_DIV_512 512
OSC_REF_DIV_1024 1024
OSC_REF_DIV_2048 2048
OSC_REF_DIV_4096 4096
OSC_REF_DIV_8192 8192
OSC_REF_DIV_16384 16384
OSC_REF_DIV_32768 32768
trimValue
1 refOscDiv + trimValue = 5.4258
2
…
512
Symbol Name
nd 200 MHz?
eripheral clock
PBCLK1) can
bled.
PBCLK7 is the
clock for the core
FREFIN
(
2 refOscDiv +
trimValue
512 )
MHz
3 REFCLK outputs
heralBusClkDiv);
/default value set by FSOSCEN
/default value set by FSOSCEN
//default value set by FNOSC
ontrols "ON" bit in PBxDIV register
ontrols "ON" bit in PBxDIV register
/enables USB or System PLL
/disables USB or System PLL
/default value set by FPLLRNG
/default value set by FPLLICLK
//default value set by FPLLIDIV
/default value set by FPLLMULT
/default value set by FPLLODIV
, refOscBaseClock);
efOscDiv);
PIC32MX
Oscillator
Block Diagram
PIC32MZ
Default PIC32MZ Oscillator Configuration Settings: