Proceedings of the Second International Conference on Intelligent Computing and Control Systems (ICICCS 2018)
IEEE Xplore Compliant Part Number: CFP18K74-ART; ISBN:978-1-5386-2842-3
Sensitivity analysis of Junctionless FinFET
for analog applications
SACHINDRA BHARTI
School of VLSI Design & Embedded System
National Institute of Technology Kurukshetra
Kurukshetra, India
Sachindraece16@gmail.com
Abstract- This study gives an insight of
junctionless FinFET device, by targeting sensitivity of
device analog performance metrics with respect to
geometrical variations. Effect of geometrical
parameters are studied on analog performance
metrics such as transconductance (gm), output
conductance (gds), intrinsic voltage gain (Av), gate
capacitance (Cgg) and unity gain frequency (fT).
Parameters such as gm, gds, Av, Cgg and fT are found
more sensitive to Fin thickness (~62.67%), gate length
(~59.49%), oxide thickness (~64.29%), gate length
(~39.53%) and Fin thickness (~73.70 %), respectively.
This analysis improves the understanding of
junctionless device sensitivity against the geometrical
variations for analog applications.
Keywords: Sensitivity, Junctionless Fin field-effect
transistor, Geometrical variations.
I. INTRODUCTION
With the advancement of semiconductor
technology, all the electronic devices are getting
smaller and smaller in size [1]. Due to the scaling
of conventional bulk MOSFET, control of the gate
over the channel reduces resulting in poor short
channel effects (SCEs) [2]. Further, formation of
ultra-steep junctions become very difficult below
20 nm node. Many researchers inspected the
aforesaid issue of construction of ultra-sharp
junctions in conventional MOSFET and
recommended a highly scalable novel device
referred as Junctionless transistor (JLT). In
Junctionless transistor, doping of source, channel
and drain region are kept to be same and very high
of the order of 1019 atoms/cm3. This eliminates the
need of formation of junctions with sharp doping
profile [3]. Therefore, JLTs seem to be a potential
candidate to the conventional bulk MOSFETs. It is
a depletion mode device as it can be turned-off by
depleting the electrons from the channel region
with the application of gate work function. Thinner
silicon film depletes the channel easily, so cross-
section of JLT must be small enough [4]. Initially
when gate voltage is not applied, channel is
978-1-5386-2842-3/18/$31.00 ©2018 IEEE
GAURAV SAINI
School of VLSI Design & Embedded System
National Institute of Technology Kurukshetra
Kurukshetra, India
gaurvavsaini@nitkkr.ac.in
completely depleted due to difference in work
function of gate metal and semiconductor creating
an effective barrier against majority carriers
transport from source to drain. When the gate
voltage (Vgs) increases, depletion of channel is
eliminated gradually resulting in increase in
electron concentration and decrease in channel
resistance. When electron concentration reaches to
channel doping concentration, area under the gate
becomes electrically neutral [5]. JLT is basically a
variable resistor in which mobile carrier density is
modulated by varying the gate voltage [4-5]. JLT
has simple fabrication process and low fabrication
cost. However, it suffers from lower current drive
compared to conventional inversion mode (IM) and
accumulation mode (AM) devices, due to high
doping in channel region [6]. To solve the problem
of lower drain current, several techniques and
methods have been proposed till now [7-8]. All
these techniques can be classified into two major
categories, namely- a) Gate engineering – It is
based on the effect of spacer dielectrics, gate
oxides and gate metal work-function. b) Channel
engineering – It is based on the effect of channel
doping concentrations, dopant types and their
placement strategy. Since it is well known that,
scaled MOSFET suffers from poor SCEs at scaled
device dimensions. Moreover, it is challenging to
control the geometrical parameters precisely at
scaled gate lengths. In past, many researchers have
reported the effect of device parametric and process
variation on Junctionless FinFET [9-13] and IM
devices [14]. Hence, it is important to know the
dependence of Hfin, Tfin, Tox and Lg on the
junctionless FINFET structures. Rest of this paper
is organized as follows. In section II, simulation
setup and device structure are presented. Section III
describes the impact of geometrical parameters on
the analog performance of Junctionless SOI
FinFET. Conclusion of the study is given in section
IV.
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Proceedings of the Second International Conference on Intelligent Computing and Control Systems (ICICCS 2018)
IEEE Xplore Compliant Part Number: CFP18K74-ART; ISBN:978-1-5386-2842-3

II. DEVICE STRUCTURE AND SIMULATION

SETUP

The source-channel-drain are heavily doped as

n-type with doping concentration 1019 atoms cm-3.
Gate Effective oxide thickness (EOT) is set to 1 nm
except stated otherwise. The 3-D TCAD Synopsis
Sentaurus device simulator [15] is used to simulate
the junctionless FinFET. Mixed-mode simulator is
used to simulate analog performance parameters of
the device [15-16]. The models used in the
simulation setup are Shockley-Read-Hall (SRH)
recombination/generation, Lombardi mobility,
oldslotboom bandgap narrowing phenomenon. Fig.2: Basic structure of Junctionless FinFET with
Density gradient quantization model is used to spacer
account the quantum confinement effects. By
varying the spacer length and BOX height from 5 Table I
to 20 nm we have seen that device with spacer Nominal parameters for simulated devices
length 15nm and BOX =10nm gives better results, Parameters Value
so we have feezed our device with the parameter Channel thickness (Tsi) 10 nm
mentioned in Table 1. Fig. 1 shows the schematic
Buried oxide thickness (Tbox) 10 nm
view of the device structure of n-channel Triple
Gate oxide thickness (Tox) 0.8 -1.4 nm
gate-Junctionless FinFET used in this paper. Fig. 2
Thickness of substrate (Tsub) 10 nm
shows the same device filled with low dielectric
Gate length (Lg) 12-21 nm
constant (k) spacer. The work function of all the
Source/Drain length 5 nm
devices are tuned in such a way that all the devices
Work function 4.62-5.03 eV
have equal threshold voltage of 0.3 Volt.
Fin height 10-45 nm
Silicon film doping (ND) 1.5×1019/cm3
Substrate doping (Nsub) 5×1018/cm3
Threshold voltage (Vth) 0.3 V
Fin thickness 5-14 nm

III. SIMULATION RESULTS

On current and off current are extracted as the

current at the gate voltages (Vgs) 1.0 V and 0 V
respectively for drain voltage (Vds) of 1.0 V with a
fixed threshold voltage. Higher Ion/Ioff means device
has better switching control. Capacitance,
transconductance, output conductance are found by
ac device simulations at a frequency of 1 MHz and
Vgs = Vds = 1 V. Unity gain cut-off frequency (fT)
and intrinsic voltage gain (Av) is defined as:

fT= (1)
( . )

Fig.1: Basic structure of Junctionless FinFET

Av = 20 log (gm/gds) dB (2)

A. Fin Height (Hfin)

This section investigates how fin height (Hfin)

affects the analog performance of junctionless
FinFET when varied from 10 nm to 45 nm at a

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Proceedings of the Second International Conference on Intelligent Computing and Control Systems (ICICCS 2018)
IEEE Xplore Compliant Part Number: CFP18K74-ART; ISBN:978-1-5386-2842-3

fixed fin thickness (Tfin) of 10 nm. The device

performance and analog performance parameters
like on-current (Ion), off-current (Ioff), on to off
current ratio (Ion/Ioff), DIBL and SS,
transconductance (gm), output conductance (gds),
gate capacitance (Cgg), intrinsic voltage gain (AV)
and unity gain cut-off frequency (fT) are studied as
shown in Fig. 3. By upscaling of Hfin DIBL, SS, Ioff
increases and Ion/ Ioff decreases. However, upscaling
of Hfin improves the gm, Ion, Av and fT. . Moreover,
Cgg decreases with upscaling of Hfin.

Table II
Sensitivity Hfin(%) Tfin(%) Lg(%) Tox(%)

gm 12.31 62.67 18.96 4.9

gds 22.11 55.23 59.49 18.15
Av 1.98 1.94 27.93 64.29
Cgg 2.98 8.81 39.53 34.65
fT 17.09 73.70 17.76 15.10
DIBL 23.72 60.38 51.88 40
SS 2.8 42.02 13.87 13.62

The decrease in Cgg with upscaling of Hfin results in

upgradation of unity gain cut-off frequency. The
percentage sensitivity of gm, gds, Av, Cgg and fT with
respect to Hfin are found to be 12.31, 22.11, 1.98,
2.98 and 17.09 % respectively and shown in Table
II. The percentage Sensitivity (S) of performance
parameters are calculated by varying Hfin from 10 to
45 nm. The sensitivity to parameter variation is
estimated using sensitivity formula as shown below
[16].

S=((ΔPerformance/performance)/(ΔParameter/Para
meter)×100) %

B. Fin Thickness (Tfin)

This section investigates how fin thickness
(Tfin) affects the analog performance of JLFinFET
when varied from 6 nm to 14 nm at a fixed Hfin of
10 nm. The device characteristic like SS, DIBL, Ion,
Ioff, Ion/Ioff , gm, gds, Cgg, Av and fT of junctionless
FinFET for different value of thickness (T fin). are
shown in Fig. 4. By upscaling of T fin, DIBL, SS, Ioff
increases. However, upscaling of T fin. Improves the
gm, Ion, Av and fT. Moreover, Cgg decreases with
upscaling of Tfin. The decrease in Cgg with
upscaling of Tfin results in upgradation of unity gain
cut-off frequency. The percentage sensitivity of
gm, gds, Av, Cgg and fT with respect to Tfin are found
to be 62.67, 55.23, 1.94, 8.81 and 73.70 %
respectively and shown in table II. The percentage
Sensitivity of performance parameters are
calculated by varying Tfin from 6 nm to 14 nm. Fig. 3 Variation of (a) DIBL and SS (b) Ion and Ioff
(c) gm and gds (d) (Ion)/(Ioff) and Gain (e) Cgg and fT

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Proceedings of the Second International Conference on Intelligent Computing and Control Systems (ICICCS 2018)
IEEE Xplore Compliant Part Number: CFP18K74-ART; ISBN:978-1-5386-2842-3

C. Effect of Gate Length

Gate dimension is the physical length of the

gate and can be precisely measured by a scanning
electron microscope (SEM). This section
investigates how JL FinFET gate length (Lg) affects
the analog performance of JL FinFET when varied
from 12 nm to 21 nm at a fixed Hfin and Tfin of 10
nm. The device characteristic like SS, DIBL, Ion ,
Ioff, Ion/ Ioff , gm, gds Cgg, Av and fT of simulated
junctionless FinFET for different value of gate
length. are shown in Fig. 5. By upscaling of gate
length DIBL, SS, decreases and Ion/ Ioff increases.
However, upscaling of gate length. improves the
gm, gds, and AV. Moreover, Cgg increases with
upscaling of Lg. The increase in Cgg with upscaling
of Lg results into reduction in fT. The percentage
(%) sensitivity of gm, gds, Av, Cgg and fT with
respect to Lg are found to be 18.96, 59.49, 27.93,
39.53 and 17.76 % respectively and shown in Table
II. The percentage Sensitivity (S) of performance
parameters are calculated by varying Lg from 12 to
21 nm.

D. Effect of Gate Oxide Thickness

This section investigates how the gate oxide

thickness affects the analog performance of JL
FinFET when the gate oxide thickness (Tox) is
varied from 0.8 nm to 1.4 nm at a fixed Hfin and Tfin
at 10 nm. Reduction in oxide thickness increases
oxide capacitance which improves on-current. The
device characteristic like SS, DIBL, Ion, Ioff, Ion/Ioff,
gm, gds, Cgg, Av and fT of simulated JL FinFET are
shown in Fig. 6. By upscaling of T ox, DIBL, SS, Ioff
increases and on-current to off-current ratio
decreases. However, upscaling of oxide thickness
decreases the gm, Ion, Av and fT. Moreover, Cgg
decreases with upscaling of Tox. The decrease in
Cgg with upscaling of oxide thickness results in
upgradation of fT. The percentage (%) sensitivity of
gm, gds, Av, Cgg and fT with respect to Tfin are found
to be 4.90, 18.15, 64.29, 34.65 and 15.10 %
respectively and shown in Table II. The percentage
Sensitivity (S) of performance parameters are
calculated by varying Tox from 0.8 nm to 1.4 nm.

Fig. 4 Variation of (a) DIBL and SS (b) Ion and Ioff

(c) gm and gds (d) (Ion)/(Ioff) and Gain (e) Cgg and fT

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Proceedings of the Second International Conference on Intelligent Computing and Control Systems (ICICCS 2018)
IEEE Xplore Compliant Part Number: CFP18K74-ART; ISBN:978-1-5386-2842-3

Fig. 5 Variation of (a) DIBL and SS (b) Ion and Ioff Fig.6 Variation of (a) DIBL and SS (b) Ion and Ioff
(c) gm and gds (d) (Ion)/(Ioff) and Gain (e) Cgg and fT (c) gm and gds (d) (Ion)/(Ioff) and Gain (e) Cgg and fT

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Proceedings of the Second International Conference on Intelligent Computing and Control Systems (ICICCS 2018)
IEEE Xplore Compliant Part Number: CFP18K74-ART; ISBN:978-1-5386-2842-3

IV. CONCLUSIONS [10] Pankaj Kumar et al,” Characteristics and Sensitivity

We have investigated the sensitivity analysis by
varying the fin-height (Hfin), fin-thickness (Tfin),
gate length (Lg), and oxide thickness (Tox) of the
JL-FinFET. The device has been studied using
extensive device simulations. This study is useful
for designing JLFinFET for analog application.
Therefore, necessary attention can be given to the
respective geometrical parameters which affect
analog metrices of device. It is observed that
transconductance gm is more sensitive to Tfin
followed by Lg, Hfin and Tox. Output conductance
gds is more sensitive to Lg followed by Tfin, Hfin and
Tox. Voltage gain (Av) is more sensitive to Tox
followed by Lg, Hfin and Tfin. Gate capacitance
(Cgg) is more sensitive to Lg followed by Tox, Tfin
and Hfin. fT is more sensitive to Tfin followed by Lg,
Hfin and Tox. From 3-D simulation study
transconductance (gm), output conductance (gds), voltage
gain (Av), gate capacitance (Cgg) and unity gain
frequency (fT). gm, gds, Av, Cgg and fT are more sensitive
to Fin thickness (62.67%), gate length (59.49%), oxide
thickness (64.29%), gate length (39.53%) and Fin
thickness (73.70 %) respectively
Analysis of Gate Inside Junctionless Transistor (GI-JLT),” IEEE
20th International Conference, pp. 56-59, Dec.2013
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[14] Shiying Xiong and J. Bokor, “Sensitivity of double-gate
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[15] Sentarus Device User Guide. [online]. Available:
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dual-k sidewall spacers for enhanced analog/RF FOMs,”
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V. ACKNOWLEDGEMENTS

Authors would like to thank Ministry of

Electronics & Information Technology (MeitY) for
SMDP-C2SD program.

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