MUX:

1. Write Verilog code for 4 to 1 MUX using conditional operator and

construct 16 to 1 MUX using 4 to 1 MUX. Perform functionality test.
2. Write Verilog code for 4 to 1 MUX using case statement and construct 16
to 1 MUX using 4 to 1 MUX. Perform functionality test.
3. Write verilog code for implementing higher order using lower order mux
and perform exhaustive functionality test.
4. Construct 8​:1 mux using 2:1 mux. Write verilog code for the same and peroform
exhaustive functionality test.
DEMUX:

1. Write Verilog code for 1 to 4 DEMUX using case statement and construct 1
to 16 DEMUX using 1 to 4 DEMUX. Perform functionality test.
2. Write verilog code for 1 to 4 demux using conditional operator and
construct 1 to 16 demux using 1 to 4 demux. Perform functionality test.

3. ​Construct 1:16 DEMUX using 2 to 4 decoders. Write Verilog code for the
same and perform exhaustive functionality test.

4. code for implementing higher order using lower order demWrite verilog
ux mux and perform exhaustive functionality test.
ENCODER:

1. Write Verilog code for 8 to 3 priority encoder using case statement.

Perform functionality test.
2. Write verilog code for 8 to 3 encoder using if else statement. Perform
exhaustive functionality test.
3. Write verilog code for 8 to 3 encoder using without priority. Perform
exhaustive functionality test
4. Write verilog code for 4 to 2 encoder using if else statement. Perform
exhaustive functionality test.

DECODER:
 1. Write Verilog code for the 3 to 8 decoder using case statement and
Construct 4 to 16 decoder using 3 to 8 decoders by using instantiation
process. Perform exhaustive functionality test.

2. ​Construct 4 to 16 decoder using 3 to 8 decoders. write Verilog code for

the same and perform exhaustive functionality test.

3. ​Implement the following functions using a 3 to 8 decoder. Write Verilog

code for the same and perform exhaustive functionality test.
4. Write verilog code for 2 to 4 decoder using case statement. Perform
exhaustive functionality test.
ADDERS:

1. Design a 4 bit ripple substractor using 1 bit adder. Write Verilog code for
the same and perform functionality test.

2. Design a 4 bit ripple carry adder using 1 bit adder. Write Verilog code for
the same and perform functionality test.
3. Write verilog code for unsigned 8-bit adder with carry in. perform
exhaustive functionality test.
4. Write verilog code for unsigned 8-bit adder with carry out. perform
exhaustive functionality test.

COMPARATORS:

1. Design 2 bit comparator using 2 to 4 decoder and logic gates. Write Verilog
code for the same and perform exhaustive functionality test.
2. Write verilog code for 4 bit magnitude comparator and perform exhaustive
functionality test.
3. Write verilog code for 8 bit multiplier and perform perform exhaustive
functionality test.
4. Design 4 bit multiplier using full adder. Write verilog code for the same and
perform exhaustive functionality test.