Escolar Documentos
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2018/2019
2C/1L, MDCR
Attendance at minimum 7 sessions (course +
laboratory)
Lectures- associate professor Radu Damian
Friday 09-11, II.13
E – 50% final grade
problems + (2p atten. lect.) + (3 tests) + (bonus activity)
▪ 3p=+0.5p
all materials/equipments authorized
Laboratory – associate professor Radu Damian
Wednesday 12-14, II.12 odd weeks
L – 25% final grade
P – 25% final grade
http://rf-opto.etti.tuiasi.ro
dB = 10 • log10 (P2 / P1) dBm = 10 • log10 (P / 1 mW)
0 dB =1 0 dBm = 1 mW
ZL *
Zi
Z Z0 L i*
Z Z0
Im Γ
Γi
complex numbers
in the complex plane
Re Γ
ΓL
Lecture 3-4
Scattering parameters
+ +
V1 V2 V1 S11 S12 V1
- - V2 S 21 S 22 V2
V1 V2
[S] Γ2 V1 V2
S11 S 21
V1 V2 0
V1 V2 0
V2 0
meaning: port 2 is terminated in
matched load to avoid reflections towards
the port
2 0 V2 0
a1 a2 b1 S11 S12 a1
b S
2 21 S 22 a2
b1 b2
[S] Power in Z 0 load
2
S 21
Power from Z 0 source
a,b
information about signal power AND signal phase
Sij
network effect (gain) over signal power including
phase information
Impedance Matching
+1 Im Γ
|Γ|=1
|Γ|
-1 θ=arg Γ +1
Re Γ
-1
+1 Im Γ
|Γ|=1
|Γ|
-1 θ=arg Γ +1
Re Γ
-1
Impedance Matching with Stubs
Shunt Stub
Series Stub
difficult to realize in single conductor line
technologies (microstrip)
Im Γ
+1
gL = 1 rL = 1
-1 +1
Re Γ
-1
Charaterized with S parameters
normalized at Z0 (implicit 50Ω)
Datasheets: S parameters for specific bias
conditions
Touchstone file format (*.s2p)
! SIEMENS Small Signal Semiconductors
! VDS = 3.5 V ID = 15 mA
# GHz S MA R 50
! f S11 S21 S12 S22
! GHz MAG ANG MAG ANG MAG ANG MAG ANG
1.000 0.9800 -18.0 2.230 157.0 0.0240 74.0 0.6900 -15.0
2.000 0.9500 -39.0 2.220 136.0 0.0450 57.0 0.6600 -30.0
3.000 0.8900 -64.0 2.210 110.0 0.0680 40.0 0.6100 -45.0
4.000 0.8200 -89.0 2.230 86.0 0.0850 23.0 0.5600 -62.0
5.000 0.7400 -115.0 2.190 61.0 0.0990 7.0 0.4900 -80.0
6.000 0.6500 -142.0 2.110 36.0 0.1070 -10.0 0.4100 -98.0
!
! f Fmin Gammaopt rn/50
! GHz dB MAG ANG -
2.000 1.00 0.72 27 0.84
4.000 1.40 0.64 61 0.58
Stability
For an amplifier two-port we are interested in:
stability
power gain
noise (sometimes – small signals)
linearity (sometimes – large signals)
S12 S 21 L
in 1 S11 1
1 S 22 L
S11 L 1 S22 L
2 2
S11 L 1 S22 L
Im Γ x x0 2 y y0 2 R 2
+1
0 R 0 R
R
y0 Γ0
-1 +1
x0 Re Γ
-1
L
* *
S 22 S11
S12 S 21
L CL RL
2 2 2 2
S 22 S 22
CL
* *
S 22 S11 RL
S12 S 21
2 2
S 22
2 2
S 22
|Γ| = 1 log10|Γ| = 0, the intersection with the
plane z = 0 is a circle
2 2 2
1 S11 S 22
K S11 S22 S12 S21
2 S12 S 21
The two-port is unconditionally stable if:
two conditions are simultaneously satisfied:
K>1
|Δ| < 1
together with the implicit conditions:
|S11| < 1
|S22| < 1
2 2 2
1 S11 S 22
K 1 S11 S22 S12 S21 1
2 S12 S 21
Rollet’s condition cannot be used to compare the relative
stability of two or more devices because it involves
constraints on two separate parameters, K and Δ
2
1 S11
1
S 22 S11 S12 S 21
The two-port is unconditionally stable if:
μ>1
together with the implicit conditions:
|S11| < 1
|S22| < 1
In addition, it can be said that larger values of μ imply
greater stability
μ is the distance from the center of the Smith Chart to the closest
output stability circle
Dual parameter to μ, determined in relation to
the input stability circles
1 S 22
2
1
S11 S 22 S12 S 21
The two-port is unconditionally stable if:
μ’ > 1
together with the implicit conditions:
|S11| < 1
|S22| < 1
In addition, it can be said that larger values of μ’ imply
greater stability
μ’ is the distance from the center of the Smith Chart to the closest
input stability circle
ATF-34143 at Vds=3V Id=20mA.
@0.518GHz
ATF-34143 at Vds=3V Id=20mA.
Unconditionally
@0.518GHz Stable
Conditionally
Stable
ATF-34143 at Vds=3V Id=20mA.
Unconditionally
@0.518GHz Stable
Conditionally
Stable
The procedure can be applied similarly at the
output (finding g/r circles tangent to CSOUT)
From previous examples, resistive loading at
the input has a positive effect over output
stability and vice versa (resistive loading at
the output, effect over input stability)
Rsmin Rpmax
Power Gain of Microwave Amplifiers
For an amplifier two-port we are interested in:
stability
power gain
noise (sometimes – small signals)
linearity (sometimes – large signals)
Maximum power gain (complex conjugate matching):
in S* out L*
For lossless matching sections
GT max
2
S 21 1 S
2
1
L
2
GT max
1
2
2
S 21
1 L
2
2
2
1 S in 1 S 22 L
2 1 S 1 S 22 L
For the general case of the bilateral transistor (S12≠0)
Γin and Γout depend on each other so the input and
output sections must be matched simultaneously
Simultaneous matching can be achieved if
and only if the amplifier is unconditionally
stable at the operating frequency, and |Γ|<1
solutions are those with “–” sign of quadratic
solutions
2 2
B1 B12 4 C1 B2 B22 4 C2
S L
2 C1 2 C2
2 2
B1 1 S11 S 22
2 2 2
B2 1 S 22 S11
2
C1 S11 S 22
*
C2 S 22 S11
*
Indicator across full frequency range of the
capability to obtain a power gain
graph is continuous S 21
MAG GT max K 1 GMSG
MSG S12
GMSG
[dB]
GMAG = GT max
K< 1 K≥ 1
Conditionally stable, Unconditionally stable, log(f)
Simultaneous matching Simultaneous matching
impossible possible
Design for Specified Gain
For an amplifier two-port we are interested in:
stability
power gain
noise (sometimes – small signals)
linearity (sometimes – large signals)
In many cases we need an approach other
than “brute force” when we prefer to design
for less than the maximum obtainable gain,
in order to:
improve noise behavior (L3 + C9)
improve stability
improve VSWR
control performance at multiple frequencies
improve amplifier’s bandwidth
Certain applications may require a certain ratio
between maximum / minimum line voltage
Vmax 1
VSWR
Vmin 1
Quality factor Q
X G
Q const
R B
High quality factor is equivalent with narrow
bandwidth
Design for maximum gain at two different
frequencies creates an frequency unbalanced
amplifier
MAG
MSG
[dB]
f1 f2 log(f)
Design for maximum gain at highest frequency
Controlled mismatch at lower frequency
eventually at more frequencies inside the bandwidth
MAG
MSG
[dB]
f1 f2 log(f)
Assumes the amplifier device unilateral
Input and output can be
treated independently
2 2
2 1 S 1 L
GTU S 21 2
2 S12 0 in S11
1 S11 S 1 S 22 L
S12 = 0.119-21°
1 S 1 S
11
2
22
2
GTU S 21
2
1 S11 S 1 S 22 L
2 2
2 2
1 S 2 1 L
GS 2
G0 S 21 GL 2
1 S11 S 1 S 22 L
GS GS S GL GL L
If the unilateral assumption is justified :
power gain added by the input matching circuit is not
influenced by the output matching circuit GS GS S
power gain added by the output matching circuit is not
influenced by the input matching circuit GL GL L
Output /Input match can be designed independently
We can impose different demands for input/output
Total gain is:
GT GS G0 GL GT dB GS dB G0 dB GL dB
2
1 S
GS 2
1 S11 S
S12 = 0.119-21°
1 S 1 S
11
2
22
2
Circles
2
1 S
GS 2
1 S11 S
GS max GS S S11
*
1 2
GS dB 10 log S
1 S 2
11 S
GS max GS S S11
*
The normalized gain factor (linear scale!)
2
GS 1 S 2
gS 2
1 S11 1
GS max 1 S11 S
Locus of the points with fixed values gs<1
1 1 S
2 2 2
g S 1 S11 S S 11
g S S11
2
1 S11
2
S
g S S11
2
S S *
11
S 1 S11 g S
*
2
S 2
g S2 S11
2
gS S *
*
1 S11 g S
S S*
1 1 g S
11 S 11 S
1 1 1 g S S11 2 2
2 2
1 g S S11 S 11
S
g S S11
*
1 g S 1 S11
2
S CS RS
1 1 g S S11 1 1 g S S11
2 2
CS
g S S11
*
RS
1 g S 1 S11
2
1 1 g S S11 1 1 g S S11
2 2
RS
1 g S 1 S11
2
1 1 g S S11 1 1 g S S11
2 2
1
Maximum gain for L *
S22 GL max 2
1 S 22
2
GL 1 L 2
gL 2
1 S 22 1
GL max 1 S 22 L
Similar computations
CL
*
g L S 22
RL
1 g L 1 S 22
2
1 1 g L S 22 1 1 g L S 22
2 2
1
GL max 1.051 0.215 dB
Example 1 S 22
2
2
1 L
GL 2
1 S 22 L
2
1 L
GL 2
1 S 22 L
GL max GL
L S 22
*
1 2
GL dB 10 log L
1 S 2
22 L
GL max GL
L S 22
*
Circles are plotted for requested values (in dB!)
It is usefull to compute GSmax and GLmax before
in order to request relevant circles
We compute G0, GSmax , GLmax
To obtain the design gain we choose supplemental
gain needed (supplemental to constant G0)
we account for the deviation that might arise from the
unilateral assumption (using unilateral figure of merit U)
GdesigndB GS _ designdB G0 dB GL _ designdB
We plot the circles for design (chosen) values
GS_design , GL_design
We design input and output matching circuits
which move the reflection coefficient on or inside
the design circles (depending on specific
application requirements)
Low-Noise Amplifier Design
For an amplifier two-port we are interested in:
stability
power gain
noise (sometimes – small signals)
linearity (sometimes – large signals)
The noise figure F, is a measure of the reduction in signal-
to-noise ratio between the input and output of a device,
when (by definition) the input noise power is assumed to
be the noise power resulting from a matched resistor at T0
= 290 K (reference noise conditions)
Si N i
F
So N o T0 290 K
The noise figure F, is not directly a measure of the
reduction in signal-to-noise ratio between the input
and output of a device, when the input noise power is
different from that of the reference noise conditions
Si N i
F
So N o T0 290 K
In general, the output noise power consists of
two elements:
the input noise power amplified or attenuated by the
device (for example amplified with the power gain G
applied also to the desired signal)
a noise power generated internally by the network if
the network is noisy (this power does not depend on
the input noise power)
P1 S1 N1 P2 S2 N 2
Estimation of the internally generated noise
power can be done using the Noise Figure F
definition:
S2
N2 F N0 F N0 G
S1 N1 S1
F
N 2 N0 G F 1 N0 G
S2 N 2 T0 290 K , N1 N 0
P1 S1 N1 P2 S2 N 2
We identify the two terms:
amplified input noise
N 2 N0 G F 1 N0 G
internally generated noise
When the input noise does not
correspond to reference noise
conditions (N1 ≠ N0) N 2 N1 G F 1 N0 G
the internally generated noise
does not change
P1 S1 N1 P2 S2 N 2 P3 S3 N3
P1 S1 N1 P3 S3 N3
P1 S1 N1 P3 S3 N3
Gech G 1
2
N 2 N1 G 1 F 1 N 0 G N1 G 1
2 2
F 1
1
2
N0 G 1
2
F 1
N 2 N1 Gech Fech 1 N0 Gech Fech 1 F
1
2
!FREQ Fopt GAMMA OPT RN/Zo
Fmin = 0.54 (tipic [dB] !)
!GHZ dB MAG ANG -
RSS 1 10
RPS 10 100
RSL 1 10
RPL 10 100
3 noise parameters (2reals + 1 complex):
RN
Fmin , rn , opt
Z0
RN 2 1 1 S 1 1 opt
F Fmin YS Yopt YS Yopt
GS Z 0 1 S Z 0 1 opt
2
S opt
F Fmin 4 rn
1 1
S
2
opt
2
S opt
*
S
opt N 1 S
* 2
2
S S* N S S opt *
S* opt opt opt
*
2
N
2
S opt S opt
* *
N opt opt
S S
*
opt opt
*
N 1 N 1 N 12
S
opt
N N 1 opt
2
Im Γ
+1 x x0 2 y y0 2 R 2
N 1 N 1 0 R
R
S CF RF
y0 Γ0
-1 +1
x0 Re Γ
-1
2
N N 1 opt
opt S CF RF
S
N 1 N 1
2
N N 1 opt
opt
CF RF
N 1 N 1
The locus in the complex plane ΓS of the points with
constant noise figure is a circle
Interpretation: Any reflection coefficient ΓS which plotted
in the complex plane lies on the circle drawn for Fcircle will
lead to a noise factor F = Fcircle
Any reflection coefficient ΓS plotted outside this circle will lead
to a noise factor F > Fcircle
Any reflection coefficient ΓS plotted inside this circle will lead to
a noise factor F < Fcircle
The noise internally generated by the transistor
depends only by the input matching circuit
A minimum noise figure is possible (NFmin – a
datasheet parameter for the transistor)
If we design a low noise amplifier (LNA) the
usual design technique is as follows:
design of the input matching circuit solely (largely) for
noise optimization
design of output matching circuit for gain
compensation/optimization (if lossy circuits are used
the output matching circuit noise can be added but
the transistor noise is not influenced)
Usually a transistor suitable for implementing an LNA
at a certain frequency will have input gain circles and
noise circles in the same area for ΓS
Connecting the amplifier (transistor) directly
to the source with Z0 generate a reflection
coefficient seen towards the source equal
with 0 (complex, 0 = 0 + 0·j)
most of the time this reflection coefficient does
not offer optimum noise/gain
Z0 Γ0 = 0 ΓS = 0
V0 [S]
We plot on the complex plane (Smith Chart) the stability/gain/noise
circles (depending on the particular application)
We choose a point with a suitable position relative to these circles
(also application dependent)
We determine the input reflection coefficient corresponding to this
point, S
S 0.412 177.966
We insert the input matching circuits which
allows the transistor to see towards the source
the previously determined reflection coefficient
S
Z0 Γ0 = 0 ΓS 0
Input
V0 matching
circuit
[S]
Easiest to design matching section consists in
the insertion of (in order from the transistor
towards the Z0 source):
a series Z0 line, with electrical length
a shunt stub, open-circuited, made from a Z0 line,
with electrical length sp
Z0 Γ0 = 0 Z0 , ΓS 0
V0 Z0 ,sp [S]
Computation depends solely on S (magnitude
and phase)
2 S
cosS 2 S tan sp
1 S
2
V0 Z0 ,sp [S]
|Γ|=1 90° Zin,Γ0 ΓL
-1.0
-2.0 Z0 Z0,β·l
135° -0.5 45° ZL
V0
-0.2
180°
2.0 1.0 0.5 0.2 0°
Γ0 ΓL
+0.2 Z0
j·B1 YL
+0.5
V0
225° +2.0 315°
+1.0 in L gin 1
270°
ATF-34143 at Vds=3V Id=20mA.
@5GHz !ATF-34143
!S-PARAMETERS at Vds=3V Id=20mA. LAST UPDATED 01-29-99
!FREQ Fopt GAMMA OPT RN/Zo
Fmin = 0.54 (tipic [dB] !)
!GHZ dB MAG ANG -