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VLSI DESIGN
UNIT-I CMOS TECHNOLOGY
MOS TRANSISTOR - Introduction
Si Si Si
Si semiconductor Forms basic material
Si Si Si
for Large Class of ICs
Si Si Si
+ -
Si As Si Si B Si
Structure is created by
Superimposing several Layer of Si Si Si Si Si Si
Conducting &
Insulating materials To
Form a structure like
Sandwich
SYMBOLS
nMOS pMOS
CROSS – SECTION:
Now
n+ n+ Gate is typically formed
p bulk Si from
Polycrystalline silicon POLYSILICON
nMOS transistor:
Physically equivalent
& interchangeable.
Body typically Grounded.
pMOS transistor:
Consider,
An Isolated MOS structure NO D (or) S
Only Gate & Body
0 < V g < Vt
+
depletion region Depletion
-
( Vgs Vt )
(b)
V g > Vt
+
inversion region Inversion
- depletion region
So
pn junction of S & D Body RB.
Transistor = OFF
ii) If G volt Creates Electric Field
&
Source Gate Drain
Polysilicon Starts to attract free Electrons
SiO2 underside of Si - SiO2 interface………….
1
n+ n+
S D
p bulk Si
Transistor = ON.
PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.
Consider
pMOS transistor
Pn junctions of S & D RB
No current flows
Source Gate Drain Transistor = OFF.
Polysilicon
SiO2
p+ p+
n bulk Si
When,
Gate = V
Transistor = ON .
NOTE :
High pot. VDD (or) power Logic ‘1’ 5v (or) occasionally Higher
d d d
nMOS g OFF
ON
s s s
d d d
pMOS g OFF
ON
s s s
Called 'S'&'D']
Cut off : no channel ( Ids = 0)
i] Vgs < Vt :
Ids = 0
This mode of operation is called
Cut Off.
ii] Vgs>Vt:
Inversion region of electrons (majority carriers) called Channel .
Vgs > Vt
Vgd = Vgs
o No electric field tending to push ct.
+ g +
- -
From D S.
s d
n+ n+ Vds = 0
When a small (+)ve potential is applied (Vds)
p-type body Ids flows Channel
b from D S.
Vgs > Vt
+ g +
Vgs > Vgd > Vt This mode of Operation is
- - Ids Linear, Resistive and Unsaturated.
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b
Ct. with both Drain Voltage
& Gate voltage.
PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.
n+ n+
near the drain
Vds > Vgs-Vt
&
p-type body
b
Accelerated drain.
Ct. Id Vds.
IDEAL I – V CHARACTERISTICS
Mos Tr. 3 regions of operation:-
i] Cut off (or) Sub threshold region
ii] Linear (or) Non saturation region
iii] Saturation region
To form channel .
Where,
Cg Capacitance of gate.
Vgc Amt. of voltage attracting charge
to the Channel beyond the min.
required to Invert from p to n.
Gate voltage reference to the channel
If G Length, L
Width, W &
Oxide thickness, tox.
Then, capacitance, Cg =ox WL
tox
Permittivity, ox= 3.90
polysilicon
gate Permittivity of free space (8.85x10-14 f/cm)
W
ox
tox
tox cox capacitance/unit area of gate oxide
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.9)
p-type body Tr. Dimensions In cut off : Vds < Vt ; Ids = 0
i]Assume (Vds < Vdsat) : Gate is not saturated [Vgs > Vt] [Vds < Vgs – Vt]
In this region voltage along the channel varies linearly with distance, x from
the source due to IR drop in channel.
Charge/unit area = Eg
Permittivity
r o
Induce charge, Qc = Eg WL
oxide thickness
0 Vgs Vt cutoff
I ds Vgs Vt ds Vds Vds Vdsat
V
linear
2
t
2
V gs V Vds Vdsat saturation
2
Ids (A)
400
Vgs = 1.8
300
Vgs = 1.5
200
Vgs = 1.2
100
Vgs = 0.9
Vgs = 0.6
0 Vds
0 0.3 0.6 0.9 1.2 1.5 1.8
Plot I vs. V
ds ds
– V = 0, 1, 2, 3, 4, 5
gs
– Use W/L = 4/2
PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.
C – V CHARACTERISTICS
I. Simple Mos - capacitance models
II. Detailed Mos - gate capacitance model
III. Detailed Mos - diffusion capacitance model
When Tr. = ON
So,
Gate capacitance terminating at the source
&
Thus called as capacitance Cgs.
PREPARED BY A.KARTHIKAYEN AP/ECE
PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.
Where,
Cper micron = Cox L = (ox/tox). L
If we develop a more advanced manufacturing process in which
“both channel length &
oxide thickness” are reduced by
same factor,
Cper micron remains uncharged.
[1.5 - 2 fF/µm]
In addition to the Gate,
Source & Drain also have capacitance .
i.e. Co = WL Cox
I. Cut off :
When transistor = OFF [Vgs = 0]
II. Linear :
When, Vgs > Vt
So,
Greater fraction of the cap. is attributed to the source
&
Smaller fraction to drain.
III. Saturation:
At Vds > Vgs – Vt
Transistor saturation &
Channel pinches off.
At this pt.
All the intrinsic
capacitance is to the source.
Because of pinch off ,
Capacitance in saturation
Cgs = 2/3 C0 .
(For an Ideal Transistor)
PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.
2. Overlap capacitance:-
Vg – Vt values .
Note:-
o At Vds = 0;
Cgs = Cgd = C0/2
As Vds Cgs = (2/3) C0
& Cgd = 0
When transistor saturated.
Short channel transistor [W = 49.2µm, L = 0.75µm]
Cg = Cgs+Cds+Cgh ≈ C0.
PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.
ψ0 = VT ln NA ND
n2i
where,
VT = Thermal voltage = (kT)/q ( not threshold)
(26 mv at room Temp. )
K = 1.380 x 10-23 J/K (Boltzmann const.)
T = Abs. Temp.(300k at room temp.)
q = 1.602x10-19c
NA = doping levels of the body & source diffusion
region.
ND = Intrinsic carrier concentration in undoped
Silicon. (1.45 x 1010 cm-3 at 300k)
Sidewall Capacitance,
Cjbssw CJsw [1+Vsb/ψ0] –MJsw
PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.
Compares Characteristics in the Linear & Saturation Regions with Ideal Device
IG = Ideally ZERO
However,
Thickness of Gate oxides only a small no. of atomic layers
&
Causes some „G‟ ct. IG
1) VELOCITY SATURATION
2) MOBILITY DEGRADATION
3) CHANNEL LENGTH MODULATION
4) BODY EFFECT
5) SUBTHRESHOLD CONDUCTION
6) JUNCTION LEAKAGE
7) TUNNELING
8) TEMPERATURE DEPENDENCE
9) GEOMETRY DEPENDANCE
Refers to the limiting of carrier velocity at high field
1) VELOCITY SATURATION:-
(Different from saturation region of Tr.)
W. k. t,
Carrier velocity , V = µE
E Electric field
µ Electron (or) Hole mobility
V Carrier drift velocity
Carrier velocity,
sat / 2
μElat
v vsat μEsat
E
1 lat
slope = Esat
0
0 Esat 2Esat 3Esat
Elat
Vgs = 0.9
0
0 0.3 0.6 0.9 1.2 1.5 1.8 V
Vgs = 0.6 Called Velocity Saturation Index.
ds
But,
- Power fit Reasonably good.
There is no performance
Benefit to raising VDD.
2) MOBILITY DEGRADATION:-
Ideal, Ids independent of Vds for a Tr. in saturation .GND VDD VDD
Source Gate Drain
Depletion Region
Makes the transistor as a perfect current Width: Ld
Source
L
n+ n+
RB pn jn. between the D & body forms a Leff
p GND bulk Si
depletion region
with a
Width, Ld that with Vdb.
Vgs = 1.8
Assume source voltage is close to the body voltage,
300 So Vdb ≈ Vds
Vgs = 1.5
200
Hence Vds Effective channel length.
Vgs = 1.2
100
Vgs = 0.9 Shorter channel length ,
Vgs = 0.6
0 Result: higher current.
0 0.3 0.6 0.9 1.2 1.5 1.8 Vds
[ Ids↑ with ↑Vds in saturation ]
I-V Characteistics of Nmos transistor with channel length modulation
Modeled by,
2
In sat region , Ids = β [(Vgs – Vt) /2 ] (1+λVds)
4) BODY EFFECT:
Vsb
As Overall Effect :
Threshold voltage ,Vt .
PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.
i.e ) Pot. Diff. between S & Body, Vsb Affects the threshold voltage.
Vt Vt 0 s Vsb s
Where,
Vto Threshold voltage when „S‟ is at the body Potential.
tox 2q si N A
2q si N A
ox Cox
5) SUBTHRESHOLD CONDUCTION:
Ideal transistor I-V model assumes
Current only flow from S D
o Leakage Exponentially
As Vt (or) As Temp.
i.e.)
V‟t = Vt - ηVds
Where,
η DIBL co-eff [typically 0.02 – 0.1]
ID = Is [℮ VD/VT - 1]
PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.
Leakage Sources
Subthreshold conduction
– Transistors can’t abruptly turn ON or OFF
Junction leakage
– Reverse-biased PN junction diode current
Gate leakage
– Tunneling through ultrathin gate dielectric
Subthreshold leakage
o Biggest source in modern transistors
6) JUNCTION LEAKAGE:
p+ n+ n+ p+ p+ n+
n well
p substrate
o Substrate GND
To ensure diodes RB.
o Well VDD
o However,
RB diodes still conduct a small amount of current , ID.
Is depends on
– Doping levels
– Area and Perimeter of diffusion regions
– Typically < 1 fA/mm2
–
PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.
7) TUNNELING:
According to Quantum Mechanics
there is a finite probability that carriers
Will tunnel thro‟ the gate oxide.
10 9
tox
6
VDD trend 0.6 nm
10
0.8 nm
JG (A/cm )
1.0 nm
10 3
2
1.2 nm
10 0 1.5 nm
1.9 nm
10 -3
10 -6
10 -9
Gate leakage current density, JG Vs Voltage (VDD) for various oxide thicknesses.
Note:
Key challenge is Finding material that form a high
Quality interface with silicon.
(1 contender is silicon nitride
with a (Si3 N4) dielectric constant of 7.8)
Tunneling current is an
Order of magnitude Higher for nmos
than
Pmos Trs. with Sio2 Gate dielectrics
Because,
Electrons tunnel from the Conduction band
Note:
Different dielectrics may have different tunneling properties.
8) TEMPERATURE DEPENDENCE:
Where,
T Absolute temp.
Tr Room temp.&
Kµ Fitting parameter [1.2 – 2.0]
Conversely ,
Temperature Sensitivity :
Increasing temperature I ds
o Reduces mobility
o Reduces Vt increasing
temperature
ION decreases with temperature
IOFF increases with temperature
Vgs
9) GEOMETRY DEPENDENCE:
For E.X:
Manufacturer may create marks with narrower
Polysilicon (or)
May over etch polysilicon
Provides
Shorter channels (-XL)
without Changing the overall
Design rules (or) metal pitch.
Moreover,
S & D tend to Diffuse laterally under the Gate by LD.
Producing a
Shorter Effective Channel Length
|||ly,
Diffusion of the bulk by WD ↓d Effective Channel Width.
Combining Threshold,
Effective channel length &
Channel Length modulation
Effects a tr. of
GEOMETRY DEPENDENCE: