Scribd Logo
Fazer o upload

Bem-vindo(a) ao Scribd!

  • Sms Com52c50

    Enviado por

    Ashish Singh
    23 visualizações18 páginas
    Sms

    Direitos autorais

    © © All Rights Reserved

    Formatos disponíveis

    PDF ou leia online no Scribd

    Você considera este documento útil?

    Este conteúdo é inapropriado?

    Denunciar este documento
    Sms

    Direitos autorais:

    © All Rights Reserved
    Baixe no formato PDF ou leia online no Scribd
    Sinalizar o conteúdo como inadequado
    23 visualizações18 páginas

    Sms Com52c50

    Enviado por

    Ashish Singh
    Sms

    Direitos autorais:

    © All Rights Reserved
    Baixe no formato PDF ou leia online no Scribd
    Sinalizar o conteúdo como inadequado
    de 18
    STANDARD MICROSYSTEMS CORPORATION — COM52C50 PRELIMINARY TWINAX Interface Circuit (TIC) FEATURES conforms 0 IBM® 6250 Standard used in IBM System (36 and /38. 1 Operates at {Mbps Data Rate 7 Transmits and Receives Manchester Il Encoded Data i On Chip Odd or Even Parity Generation and Checking 1 Programmable Interframe Zero Bit Insertion i Handles Multi Byte and Single Byte Transfers (1 Mutiple Address Select Register Alows for Up to 7 Node Address Emulation © Programmable Extended TX Enable 1 Internal/External Loopback Capability for Sel Test Diagnostics On Board Predistorton Circuitry 1 Low Power CMOS 1D On Board Crystal Osciator Simplifies Clock Generation 11 8 MHz Clock Output for General Use C1 Incorporates a Three Level Receive FIFO to Simply Processor Intertace © Compatible with high speed microprocessor with no wait state up to 10 MHz (80186, 68000 etc.) 1D Programmable DMA and Jump Vectoring Interface 1 Independent RX DMA and TX DMA Request Signals Cl Programmable Interrupt Selection 1 28 Pin Plastic Dual In Line and Chip Carrier Packages 1D Open Drain Output on interrupt Pins D1 TTL Compatible Inputs and Outputs 1 Single +5v Supply PIN CONFIGURATION wa Rr. FEST RK OMA Xtal: cuxour veh @xowa 7p ciKour wep or IAL, EN XI PACKAGE: 28-pin PLOC GENERAL DESCRIPTION The COMS2C50 TWINAX controller is a CMOS device that performs the communications interface to the IBM 5250 FWINAXIAL bus. interfaces to a general purpose micro- processor on one side and fo the IBM 5250 TWINAXIAL Dus onthe other side. The COMS2C50 handles the paralle| toserial and serialto paralle! conversion of data to and from the TWINAXIAL bus and the encoding and decoding of (90> isa registered rademar« ofthe International Bsiness Machines Corporation 7 data in Manchester Il format, The COMS2C50 consists of a RECEIVE BLOCK, a TRANSMIT BLOCK, and CONTROL circuitry. The Receive and Transmit sections of the COM52C50 are separate and may be used independent of one another. The COM52C50 generates and detects the bit Syne, frame syne, parity, and the fil zero bit patterns ‘according to the IBM 5250 standard, =] spores a Tae] contmon recevestatus || pany once Lf peceve REGISTER Faaite Grex [| conto. 1 ee surracoisren [7] “tocie™” [fan CONTROL +— Cay wien KX] ———— 5 Boe vs U ob a ODE peosteR conTROL 2a omggere | iy J obit 2 ADDRESS SELECT] Teast REGEIER eurrER sratusaeticren! —} forester I | INTERRUPT Asi Tansy freavsser starus][~ Trans |_[parirea reane ee xen reasten Connor (GENERATION conto: [Me emu — we ig. 1— COM52C50 INTERNAL BLOCK DIAGRAM Eee DA eee Tx DMA ZF TWMNaxtat oe = AOA ryan renrace 7% ware | dv cnt FD | +|AD aM a nv 7 = INTERRUPT = Px REGUES! inte | RESET CLKOUT XTAL1 XTAL2 systeu T L 0 J ewaz 1 wz Fig. 2—TYPICAL COMS2C50 INTERFACE 78 ‘TABLE 1 - COM52C50 TWINAX DESCRIPTION OF PIN FUNCTIONS: [_PINNO. NAME ‘SYMBOL DESCRIPTION WE jg | Bdactonad— | Oe-Ds 7b BLDATA BUS is ved to rertace te COMS2080 he oF processor Data Bus. 3 Write Data mA ‘A low pulse on tis input (when OS is low) enables the COMS2C50 | Strobe | facet te ata or orl ilomaton rom fe DATA BUS ine | the COMS2650 4 TX Enable KEN | This ouput is active aw when he ans data is val, Ris used to | enable the external TX driver circulty 5 Delayed TX oR Delayed TX Manchester encoded. | x Data ™ “Transmit data Manchester encoded 7 Treste | ow | The Due ead aaa onrein 8 PX Data »K “This input accepts the receive Manchester Il encoded bit stream " Reset Fst ‘This pin resets the COMS2C50 lo a known stale. Inaction it disables, the TX and pus an inacve sate on the interrupt ines. 2 coal? sae | Anexomal 6 tents connate hese wo ps an enteral 3 Gystal 1 xTALy Foe eects tskoud be comeced io TAL, wha | | £380 ohm pulup resistor XTAL, must be let floating | cone ono Ground | 7 | Clock out cLKOUT This is @ divide by two of the XTAL:, 16 MHz input clock. it has a 50/50 | uty cycle and can be used as @ clock input othe host microprocessor 8 | mxeuter | xDMA | Tho RX Bute Ful signals used as a receive DMA request | | Error Related =| NTs Tis active low open drain ouput provides he intemust signalfor | interupt error related operations. | 20 Data Relates | NT. | This active low open drain output provides the inerupt signal for | toterupt | dala related operatons 2 fagser | | dung recess o cOMsz080 communicates. hese inputs are | 2 Address Select | x Used fo nciate which internal register willbe selected fo access by 2 fe the processor: | 24 Read Data ®D | ow pulse on tis input when Cis ow) enabes the COMSZCSO 10 | Srobe piace the data or status information on the DATA BUS. | 25 Chip Select les | Alovr tevei on this input enables the COM52C50 for reading and | | tring by be processor nen CS is hgh ho DATABUS 6 nigh | impedance and the WA and FD will have no effect on the ip. 28 Power Supply | Vee | *5V Power Supply Neen FUNCTIONAL DESCRIPTION RECEIVE BLOCK ‘The COMS2C50 recovers frames that conform to the IBM 5250 protocdl.It also checks the received frame for proper syne, parity and trailing zeros. The RX inputis sampled at 8 times the bit rate. The receive logic is brought into synchronization during bit and frame synchronization patterns. The internal receive clock is adjustéd after each AX transition to compensate for bit iter and distortion inthe received data signal. In addition to the Receive Shift Register, the Receive block incorporates a two level First in-First-out (FIFO) buffer, Al the start of a message, the host microprocessor is alerted by handshake signals like Line Idle, Frame Sync Detect, Poll Command Detect, and ‘Address’ Match. Thereafter, the RX Buffer Full signal informs the host microprocessor of the availablity of received data, Tho end of a receive message is marked by ‘ether the detection of 1) End Of Message sequence 2) Line Idle or 3) Receive Error 73 ‘TRANSMIT BLOCK ‘The COMS2C50 transmits data frames that conform to the IBM 5250 protocol, The transmit block consists of an 8 bit data buffer register, a present address register, 16 bit parallel to serial shif register, and parity generation logic. A {ransmit operation is initiated by loading the transmit buffer, register. The transmitted frame will consist of the sync bit, the 8 bits loaded by the host microprocessor into the buffer, register, the present address from the PRESENT [ADDRESS REGISTER, or the (111} end of message code it the last frame is being transmitted, followed by a parity and three zero fillbits. After the host microprocessor loads the transmit buffer register, the TRANSMIT BUFFER EMPTY bit in the status register will become inactive. After a transfer of a data frame from the buffer register to the shift, ragisteris accomplished, the TRANSMIT BUFFER EMPTY bitinthe INTERRUPT AND TRANSMIT STATUS REGISTER becomes active, BIT STREAM J 1 te The bit stream Is serially transmitted to (or received from) the System Unitata transmission bitrate of | Mbps (+2) Therefore, 1 microsecond is requires for each bit, and 16 microseconds are required for each frame. All information between a station and the System Unitis transmitted on the twinaxial cable, The COMS2C5O provides the transmitted J+ 1ys ——+le—— ys ——Je us —x] serial data in Manchester encaded format where a {one} bit is represented by a halt bit cell of logical high followed by a halt bit cell of logical low, and a0 (zer0) ots represented byahalfbitcellofiogicallow followed byanalf A message contains a bit sync pattern, a frame syne bitceiloflogical high. In addition, the COMS2C50 provides pattern, and a frame. The bit sync and the trame sync a Delayed Transmit Data signal which is delayed by 1/4 o! patterns establish synchronization between the station and a bit ime to simplify the interface to the external driver the SystemUnit,and are ransmited prior to transmission of circuitry the first frame. TABLE 2 - IBM 5250 FRAME FORMAT The frame format for command and data to and from the IBM 5250 attachment is a fixed 16 bit frame. Only 13 bits contain information. The general format is as follows: Transmission start soquence (One 5250 kame (16 ts Saas Se pee 10] 10]10] 10] 10] 1] 10] 00] s Joo} 0x42] 03] 04] os] os] o7]ao | ar]a2| » | ox or or —— —_— Sichionzaboy \ ~ Frame synerarz aT | DESCRIPTION 0-2 | These bis are always a 3 | Tis is designated as the party bt and wi be seo ensure even party in each Kame 4-6 | These ae the physical staton address. Valid accresses are 000 to 110, and 111 isthe end of message delimiter forthe cable frame coniamning a 11 staton address causes tho station to ignore al folowing cable actvty ntl abit and name sychronization is decid folowing ale turnaroung. In adiion only one Fame | is sen om the ysiem unt, thse bts represent he station adress, only one ame s sent am the werk sation, these bis ae set io 111 7-14 | thasebis conan commana ntraton They epost adbeast bom he San they representa dala byte ora command trom the system unt Ls hiss the syne bit isthe fst bt onthe ino anditis always set10 1 RESETTING THE COMS2C50 should write a “one” in bt 0 of the Control Register. The COMS2C50 must be resel on power up. This is Writes tothe Control Register bitO should be spaced accompishedby eter of two methods: Hardware Reset or such that the Internal Reset signal has a minimum Software Reset duration of iy. Hardware Reset Upon reset, ll of the internal registers of the COMS2C50 — will be cleared. in addition, the COMS2C50 enters an idle Onthe COMS2C50 aRESET pinis dedicatedto allow state in which it can neither transmit nor receive data. To ‘esetting of the device by applying a low level on the disable undesired interrupts, the Interrupt Mask Flegiste is RST pin. The RESET signal should have aminimum set 1000 and the Status Registers bits are all inactive. duration of 14s, Software Reset: INITIALIZING THE COM52C50 The chip will also be reset when the Software Reset Following RESET, the COM52C50 should be initialized by bit in the Control Register is asserted. The host writing a vali bit pattern to the Interrupt Mask Register, the microprocessor asseris Software Reset by writing a Mode Register the Station Address Select Register. At this "zer0" in bit O of the Control Register. To take the point, the Control Register can be used to enable Receive COMS2C5O out of reset, the host microprocessor and Transmit 80 ‘TABLE 3 - REGISTER DECODE & TRUTH TABLE FOR INTERNAL REGISTER SELECT [ aporess | a2 A1 AO RD WA i 00 tO | Mode Regiser | w 80 88S Nettie im or Qo 0 1 1 © | Interrupt Mask Register Ww | f 8 8 4 oF J leptin Retr ® @ | 0 3 8 xo | ates Sect Regt: w | 0 1 9 0 1 RX Status Register R | ° 0 tt tO, Canto Register w 0 1) 4 Ot | FX Buter R a jw pa 8 8 oF | Nettie z 05, 1 o 4 1 0 | Present Address Register | w 1 8 to S| Present Adress Register ® | 06 1 1 ° 1 o | TxButer w | 5 07 1 1 1 1 o | TXButfer EOM lw Pod 4 oF | Pastas Reger LR REGISTER DESCRIPTIONS frames, Up to 256 zero bits may be inserted in between aeaoeaenl trames Iho zero bit filig required, tis register should De This is the second level af a two byte deep Receive FIFO where the COMS2C50 Receive Block provides new data land the microprocessor reads it This register contains the 8 bit information field of an IBM5250 frame [bits 14-7). Itis readby the host microprocessor after each frame reception which is indicated by the AX Buffer Full bit. This is an 8 bit read only register. ‘TX BUFFER, This register contains the 8 bit information field of an 1BM5250 frame (bits 14-7). It is written to by the host microprocessor and contains the information to be sent out in the next frame, This is an 8 bit wite only register. ZERO FILL REGISTER This eightbit register is loaded by the host microprocessor and contains the number of zero bits that should be filled between two frames. The host microprocessor would read a Set Mode Command and find out how many zero bytes mustbe padded on the next reply and then convertitto bits and write itto this register. The COM52C50 takes care of inserting the programmed number of zero bits between two Cleared by writing @ zero. The host microprocessor may not ‘write to this register during data transmission. This register is cleared following RESET. INTERRUPT MASK REGISTER ‘This is an 8 bit write only register whichis loaded by the host mmcroprocessor. This register controls interupt generation ontothine INTiand INT? iteruptpns, Themostsgniicat 5 bits enable the generation of INTi, the least significant 3 bits enable the generation of INT2, iNT A logical one in a particular bit position will enable the corresponding bitin the Interrupt Status Register (bits 7-3) to cause an interrupt when itis set. INT2 ‘logical one in a bits (2-1 -0} wil enable bits (7-6-§) inthe RX Status Register to cause an INT2 interrupt when itis set Upon Reset, this register is cleared to all zeros thereby disabling interrupts. This is an 8 bit write only register. ADDRESS SELECT REGISTER ‘Thisis an eightbit Write Only Register that controls address bit recognition of any of the seven possible node addresses, Anode may emulate more than one address at atime by programming a “one” in the corresponding bit of the Address Register. ‘A“one’ in any one or more of the Address Selectbits allows, the COMS2C50 to respond to that group of addresses, ors st [ one | oe [ms | oe | me | ee | ed ramps ae |_ Era oneaaoss Dyepeteys foley Emulate four adoresses:(6-4-8-0) t ti fops ta Saat at a @ 8 iy on | mm | an | ou | ma | on woe"! oer | owe | om | owz | ome | so Oa HPL “aveiou SENS NL. is on J me | an | ow | ma | on | om | on | oo ez | vowma || cee | oz | one | ome | om | 90 x “eine XL TovsiBog smIES XL oy | w]e | om | owz | owz | os | owe | so | ov | w | zy | ome | awe | owe | owe | om | so “ermioy saeippy 1usHeId “einiag supp WoREIE oo | so | 2a | co | mm | ca | 0 | 1 | peenion v0 “ereiou ng OZ we] e] wns | vAO | oS oe attmyoe | aaeve | oneio | onevs’ | ‘ones | anesp | oz | esa | a ow | ow | am | om | wa | ow | oe | oe | oo 7eveiogjonueg ene ee eee 1] pa [29 | cen, ov wl aw lw] wl] wv | w | ow ral ose | oy w | av | scum | abessow] “op a) 2 xe sp pue oul La 42918168y Deis sSeIpPY sorsiBoy smeis Xu freezes af yp arson pou x oud Jp vr aie | Bae Tae | ep "im | —018| an] kis] — | aR PaRP stessou) “ape | sioue | soyra | sopra |puewuce| urew | ‘sue | yo | ued | oseuda | unnoro | oyna | sauna [powunaco| yoow | ‘auxe | ig opus | ots | xu | Se | xm [tod | stone | ouey we ar | | ar tos] ssappe | owe daysiBoy xSeW JaneW seysiBoy smieis dnsayuy waa | ace ex mua | Aa epow | sig | wo | pow | 00 doo | ewan xe x 389, sige” one Ba. eee “eyai6ou 20H, vie | tue [ena [ene [vue | sue | oie | cue cue | tie [ene [cue | vue | sue | ene [cue NOwamosI0_—_sSaNaav Nowawosa0a—— _Séauaay ‘SUSLSIOSU JILIN, SWVUOVIC UaISIOSH - ¥ FTavL PRESENT ADDRESS REGISTER This register holds the present address information of the first frame following frame sync, Its used to convey the ‘address information to the host micropracessor and hasthe ‘address field information on all outgoing frames. This register is loaded by the Receive Block with the address information from the frst frame following frame sync detect. This register can also be written to by the host microprocessor prior toinitating a Transmit sequence. The Contents of this register are fed to the address compare logic which compares the Present Address to the Address Select Register. Ifa valid compare is detected, the Address Match bitin the Interrupt Status Register is set. During a receive session, the contents of this register are valid only after the AX Buffer Full bit is set “one” This is an eight bit readiwrite register. ES ‘TABLE 5—COMS52C50 INTERRUPT STATUS REGISTER (BITS 0-7) This is an eight bit register that can be read by the host microprocessor. The Interrupt Status Register is cleared following sotware or hardware reset. The bits in this register are used 10 indicate the following information: Bir DESCRIPTION RX PARITY ERROR ‘Signals the microprocessor that the frame received contained an incorrect number of binary "1" bts. This bits Set when the received frame has an incorrect party bit and parity is enabled This bit is cleared by: 'a clearing FX Enable in the Control Register | |b setting Reset Errors n the Control Resistor ¢, asserting internal RESET. 4. asserting extemal hardware Reset 7 | RXBIPHASE ERROR frame | This otis cleared by '. clearing RX Enable in the Control Register ©. setting Reset Errors in the Control Regster ©. asserting internal RESET. 1. asserting external hardware Reset ‘Signals the microprocessor that a bit within a received frame has violated Biphase Manchester code (ie. the two hal bit cels of @ bt were not complements}. This bitis sel when a Biphase error occurs during bits 150 2 | BX OVERRUN ERROR This bit is cleared by. 2. clearing AX Enable in he Control Register. ©. Setting Reset Erors in the Control Register. ©. asserting Internal RESET. 4. asserting External Hardwave Reset Frame Sync Detect going active. 3 | TXBUFFER EMPTY to the Transmit Shit Register. This bit is cleared by: ‘2. Writing to the Transmit Buffer Register ©. cleaning TX Enable in the Control Register ©, asserting intemal RESET, 6. asserting external hardware Reset | 7x butler empty is zero, | AX BUFFER FULL Holding Register This bit i cleared by: a, reading the Receive Holding Register 5. clearing RX Enable in the Control register «, Frame Syne Detect going active d asserting internal RESET. ‘asserting external hardware Reset Signals the mecoprocessor that an Overrun condition has occured. This bts set when a byte stored in the Roce ve Holding Register is overwritien with a new byte from the Receive Shit Register before the microprocessor has tead the Receive Holding Register. Signals the processor that the Transmit Character Butferis empty and that the COMS2C50 can accept a new ‘characte for ransmission, This bts set when a character has been loaded from the Transmit Holding Register ‘This bit is nally set when the transmitter logic is enabled by setting the TXenable bitin the Control Register {also TX BUFFER is empty because of reset. Data can be overwmiten fa consecutive write is performed while Signals the processor that a completed characteris present in the Receive Butfer Register for transfer to the processor This bit is set when a character has been loaded trom the receive deserialization logic to the Receive ‘TABLE 5—COMS52C50 INTERRUPT STATUS REGISTER (BITS 0-7) CONTINUED air = = DESCRIPTION 5 | POLL GOMMAND DETECTED Signals the microprocessor thatthe command in the Receive Holding Register is a POLL command. [o0810000) This bit is set when the firs frame following Frame Sync nas the binary 10000 pattern in the least significant 5 bis ofthe data section This btis cleared by: ‘2 reading the RX Buffer Register when RX Buffer Ful is set bb. Frame Sync Detect going active asserting internal RESET. 6. asserting external hardware Reset | 6 | ADDRESS matcH Signals the microprocessor that a match has occured between the address field ofthe frst frame following Frame Sync and any bit within the Address Select Register. This bi is set aftr a valid compare has occured between the addeess feid of the fist frame following kame syne and any bit of he Address Select Register. This bit is cleared by: ‘a. reading the FX Butfer Register when RX Butfer Fullis set 1. Frame Sync Detect going active ©. asserting internal RESET. 4. asserting external hardware Reset. 7 | FRAME SYNC DETECTED | | Signals the microprocessor that a Frame Sync has been detected on the RX pin of the COMS2C50. The Frame Syne detect circutry checks for one "1" bit (10 hal bit) folowed by a three half bit times of ones folowed by a tee hal times of zeros (11000) Ths Bs et when a Va Frame Sync paler s detected is bitis cleared by. { 2. reading the Interupt Status Register B. Line idle going active © asserting internal RESET. 6. assering external hardware Reset RESETTING OF INTERRUPTS: ‘The INTi and INT2 signals feature an automatic interrupt action is taken by the processor. The following describes acknowledge that will take interrupt away when the proper _how each of the eight interrupting conditions get cleared. When ie ileus caused by. | The intoruplis cleared by Reading the Interrupt Status Register tw: Line Idle going active Internal Reset External Reset | Address Match Frame Syne Detect | Reading the AX Butter Register when the RX Butter is full | Internal Reset External Reset Poll Command Detect Frame Syne Detect | | Reading the AX Butfer Register when RX Buller is full | Internal Reset | External Reset RX Buffer Full Glearing the RX Enable bit Reading the RX Butfer Register when the RX Buller is full Internal Reset | Extormal Reset TX Bur Empty Writing to the TX Butfer Register Clearing the TX ENable bit Internal Reset |_ External Reset | RX Errors ‘Asseriing Reset Errats | Clearing RX Enable Internal Reset |_ External Reset Line Idle Detect Reading the RX Status Register twice Internal Reset | Exemal Reset : End of Message Reading the AX Status Register twice (EOM) Detect internal Reset | External Reset ‘TABLE 6—COMS2C50 RX STATUS REGISTER (BITS 0-7) This is an eight bit register that can be read by the host microprocessor The bits in this register are used to indicate the following information’ ar | DESCRIPTION 0 FIXED ZERO i 1-3 | PRESENT ADDRESS BIT 0-1-2 ‘These three bits hold the value ofthe Present Address, They are the same as the bts 1, 2,3, ofthe Present Adaress Register 4 RX BUFFER FULL ‘Signals the processor that a completed characte” is present in the Receive Butfer Register for transfer to the processor This bts set when a character has been loaded from the receive deserialization logic to the Receive Butler Register This bit is cleared by: ‘a. reading the Receive Butler Register 4. asserting intornal RESET ®. clearing RX Enable in the Control register © asserting external hardware RESET , Frame Syne Detect going active 5 LAST FRAME/End Of Message (EOM) Signals the microprocessor that a "1 1 pattern has been detected in the address field of an incoming frame. ‘Tis bil is propagated through the AX FIFO logic and it corresponds to the data byte immediately available to the processor This Dt is set when the 3 bit address field of a frame gets @ match with a constant "t 1 1” pattern. This bit is cleared by: 'a. Frame Sync Detect going active . asserting internal RESET, ©. clearing RX Enable in the Control Register. {asserting extornal hardware RESET é LINE IDLE Signals the microprocesso: that the RX ne has not seen a transition for the past us ime interval, This can be Used by the microprocessor to loarn thatthe FX line is dle, This bits set when the RX line remains idle for a 3 microseconds duration This bits cleared by. a. activity on the BX line «, asserting Internal RESET. », clearing RX Enable inthe Control Register 1. asserting External Hardware Reset. | 7 RX ERRORS, Signals the microprocessor that a Receive Error condition has occured. This bt is set when any one or both of the Intecrupt Slatus Register bts 0 and 1 are set This bit is cleared by. '2 asserting Reset Errors in the Control Register ¢. asserting Intemal Sofware RESET. . clearing AX Enable in the Control Register. 6, asserting External Hardware RESET. EEUU EEE EEE ‘TABLE 7—COMS2C50 TX STATUS REGISTER (BITS 0-7) (car ~ DESCRIPTION 3 | Fed azo TX BUFFER EMPTY Rae er erste athe Transmt But: Register is empty and that he COMS2C50 can accept anew Seer cee Th ots tena hare hasbeen faded Yom he raamd Suter Regn © fhe ranma Sat Pogo | Tha bts cleared by ting re Tansmt Butler Roger ¢,assoring internal stare RESET, 8: Soarby TX Erle nthe Conra Register 4 Steer onernalNarnare RESET, ‘Th bts italy et when the vanoriter loi enabled by sting the TXenabl bi in the Cantol Register Data | Tani Seton a conascutve vite pefemed hie TXbur empty ro [27x UNoERRUN ERROR Faeae eeu cretor hat an Underun contin has occured. This st when. during a warsision Sanat Mss coprocessor unis tote Te Fang Reger afer he TX Sn Rgitr has aeady shied ts fast bit out | This bit is cleared by. ‘2. clearing TX Enable in the Control Register. «. asserting internal RESET ©. senting Reset Errors in tne Control Register. asserting External Hardware RESET. 3-7 | Those bits are fixed zeros. |The TX Slatus Register ie cleared following software or hardware reset. 85 ‘TABLE 8—COMS52C50 CONTROL REGISTER (BITS 0-7) The Control Registers an eightbtwrit ony register nats used by the microprocessor to control the COM52C50. Following External Reset allbits of the Control Register are cleared to "zero" except forthe Sofware Reset bit Internal Reset does not affect any of the Control Register bts. The bits of the Control Register are defined as follows: Br DESCRIPTION _ 0 ‘SOFTWARE RESET ‘This bitis used by the microprocessor to reset the COMS2C50 via a software command. When this bit is cleared Internal Reset is asserted and the COMS2C50 is reset. Ths bit should be set to “one” during normal operations. 1 ENABLE RECEIVE ‘This bitis used by the microprocessor to enable the Receive Logic in the COMS2C50 to function. When this bits ‘cleared, the RX BUFFER FULL bt in the Status Register will be disabled. This bit should be set to “one” during | normal eperatons. - 2 ENABLE TRANSMIT Daa transmission cannot take place via the COMS2C50 unless this bits set to logic “one”, When this bits reset (disabled), transmission willbe disabled only ater the previously writen data has been transmitted, (This simply disables loading of the TX Butter Register) 3 ENABLE RX DMA ‘This bit, when set, will enable the BX DMA handshake signal on the COMS2C50. When this bits cleared, the AX DMA signal on the COMS2C50 is kept low 4 | ENABLE TX DMA | This bit, when set, will enable the TX DMA handshake signal on the COMS2C50. When this bit is cleared, the TX DMA signal s Kept iow. 5 DISABLE BIPHASE ERRORS ‘This bit when se, will disable the detection of biohase errors in the receive block. This bit is cleared upon power | _up and biphase error detection is enabled é NOT USED—MUST BE ZERO 7 RESET ERRORS. This bit, when set, will clear the Receive Error Status bits inthe Interupt Status Register (Parity, Biphase, Overrun}. As a result of his, the FX Error bit inthe FX Status Register wil be cleared. Reset Errors also resets the ‘TX Underrun status bitin the TX Status Register. No latch is provided inthe Control Register for saving the state ofthis bit therefore there is no need for clearing t ‘THE COM52C50 ON CHIP CRYSTAL OSCILLATOR ‘The COMS2CS0 incorporates an on chip crystal oscillator. A146 MHZ parallel resonant crystal is connected to the XTAL1 and the XTAL2 pins of the COM52C50 along with a 4.0 MOhm resistor across the crystal and two 22pf, capacitors from each nade of the crystal to ground. (see figure 18, CONNECTION DIAGRAM FOR PARALLEL RESONANT CRYSTAL) ATTL clock can also be used to supply the clock signal o the COM52C50, Thisis done by supplying TTL level clock to the XTALI pin of the COMS2C50 along with a 390 ohm resistor from the XTAL1 pin to Vec. The XTAL2 pin should not be connected when an external clock is supplied. (see figure 18, RECOMMENDED EXTERNAL TTL CLOCK CONNECTION} DMA OPERATION The COMS2C50 features two independent DMA Request, signals, These signals are provided to allow the (COM52C50 to interface to one or two channels of a DMA, controller such as that of the 80188 and the 80186. Each of the RX DMA and TX DMA request signals can be individually enabled via software commands in the Control Register. DMA interface is most useful when moving blocks. of data following an activate read or an activate write command. 86 RX DMA. Following an active read command, the host microproces- ‘sor would initialize the RX DMA channel and enable AX DMA by writing a one in the Control Register bit 3. The COMS2C50 will automatically generate the RX DMA Request signal as soon as a received frame is moved from the Receiver Shift Register to the Receiver FIFO. At this time, the DMA channel wil intiato a Read Receive Butter cycle which in turn will be used as an automatic DMA ‘Acknowledgment. When a new frame arrives and is ready to be read by the DMA channel, the COM52C50 will assert the RX DMA Request signal and inform the DMA channel of the availabilty of the next word. The Receiver FIFO will be inuse during DMA operations. This gives the DMA channel, ‘a maximum of three frame times for DMA latency. On the average, however, the DMA channel must be able to keep up with the COMS2C50 byte rate. TXDMA When transmitting blocks of data, the host microprocessor ‘would initialize the TX DMA channel and enable TX DMA by writing a one in the Control Register bit 4. The COMS2C50 will automatically generate the TX DMA Fooquest signal when the TX Buffers emply. When the DMA channel periorms a write cycie to the COMS2C50 TX Buffer, ne TX DMA Request signal willbe inactive until the ‘TX Buifer becomes empty again. After wring the last data frame to the TX Butter, the host microprocessor can disable the TX DMA Request signal by writing to the Control Register ‘TABLE 9—COMS2C50 MODE REGISTER DESCRIPTION (BITS 0-7) BIT DESCRIPTION (0 | NORMALILOOPBACK MODE ‘This bit when set will put the COMS2CS0 in loopback mode. When in loopback mode, bt 1 ofthe Mode Register specifies Internal or External loopback modes. 0 NORMAL OPERATION 1 LOOPBACK MODE 1 EXTERNALINTERNAL LOOPBACK ‘This bit specifies External or Internal loopback Modes. When bit ofthe Mode Register specifies normal mode of ‘operation this bit is @ don't care. 0 EXTEANAL LOOPBACK 1 INTERNAL LOOPBACK 2 | EVENIODD AK PARITY This bit species Even or Od party forthe receive section ofthe COMES. 0 EVENAXPARITY 1 ODD AX PARITY 3 | EVENIODD Tx PARITY - “This bit specitios Even oF Océ party for the ransmit secon of the COMS2CSO. © EVENTX PARITY 1 ODD TK PARITY 4 | NORMALTEST MODE This bit when set puts the COMS2C50 in a VLSI test mode, This bits cleared upon Reset and should be cleared for normal operation (0 NORMAL OPERATION 1 TEST MODE 5 | TKENABLE 250ns/16us. ‘This bit controls the amount of ime the Transmit Enable Signal will remain active aftr the last TX bits shifted out ‘When set to.'zero” the TX Enable signal goes inactive atter 250ns folowing the last TX data bit. When set to “one”, the TX Enable signal goes inactive after 16us following the last TX data bit. This can be used to drive the Twinax Cable after a transmission in order to reduce line reflection etfect. © Tenable 250ns 1 Tenable 16s 6 | EOMAuto 111 ‘This bit determines if Automatic 111 address should be inserted on a transmitted message upon transmitter ‘nderrun, When this bit is a "zero" the microprocessor has to write to TX Butfer EOM to force a 111 address on the last frame of vansmitted data 0 EOMI11 1 Auto tt 7 | NORMALITEST MODE This bit when set puts the COMS2C5O in a VLSI test mode, This bits cleared upon Reset and should be cleared for normal operation. 0 NORMAL OPERATION 1 TESTMODE Following RESET, the mode register will be cleared to all "zero's” and the default Mode Setting willbe: BITO- 0 NORMAL OPERATION BiT1- 0 EXTERNAL LOOPBACK BT2- 0 EVEN AX PARITY BIT3- 0 EVEN TX PARITY BIT4- 0 NORMAL OPERATION BITS- 0 ‘TK ENABLE.250, siré- 0 OMI BIT7- 0 NORMAL OPERATION 87 ELECTRICAL CHARACTERISTICS MAXIMUM GUARANTEED RATINGS’ ‘TABLE 11-ELECTRICAL CHARACTERISTICS (T, = 0°C to +70°C, Vee Operating Temperature Range ......csccceceeseeessssesssesssseseeaseeeeeses peeves t0 70°C Storage Temperature Range : 55 to 180°C Lead Temperature (soldering, 10 seconds) DTs328°¢. Positive Voltage on any pin. .....- Vec+03V Negative Vaage on any pi, with Fespect to ground -03v Maximum Vee A TIE +70 “Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operations of the device at these or any other condition above those indicated in the operational sections of this specifications is not impliec NOTE: When powering this device from the laboratory or system power supplies, itis important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or iglitches” on their outputs when the AC power is switched on and off.n addition, voltage transients on the AC powerline may appear on the DC output If this possibity exists, t's suggested hata clamp crcuit be used, PARAMETER | SYMBOL [WIN | TYP" 6 cHanacTenisri¢s T TGWINPUTVOLIAGE | Vas J oe |v | excep tui | eck HIGH INPUT VOLTAGE Vows | 20 v Except TTL input | ‘Gok | LOW INPUT VOLTAGE Vee 10 v TTL Clock Input | HIGH INPUT VOLTAGE Vive vec-05V v TTL Clock input tow ourpurvouIaGe | Vis ae ay Tanase HigH OUTPUT WOLAGE | Voy | a ¥ 2 Bogue tow output vouase | vars so | ¥ | FotGoce utp HIHOUTPUTVOLIAGE | Vans 30 Y | Freee Oupat INPUT Leakace cunrent | | 10 Pn INPUT CAPROTANGE | Go ® POWER SUPPLY CURRENT | Is [ee AL coe Las ——paRaweren | svpot [win | Tye" [max | UNITS | COMMENTS | Re characteristics WATE CYCLE | Fia.s | Adtess Setp Tine ‘ 50 ns | | Fig.3 | Address Hold Time tb ° ns, | Fig 3 | WRPulse Wiath b 150 ns Fai | Data Soup Time u 75 4 Fag.3 | Data hold Time ‘ 10 te READ CYCLE | | Fg 4 | Address Seup Time 5 50 = Fag | Adctess Hold Time ee = Fay 4 | RO Pulse Wen i 3 pico ts roa | To ® ole ee ros | te fe 3 oq a | Fag | READWAITE INTERVAL | ts 100 os i j | INTERRUPT ACKNOWLEDGE TIMING Fg.6 | Read in. Staus Reg to | int inactive te | 300 1s | oa acksomence | | Thang / Fq.7 | Read Fx aufero PXDMA inactive te 200 18 Fae | write Tx Buterto | TXDMA naive Lie 200 = 88 FIG.NO.| SYMBOL PARAMETER [SYMBOL | MIN. | TYP" | MAX | UNITS | COMMENTS TTL CLOCK INPUT TIMING. I Fig.9 | Input Clock fall time to 10 ns Fig.9 | Input Clock rise time be 10) ns Fig 9 | Input Clock high time to 20 ne Veco Fig. 9 | Input Clock ow time te 20 ns @osv Fig 9 | Input Clock period os 625 8 @isv fig 10] Crock Outfaitine tes 10 | ns.) @S0pF max Fig 10| Clock Outrise time te | 50 | os | @809F max Fig 10/ Clock Out nigh time te 58 ns | @50pF max Fig. 10| Clock Out low time: ten 55 | ns, @SOpF max TX DATA TMING | \ Fig,11| Wt Butler TRENABLE te 1500 | 8 Fig.11) TRENABLE active to | TX DELAY & 250 ns j Fig. 11] DTXto TRENABTE inactive | te 250 a8 Fig.11| TX.DTX half et cel we 500 ns Fig 11) TX.OTX ful bicell | we 1000 ns Fig.11| TX.OTK rise tie 10 18 1X, DIX alltime | 10 ns | RX DATA TIMING | AX half bit cel pu'se wien | 500 | ns. | uiter Tolerance +20% er ieue guaran [cco ae RESET TIMING | | fig. 12) Internal Reset pulse width| to is 9. 13| External Reset pulse with | ts 1s Input Clock Frequoney 16 | Miz. “ALL TYPICAL VALUES ARE AT 25°C AND Ve 2 | ia D-ouT Fig.4—PROCESSOR READ COMS52C50 CYCLE [ [ PDN, | | STATUS REG. \ | [ Fig, 6—INTERRUPT ACKNOWLEDGE TIMING 20 AD_pK BUFFER | { Vi ' 1 WAX BUFFER d IL —27V CLKIN ———— 06v 27v clk our Fig. 10-8 MHZ CLOCK OUT TIMING a wR internal RESET Fig. 12—INTERNAL RESET TIMING external RESET Fig. 13—EXTERNAL RESET TIMING [sr sreencan—_r}a—FraneSyenanaaton ef Bl nfe-Di-ote-DI—o} aa ee ee eee ee eee ™ Le tt PLOLrTI4 Fig. 14—COMS2C50 TRANSMIT START TIMING 2 ROUT [e-05 a 05 nab la ef ssage pe Pee Bis 0099 LYLE ir. ggg Ve ge gL D gd eed eed ee) TENABLE HDS oD POT eat oe et oe oe nto STS. Fig. 15—COM52C50 TRANSMIT END TIMING [ent tee ng ele ela Fame Synctrangeton eet oe 00H | l ttt JET + Fig. 16—COM52C50 RECEIVE START TIMING Fe 05 -efe Oba 07 eb epee Poo eel i Seo a TT — POL CONRAN Der | eon Fig. 17—COMS2C50 RECEIVE END TIMING ale al 20F ure | 20 Monn = 21mes Crystal Laas Capactance Fig, 18—-CONNECTION DIAGRAM FOR PARALLEL RESONANT CRYSTAL “y 74804 390 nm xia — "No Gonnecton Fig. 19—RECOMMENDED EXTERNAL TTL CLOCK ‘CONNECTION 93 STANDARD MICROSYSTEMS 3g Ei 3 _ i a, 3 388 5 , ; ® 8 3 538 : Rs g 238 Baye : 5 BRE bbl He 36 i ABs T 245 i 28 B: ‘3 : 9 , 5 & F 3 : 2 z 8 2 e 8 3 3 ae eo 8 aan = “4 25 / 8 28 Ng g 5 3 8 és 3 # g 3 2 ts 3 a8 J eN\ zs a 38 ; Sa 5 3 z @ z i e 3 i ro> g Be i : 3 8 = e 2 Dg ; g 3 g : a z oD Z g ; 3 3 a o ——— er cally cechosardis She maton hes bee oy rcceaony seins acetcn Fureuryeh ea CSitottesay niente nas ots reser oo SC tobe ence lable Hoye oregon aust rend sup he bes owe poe io aero p we design a ey tho purse ihowae to mpone

    Você também pode gostar