LDICA Digital Notes

LINEAR AND DIGITAL IC APPLICATION
LINEAR AND DIGITAL IC APPLICATIONS
Page 1
B.Tech. III Year I Sem. LTP C

Course Code: EC502PC 400 4
Course Objectives:
The main objectives of the course are:
1. To introduce the basic building blocks of linear integrated circuits.
2. To teach the linear and non - linear applications of operational amplifiers.
3. To introduce the theory and applications of analog multipliers and PLL.
4. To teach the theory of ADC and DAC.
5. To introduce the concepts of waveform generation and introduce some special function ICs.
6. To understand and implement the working of basic digital circuits
Course Outcomes:
On completion of this course, the students will have
1. A thorough understanding of operational amplifiers with linear integrated circuits.
2. Understanding of the different families of digital integrated circuits and their characteristics.
3. Also students will be able to design circuits using operational amplifiers for various applications.
UNIT - I
Operational Amplifier: Ideal and Practical Op-Amp, Op-Amp Characteristics, DC and AC
Characteristics, Features of 741 Op-Amp, Modes of Operation - Inverting, Non-Inverting,
Differential, Instrumentation Amplifier, AC Amplifier, Differentiators and Integrators,
Comparators, Schmitt Trigger, Introduction to Voltage Regulators, Features of 723 Regulator,
Three Terminal Voltage Regulators.
UNIT - II
Op-Amp, IC-555 & IC 565 Applications: Introduction to Active Filters, Characteristics of
Band pass, Band reject and All Pass Filters, Analysis of 1st order LPF & HPF Butterworth
Filters, Waveform Generators – Triangular, Saw tooth, Square Wave, IC555 Timer -
Functional Diagram, Monostable, and Astable Operations, Applications, IC565 PLL - Block
Schematic, Description of Individual Blocks, Applications.
UNIT - III
Data Converters: Introduction, Basic DAC techniques, Different types of DACs-Weighted
resistor DAC, R-2R ladder DAC, Inverted R-2R DAC, Different Types of ADCs - Parallel
Comparator Type ADC, Counter Type ADC, Successive Approximation ADC and Dual
Slope ADC, DAC and ADC Specifications.
Page 2
UNIT - IV
Digital Integrated Circuits: Classification of Integrated Circuits, Comparison of Various Logic
Families Combinational Logic ICs – Specifications and Applications of TTL-74XX & Code
Converters, Decoders, Demultiplexers, LED & LCD Decoders with Drivers, Encoders, Priority
Encoders, Multiplexers, Demultiplexers, Priority Generators/Checkers, Parallel Binary
Adder/Subtractor, Magnitude Comparators.
UNIT - V
Sequential Logic IC’s and Memories: Familiarity with commonly available 74XX & CMOS
40XX Series ICs – All Types of Flip-flops, Synchronous Counters, Decade Counters, Shift Registers.
Memories - ROM Architecture, Types of ROMS & Applications, RAM Architecture, Static &
Dynamic RAMs.
TEXT BOOKS:
1. Op-Amps & Linear ICs – Ramakanth A. Gayakwad, PHI, 2003.

2. Digital Fundamentals – Floyd and Jain, Pearson Education, 8th Edition, 2005.
REFERENCE BOOKS:
1. Linear Integrated Circuits –D. Roy Chowdhury, New Age International

(p) Ltd, 2nd Ed., 2003.
2. Op Amps and Linear Integrated Circuits-Concepts and Applications James
M. Fiore, Cengage Learning/ Jaico, 2009.
3. Operational Amplifiers with Linear Integrated Circuits by K. Lal Kishore
– Pearson, 2009.
4. Linear Integrated Circuits and Applications – Salivahanan, MC GRAW HILL EDUCATION.
5. Modern Digital Electronics – RP Jain – 4/e – MC GRAW HILL EDUCATION, 2010.
COURSE OBJECTIVES
The main objectives of the course are:

• To introduce the basic building blocks of linear integrated circuits.
• To teach the linear and non - linear applications of operational amplifiers.
• To introduce the theory and applications of analog multipliers and PLL.
• To teach the theory of ADC and DAC.
• To introduce the concepts of waveform generation and introduce some special function ICs.
• To understand and implement the working of basic digital circuits
COURSE OUTCOMES
On completion of this course, the students will have:

• A thorough understanding of operational amplifiers with linear integrated circuits.
• Understanding of the different families of digital integrated circuits and their characteristics.
• Also students will be able to design circuits using operational amplifiers for various
applications.
TABLE OF CONTENTS
S.NO. TOPIC NAME PAGE

NO.
UNIT – I Operational Amplifier 1-63
1.1 Introduction 10
1.2 Operational Amplifier 11
1.3 Ideal Op-Amp 13
1.4 Practical Op-Amp 14
1.5 Op-Amp Internal Circuit 15
1.6 Modes Of Operation Of Op-Amp 16
1.6.1 Open loop OPAMP mode 16
1.6.2 Closed loop op-amp mode 17
1.6.3 Inverting Amplifer 17
1.6.4 Practical Inverting Amplifier 18
1.6.5 Non-Inverting Amplifier 21
1.6.6 Practical non-inverting amplifier 21
1.6.7 Voltage follower 22
1.6.8 Differential amplifier 23
1.6.9 Common mode rejection ration: (CMRR) 24
1.7 Op-Amp Characteristics 25
1.8 Dc Characteristics Of An Op-Amp 25
1.8.1 Input bias current (IB) 25
1.8.2 Input offset current (IOS) 27
1.8.3 Input offset voltage (Vios) 29
1.8.4 Total output offset voltage (VOT) 30
1.8.5 Thermal Drift 31
1.9 Ac Characteristics Of An Op-Amp 31
32
1.9.1 Frequency Response
34
1.9.2 Stability of an OP-Amp
1.9.3 Slew Rate 35
1.10 Features Of 741 Op-Amp 36
1.11 Summing Amplifier 37
1.11.1 Inverting Summing Amplifier 37
1.11.2.Non- Inverting Summing Amplifier 37
1.12 Instrumentation Amplifier 38
1.13 Ac Amplifier 41
1.13.1 Inverting Ac Amplifier 41
1.13.2 Non-Inverting Ac Amplifier 42
1.13.3 Ac Voltage Follower 42
1.14 Differentiator 43
1.14.1 Practical Differentiator 44
1.15 Integrator 47
1.15.1 Practical Integrator 48
1.16 Comparators 52
1.16.1 Non-inverting comparator 52
1.16.2 Inverting comparator 53
1.16.3 Applications of comparator 54
1.17 Schmitt Trigger 55
1.18 Introduction To Voltage Regulators 57
1.19 Three Terminal Ic Voltage Regulators 58
1.19.1 Boosting IC Regulator output current: (Boosting a Three 59
Terminal Voltage Regulator)
1.20 Features Of 723 –General Purpose Regulator 60
1.20.1 Functional Block Diagram Of 723 Regulator 62
UNIT II OP-AMP, IC-555 & IC 565 APPLICATIONS 66-128
2.1 Introduction to Active Filters 67
2.2 Characteristics of filters 69
2.2.1 Band Pass Filter 69
2.2.1.1 Narrow Band Pass Filter 70
2.2.1.2 Wide Band Pass filter 73
2.2.2 Band reject filter 75
2.2.3 All pass filter 80
2.3 Analysis of 1st order LPF Filters 82
2.4 Analysis of 1st order HPF Butterworth Filters 83
2.5 Waveform Generators 84
2.5.1 Sine wave generator 85
2.5.2 Square wave generator 91
2.5.3 Triangular wave generator 96
2.5.4 Saw tooth wave generator 98
2.6 IC555 Timer 99
2.6.1 Functional diagram of IC 555 timer 100
2.6.2 Monostable operation 101
2.6.2.1Applications 103
2.6.3 Astable operation 108
2.6.3.1Applications 110
2.7 IC565PLL 113
2.7.1 Block Schematic 113
2.7.2 Description of Individual Blocks 116
2.7.3 Application 124
UNIT III DATA CONVERTERS 129-152
3.1 Introduction 130
3.2 Basic DAC techniques 130
3.3 Different types of DACs 131
3.3.1 Weighted resistor DAC 131
3.3.2 R-2R ladder DAC 133
3.3.3 Inverted R-2R ladder DAC 135
3.4 Analog to digital converters 137
3.5 Different Types of ADCs 135
3.5.1 Parallel Comparator Type ADC 135
3.5.2 Counter Type ADC 141
3.5.3 Successive Approximation ADC 142
3.5.4 Dual Slope ADC 145
3.6 DAC and ADC Specifications 148
UNIT IV DIGITAL INTEGRATED CIRCUITS 153-201
4.1 Introduction 154
4.2 Classification of integrated circuits 155
4.3 Comparison of various logic families 164
4.4 Combinational logic ICs 166
4.4.1 CMOS circuits/CMOS gates 166
4.4.2 CMOS inverter gates 166
4.4.3 Non inverting gates 168
4.4.4 CMOS AND-OR Invert gate 169
4.4.5 CMOS OR-AND-Invert gate 170
4.4.6 Open drain CMOS gate 171
4.4.7 Tristate CMOS gate 171
4.4.8 CMOS transmission gate 172
4.4.9 Interfacing 173
4.5 Specifications and applications of TTL 175
4.5.1 Code converter 175
4.5.2 Decoder 179
4.5.3 LED and LCD Decoders with Drivers 184
4.5.4 Encoders 187
4.5.4.1 Priority Encoders 187
4.5.5 Multiplexers 190
4.5.6 Demultiplexers 195
4.5.7 Parity Generators/Checkers 195
4.5.8 Parallel Binary Adder/Subtractor 196
4.5.9 Magnitude Comparators 198
UNIT V SEQUENTIAL LOGIC IC’S AND MEMORIES 202-237
5. Familiarity with commonly available 74XX & CMOS 40XX Series 203
ICs
5.1 All Types of Flip-flops 203
5.1.1 74LS279A-Set-Reset Latch 204
5.1.2 74LS75-D latch 205
5.1.3 74AHC74 – Dual D flip-flop 205
5.1.4 74HC112 Dual J-K flip-flop 206
5.2 Asynchronous Counters 206
5.2.1 2- Bit Asynchronous Binary Counter 207
5.2.2 3- Bit Asynchronous Binary Counter 208
5.2.3 4-bit Asynchronous binary counter (using –ve edge triggered JK 209
flipflops)
5.2.4 Asynchronous Decade Counter (MOD 10 Counter / BCD Counter) 212
5.2.5 IC 74x90 – Asynchronous Decade counter 213
5.2.6 74LS93 4-bit Asynchronous Binary Counter 213
5.3 Synchronous Counters 214
5.3.1 2-bit Synchronous binary counter 214
5.3.4 74HC163 4-bit Synchronous binary counter 219
5.3.5 74X169 – Up/Down Counter 220
5.4 Decade Counters 220
5.4.1 4-bit Synchronous decade counter 221
5.4.2 74HC190 up/down decade counter 221
5.5 Shift Registers 222
5.6 Shift Register IC’s 222
5.6.1 74X194 4 –bit Universal Shift Register 224
5.6.2 74X299 8 –bit Universal Shift Register 225
5.6.3 74HC195 4-bit Parallel- Access Shift Register 226
5.7 Memories 229
5.7.1 ROM Architecture 232
5.7.2 Types of ROMS 233
5.7.3 Applications 233
5.7.4 RAM Architecture 223
5.7.4.1 Static RAMs 234
5.7.4.2 Dynamic RAMs 234
Appendix
I Tutorial sheets 236
II Assignment questions 240
III Unit wise important questions 246
IV Objective questions 253
V Previous University examination question paper 257
VI References 266
UNIT I
OPERATIONAL AMPLIFIER
1.1 INTRODUCTION
Definition of INTEGRATED CIRCUIT

• An Integrated Circuit (IC) is a miniature, low cost electronic circuit consisting of active and
Passive components that are irreparably joined together on a single crystal chip of silicon.
• The active components are transistors and diodes and passive components are resistors and
capacitors.
ADVANTAGES OF INTEGRATED CIRCUITS (over circuits made by interconnecting

discrete components)
1. Miniaturization and hence increased equipment density.

2. Cost reduction due to batch processing.
3. Increased system reliability due to the elimination of soldered joints.
4. Improved functional performance.
5. Matched devices.
6. Increased operating speeds.
7. Reduction in power consumption.
CLASSIFICATION OF IC’S:
• Integrated circuits offer a wide range of applications and could be broadly classified as:
1. Digital IC’s
2. Linear IC’s
• Based upon the above requirements, two distinctly different IC technologies are developed.
1. Monolithic technology
2. Hybrid technology
• In Monolithic Integrated Circuits, all circuit components, both active and passive
elements and their interconnections are manufactured into (or) on top of a single chip of
silicon.
• In Hybrid Integrated Circuits, separate components parts are attached to a ceramic
substrate and interconnected by means of either metallization pattern (or) wire bonds.
1.2 OPERATIONAL AMPLIFIER: (OP-Amp)
• Linear IC’s are used in a number of electronic applications such as audio and radio
communication, medical electronics, instrumentation control, etc.
• The most important and most widely used linear IC is an op-amp.
• The operational amplifier is a versatile device that can be used to amplify dc
as well as ac input signals.
• The op-amp was originally designed for performing mathematical functions
such as addition, subtraction, multiplication, and integration. Thus the name
operational amplifier stems from its original use for these mathematical
operations and is abbreviated to op-amp.
• With the addition of suitable external feedback components, the modern day
op-amp can be used for a variety of applications, such as ac and dc signal
amplification, active filters, oscillators, comparators, regulators, and others.
• The most widely used op-amp is IC741.
OP-AMP CIRCUIT SYMBOL:

• The op-amp circuit symbol is a triangle that points in the direction of signal
flow.
• It has ’2’ input terminals and ‘1’ output terminal and ‘2’ power supply
terminals.
• The terminal with a (-) sign is called inverting input terminal and the
terminal with (+) sign is called the non-inverting input terminal.
Fig: Op-Amp Circuit Symbol
IC PACKAGE TYPES
The op-amp ICs are available in various packages. The IC packages are classified as,
1. Metal Can (TO) package.
2. Dual In Line package(DIP)
3. Flat Package
Fig. Various packages of µA741 op-amp
PIN DIAGRAM OF IC 741

POWER SUPPLY CONNECTIONS
• The op-amp uses ‘2’ power supply terminals V+ & V-
• The power supply voltage range is ±5V to ±22V.
• The common point of the two sources must be grounded, otherwise twice the supply
voltage will get applied and it may damage the op-amp.
1.3 IDEAL OP-AMP
Fig (a) Ideal op-amp
An ideal op-amp would exhibit the following electrical characteristics:

Characteristics of Ideal op-amp:
1. Open loop voltage gain AoL = ∞, for ideal op-amp the Vd=0 and V1=V2.
2. Input impedance Ri = ∞, so the current drawn from the input terminals
is ‘0’ i.e i1=i2=0. Because of Infinite input resistance so that almost any
signal source can drive it and there is no loading on the preceding
driver stage.
3. Output impedance Ro = 0, so that output can drive an infinite number of other
devices.
4. Bandwidth = ∞, so that any frequency signal from 0 to ∞Hz can be
amplified without any distortion.
5. Zero offset voltage i.e Vo=0 when V1=V2=0
6. Common mode rejection ratio (CMRR)= ∞, so that the output common-mode
noise voltage is zero.
7. Slew rate = ∞, so that output voltage changes occur simultaneously with
input voltage changes.
8. No effect of temperature.
Ideal Voltage Transfer Curve: (or) Transfer characteristics of an ideal op-amp :
Fig. Ideal voltage transfer curve
• The graphic representation of the output equation is shown in fig. in which

the output voltage Vo is plotted against differential input voltage Vd, keeping
gain Ad constant.
• The output voltage cannot exceed the positive and negative saturation
voltages. These saturation voltages are specified for given values of supply
voltages. This means that the output voltage is directly proportional to the
input difference voltage only until it reaches the saturation voltages and
thereafter the output voltage remains constant.
• Thus curve is called an ideal voltage transfer curve, ideal because output
offset voltage is assumed to be zero. If the curve is drawn to scale, the
curve would be almost vertical because of very large values of Ad.
1.4 EQUIVALENT CIRCUIT OF AN OPAMP (PRACTICAL OP-AMP):
• In practical op-amp, AoL ≠ ∞, Ri ≠ ∞and Ro ≠ 0.
• Basically the op-amp is a voltage controlled voltage source.
• Hence the output side is represented by a thevenin’s equivalent model.

AoL Vd is an equivalent Thevenin’s voltage source and
RO is the Thevenin’s equivalent resistance.
Fig. (b) Equivalent circuit of OP-AMP

• From figure, the output voltage is
VO = AoL(V1-V2) = AoLVd
• The output equation shows that op-amp does not amplifies V1 & V2 themselves but it
amplifies difference of the two inputs V1 & V2.
1.5 OP-AMP INTERNAL CIRCUIT
• The internal block diagram of an opamp is shown in the fig.

• The input stage is the dual input balanced output differential amplifier.
This stage generally provides most of the voltage gain of the amplifier and
also establishes the input resistance of the op-amp.
• The intermediate stage is usually another differential amplifier, which is
driven by the output of the first stage. On most amplifiers, the intermediate
stage is dual input, unbalanced output.
• Because of direct coupling, the dc voltage at the output of the intermediate
stage is well above ground potential. Therefore, the level translator
(shifting) circuit is used after the intermediate stage downwards to zero
volts with respect to ground.
• The output stage is usually a push pull complementary symmetry
amplifier output stage. The output stage increases the voltage swing and
raises the ground supplying capabilities of the op-amp. A well designed
output stage also provides low output resistance.
Fig. Internal circuit of OP-AMP

1.6 MODES OF OPERATION OF OP-AMP

There are 2 modes in which an op-amp operates:
1. Open loop mode
2. Closed loop mode
1.6.1 OPEN LOOP OPAMP MODE

In the case of amplifiers the term open loop indicates that no connection exists between input
and output terminals of any type. That is, the output signal is not fedback in any form as part of the
input signal. In open loop configuration, The OPAMP functions as a high gain amplifier. There are
three open loop OPAMP configurations.
1. The Differential Amplifier:
Fig. below shows the open loop differential amplifier in which input signals vin1 and vin2 are applied
to the positive and negative input terminals.
• Since the OPAMP amplifies the difference the between the two input signals, this configuration is
called the differential amplifier. The OPAMP amplifies both ac and dc input signals. The source
resistance Rin1 and Rin2 are normally negligible compared to the input resistance Ri. Therefore
voltage drop across these resistances can be assumed to be zero.
Therefore v1 = vin1 and v2 = vin2.
vo = Ad (vin1- vin2 ) where, Ad is the open loop gain.
2. The Inverting Amplifier:
If the input is applied to only inverting terminal and non-inverting terminal is grounded then
it is called inverting amplifier. This configuration is shown in figure below
v1= 0, v2 = vin.
vo = -Ad vin
The negative sign indicates that the output voltage is out of phase with respect to input 180 °
or is of opposite polarity. Thus the input signal is amplified and inverted also.
3 .The non-inverting amplifier:
In this configuration, the input voltage is applied to non-inverting terminals and inverting
terminal is ground as shown in fig below
V1=+Vin V2=0
V0=+Ad Vin
This means that the input voltage is amplified by Ad and there is no phase reversal at the
output.
Note: Reason why open loop op-amp is not used in linear applications:
• In all there configurations any input signal slightly greater than zero drive the output to saturation
level. This is because of very high gain. Thus when operated in open-loop, the output of the
OPAMP is either negative or positive saturation or switches between positive and negative
saturation levels. Therefore open loop op-amp is not used in linear applications.
1.6.2 CLOSED LOOP OP-AMP MODE

• As the open loop DC gain of an operational amplifier is extremely high we can therefore afford to
lose some of this high gain by connecting a suitable resistor across the amplifier from the output
terminal back to the inverting input terminal to both reduce and control the overall gain of the
amplifier.
• This then produces and effect known commonly as Negative Feedback, and thus produces a very
stable Operational Amplifier based system.
• As we are not using the positive non-inverting input this is connected to a common ground or
zero voltage terminal , but the effect of this closed loop feedback circuit results in the voltage
potential at the inverting input being equal to that at the non-inverting input producing a Virtual
ground summing point because it will be at the same potential as the grounded reference input.
In other words, the op-amp becomes a "differential amplifier".
There are three closed loop OPAMP configurations.
1.6.3 INVERTING AMPLIFER
Fig. Inverting amplifier

• The output voltage V0 is fedback to the inverting input terminal through the resistors Rf-R1
network, where Rf is feedback resistor.
Analysis:
• Assume ideal op-amp. As Vd=0, node ‘a’ is at ground potential and the current i1 through R1 is
• Also op-amp draws no current, all the current flowing through R1 must flow through Rf. The
output voltage,
• Hence the gain of the inverting amplifier (also referred as closed loop gain) is,
Voltage gain < Unity

• Alternatively,
The nodal equation at node ‘a’ is
Where Va is the voltage at node ‘a’

• Since node ‘a’ is at virtual ground Va=0, we get
• The negative sign indicates a phase shift of 1800 between vi and v0.
• If the resistances R1 and Rf are replaced by impedances Z1 and Zf respwctively then the voltage
gain is
𝒁𝒇
AcL = −
𝒁𝟏
1.6.4 PRACTICAL INVERTING AMPLIFIER

• For practical op-amp the expression for the closed loop voltage gain should be calculated using
the low frequency model of practical op-amp.
• The equivalent circuit of a practical inverting amplifier is as shown in fig(a)
fig(a) Equivalent circuit of a practical op-amp inverting amplifier

• This circuit can be simplified by replacing the signal source Vi and resistors R1 and Ri by
Thevenin’s equivalent as shown in fig (b).
Fig (b) Simplified circuit by using Thevenin’s equivalent.

We assume , the input impedance Ri is much greater than R1,
From output loop from fig(b)
…..(1)
..(2)
Putting the value of ‘vd’ from eq(1) to eq(2), we get
….(3)
Also the KVL loop gives,
….(4)
𝐯𝟎
Putting the value of ‘I’ from eq(3) to eq(4) and solving for closed loop gain AcL= gives,
𝐯𝐢
…..(5)
From eq(5), if AoL >> 1 & AoLR1 >> R0+Rf & neglecting R0, we get
Input Resistance Rif (with feedback)
From fig(b),
Writing loop equation and solving for Rif,
We obtain,
Output Resistance Rof (with feedback)
• Output impedance Rof (without any load resistance RL)is calculated from the open circuit output
voltage Voc and short circuit output current isc.
• Now consider the circuit as shown in fig(c).
Fig (c) Equivalent circuit for computing Rof.

Under short circuit conditions at output,
…….(7)
……(8)
Since,
&
Solving isc = iA + iB , we obtain
……(9)
Since &
…..(10)
Putting the value of AcL from eq(5) into eq(10), we obtain
……..(11)
Equation (11) can be alternatively written as,
…..(12)
It seems that numerator consists of Ro║(R1+Rf) and is therefore smaller than Ro.
• The output resistance Rof(with feedback) is therefore always less than Ro and for
1.6.5 NON-INVERTING AMPLIFIER
Fig. Non-inverting amplifier
• As the differential voltage vd at the input terminal of op-amp is zero, the voltage at node ‘a’ in fig
is vi, same as the input voltage applied to non-inverting input terminal.
• Now Rf and R1 forms a potential divider. Hence
As no current flows into the op-amp
• Thus, for non-inverting amplifier the voltage gain,
voltage gain > unity
1.6.6 PRACTICAL NON-INVERTING AMPLIFIER

• The analysis of the practical non-inverting amplifier can be performed by using the equivalent
circuit as shown in fig.
Fig . Equivalent circuit of non-inverting amplifier using low frequency model

• Writing KCL at the input node,
….(1)
Similarly at the output node KCL gives,
…..(2)
Now solving eq’s(1) & (2) for v0/vi, we get
…….(3)
Where all admittances have been taken for simplicity
If eq(3) reduces to
1.6.7 VOLTAGE FOLLOWER

• In the non-inverting amplifier, if Rf = 0 and R1 = ∞, we get the modified circuit as shown in fig.
of voltage follower.
fig. voltage follower

• From output of the non-inverting amplifier,
𝑅𝑓 0
v0 = (1+𝑅1) vi = (1+∞ ) vi
therefore, v0 = vi i.e voltage gain AcL= unity

• The unity gain circuit has high input impedance (MΩ order) and output impedance is zero.
• The output voltage is equal to the input voltage, both in magnitude and phase.
• The output voltage follows the input voltage exactly. Hence, the circuit is called a voltage
follower.
• Voltage follower can be used as a buffer for impedance matching.
1.6.8 DIFFERENTIAL AMPLIFIER
• From ideal characteristics of op-amp, the differential voltage at the input terminals of the op-amp
is zero, nodes ‘a’ and ‘b’ are at the same potential, designated as ‘v3’
• The nodal equation at node ‘a’ is,
…..(1)
The nodal equation at node ‘b’ is
……(2)
Subtract (2) from (1), we get
Therefore,
• Such a circuit is very useful in detecting very small differences in signals, since the gain R2/R1
can be chosen to be very large.
• Example, if R=100R1, then a small difference v1-v2 is amplified 100 times.
Difference mode and common mode gains:

• In ideal op-amp, if v1=v2 then vo=0, so that the difference mode signal ‘vd’ is defined as,
vd = v1-v2 ....(1)
• In practical op-amp, even if v1=v2 then vo ≠0, this is because the output voltage depends not only
upon the difference signal ‘vd’ at the input, but is also affected by the average voltage of the input
signals, called as the common-mode signal VcM defined as,
….(2)
• For the differential amplifier, because of the mismatch, the gain at the output with respect to the
positive terminal is slightly different in magnitude to that of the negative terminal.
• So, even with the same voltage applied to both inputs, the output is not zero. The output therefore
must be expressed as,
vo = A1v1+A2v2…..(3)
solving eqs(1) & (2),
Substitute v1 & v2 in eq(3), we get
Where &
• ADM is voltage gain for the difference signal.

• ACM is voltage gain for the common-mode signal.
1.6.9 COMMON MODE REJECTION RATION: (CMRR)

• The CMRR is defined as the ratio of differential voltage gain ADM to common-mode voltage gain
ADM.
• CMRR is used to define the ability of a differential amplifier to reject the common mode input
signal, and gives the figure of merit ‘ρ’ for the differential amplifier.
• CMRR is generally expressed in terms of decibels(dB)
• For µA741 op-amp has a minimum CMRR of 70 dB.
• For µA725A op-amp has a minimum CMRR of 120 dB.
• For an ideal op-amp, ACM = 0 and hence CMRR=∞
• For practical op-amp, since ADM >> ADM, CMRR is high i.e finite.
𝐯𝐂𝐌
vo= ADM vd [1 + 𝝆𝒗𝒅 ] where CMRR is denoted by ‘ρ’
• As CMRR (or) ρ → ∞ , the output voltage becomes,
vo= ADM vd
Here, the common mode voltage is nullified to a great extent.
• So, higher the value of CMRR, better is the performance of op-amp.
1.7 OP AMP CHARACTERISTICS

• An ideal op-amp respond equally to both AC & DC input voltages.
• But a practical op-amp does not behave this way.
• A practical op-amp has some dc voltage at the output even with both the inputs grounded i.e when
v1=v2=0v
i.e v0 ≠ 0
• Under AC conditions, practical op-amp is frequency dependent & temperature independent and
ideal op-amp is frequency independent & temperature dependent.
1.8 DC CHARACTERISTICS OF AN OP-AMP

• Ideal op-amp does not draw the current from the input terminals.
• In practical op-amp, current is taken from source into the op-amp inputs. Also the two inputs
respond
differently to current and voltage due to mismatch in transistors.
• The non-ideal dc characteristics that add error components to the dc output voltage are:
➢ Input bias current
➢ Input offset current
➢ Input offset voltage
➢ Thermal drift
1.8.1 Input bias current (IB)

• The op-amp’s input is a differential amplifier, which may be made of BJT or FET. The input
transistors
must be biased into their active region by supplying base currents.
• In ideal op-amp, no current is drawn from input terminals.
• In practical op-amp, input terminals draws small value of dc current to bias the transistors.
Fig. (a) Input bias currents (b) Inverting amplifier with bias currents
• The base currents entering into the inverting terminal is IB- & non-inverting terminal is IB+
• Even though both the transistors are identical, IB- & IB+ are not exactly equal due to internal
imbalances
between the two inputs.
• The input bias current IB is defined as the average value of the base currents entering into the
terminals
of an op-amp.
• For 741, a bipolar op-amp, the bias current is 500nA or less

FET op-amp the bias current is 50pA
• Consider the basic inverting amplifier of fig.(b)
• If Vi=0v the output voltage V0 should be 0V.
• Instead we get that output voltage is offset by,
V0 = (IB-)Rf
• For 741 op-amp with 1MΩ feedback resistor V0= 500nA*1MΩ = 500mV
• Hence due to bias currents the output is 500mV with zero input
V0 = 500mv with Vin = 0v
• Inorder to avoid this a compensation resistor Rcomp has been added between the non-inverting
input terminal and ground. It is as shown in fig (c).
Fig (C) Bias current compensation in an Fig (d) Bias current compensation in an
inverting amplifier non-inverting amplifier
• Current IB+ flowing through the comnpensating resistor Rcomp develops a voltage V1 across it.
Then by KVL, we get,
-V1+0+V2-V0 = 0
V0 = V2-V1 ……(1)
• By selecting the proper value of Rcomp, V2 can be cancelled with V1 and the output V0 will be
zero.
The value of Rcomp is derived as
𝐕𝟏
V1 = IB+ Rcomp or IB + = …..(2)
𝑹𝒄𝒐𝒎𝒑
• The node ‘a’ is at voltage (-V1) because the non-inverting input terminal is –V1. So with Vi=0,
we get,
𝑉1 𝑉2
I1 = 𝑅1 and also I2 = 𝑅𝑓
• For compensation V0 should be zero for vi=0 i.e from equation (1)
𝑉1
So that, I2 = 𝑅𝑓
KCL at node ‘a’ gives
𝑽𝟏 𝑽𝟏 𝑽𝟏(𝑹𝟏+𝑹𝒇)
IB- = I1+I2 = + 𝑹𝒇 = ………(3)
𝑹𝟏 𝑹𝟏𝑹𝒇
Assuming IB- = IB+ and using equations (2) & (3) we get,
𝑉1(𝑅1+𝑅𝑓) V1
=
𝑅1𝑅𝑓 𝑅𝑐𝑜𝑚𝑝
𝑹𝟏𝑹𝒇
Rcomp = = R1║Rf
𝑹𝟏+𝑹𝒇
• To compensate for bias currents the compensating resistor Rcomp should be equal to the parallel
combination
of resistors connected to the inverting input terminal.
• The effect of input bias current in a non-inverting amplifier can also be compensated by placing a
compensating reisistor, Rcomp in series with the input signal Vi as shown in fig(d).
• The value of the Rcomp is again equal to
Rcomp= R1║Rf
• As the circuits for inverting amplifier and non-inverting amplifier shown in fig (c) & (d) becomes
same
with input signal Vi made equal to zero.
1.8.2 Input offset current (IOS)

• Input bias current compensation will work only when both IB- & IB+ are equal. But due to slight
mismatch
in transistors there will be some small difference between the IB- & IB+. it is called as offset
current Ios.
• For BJT op-amp offset current Ios=200mA

• For FET op-amp offset current Ios=10pA
• Even with bias current compensation offset current will produce an output voltage when the input
voltage Vi= 0
From fig(c) bias current compensation in an inverting amplifier
𝑉1 IB+ Rcomp
V1 = IB+ Rcomp & I1 = 𝑅1 = 𝑅1
KCL at node ‘a’ gives,
𝑅1𝑅𝑓
Substituting Rcomp = = R1║Rf in above equation weget,
𝑅1+𝑅𝑓
• So, even with bias current compensation and with the feedback resistor of 1MΩ, a 741 BJT op-
amp has
an output offset voltage V0=200mV.
V0= 1MΩ * 200nA = 200mV with a zero input voltage (Vin=0V)
• If we assume Rf as a small then the effect of offset current can be minimized.
• But to obtain high input impedance R1 must be kept large.
• With R1 large, the feedback resistor Rf must also be high so as to obtain reasonable gain.
• The “T- feedback network” is a good solution.
fig. inverting amplifier with T- feedback network

• This will allow large feedback resistance while keeping the resistance to ground (seen by
inverting input)
low as shown in the dotted network.
• The T-network provides a feddback signal as if the network were a single feedback resistor.
• By T to π conversion,
• To design a T-network, first pick Rt<<Rf/2

Then calculate
1.8.3 Input offset voltage (Vios)

• Even though the above compensation techniques are used still there is some output voltage with
zero input voltage.
• This is due to unavoidable imbalances inside the op-amp.
• Applying a small voltage at the input terminals, to make output voltage zero. Thios voltage is
called
as input offset voltage Vios.
• This is the voltage required to be applied at the input for making output voltage to zero volts as
shown in fig(a).
Effect of Vios on the output of non-inverting & inverting op-amp amplifiers:
• If Vi is set to 0V, the circuit of fig(b) & (c) become the same as shown in fig(d).
• The voltage ‘V2’ at the (-) input terminal is given by
• The output offset voltage of an op-amp in closed loop configuration(inv or non-inv)
1.8.4 Total output offset voltage (VOT)

• The total output offset voltage VOT could be either more or less than the offset voltage produced
at the
output due to input bias current or input offset voltage done.
• Therefore the maximum offset voltage at the output of an inverting and non-inverting amplifier
without any compensating technique used is given by
• With Rcomp in the circuit the total output offset voltage will be given by
• Many op-amps provide offset compensation pins to nullify the offset voltage.
• For IC 741 op-amp, ‘1’ & ‘5’ pins are offset null pins. A 10kΩ potentiometer is placed across
pins 1& 5
and the wiper be connected to the negative supply pin 4.
• The position of the wiper is adjusted to nullify the output offset voltage and is shown in fig(a).
Fig.
• When the given op-amp does not have these offset null pins external balancing techniques are
used.
The figure (b) & (c) shows the balancing circuits for inverting and non-inverting op-amps.
1.8.5 Thermal Drift

• Bias current, offset current and offset voltage change with temperature.
• A circuit carefully nulled at 250c may not remain so when the temperature rises to 350c. This is
called drift.
• Offset current drift is expressed in nA/0c
• Offset voltage drift is expressed in mV/0c
Techniques to minimize the effect of thermal drift:

1. By using careful printed circuit board layout to keep op-amps away from source of heat.
2. Forced air cooling may be used to stabilize the ambient temperature.
1.9 AC CHARACTERISTICS OF AN OP-AMP

• Under ac conditions the parameters of op-amp are frequently dependent.
• The AC characteristics which will effect the output of an op-amp are:
➢ Frequency response
➢ Stability of op-amp
➢ Slew rate
1.9.1 FREQUENCY RESPONSE
• From the frequency response we can find the bandwidth of the op-amp.
• In the frequency response we observe two plots
i) Magnitude plot(gain v/s frequency)
ii) Phase plot (phase v/s frequency)
• Ideally the op-amp must have infinite bandwidth i.e gain is constant for all frequencies i.e from o
to ∞ Hz.
• Practically the gain of op-amp decreases (rolls-off) at higher frequencies.
• This decrease in gain at high frequencies is because of the presence of capacitive component.
• This capacitance is due to the physical characteristics of the device used and the internal
construction of op-amp.
• The capacitance effect is negligible at low frequencies and but at high frequencies it is more.
• The equivalent circuit of practical op-amp at high frequencies include a capacitor at the output.
Fig.(a) High frequency model of an op-amp with single corner frequency.

• The high frequency model is modified version of the low frequency model with a capacitor C at
the output.
• There is one pole due to R0C and one -20 dB/decade roll-off.
• The open loop voltage gain of an op-amp with only one corner frequency is obtained from fig (a)
as
• The magnitude of open loop voltage gain is

• The phase angle of open loop voltage gain is
Magnitude plot:
• The f1 is the corner frequency or break frequency or cut-off frequency.

• From magnitude plot we can observe,
i) f < f1 ,gain is constant
ii) f = f1 ,gain is -3dB
iii) f >f1 ,gain roll off by -20dB/decade
iv) f is very high , gain is 0dB
• And at particular frequency it becomes zero. i.e gain in dB = 0dB. This is called as unity gain
cross over frequency (or ) unity gain bandwidth(UGB) or small signal bandwidth.
• The UGB for µA741 op-amp is 1MHz.
Phase plot:
For f =0 , ϕ = 00
f =f1 , ϕ= -450
f = ∞ , ϕ= -900
• The magnitude in terms of s-domain can be written as
• A practical op-amp has no.of stages and each stage produces a capacitive component. Thus due to
a no. of pole pairs ther will be a no. of different break frequencies.
• The transfer function of an op-amp with 3 break frequencies can be assumed to as,
1.9.2 STABILITY OF AN OP-AMP

• Op-amps are rarely used in open loop configuration because of its high gain.
• Consider an op-amp amplifier as shown in fig (a) . it uses negative feedback and may be used
as inverting amplifier for V2=0 and ad non-inverting amplifier for V1=0
• From the negative feedback concepts, closed loop gain AcL is
𝐴𝑜𝐿
AcL =
1+𝐴𝑜𝐿𝛽
AoL is open loop gain & βis feedback ratio
fig(a). Resistive feedback in op-amp

• Here the stability of op-amp is decided by the loop gain AoLβ.
• The characteristic equation (1+AoLβ) = 0, the circuit will become just unstable i.e lead into
sustained oscillation.
• Rewrite the equation we have 1- (- AoLβ) = 0
AoLβ= -1 = -1+j0
Since AoLβ is a complex quantity it has magnitude and phase.
|AoLβ| = 1 ..magnitude condition …….(1)
….angle condition…..(2)
• Here (1) & (2) are the conditions for oscillations. These are called as Barkhausen criterion.
|AoLβ| ≥1 unstable
• The condition for stability of op-amp is |AoLβ| < 1
• In the circuit, feedback network is a resistive network. So it does not provide any phase shift.
• For stability of op-amp the AoL & AcL does not exceed -20dB/decade roll off rate & phase shift
must be minimum.
1.9.3 SLEW RATE

• For small signals i.e the signals having peak amplitude Vm< 1v, the speed of the op-amp is
specified by rise time.
• Rise time is defined as the time taken by the output voltage to change from 10% to 90%
of final value for a step input.
0.35
tr =
𝐵.𝑊
• For large signals i.e signals having peak value Vm>1v, the op-amp speed is specified by slew
rate.
Slew Rate: It is the maximum rate of change of output voltage for a change in input voltage.
𝒅𝑽𝟎
Slew rate = /max Units -V/µsec
𝒅𝒕
• For ideal op-amp B.W = ∞ and slew rate = ∞
• For practical op-amp larger B.W , slew rate higher
• Slew rate increases with closed loop gain & DC supply voltages.
• Slew rate decreases with increase in temperature.
• For practical op-amps, the range of slew rate is 0.1v/µsec - 10001v/µsec
Causes of slew rate:

• The slew rate is because, presence of capacitor at the output of an op-amp at higher frequencies in
equivalent circuit.
• This capacitor prevents the output voltage from responding immediately to a fast charging input.
𝑡
• The rate at which the voltage across capacitor Vc increases is given by, Vc= 1/c∫0 𝑖 𝑑𝑡
𝒅𝑽𝒄 𝑰
=
𝒅𝒕 𝑪
Where I is max current furnished by op-amp to the capacitor ‘C’
𝒅𝑽𝒄 𝑰𝒎𝒂𝒙
Slew Rate SR = /max =
𝒅𝒕 𝑪
For IC 741, Imax = 15µA, C=30pF
𝒅𝑽𝒄 𝑰𝒎𝒂𝒙 𝟏𝟓µ𝑨

SR = /max = = = 0.5 v/µs
𝒅𝒕 𝑪 𝟑𝟎𝒑𝑭
Expression for slew rate:

• Consider a voltage foller circuit as shown in figure
fig (a) voltage follower (b) input/output waveforms
• For voltage follower, Vi= Vo = Vm sin ω t
• The maximum rate of change of the output occurs when cos ω t = 1
• The maximum frequency of the input signal for which we get undistorted output of peak value
‘Vm’ is
Where fmax is also called as full power response
1.10 FEATURES OF 741 OP-AMP

1. IC 741 is a high performance monolithic op-amp.
2. IC 741 is useful for integrator, summer, voltage follower and other feedback applications.
3. IC 741 is available in all three packages as 8-pin metal can, 10 pin flat pack and 8 or 14 pin DIP.
4. IC 741 can operate over a temperature range of -550c to +1250c
5. IC 741is internally frequency compensated op-amp.
6. Short circuit Protection
7. IC 741 has Off Set Null Capability
8. Large Common mode and differential Voltage ranges
9. Low Power consumption
10. No-Latch up Problem
1.11 SUMMING AMPLIFIER

1.11.1 INVERTING SUMMING AMPLIFIER
• The non-inverting input terminal is at ground potential.

• The voltage at node ‘a’ is zero as the non-inverting input terminal is grounded i.e Va = 0.
• The nodal equation by KCL at node ‘a’ is
• When R1=R2=R3=RF, we have
• When R1=R2=R3=3RF, we have
1.11.2.NON- INVERTING SUMMING AMPLIFIER
fig Non- inverting summing amplifier

• Let the voltage at the (-) input terminal be ‘Va’
• The voltage at (+) input terminal will also be ‘Va’.
• The nodal equation at node ‘a’ is given by
𝑉𝑎−𝑉1 𝑉𝑎−𝑉2 𝑉𝑎−𝑉3
+ + =0
𝑅1 𝑅2 𝑅3
• The op-amp and two resistors Rf and R constitute a non-inverting amplifier with
• Let R1 = R2 = R3 = R = Rf/2 ,then
1.12 INSTRUMENTATION AMPLIFIER

• In a no. of industrial and consumer applications, one is required to measure and control physical
quantities.Some typical examples are measurement and control of temperature, humidity, light
intensity, water flow, etc. These physical quantities measured with the help of transducers.
• The output of transducer has to be amplified so that it can drive the indicator (or) display system.
This function is performed by an instrumentation amplifier.
• The important features of an instrumentation amplifier are :
(i) High gain accuracy
(ii) High CMRR
(iii) High gain stability with low temperature coefficient
(iv) Low dc effect
(v) Low output impedance
• There are specially designed op-amps such as µA725 to meet the above stated requirements
of a good instrumentation amplifier.
• Monolithic (single chip) instrumentation amplifier are also available commercially such as
AD521 , AD524 , AD620 , AD624 by analog devices , LM -363.xx(xx→10,100,500) by national
semiconductor and INA101 , 104 , 3626, 3629 by Burr- Brown.
• Consider the basic differential amplifier as shown in fig(a)
Fig (a) Differntial Amplifier using Single op-amp

𝑹𝟏 𝑹𝟑
• The output voltage Vo is given by , for =
𝑹𝟐 𝑹𝟒
𝑹𝟐 𝑹𝟐
V0 = (V1-V2) where gain =
𝑹𝟏 𝑹𝟏
• In the circuit of fig (a), source V1 sees an input impedance of R3+R4(=101kΩ) and the
impedance seen by source V2 is only R1(1kΩ).
• This low impedance may load the signal source heavily. Therefore, high resistance buffer is used
preceding each input to avoid this loading effect as shown in fig (b).
Fig (b) An improved Instrumentation Amplifier using ‘3’ op-amp’s.
• The op-amps A1 and A2 have differential input voltage as zero.

I.e. vd=0, i.e. v1=v2.
• For V1=V2, i.e. under common mode condition, the voltage across R will be zero.
• As no current flows through R&R1 ,the non –inverting amplifierA1 act as voltage follower, so its
output v21 =v2.
• Similarly op-amp A2 acts as voltage follower having output v11=v1.
• If v1≠v2, current flows in R and R1, and (v21-v1) > (v2-v1).
This circuit has differential gain and CMRR is more compared to the single op-amp circuit
of fig (a).
• The output voltage v0 can be calculated as follows:
• The voltage at the (+) input terminal of op-amp A3 is R2V1’/R1+R2 using super position
theorem,
We have ,
…..(1)
𝒗𝟏−𝒗𝟐
• Since, no current flows into op-amp, the current I flowing (upwards) in R is I = and
𝑹
passes through the resistor R1.
….(2)
…..(3)
Substitute eq’s (1) & (2) in eq(1), we get
…….(4)
• In eq’n (4), if we choose ,R2=R1=25kΩ & R1=25kΩ ,R=50Ω, then a gain of
can be achieved.
• The difference gain can be varied by varying R(potentiometer) as in fig (b)
i.e
And R should never be made equal to zero i.e. R≠0, R=0, Ad=∞
• To avoid such a situation, in a practical ci rcuit, a fixed resistance in series with a potentiometer is
used in place of ‘R’.
INSTRUMENTATION AMPLIFIER USING TRANSDUCER BRIDGE

• The circuit uses a resistive transducer whose resistance changes as a function of the physical
quantity to be measured.
• The bridge is initially balanced by a dc supply voltage vdc so that v1=v2.
• As the physical quantity changes, the resistance RT of the transducer also changes ,causing an
unbalance in the bridge (v1≠v2).
• This differential voltage now gets amplified by the three op-amp differential Instrumentation
Amplifier.
• There are a no. of practical applications of instrumentation amplifier with the transducer bridge,
such as temperature indicator, temperature controller ,light intensity meter….
FIG(C) Instrumentation Amplifier using Transducer Bridge
1.13 AC AMPLIFIER
• The inverting and non –inverting op-amp configurations, respond to both ac and dc signals.
• If one wants to get the ac frequency response of an op-amp (or) if the ac input signal is super
imposed with dc level, it becomes essential to block the dc component.
• This is achieved by using an ac amplifier with a coupling capacitor,
• AC amplifiers are of ‘2’ types
(1) Inverting AC amplifiers
(2) Non- Inverting AC amplifiers
1.13.1 INVERTING AC AMPLIFIER

• The circuit is as shown in fig
fig(a): Inverting AC amplifier

• The capacitor C blocks the dc component of the input and ‘C’ together with the resistor R1sets the
lower 3dB frequency of the amplifier.
• Since node ‘a’ is at virtual ground , the output voltage (as a function of complex variables) is
given by,
…..(1)
…..(2)
• From eq’n (2) that the lower 3dB frequency is,

• In the mid-band range of frequencies , capacitor C behaves s a short circuit and therefore eq’n (2)
becomes,
1.13.2 NON-INVERTING AC AMPLIFIER
• The circuit is as shown in fig(a)
Fig(b) Non- inverting AC amplifier Fig(c) High i/p impedance non-inv AC amplifier
• Here a resistor R2 is added to provide a dc return to ground

• This reduces the overall input impedance of the amplifier, which is approximately equal to R2.
• This problem of flow input impedance is eliminated by connecting a capacitor C3 as shown in
fig(b).
• Capacitor C3 is large enough to act as short circuit to ac signals.
• The non- inverting terminal and the node ‘n’will be almost at the same potential so that R2 carries
almost no current . Hence the circuit will have an extremely high input impedance.
1.13.3 AC VOLTAGE FOLLOWER

• The circuit of a practical ac voltage follower is as shown in fig.
• The circuit is used as a buffer to connect a high impedance signal source to a low impedance load
which may even be capacitive.
• The capacitor C1 and C2 are chosen high so that they are short circuit at all frequiences of
operation.
• Resistors R1 and R2 provide a path for dc input current into the non –inverting terminal
• C2 acts as a bootstrapping capacitor and connects the resistance R1 to the output terminal for ac
operation .
• Hence, the input resistance=∞

• Here AcL≡1[vo=vi]for voltage follower
• Where AcL is the gain of the voltage follower which is close to unity(0.9997).
• Thus very high input impedance can be obtained.
1.14 DIFFERENTIATOR
fig.(a) Op-Amp Differentiator

Analysis:
• The node ‘N’ is at virtual ground potential i.e. VN=0.
• The current iC through the capacitor is,
• The current iF through the feedback resistor is, Vo/RF and there is no current into the op-amp.
• The nodal equation at node ‘N’ is iC+iF=0.
….(1)
• Thus the output voltage vo is a constant (-RFC1) times the derivate of the input voltage vi and the
circuit is a differentiator.
• The ‘-‘ minus sign indicates a 1800 phase shift of the output waveform vo with respect to the
input signal.
• The phasor equalent of eq’n(1) is,
• V0(s)=-RFC1 SVi(s)
• In steady state, put s=jw.
• The magnitude of gain A of the differentiator is,
….(2)
where ….(3)
• At f=fa, |A| = 1, i,e.0dB, and the gain increases at a rate of +20dB/decade.
DRAWBACKS OF BASIC DIFFERENTIATOR :

• At high frequency a differentiator may become unstable and break into oscillations.
• The input impedance (1/ωc1) decreases with increase in frequency, there by making the circuit
sensitive to high frequency noise.
1.14.1 PRACTICAL DIFFERENTIATOR
• A practical differentiator will eliminate the problem of instability and high frequency noise.
• A practical differentiator is as shown in fig.(b)
Fig.(b) Practical Differentiator

• The transfer function for the circuit is given by,
…..(4)
• From eq(4), if RFC1 >> R1C1 (or) RFCF ,
𝑣𝑜
= -s RFC1
𝑣𝑖
𝒅𝒗𝒊
Vo = - RFC1 The output voltage expression is same as ideal differentiator.
𝒅𝒕
• For RFCF = R1C1, we get,
…..(5)
Where ….(6)
• From eq’n(5), the gain increases at +20dB/decade for frequency f<fb and the gain decreases at -
20dB/decade for frequency f >fb.
• The frequency response for basic and practical differentiator is as shown in fig(c)
Fig(c) Frequency Response

• For the basic (or) ideal differentiator of fig(a), the frequency response increases continuosly at the
rate of +20dB/decade, even beyond ‘fb’causing stability problem at high frequency.
• Thus the gain at high frequency response i.e(f>fb) is reduced significantly to
-20db/decade in the frequency response of practical differentiator, thereby avoiding the high
frequency noise and stability problems.
• The value of the fb should be selected such that,
fa<fb<fc
Where fc is the unity gain –bandwidth of the op-amp in open –loop configuration.
• For good differentiator one must ensure that the time period ‘T’ of the input signal is larger than
(or) equal to RFC1, i.e
T ≥ RF C 1
• A resistance Rcomp(=R1║RF) is connected to the (+) input resistance terminal to compensate for
the input bias circuit.
A good differentiator may be designed as per the following steps

(1) Choose fa equal to the highest frequency of the input signal. Assume a practical value of
C1(<1µF) and then calculate RF.
(2) Choose fb=10fa now calculate the values of R1 and CF so that R1C1=RFCF.
Applications of Differentiator
• The differentiator is most commonly used in
i) Wave shaping circuits to detect high frequency components in an input signal.
ii) As a rate-of change detector in FM modulators.
PROBLEM
• (a) Design an op-amp differentiator that will differentiate an input signal when
fmax = 100 Hz.
(b) Draw the output waveform for a sine wave of 1V peak at 100Hz applied to the
differentiator.
(c) Repeat part (b) for a square wave input.
Solution:
1.15 INTEGRATOR
Fig (a) Op-Amp Integrator

Analysis:
• The nodal equation at node ‘N’ is, i1+ i2 = 0
Integrating both sides, we get
….(1)
Where vo(0) is the initial output voltage.
• The circuit thus provides an output voltage which is proportional to the time integral of the input
and R1CF is the time constant of the integrator
• A simple low pass RC circuit can also be work as an integrator when time constant is large. This
requires very large values of R & C.
• The phasor notation for eq(1) is written as,
…..(2)
• In steady state put s=jω and we get,
• So, the magnitude of the gain or integration transfer function is
…..(3)
|A| = |fb/f| where ….(4)

• From eq(3) at ω=0, the magnitude of the integrator transfer function is infinite |A| = ∞
• At dc i.e ω=0, the capacitor CF behaves as an open circuit and there is no negative feedback.
• The op-amp thus operates in open loop resulting in an infinite gain.
• In practice output never becomes infinite rather the output of the amplifier saturates at a voltage
close to the power supply depending on the polarity of the input dc signal.
i.e v0 = ±vsat, i.e v0 ≠∞.
Drawbacks of basic integrator:

• As the gain of the integrator decreases with increase in frequency i.e at low frequencies such as at
dc (ω≡0), the gain become infinite or saturates.
1.15.1 PRACTICAL INTEGRATOR (LOSSY INTEGRATOR)

• The gain of the integrator at low frequency(dc) can be limited to avoid the saturation problem if
the feedback capacitor is shunted by a resistor Rf as shown in fig (b).
• The parallel combination of Rf and Cf behaves like a practical capacitor which dissipates power
like an ideal capacitor.
• For this reason the circuit is also called as lossy integrator.
• The resistor RF limits low frequency gain to –RF/R1(generally RF = 10 R1) and thus provides dc
stabilization.
Fig (b) Practical (or) Lossy Integrator

ANALYSIS:
• The nodal equation at the (-) inv input terminal of the op-amp is,
i1+i2+i3 = 0
• If RF is large, the lossy integrator approximates the ideal integrator. Rf=∞, R1/RF=0
expression same as ideal integrator.

• For s=jω, magnitude of the gain of lossy integrator is given by
…..(5)
• At low frequencies (ω=0), gain is constant at RF/R1
• The break frequency (f=fa) at which the gain is 0.707(RF/R1) (or -3dBbelow its value of RF/R1)
is calculated from eqn(5) as
𝑓
Solving for f=fa, √1 + (𝑓𝑎) 2 = √2
Where fa is lower frequency limit of integration, ….(6)

• If input frequency f< fa, the circuit acts like a simple inverting amplifier and no integration
results.
• At input frequency f=fa, 50% accuracy results.
• If input frequency is 10 times fa, i.e f=10fa, then 99% accuracy results.
i.e at f > fa, Perfect Integration.
• The bode plot or frequency response of a basic & lossy integrator is as shown in fig(c).
Fig (c) frequency response of abasic and lossy integrator.
Applications of Integrator
• The integrator is most commonly used in
i) Analog computers
ii) Analog –to- digital converter(ADC)
iii) Signal wave shaping circuits.
PROBLEM:
• For a lossy integrator circuit, if R1=10kΩ, RF=100kΩ, CF=10nF, determine the lower
frequency limit of integration and study the response for the inputs
(i) Sine wave input of 1Vpeak, 5kHz
(ii) Step input of Vi=1v for 0 ≤t ≤0.3msec
(iii) Square wave input 1Vpeak,5kHz.
Solution:
Given data,
R1=10kΩ, RF=100kΩ, CF=10nF
Lower frequency limit of integration fa is
• For 99% accuracy, the input frequency should be atleast one decade above fa
i.e f=10fa = 10*159 = 1590Hz = 1.59kHz
(i) Sine wave input of 1Vpeak, 5kHz
For an input of 1V peak sine wave at 5kHz, the output vo is
The output is a cosine wave with a peak amplitude of 0.318v as shown in fig (a)
• If the frequency of the input is raised by a factor of 10 to 50kHz the output would be a cosine
wave of frequency 50kHz but with an amplitude of 31.8mv only(frequency increases, amplitude
decreases)
(ii) Step input of Vi=1v for 0 ≤t ≤0.3msec
If input is a step voltage vi = 1v for 0 ≤t ≤0.3msec, then the output voltage at t= 0.3ms is
The output voltage is a ramp function with a slope of 10v/ms and is shown in fig(b)
(iv) Square wave input 1Vpeak,5kHz
• For the input of 5kHz, 1V peak square wave, the output vo is
• The output for each of these half periods will be ramps for the step inputs. Thus the expected
output waveform will be a triangular wave as shown in fig(c).
For +ve peak of input, vi=1v from 0-0.1ms, vo= -1v
For -ve peak of input, vi= -1v from 0.1 -0.2ms, vo= 1v
1.16 COMPARATORS
• A comparator is a circuit which compares a signal voltage applied at one inputof an op-amp with
a known reference voltage at the other input.
• It is basically an open loop op-amp with output ±vsat(=Vcc) as shown in ideal transfer
characteristics.
Fig Tranfer characteristics (a) Ideal comparator (b) Practical comparator.

• Depending upon which terminal the input is applied to comparator there are two types of
comparators.
1) Non-inverting comparator.
2) Inverting comparator.
1.16.1 Non-inverting comparator

• In this, the input voltage is applied to non-inverting input terminal and the reference voltage is
applied to the inverting input terminal.
Fig. (a) Non-inverting comparator (d) Practical Non-inverting comparator

• In practical circuit, vref is obtained by using 10kΩ potentiometer which forms a voltage divider
with the supply voltages v+ and v- with the wiper connected to (-ve) input terminal.
• Here vref is +ve or –Ve voltage.
When vin > ±vref, then v0 = +vsat
vin < ±vref, then v0 = -vsat
vi =vref, then v0 changes from one saturation level to another.
Fig. Input & output waveforms (b) Vref positive (c) Vref negative
1.16.2 INVERTING COMPARATOR

• In inverting comparator the input voltage is applied to inverting input terminal and reference
voltage is applied to non-inverting input terminal.
fig(a) Practical Inverting comparator

• Here vref is +ve or –ve voltage.
• Operation:
When vin > ±vref, then v0 = -vsat
vin < ±vref, then v0 = +vsat
vi ≡vref, then v0 changes from one saturation level to another.
(b) (c)
Fig. Input & output waveforms (b) Vref positive(Vref>0) (c) Vref negative(Vref<0)
1.16.3 APPLICATIONS OF COMPARATOR

• The important applications of comparator are
1) Zero crossing detector
2) Window detector
3) Time marker generator
4) Phase meter
1) ZERO CROSSING DETECTOR: (SINE TO SQUARE WAVE CONVERTER)
• An inverting zero crossing detector is shown in figure…with vref=0v.
• Operation:
When vi>0, then v0= - vsat
vi<0, then v0= +vsat
Fig (a) Zero crossing detector (b) Input & output waveforms
Applications:
• Zero crossing detector is used in detecting no. of zero crossings for detecting noise.
• Used in TV and radio receivers for noise detection.
2) WINDOW DETECTOR:
• In some applications we have to determine when an unknown input is between two threshold
levels the can be achieved by a circuit called window detector.
Table: Three level comparator LED specifications

Application:
• Window detectors are used in industrial alarms, level detectors and controls, digital computers
and production line testing.
Fig .Three level comparator with LED indicator
3) TIME MARKER GENERATOR: (PULSE GENERATOR)

• The time instant at which the input voltage attains the reference level can be measured by
using Time marker generator.
• The zero crossing detector followed by differentiator is used as a time marker generator.
Fig (a) Time marker circuit (b) Input waveform (c)Output vo (d) Differentiator output
v’ (e) Output pulses
Application:
• Time marker generators are used for triggering the monoshots, SCR, sweep voltage of CRT.
4) PHASE DETECTOR: (PHASE METER)
• The phase angle between two voltages can be measured using the comparator.
• Both voltages are converted into spikes and the time interval between the spikes of one input
and other input is measured.
• The time interval is proportional to the phase difference.
• One can measure phase angles from 0 to 3600 with this phase meter.
θ = ωt = 2Πft & θαt
where f is frequency of input signal & t is time interval between the spikes of two voltages.
1.17 SCHMITT TRIGGER: (REGENERATIVE COMPARATOR)

• This circuit uses inverting comparator with positive feedback circuit.
• It converts any arbitrary waveform into square wave so it is called as squaring circuit.
Fig . (a) An Inverting Schmitt trigger (b)Transfer characteristics for vi increasing (C) vi decreasing
(d) composite input-output curve.
• The input is applied to the (-ve) input terminal and feedback voltage to the (+ve) input terminal.
• The input voltage vi triggers the output vo every time it exceeds certain voltage level. These
voltage levels are called upper threshold voltage (VUT) and lower threshold voltage (VLT).
UPPER THRESHOLD VOLTAGE (VUT):

• Let the output v0 = +Vsat. The voltage at (+ve) input terminal can be obtained by using
superposition.
As vi < VUT , the vo remains constant at +Vsat.

When vi > VUT , the vo switches from +Vsat to -Vsat
LOWER THRESHOLD VOLTAGE (VLT):

• Let the output v0 = -Vsat. The voltage at (+ve) input terminal is,
When vi ≤ VLT , then vo switches from –Vsat to +Vsat.

• A regenerative transition takes place and the output vo returns from –Vsat to +Vsat almost
instantaneously.
• If VLT < VUT, and the difference between these two voltages is the hysteresis width VH and can be
written as
𝑹𝟐𝑽𝒔𝒂𝒕
• If Vref = 0, then VUT = - VLT =
𝑹𝟏+𝑹𝟐
Fig (e) Schmitt trigger used as squarer (f) VUT = - VLT
1.18 INTRODUCTION TO VOLTAGE REGULATORS

• The function of a voltage regulator is to provide a stable dc voltage for powering other electronic
circuits.
• A voltage regulator should be capable of providing substantial output current.
• Voltage regulators are classified as
1) Series regulators (linear regulators)
2) Switching regulators
1) SERIES REGULATOR:
• Series regulators use a power transistor connected in series between the unregulated dc input and
the load. The output voltage is controlled by the continous voltage drop taking place across the
series pass transistor sice the transistor conducts in the active or linear region. These regulators
are also called as linear regulators.
• Linear regulators may have fixed or variable output voltage and could be +Ve or –Ve.
1) Fixed output voltage regulators(or) three terminal voltage regulators
Ex: IC 78xx,79xx series
2) Adjustable output voltage regulators (or) Variable output voltage regulators.
Ex: IC 723 general purpose regulator.
2) SWITCHING REGULATOR:
• Switching regulators operate the power transistor as a high frequency ON/OFF switch so that the
power transistor does not conduct current continuously, this gives improve the efficiency over
series regulator.
1) SERIES OP-AMP REGULATOR:

• A voltage regulator is an electronic circuit that provides a stable dc voltage independent of the
load current, temperature and ac line voltage variations
• The figure shows a regulated power supply using discrete components.
Fig . A Regulated Power Supply

• The circuit consists of following four parts:
1) Reference voltage circuit.
2) Error amplifier
3) Series pass transistor(Q1)
4) Feedback network
• Here Q1 acts as an emitter follower(v0 = vi)
1.19 THREE TERMINAL IC VOLTAGE REGULATORS

1) 78XX series : are three terminal, positive fixed ouput voltage regulators. There are ‘7’ output
voltage options available such as 5,6,8,12,15,18 and 24V.
78XX - XX indicates output voltage.
Ex: 7815 – represents a 15V regulator i.e v0=15V
2) 79XX series : are three terminal, negative fixed output voltage regulators. There are ‘9’ output
voltage options available such as -2,-5,-5.2,-6,-8,-12,-15,-18 and -24V.
79XX - XX indicates output voltage.
Ex: 7915 – represents a -15V regulator i.e v0= -15V
• These regulators are available in two types of packages
1) Metal package(TO – 3type)
2) Plastic package(TO – 220 type)
• The standard representation of monolithic voltage regulator is as shown in figure.
Fig . Standard Representation Of Three Terminal Positive Monolithic Voltage Regulator
CHARACTERISTICS:
There are ‘4’ characteristics of three terminal IC regulators.
1. Vo: The regulated output voltage is fixed at value as specified by the manufacturer.
2. |Vin| ≥ |Vo| + 2volts: The unregulated input voltage must be at least 2v more than the regulted
output voltage.
3. Io(max): The load current may vary from 0 to rated maximum output current the IC is usually
provided with a heat sink otherwise it may not provide the rated maximum output current.
4. Thermal shutdown: The IC has a temperature (built-in) which turns off the IC when it becomes
too hot (usually 1250c to 1500c). the output current will drop and remains their until the IC has
coded significantly.
1.19.1 Boosting IC Regulator output current: (Boosting a Three Terminal Voltage Regulator)
• To boost the ouput current of a three terminal regulator, simply by connecting an external pass
transistor in parallel with the regulator as shown in fig.
• For low load currents, VBE (<0.7 V) to tuen Q1 and regulator itself supply the load current.
• As IL increasea, the voltage drop across R1 increases(VBE on increases)
• When VBE =0.7V, Q1 – ON
If IL=100mA, the voltage drop across R1 is I1*R1=100m*7 = 0.7V
• If IL increases more than 100mA, the voltage drop across R1(>0.7V) and Q1 turns ON and
supplies the extra current required.
• Since VBE(ON) remains constant, the excess current comes from Q1’s base after amplification
by β.
and
For the regulator,
Also,
• The maximum current Io(max) for a 7805 regulator is 1A

• Assume, VBE(ON) = 1V and β = 15, we get
IL = 1*(15+1) – 15*(1/7) = 16-(15/7) = 13.8A.
Limitations of three terminal regulators:

1) No short circuit protection.
2) Output voltage (positive or negative) is fixed.
• These limitations have been overcome in the 723 general purpose regulator.
1.20 FEATURES OF 723 –GENERAL PURPOSE REGULATOR
• It is a low current device it can be boosted to 5A or more current by connecting external
components
.
Features of IC 723:
1) Ability to provide IL = 150mA and it is increased to 10A by using external power transistors.
2) The input voltage ranges from 9.5V to 40V.
3) The output voltage adjustable from 2 V to 37V.
4) It canbe used as either linear or switching regulator.
5) It is available in 14-pin DIP or 10 pin metal can.
Fig .10 Pin Metal Can
Fig. 14 Pin Dip
1.20.1 FUNCTIONAL BLOCK DIAGRAM OF 723 REGULATOR

• It has ‘2’ separate sections.
• In section1, the zener diode, a constant current source and reference amplifier produce a fixed
voltage of about 7V at the terminal Vref.
• In section 2, the IC consists of an error amplifier, a series pass transistor Q1 and a current limit
transistor Q2.
• The error amplifier compares both a sample of the output voltage applied to the INV input
terminal to the reference voltage Vref applied to the NI input terminal. The error signal controls
the conduction of Q1.
A Low Voltage Regulator Using IC 723: (< 7V)
• A simple positive low-voltage (2v to 7v) regulator using IC 723 as shown in fig.
Functional Diagram for a low voltage Regulator:

• The voltage at the NI terminal of the error amplifier due to R1R2 divider is, VNI = Vo
• Since Q1 is operating as an emitter follower
•
• Any increase in load voltage or changes in input voltage can be regulated.
• The reference voltage is typically 7.15V. So the output voltage Vo is
i.e (Vo < 7.15 V)
A high Voltage Regulator Using IC 723: (>7V)
,
• The NI terminal is directly connected to Vref through R3. So the voltage at NI terminal is Vref.
• The error amplifier operates as a non-inverting amplifier with a voltage gain of
• So, the output of the circuit is,
Limitations of 723 IC:

1) No short circuit current limits.
2) No inbuilt thermal protection.
Problems
1. Design an adder circuit using an op-amp to get the output expression as
Vo = -(0.1 V1 + V2 + 10 V3)
Where V1,V2,V3 are the inputs.
Sol: The output is,
Comparing above equation with given expression, we get

Rf = 10kΩ, R1 = 100kΩ, R2 = 10kΩ, R3 = 1kΩ
2. For a square wave input of frequency 2MHZ and 8V p-p amplitude. What is the slew rate of the op-amp.
2𝜋𝑓𝑉𝑚
Sol: Slew rate = 106
V/μsec
= 100.5 V/μsec
3. Design an amplifier with a gain of -10 and input resistance is 10kΩ.
Sol: Given, ACL = -10, Ri = 10kΩ
ACL = -Rf/Ri
Rf = - ACL * Ri = -(-10) x 10K = 100kΩ
UNIT II OP-AMP, IC-555 & IC 565

APPLICATIONS
2.1 INTRODUCTION TO ACTIVE FILTERS

FILTER: An electric filter is often a frequency selective circuit that passes a specified band of
frequencies or attenuated signals of frequencies outside this band.
• Filters may be classified in a number of ways
1. Analog or digital
2. Passive or Active
3. Audio frequency or radio frequency.
ANALOG OR DIGITAL FILTER

• The classification is done depending on the nature of the input signal processing.
• Analog filters are designed to process analog signals.
• Digital filters are used to process analog signal and using digital techniques.
ACTIVE OR PASSIVE FILTER

• Depending upon the type of elements used in their construction,filters may be classified as
passive or active.
• Elements used in passive filters are resistors, capacitors and inductors.
• Active filters use transistors or OP-AMPS in addition to resistors and capacitors.
AUDIO FREQUENCY AND RADIO FREQUENCY FILTER

• Depending on the frequency range, filters may be classified as audio frequency or radio frequency
filters.
• Audio frequency (AF) filters or low frequency RC filters uses resistors and capacitors. Inductors
are not used since they are large in size ,costly and may dissipate power and also inductors emit
magnetic fields.
• Radio frequency (RF) filters or high frequency LC or crystal filters uses inductors and capacitors.
These are used because of their high Q value (figure of merit) and crystals provide more stable
operation at high frequencies.
ADVANTAGES OF ACTIVE FILTER OVER PASSIVE FILTER

An active filter offers the following advantages over a passive filter.
• Gain and frequency adjustment flexibility
➢ Since the OP-Amp is capable of providing a gain, the i/p signal is not attenucated as it
is in a passive filter.
➢ In addition active filter is easy to tune or adjust.
• No loading problem
➢ Because of the high input resistance and low output resistance of the OP-Amp, the
active filter does not cause loading of the source or load.
• Cost
➢ Typically, active filters are more economical than passive filters.This is because of the
variety of cheaper OP-Amps and the absence of inductors.
ACTIVE FILTER APPLICATIONS

• Active filters are most extensively used in the field of communication and signal processing,
they are employed in one form or another in almost all sophisticated electronic systems.
COMMONLY USED ACTIVE FILTERS

• Low pass filter
• High pass filter
• Band pass filter
1. Narrow band pass filter
2. Wide band pass filter
• Band reject filter or band stop filter
1. Narrow band reject filter
2. Wide band reject filter
• All pass filter
The frequency response of the RC active filters is shown in figure 2.1. The ideal response is shown by
dashed line. While the solid lines indicates the practical filter response.
Figure 2.1 Frequency responses of RC active filters

❖ Active filters are typically specified by voltage transfer function,
𝑽𝒐(𝑺)
H(S) = 𝑽𝒊(𝑺)
Under steady state condition (i.e S=j𝜔)
H(j𝝎) = | H(j𝝎)|. 𝒆𝒋𝝋(𝝎)
Where
• | H(j𝜔)| is the magnitude or the gain function
• 𝜑(𝜔) is the phase function
❖ Magnitude response is given in dB as 20log |H(j𝝎)| dB
2.2 CHARACTERISTICS OF FILTERS
2.2.1 BAND PASS FILTERS
There are two types of BPFs which are classified as per the figure of merit or quality factor Q.
1. Narrow band pass filter (Q> 10)
2. Wide band pass filter (Q < 10)
❖ The following relationship is important
𝑓
𝑜 𝑉𝑜
Q= 𝐵𝑊 =𝑓 & 𝑓𝑜 =√(𝑓ℎ − 𝑓𝑙 )
ℎ −𝑓𝑙
Where 𝑓ℎ = Upper cut off frequency, 𝑓𝑙 = Lower cut off frequency, 𝑓𝑜 = central frequency
2.2.1.1 Narrow Band Pass Filter (Infinite Gain Multiple Feedback Filter) (Q>10) NBPF / IGMF
❖ The important parameter in a BPF are 𝑓ℎ , 𝑓𝑙 , 𝐵𝑊, 𝑓𝑜 , the central frequency gain Ao, selectivity Q.
❖ The circuit has two feedback paths and the OP-Amp is used in inverting mode of operation as
shown in figure 2.2.
Figure 2.2 (a) band pass configuration (b) second order band pass filter
❖ Node voltage equation at node ‘A’ is ,
(VA- Vi) Y1 + (VA- VO) Y3 +(VA- VB) Y2 +VA.Y4 = 0
VA Y1 – Vi Y1 + VA Y3 - VO Y3 + VA Y2 - VB Y2+VA.Y4 = 0
VA [Y1 + Y2 + Y3 +Y4] – VO Y3- VB Y2– Vi Y1 = 0
Due to the virtual ground VB= 0
VA [Y1 + Y2 + Y3 +Y4] = VO Y3 + Vi Y1 → equ. 1
❖ Node voltage equation at node ‘B’ is,
(VB- VA) Y2 + (VB- VO) Y5 = 0
Since VB = 0, -VAY2=VOY5
−𝑉0 𝑌5
VA = eqn 2
𝑌2
Substitute eqn 2 in equ 1,
−𝑉0 𝑌5
[ Y1+Y2+Y3+Y4] = VoY3+ ViY1
𝑌2
−𝑉𝑜[Y1Y5+ Y2Y5 + Y3Y5 + Y4Y5] – VOY3Y2 =ViY1Y2

𝑉𝑜 −Y1Y2
= eqn 3
𝑉𝑖 Y1Y5+ Y2Y5 + Y3Y5 + Y4Y5+Y3Y2
For this circuit to be band pass filter put Y1=G1, Y2=SC2 , Y3 =SC3, Y4=G4 and Y5=G5
❖ Then the transfer function becomes,
𝑉𝑜(𝑆) −SG1C2
H(S)= =
𝑉𝑖(𝑆) S2 C2C3+S(C2+C3G5)+G5(G1+G4)
−𝐺1
= 𝐺5(𝐶2+𝐶3) (𝐺1+𝐺2)𝐺5
𝑆𝐶3+ 𝐶2
+ 𝑆𝐶2
❖ The transfer function of eqn 4 is equivalent to the gain expression of a parallel RLC circuit
driven by a current source G’Vi and with band pass characteristics as shown in figure 2.3
Figure 2.3 (a) Parallel RLC circuit (b) band pass characteristics
❖ The gain expression is
𝑉𝑜(𝑆) −𝐺′ −𝐺′
= = eqn 5
𝑉𝑖(𝑆) 𝑌 𝑆𝐶+𝐺+1/𝑆𝐿
❖ Comparing the gain expression of eqn 4 and eqn 5 we get
G’ = G1 & G = [G5(C2+C3)] / C3
𝐶2
L= & C = C3
𝐺5(𝐺1+𝐺4)
❖ At resonance the parallel RLC circuit has unity power factor i.e., imaginary part is zero which gives the
resonant frequency 𝜔o as
𝐺5(𝐺1+𝐺4)
𝜔o2 = 1/ LC = 𝐶2𝐶3
eqn 6
❖ The gain at resonance is,

𝐺1 𝑅5
𝑉𝑂 −𝐺′ −𝐺1 −( )𝐶2 −( )𝐶2
𝐺5 𝑅1
| 𝜔= 𝜔o = = = =
𝑉𝑖 𝐺 𝐺 𝐶2+𝐶3 𝐶2+𝐶3
❖ The Q factor at resonance is,
𝜔oL 𝜔oC 𝜔oC2C3
Q = = 𝜔ORC = = (𝐶2+𝐶3)𝐺5 eqn 7
𝑅 𝑅
❖ The bandwidth BW is given by

𝑓𝑜 𝜔o 1 𝐺 𝐺5(𝐶2+𝐶3)
𝐵𝑊 = 𝑓ℎ − 𝑓𝑙 = = = = =
𝑄𝑂 2𝜋𝑄0 2𝜋𝑅𝐶 2𝜋𝐶 2𝜋𝐶2𝐶3
❖ The centre frequency 𝑓𝑜 = √( 𝑓ℎ. 𝑓𝑙)

❖ Now for C2 = C3 =C, the gain at resonant frequency
𝑉𝑂 −𝑅5 −𝐺1
| 𝜔= 𝜔o = = -AO = eqn 8
𝑉𝑖 2𝑅1 2𝐺5
√𝐺5(𝐺1+𝐺4) 1
and 𝜔o = , B.W =
𝐶 𝜋𝑅5𝐶
−𝐺1
❖ Consider eqn 4, H(S)= 𝐺5(𝐶2+𝐶3) 𝐺5(𝐺1+𝐺4)
𝑆𝐶3+ 𝐶2
+ 𝑆𝐶2
❖ From eqn 7,
𝜔oC2C3 𝐺5(𝐶2+𝐶3) 𝜔oC3
Q= => =
(𝐶2+𝐶3)𝐶5 𝐶2 𝑄
❖ From eqn 6,
𝐺5(𝐺1+𝐺4) 𝐺5(𝐺1+𝐺4)
𝜔 o2 = => = 𝜔o2c3
𝐶2𝐶3 𝐶2
Sub in eqn 4, we get
−𝐺1
H(S) = 𝑊0 𝜔o2
𝑆𝐶3+( )𝐶3+ C3
𝑄 S
−𝐺1𝑆
= 𝑊0 {C=C2=C3}
𝑆 2 𝐶3+( )𝑆𝐶3+ 𝜔o2 C3
𝑄
𝑆𝐺1
−
𝐶
= 𝜔o
𝑆 2 +( Q )𝑆+𝜔o2
𝑾𝟎
−𝑺( ) .𝑨𝟎
𝑸
H(S) = 𝝎𝐨
𝑺𝟐 +( 𝐐 )𝑺+𝝎𝐨𝟐
From eqn 7
𝜔oC2C3
Q=
(𝐶2+𝐶3)𝐺5
𝐺1 (𝐶2+𝐶3)𝐺5 𝑊0
. = . AO
2𝐺5 𝐶2.𝐶3 𝑄
𝑮𝟏 𝑾𝟎
Thus 𝑪
= ( 𝑸
) . 𝑨𝒐
−𝑨𝟎 .𝝎𝑶 𝜶𝑺
Therefore , H(S) = {α= 1/Q}
𝑺𝟐 + 𝜶𝝎𝑶𝑺+𝝎𝒐𝟐
−𝑨𝟎 .𝝎𝑶 𝜶𝑺
In dB, we get 20log |H(S) = 20 log | |
𝑺𝟐 + 𝜶𝝎𝑶𝑺+𝝎𝒐𝟐
Where the damping factor 𝛼 = 1/ Q
❖ For w << wo & w >> wo, the gain is zero and for w = wo the gain is Ao as shown in figure 2.4
Figure 2.4 single op-amp band pass filter response

2.2.1.2 Wide band pass filter
• A wide band pass filter can be formed by cascading a HPF and LPF as shown in figure
2.5.
• If the HPF and LPF are of the first order then the band pass filter (BPF) will have a roll off
rate of -20 dB/decade as shown in figure 2.6.
Vi HPF LPF Vo
Figure 2.5 Wide band pass filter
Figure 2.6 first order band pass filter

𝑉𝑜 𝑉𝑜 𝑉1
|H(jw)| = | |=| . |
𝑉𝑖 𝑉1 𝑉𝑖
𝑅𝐹 𝑗2𝜋𝑓𝑅2𝐶2
= |[1+ ]. |
𝑅𝑖 1+𝑗2𝜋𝑓𝑅2𝐶2
𝑗(𝑓/𝑓𝑙)
= |A01 . |
1+𝑗(𝑓/𝑓𝑙)
𝑗(𝑓/𝑓𝑙)
= A01 . 𝑓 𝑓 ,
√(1+𝑗(𝑓𝑙)(𝑓𝑙))
1
Where, fl=
2𝜋𝑅2𝐶2
Similarly for the low pass filter the magnitude of A is
𝑉𝑜 𝑉𝑜 𝑉1
|H(jw)BP| = | |=| . |
𝑉𝑖 𝑉1 𝑉𝑖
𝑅𝐹 1
= |[1+ ]. |
𝑅𝑖 1+𝑗2𝜋𝑓𝑅𝐶
𝑗(𝑓/𝑓ℎ)
= A02 . |
1+𝑗(𝑓/𝑓ℎ)
𝐴02
=
√(1+(𝑓/𝑓ℎ)(𝑓/𝑓ℎ))
1
Where fh =
2𝜋𝑅1𝐶1
• The voltage gain magnitude of the wide band pass filter is the product of that of LPF and HPF.
• |H(jw)BP| = |H(jw)HP| X |H(jw)LP|
𝑉𝑜 𝐴0(𝑓/𝑓𝑙)
|H(jw)BP| = | |= where A0= A01 x A02 (or)
𝑉𝑖 2
√[1+( 𝑓 ) ][1+( 𝑓 )2 ]
𝑓𝑙 𝑓ℎ
𝑉𝑜 𝐴0(𝑓/𝑓𝑙)
|H(jw)BP| = | |=
𝑉𝑖 2
√[1+(𝑓𝑙) ][1+( 𝑓 )2 ]
𝑓 𝑓ℎ
2.2.2 BAND REJECT FILTER OR BAND STOP OR BAND ELIMINATION FILTER

• There are two types of band reject filter.
1. Wide band reject filter (WBRF)(Q<10)
2. Narrow band reject filter (NBRF) is commonly called as notch filter or (Q>10)
Wide Band Reject filter (WBRF)
• A WBRF (Q > 10) can be made using a LPF, HPF & a summer.
• The necessary conditions are
❖ The lower cut off frequency fl of the HPF should be much greater than the upper cut off
frequency fh of the LPF i.e fl > fh
❖ The pass band gain of LPF and HPF should be same.
Narrow band Reject filter (NBRF) or Notch Filter
• Notch filter is used for the rejection of a single frequency such as 50Hz power line frequency sum
as shown in figure 2.7.
• There are several ways to make notch filter
➢ One simple technique is to subtract the band pass filter otput from its input.
Figure 2.7 notch filter block diagram
we know that,
• The band pass filter (NBPF) has an inverted output as the gain or transfer function is negative.
• Therefore while implementing we must use a summer instead of a substractor
• The BPF has a gain of Ao so that output at the centre frequency is will be –Ao x Vi
• To completely substract this output the input of the summer must be precisely Ao x Vi
• Thus a gain of Ao must be added between the input signal and the summer and is shown in figure
2.8
Figure 2.8 practical notch filter block diagram

• The output of the circuit in the S domain is,
−𝐴𝑂 𝛼𝜔𝑂 𝑆𝑉𝑖(𝑆)

VO(S) = Ao.Vi(S) + [ ]
𝑆 2+ 𝛼𝜔𝑂 𝑠+𝜔𝑂 2
𝑉𝑂 (𝑆) 𝐴𝑂 𝛼𝜔𝑂 𝑆
= AO -
𝑉𝑖 (𝑆) 𝑆 𝛼𝜔𝑂 𝑠+𝜔𝑂 2
2+
𝛼𝜔𝑂 𝑆
= AO [1 - ]
𝑉𝑂 (𝑆)
H(S) =
𝑉𝑖 (𝑆)
𝐴𝑂 (𝑆 2 +𝜔𝑂 2 )
=
• This is the transfer function for a 2nd order notch filter (NBRF)
i.e for 𝜔 ≪ 𝜔𝑜 the pass band gain is |Ao| and at frequency 𝜔 = 𝜔𝑜 , the gain is zero.
Figure 2.9 twin T notch filter
• Another commonly used notch filter is twin T network called as twin T notch filter as shown in
figure 2.9.
• Here we will determine the notch frequency Q factor and bandwidth for this configuration.
• Nodal equations in S domain by KCL for the active filter circuit can be written as
At node A :
(VA – Vi)SC + (VA – VO)SC + (VA – KVO)2G = 0 [G =1/R] [VP=VO]
VA[2SC + 2G] = ViSC + Vo(SC +2KG)
𝑉𝑖𝑆𝐶+𝑉𝑜 (𝑆𝐶+2𝐾𝐺)
Therefore., VA = Eqn 1
2(𝑆𝐶+𝐺)
At node B :
(VB – Vi)G + (VB – VO)G + (VB – KVO)2SC = 0
VB[2G + 2SC] = ViG+ Vo(G +2KSC)
𝑉𝑖𝐺+𝑉𝑜 (𝐺+2𝐾𝑆𝐶)
Therefore., VA = Eqn 2
2(𝑆𝐶+𝐺)
At node P :
(VP-VA)SC + (VP-VB)G = 0
Here Vp = VO
(VO-VA)SC + (VO-VB)G = 0
VASC +VBG = VO[SC + G] Eqn 3
Sub eqn 1 and eqn 2 in eqn 3
𝑉𝑖𝑆𝐶+𝑉𝑂 (𝑆𝐶+2𝐾𝐺) ViG+VO[G+2KSC)

[ ]SC + [ ].G = VO[SC+G]
2(𝑆𝐶+𝐺) 2(𝑆𝐶+𝐺)
Vi𝑆 2 C2 + VO𝑆 2 C2 +VO2KGSC +ViG2 +VOG2+ VO2KSCG = VO.2[S2 C2 + G2 +2SCG]
Vi[G2 + S2C2] = 2VOS2C2+2VOG2+4VOSCG-VOS2C2-2VOKGSC-VOG2-2KSCGVO
= VOS2C2 + VOG2 +4VOSCG-4VOKGSC
= VO[S2 C2 + G2 + 4GSC[1-K]]
𝑉𝑜 G2 +S2 C2
H(S) = =
𝑉𝑖 S2 C2 + G2 + 4GSC[1−K]
G 2
𝑉𝑜 S2 +(C )
= = G 2
𝑉𝑖 S2 + ( ) + 4[1−K]S( )
G
C C
𝐺
• In the steady state , S=j𝜔 & 𝜔𝑜 = 𝐶
−𝜔2 +(𝜔𝑜 )2
H(j𝜔) = 2
−𝜔 +(𝜔𝑜 )2 + 4[1−K]jωωo
𝜔2 −(𝜔𝑜 )2 𝐺
= where ωo = = 1/RC &
𝜔2 −(𝜔𝑜 )2 −4j[1−K]ωωo 𝐶
fo = 1/2𝜋RC [resonant frequency or notch frequency]

• If H(j𝜔) becomes zero for ω = ωo and approaches unity as 𝜔 ≪ ωo and for 𝜔 ≫ ωo
1
• At 3 dB points, |H|=
√2
i.e., 𝜔2 − (𝜔𝑜 )2 = ±4[1 − K]ωωo

𝜔
[(𝜔 )]2 ±4[1 − K]ωωo - 1 = 0
𝑜
solving the quadratic equation we get the upper and lower half power frequencies.
For higher cut off frequency,
𝜔2 − (𝜔𝑜 )2 − 4[1 − K]ωωo=0
−𝑏±√b2 −4ac −(−4𝜔𝑜 (1−𝐾))+√(4𝜔𝑂 (1−𝐾))2 +4𝜔𝑂 2

𝜔= =
2𝑎 2
2
(4𝜔𝑜 (1−𝐾))+√(16𝜔𝑂 2 (1−𝐾)) +4𝜔𝑂 2
= 2
= 2𝜔𝑜 (1 − 𝐾)+𝜔𝑂 √4(1 − 𝐾)2 + 1
Fh = fo[√4(1 − 𝐾)2 + 1 + 2(1-K)]
For lower cut off frequency, Fl = fo[√4(1 − 𝐾)2 + 1 - 2(1-K)]
• The 3-dB bandwidth,
B.W = fh –fl = 4(1-K)fo

𝑓𝑂 1
Q= =
𝐵.𝑊 4(1−K)
• As ‘K’ approaches unity, Q factor becomes very large and B.W approaches zero
• The frequency response of notch filter as figure 2.10.
Figure 2.10 frequency response of notch filter
2.2.3 ALL PASS FILTER
• An all pass filter passes all frequency components of the input signal without any attenuation and
provides desired phase shifts at different frequencies of the input signal.
• When signals are transmitted over transmission lines such as telephone wires they undergo
change in phase. These phase changes can be compensated by all pass filter.
• Thus all pass filters as shown in figure 2.11 are also called delay equalizers or phase correctors
Figure 2.11 All pass filter

• From the figure2.10 all pass filter where Rf = R1
• The output voltage vo is obtained by using the superposition theorem
−𝑅𝐹 𝑅𝐹
Vo = Vi + [1 + ]Va eqn 1
𝑅1 𝑅1
Where Va is the voltage at node ‘A’

1
𝑠𝑐 𝑉𝑖
Va = 1 .Vi =
𝑅+ 1+𝑆𝑅𝐶
𝑠𝑐
Since Rf = R1 eqn 1 can be written as
Vo = -Vi + 2 Va
𝑉𝑖
Vo = -Vi + 2
1+𝑆𝑅𝐶
𝑉𝑖 −1−SRC+2
Vo = Vi [-1+ 2 ] = Vi[ ]
1+𝑆𝑅𝐶 1+𝑆𝑅𝐶
1−SRC
VO = Vi [ ] sub,S= j𝜔
1+𝑆𝑅𝐶
1−j𝜔RC
Vo = Vi[ ]
1+𝑗𝜔𝑅𝐶
1−j2𝜋fRC
Vo = Vi[ ]
1+𝑗2𝜋f𝑅𝐶
Vo 1−j2𝜋fRC
=[ ]
Vi 1+𝑗2𝜋f𝑅𝐶
Vo Vo √1+(𝑗2𝜋f𝑅𝐶)2
• The magnitude of is | |=
Vi Vi √1+(𝑗2𝜋f𝑅𝐶)2
• It can be seen that | Vo | = | Vi | throughout the frequency range.

• The phase shift φ between Vo and Vi is given by
2𝜋𝑓𝑅𝐶 2𝜋𝑓𝑅𝐶
Φ = -𝑡𝑎𝑛−1 ( ) - 𝑡𝑎𝑛−1( )
1 1
Φ = -2𝒕𝒂𝒏−𝟏 (𝟐𝝅𝒇𝑹𝑪)
• Φ can be varied with frequency for a given R and C
• Φ can be varied from 0° to 180° as the frequency varied 0 to α
• As Φ is –Ve , Vo lags Vi
• As Φ is +ve, Vo leads Vi
• The Φ can be made +ve by interchanging R&C
• From all pass filter circuit,
➢ if Rf = R1 = 10KΩ R=15.9KΩ f=1KHz C=0.01µF we get Φ= -90°
• The output voltage VO will have same frequency as the input Vi, but Vo lags Vi by 90° as shown in
figure.
2.3 ANALYSIS OF FIRST ORDER LOW PASS BUTTERWORTH ACTIVE FILTER
Figure 2.12 first order low pass filter

• First order filter consists of a single RC network connected to the (+) input terminal of a non-
inverting OP-Amp ampflier.
• The voltage V1 across the capacitor C in the S-domain is
1
𝑠𝑐
V1(S)= 1 .Vi(S)
𝑅+
𝑠𝑐
V1(S) 1
= where V(S) is the Laplace transform of V in time domain
Vi(S) 1+𝑆𝑅𝐶
• The closed loop gain Ao of the OP-Amp is th non-inverting amplifier,
VO (S) 𝑅
AO = = [1+ 𝐹 ]
Vi(S) 𝑅1
• The overall transfer function of the filter is
VO (S) VO (S) VO (S) AO

H(S)= = . = eqn 1
Vi (S) Vi (S) Vi (S) 1+SRC
1 1
Let 𝜔ℎ = then RC=
𝑅𝐶 𝜔ℎ
• This is the standard form of the transfer function of a first order low pass filter.
• To determine the frequency response put S=j 𝜔 in eqn 1
𝐴𝑂 𝐴𝑂
H(jw)= = 𝑊
1+𝑗𝑤𝑅𝐶 1+𝑗( )
𝑊ℎ
𝐴𝑂 1 𝜔
H(jw)= 𝑓 where fh = and f=
1+𝑗( ) 2𝜋𝑅𝐶 2𝜋
𝑓ℎ
𝐴𝑂 𝑓
|H(j𝜔)| = and φ = -𝑡𝑎𝑛−1(𝑓 )
2𝜋√1+(𝑓/𝑓𝐻 )2 𝐻
• The operation of low pass filter can be verified from the gain magnitude equation
❖ At very low frequencies i.e., f<<fH |H(j𝜔)| ≈ AO
𝐴
❖ At f=fH , |H(j𝜔)|= √𝑂 = 0.707 AO
2
❖ At f>>fH , |H(j𝜔)|<<AO (gain decreases at a constant rate of -20 dB/ decade)

FILTER DESIGN [LPF/HPF]
• A low pass filter can be designed by implementing the following
❖ Choose a value of high cut off frequency ‘fH’
❖ Select a value of C less than or equal to 1µF
1
❖ Calculate the value of R using R = 2𝜋𝑓
𝐻𝐶
❖ Finally select the values of R1 and RF dependent on the desired pass band gain AF using AF
𝑅
= 1 + 𝑅𝐹
1
FREQUENCY SCALING [LPF/HPF]

• The procedure used to convert an original cut off frequency fH to a new cut off frequency ‘fH’ is
called frequency scaling.
• Once a filter is designed there may sometimes be a need to change is cutoff frequency.
• Frequency scaling is accomplished as follows:
❖ To change a high cut off frequency fH, multiply R or C but not both by the ratio of the
original cutoff frequency to a new cut off frequency.
❖ Choose a standard value of capacitor and then calculate the value of resistor for a desired
cutoff frequency.this is because for a non-standard value of resistor a potentiometer can
be used
• For nth order butter worth filter the transfer function is
𝐴𝑂
|H(j𝜔)| =
√1+(𝑓/𝑓𝐻 )2𝑛
2.4 FIRST ORDER HIGH PASS BUTTERWORTH ACTIVE FILTER

• The voltage V1 across the resistor ‘R’ in ‘S’ domain is
𝑅 1
V1(S) = 1 = 1
𝑅+ 1+
𝑆𝐶 𝑆𝐶
• The closed loop gain AO of the OP-Amp is i.e., non inverting amplifier
𝑅𝐹 𝑉𝑂 (𝑆)
AO = 1 + =
𝑅1 𝑉1 (𝑆)
• The overall transfer function of the filter is

VO (S) VO (S) VO (S) AO
H(S)= = . = 1 eqn 1
Vi (S) Vi (S) Vi (S) 1+( )
SRC
1 1 1
Let 𝜔𝑙 = then RC= which gives fl = 2𝜋𝑅𝐶
𝑅𝐶 𝜔𝑙
𝐴𝑂 𝑆𝐴𝑂
H(S)= =
ω 𝑆+𝜔𝐿
√1+( l )
S
• To determine frequency response put S=j𝜔 in eqn 1

𝐴𝑂 𝐴𝑂
H(jw)= 𝜔 =
1+(𝑗𝜔𝑙 ) ω
√1+(jωl )2
𝑓
𝐴𝑂 𝑗𝜔𝑅𝐶 𝐴𝑂 𝑗( )
𝑓𝑙
|H(j𝜔)| or H(j𝜔) = = 𝑓
1+𝑗𝜔𝑅𝐶 1+𝑗( )
𝑓𝑙
𝐴𝑂 𝑓
|H(j𝜔)| = and 𝜑= -𝑡𝑎𝑛−1 ( 𝑙)
√1+(𝑓𝑙 /𝑓)2 𝑓
𝑓
𝐴𝑂 ( )
𝑓𝑙
Or |H(j𝜔)|=
√1+(𝑓𝑙 /𝑓)2
• Filter design and frequency scaling are same for high pass and low pass filters.
• The operation of high pass filter can be verified from the gain magnitude equation
❖ At very low frequencies i.e., f<<fl |H(j𝜔)| ≈ 0
𝐴
❖ At f=fl, |H(j𝜔)|= √𝑂 = 0.707 AO
2
❖ At f>>fl , |H(j𝜔)| ≈AO

2.5 WAVEFORM GENERATOR
• Sinusoidal wave generators (Audio frequency oscillators – low frequency 10Hz to 100KHz)
❖ RC phase shift oscillator
❖ Wein bridge oscillator
• Non sinusoidal wave generators
❖ Square wave generator or astable multivibrator
❖ Triangular wave generator
❖ Sawtooth wave generator
2.5.1 SINE WAVE GENERATOR
BASIC PRINCIPLE OF SINE WAVE OSCILLATOR
• An oscillator is basically a feedback amplifier as shown in figure 2.13
Figure 2.13 Basic structure of a feedback oscillator

OPERATION
• When Vi is applied at ‘1’ i.e., input of amplifier, Vo = AVi
• The feedback signal Vf at ‘2’ i.e Vf = A𝛽Vi ➔ Vf = 𝛽Vo
• Here A𝛽 represents loop gain of system
Vf = Vi when A𝛽 = 1
• the output signal can be continuously obtained without any input signal,if we satisfy the condition
on the loop gain i.e.,
CONDITIONS FOR OSCILLATION
❖ |A𝛽| = 1
❖ < 𝐴𝛽 = 0° or 360° or multiple of 2π (phase shift)
• This is called as barkhausen criterion for oscillations.
• The condition A𝛽=1 can be satisified only at one specific frequency ‘fO’
• If |A𝛽| < 1 then Vf decreases and does not produce oscillations.
• So |A𝛽| slightly > 1 for sustained oscillations
RC PHASE SHIFT OSCILLATOR
• The OP-Amp is used in inverting mode and therefore provides 180° phase shift
• The additional 180° provided by RC feedback network
❖ i.e., for each RC network 60°=3x60°=180° phase shift
❖ Therefore total shift = 180° + 180° = 360°
• The feedback factor ‘𝛽’ of the RC network can be calculated by writing KCL equations from
figure 2.14
Figure 2.14 phase shift oscillator
VF
❖ VF = 𝛽VO ➔ 𝛽 =VO
• Apply KCL at node ‘1’,
𝑉1 (𝑆)−𝑉0 (𝑆) 𝑉1 (𝑆)−𝑉0 (𝑆) 𝑉1 (𝑆)−0

1 + 1 + =0
𝑅
𝑆𝐶 𝑆𝐶
[𝑉0 (𝑆)−𝑉2 (𝑆)]𝑆𝐶𝑅

V1(S) = eqn 1
1+2𝑆𝐶𝑅
• Apply KCL at node ‘2’,

𝑉2 (𝑆)−𝑉1 (𝑆) 𝑉2 (𝑆)−𝑉𝐹 (𝑆) 𝑉2 (𝑆)−0
1 + 1 + = 0
𝑅
𝑆𝐶 𝑆𝐶
1
V2(S)[2SC+𝑅] = [𝑉1 (𝑆) + 𝑉𝐹 (𝑆)]SC
1
V2(S)[2SC+ ]−𝑉𝐹 (𝑆)𝑆𝐶
𝑅
V1(S) = 𝑆𝐶
1+2𝑆𝐶𝑅
V1(S) = V2(S)[ ] – VF(S)
𝑆𝐶𝑅
From eqn 1,
[𝑉0 (𝑆)−𝑉2 (𝑆)]𝑆𝐶𝑅 1+2𝑆𝐶𝑅

= V2(S)[ ] – VF(S)
1+2𝑆𝐶𝑅 𝑆𝐶𝑅
• Apply KCL at node ‘3’
𝑉𝐹 (𝑆)−𝑉2 (𝑆) 𝑉𝐹 (𝑆)−0

1 + =0
𝑅
𝑆𝐶
1
𝑉𝐹 (𝑆)[SC+ ] = V2(S)SC
𝑅
1+𝑆𝑅𝐶
∴ 𝑉2 (𝑆) = 𝑉𝐹 (𝑆)[ ] eqn 3
𝑆𝐶𝑅
𝑉𝐹 (𝑆)
Sub eqn 3 in eqn 2 and we get
𝑉𝑂 (𝑆)
𝑉𝐹 (𝑆) 𝑆 3 𝑅3𝐶 3
∴𝛽= = eqn 4
𝑉𝑂 (𝑆) 𝑆 3 𝑅 3 𝐶 3 +6𝑆 2 𝐶 2 𝑅 2 +5𝑆𝑅𝐶+1
1
𝛽= 6 5 1
1+ + +
𝑆𝐶𝑅 𝑆2 𝐶2 𝑅2 𝑆3 𝑅3 𝐶3
Put S=j𝜔,s2 =-𝜔2 , s3 =-𝑗𝜔3

1
𝛽= 6 5 1
1+ − −
𝑗𝜔𝐶𝑅 𝜔2 𝐶2 𝑅2 𝑗𝜔3 𝑅3 𝐶3
1
Substitute , α = 𝜔𝑅𝐶
1
∴ 𝛽= 6 1
1+ 𝛼−5𝛼 2 − 𝑆 3
𝑗 𝑗
1
∴ 𝛽= α eqn 5
(1−5𝛼 2 )2 + (6−𝛼 2 )
𝑗
• For A 𝛽 , 𝛽 should be real that is imaginary term in eqn 5 must be zero.
∴ 𝛼(6 − 𝛼 2 ) = 0 , (6 − 𝛼 2 ) = 0
𝜶𝟐 = 6 thus 𝛼= √6
𝟏 𝟏
= √6 which gives 𝜔=
𝜔𝑅𝐶 𝑅𝐶 √6
𝟏
• The frequency of oscillation fo is fo =
𝟐𝝅𝑹𝑪√𝟔
Sub, 𝛼 2 = 6 in eqn 5 we get
𝟏
𝛽=
−29
• The negative sign indicates that the feedback network produces a phase shift of 180°
1
| 𝛽 | = 29
Since |A 𝛽 | ≥ 1 for sustained oscillations,

Gain |A| ≥ 29
• Thus the gain of the inverting op-amp should be atleast 29. The gain AV should be be kept greater
than 29 .
• For low frequencies ( < 1KHz) op-amp 741 is used.
• For high frequencies LM 318 or LF351 should be used.
WEIN BRIDGE OSCILLATOR

• The feedback signal in this circuit is connected to the non inverting (+)input terminal so that op-
amp is working as non inverting amplifier.(phase shift is 0°)
• Figure 2.15 shows wein bridge oscillator
• The feedback network need not provide any phase shift .
• The circuit can be viewed as a wien bridge with a series RC network in one arm and a parallel RC
network in adjoining arm.
• Resistors R1 and RF are connected in remaining two arms.
• The condition of zero phase shift around the circuit is obtained by balancing the bridge .
Figure 2.15 wein bridge oscillator

• The circuit has been redrawn as shown in figure 2.16 to shown the bridge network. The output ac
signal is feedback to A of the bridge. The feedback signal VF across the parallel combination R2-
C2
is applied to the non inverting input terminal.
Figure 2.16 wein bridge oscillator showing the bridge network

𝑅𝐹
• The gain of the non inverting amplifier is A = 1 + eqn 1
𝑅3
𝑉𝐹 𝑍2
• The feedback factor 𝛽 is 𝛽= = eqn 2
𝑉𝑂 𝑍1 + 𝑍2
1 1+𝑆𝐶1 𝑅1
Where Z1 is R1 + = and
𝑠𝐶1 𝑆𝐶1
1 𝑅2
Z2 is R1 || =
𝑠𝐶1 1+𝑆𝐶2 𝑅2
Sub Z1 and Z2 in eqn 2,we get
𝑅2 ⁄(1 + 𝑅2 𝐶2 𝑆)
𝛽=
1 + 𝑆𝐶1 𝑅1 𝑅2
+
𝑆𝐶1 1 + 𝑆𝐶2 𝑅2
𝑆𝑅2 𝐶1
=
1+𝑆(𝑅1 𝐶1 +𝑅2 𝐶2 +𝑅2 𝐶1 )+ 𝑆 2 𝑅1 𝑅2 𝐶1 𝐶2
S = j𝜔
𝑗𝜔𝑅2 𝐶1
𝛽=
1+𝑗𝜔(𝑅1 𝐶1 +𝑅2 𝐶2 +𝑅2 𝐶1 )−𝜔2 𝑅1 𝑅2 𝐶1 𝐶2
• for 𝛽 to be real ; 1 - 𝜔 2 𝑅1 𝑅2 𝐶1 𝐶2 = 0
𝟏
• Thus the frequency of oscillation, fo =
𝟐𝝅√𝑹𝟏 𝑹𝟐 𝑪𝟏 𝑪𝟐
❖ For R1 = R2= R and C1= C2 =C

1 1
❖ fo = ,𝛽 =
2𝜋𝑅𝐶 3
• Since |A𝛽 | ≥ 1 for sustained oscillations,

Gain |A| ≥ 3
𝑅𝐹
• Since , A = 1 +
𝑅3
𝑅𝐹
3=1+
𝑅3
❖ RF = 2 R3
Drawback
❖ If gain |A|>3,sometimes oscillations keep growing and it may clip the output sinewave.
❖ The problem is eliminated by a practical wien bridge oscillator with adaptive negative
feedback.
Practical wien bridge oscillator wit adaptive negative feedback

Figure 2.17 practical wein bridge oscillator with adaptive negative feedback
• RF is initially adjusted to give a gain so that oscillations start.
• The output signal increases in amplitude until the voltage across R3 approaches the cut in voltage
of the diode.
• As the diode begin to turn on (one for +ve half cycle and other for –ve half cycle),the effective
feedback resistance Rf decreases because the diode is in parallel with the resistance R3.
• This will reduce the gain of the amplifier which in turn lowers the output amplitude. Hence,
sustained oscillations can be obtained.
• Further if the output signal falls the diode would begin to turn off thereby increasing Rf which in
turn increases gain.
2.5.2 SQUARE WAVE GENERATOR (ASTABLE MULTIVIBRATOR)
(Both are quasi stable state)
• Also called as a free running oscillator.
• The principle of generation of square wave output is to force an op-amp to operate in the
saturation region.
Figure 2.18 square wave generator

𝑅2
• From figure 2.18, 𝛽 =
𝑅1 +𝑅2
• VREF = 𝛽VO = ± 𝛽VSAT [∴VO=±VSAT]

• The output ‘Vo’ is also feedback to the – input terminal by means of low pass RC combination
(integrator)
• Whenever input at the – input terminal just exceeds VREF at the + input terminal switching takes
place resulting in a square wave output.
Operation
• Consider Vo = +VSAT , here VREF = + 𝛽VSAT
❖ The capacitor starts charging towards + VSAT through resistor R.
❖ When the voltage at (-) input terminal becomes just greater than this reference voltage ,the
output switches from +VSAT to –VSAT
❖ Voltage across capacitor,VC = +𝛽 VSAT
• Now VO = - VSAT, here VREF = - 𝛽VSAT
❖ The capacitor starts charging towards + VSAT through resistor R.
❖ When the voltage at (-) input terminal becomes just greater than this reference voltage ,the
output switches from–VSAT to +VSAT
❖ Voltage across capacitor,VC = - 𝛽 VSAT
• The cycle repeats itself.
Expression for frequency of oscillation
• The frequency is determined by the time it takes the capacitor to charge from - 𝛽 VSAT to +𝛽 VSAT
and vice-versa.
• The voltage across the capacitor as a function of time is given by
VC(t) = Vf + (Vi - Vf)𝑒 −𝑡⁄𝑅𝐶
Where the final value, Vf = +VSAT and intial value , Vi = - 𝛽 VSAT
∴ Vc(t) = VSAT + (-𝛽 VSAT - VSAT) 𝑒 −𝑡⁄𝑅𝐶
Vc(t) = VSAT -VSAT(1+ 𝛽) 𝑒 −𝑡⁄𝑅𝐶

• At t= T1 , VC reaches 𝛽VSAT and switching takes place. Therefore ,
VC(T1) = 𝛽VSAT = VSAT -VSAT(1+ 𝛽) 𝑒 −𝑇1⁄𝑅𝐶

• After algebraic manipulation we get
1+𝛽
T1 = RC ln 1−𝛽
This gives only one half of th period.
• Total time period
1+𝛽
T1 = 2 T1 = 2RC ln 1−𝛽
and the output waveform is symmetrical.

𝑅2
• If R1 =R2 then 𝛽 = = 0.5 and T=2RC ln 3.And for R1 = 1.16R2 it can be seen that T=2RC
𝑅1 +𝑅2
Frequency of oscillation fO = 1/2RC

• the output swings from +VSAT to –VSAT .so
Vo peak to peak = 2VSAT

Use of back to back zener diodes
• the peak to peak output amplitude can be varied by varying the power supply voltage. Better
technique is to use back to back zener diode as shown in figure 2.19
• The output voltage is regulated to ± (VZ + VD) by the zener diodes.
Vo peak to peak = 2(VZ + VD)
Figure 2.19 use of back to back zener diodes

• Resistors RSC limits the currents drawn from the op-amp to
𝑉𝑆𝐴𝑇− 𝑉𝑍
ISC = RSC
❖ It works well at audio frequencies. at higher frequencies the slew rate of the op-amp limits
the slope of the output square wave.
• If an asymmetric square wave is desired then zener diodes with different break down voltages VZ1
and VZ2 may be used.
• The output is either VO1 or VO2 where Vo1 = VZ1 + VD and Vo2 = VZ2 + VD
1+𝛽𝑉𝑜2 ⁄𝑉𝑜1
T1 = RC ln
1−𝛽
• Alternative method to get asymmetric square wae is to add dc voltage source V in series with
R2.capacitor swings between (𝛽VSAT + V) and (−𝛽VSAT + V)
MONOSTABLE MULTIVIBRATOR
• Monostable multivibrator has one stable state and the other is quasi stable state.It is also called as
one shot mulivibrator.
• This circuit requires triggering, as the output stays in stable state until triggering pulse is applied.
• This circuit is used to generate rectangular pulse or delayed pulses or gating pulses.
• The width of the output pulse depends nly on external components connected to the op-amp.
• The monostable multivibrator is a modified form of astable multivibrator and is shown in figure
as shown in figure 2.20
Figure 2.20 (a) Monostable mulivibrator

• A diode D1 clamps the capacitor voltage to 0.7 V when the output is at +VSAT
• A negative going pulse signal of magnitude V1 passing through the differentiator R4C4 (spikes)
and diode D2 produces a negative going triggering impulse.
Operation
• Assume in stable state , VO = +VSAT
❖ Diode D1 conducts and VC the Vc the voltage across the capacitor C gets clamped to + 0.7
V
❖ The voltage at the (+) input terminal through R1R2 potentiometeric divider is + 𝛽VSAT.
❖ Now if a negative trigger of magnitude V1 is applied to the (+) input terminal so that the
effective signal at this terminal is less than VC that is 0.7 V. the output of the op-amp will
switch from +VSAT to -VSAT.
❖ Here the output is VO = - VSAT
• The diode D1 is reverse biased and the capacitor starts charging exponentially to -VSAT through the
resistor ‘R’
❖ The voltage at (+) input terminal is now - 𝛽VSAT
❖ When the capacitor voltage VC becomes just slightly more negative than - 𝛽VSAT the
output of the op-amp switches back to +VSAT
• Then D1 conducts and the capacitor ‘c’ now starts charging to +VSAT through R until VC = 0.7V
as ‘C’ gets clamped to the voltage.
• The output waveforms are shown in figure 2.20
Figure 2.21 (b)-ve going triggering signal (c)capacitor waveform (d)output voltage waveform
Expression for pulse width ‘T’

• For a single time constant low pass RC circuit with Vi and Vf as initial and final values is,
VC = VF + (Vi - Vf)𝑒 −𝑡⁄𝑅𝐶
Where the final value, Vf = -VSAT and intial value , Vi = VD
∴ Vc = -VSAT + (VD + VSAT) 𝑒 −𝑡⁄𝑅𝐶

• At t= T, VC = - 𝛽VSAT
∴ 𝛽VSAT = -VSAT + (VD + VSAT) 𝑒 −𝑇⁄𝑅𝐶

• After simplification pulse width T is obtained as
(1+𝑉𝐷 ⁄𝑉𝑠𝑎𝑡)
T = RC ln 1−𝛽
𝑅2
Where 𝛽 =
𝑅1 +𝑅2
• If ,VSAT >> VD and R1 = R2 so that 𝛽= 0.5,then
T = 0.69 RC
2.5.3 TRIANGULAR WAVE GENERATOR
• A triangular wave (rise time = fall time) can be simply obtained by integrating a square wave as
shown in figure a
• The frequency of the square wave and the triangular wave is the same as shown in figure 2.22.
Figure 2.22 triangular waveform generator

• Although the amplitude of the square wave is constant at ±VSAT, amplitude of the triangular wave
will decrease as the frequency increases.
• Another triangular wave generator using lesser number of components is shown in figure 2.23
Figure 2.23 triangular waveform generator using lesser components

• The output of the comparator A1 is a square wave of amplitude ±VSAT and is applied to the (-)
input terminal of the integrator A2 producing a triangular wave.
• This triangular wave is fedback as input to the comparator A1 through a voltage divider R2R3.
Operation
• Let us consider, the output of comparator A1 is at +VSAT
• Output of integrator A2 is at –Vramp (negative going ramp)
• Thus one end of voltage divider R2R3 is at a voltage +VSAT and other at the negative going ramp
of A2
• At the time t=T1,when the negative going ramp attains a value of –VRAMP the effective voltage at
point ‘P’ becomes slightly less than 0 V
• Thus the output of A1 switches from +VSAT to –VSAT
• At the time t=T2 the voltage at point ‘P’ becomes just above 0 V thus output of A1 switches from
–VSAT to +VSAT
• The cycle repeats and generates a triangular waveform.
• Amplitude of triangular wave depends upon RC value of the integrator A2 and the output voltage
level of A1
• The frequency of square wave and triangular wave will be same
Expression for the frequency of triangular waveform
• Let us consider initially output of A1 is +VSAT and output of A2 is -VRAMP
• The effective voltage at point ‘P’ during the time when output of ‘A1’ is at +VSAT level is given
by,
𝑅2
VP = -VRAMP + [+VSAT –(-VRAMP)]
𝑅2 +𝑅3
• At t=t1, the voltage at point ‘P’ becomes equal to zero i.e., VP = 0

𝑅2
∴ - VRAMP + 𝑅 [+VSAT –(-VRAMP)] = 0
2 +𝑅3
𝑅2 𝑅2
- VRAMP [1- ] = +VSAT [- ]
𝑅2 +𝑅3 𝑅2 +𝑅3
𝑅2
∴ - VRAMP = - (+VSAT )
𝑅3
• Similarly at t=t2 , when the output of A1 switches from - VSAT to +VSAT

𝑅2 𝑅
∴ + VRAMP = - (- VSAT ) = 𝑅2 (VSAT)
𝑅3 3
• Therefore peak to peak amplitude of the triangular wave is

𝑅2
Vop.p = +VRAMP – (-VRAMP ) = 2 VSAT eqn 1
𝑅3
• The output switches from -VRAMP to + VRAMP in half the time period T/2.
❖ From basic integrator equation,
1
VO = -
𝑅𝐶
∫ 𝑉𝑖 . 𝑑𝑡
1 𝑇/2 𝑉
Vop.p = - ∫0 −𝑉𝑆𝐴𝑇 . 𝑑𝑡 = 𝑅𝑆𝐴𝑇 X [T/2]
𝑅1 𝐶1 𝐶 1 1
𝑉𝑜𝑝.𝑝
∴ T = 2𝑅1 𝐶1 eqn 2
𝑉𝑆𝐴𝑇
Sub eqn 1 in eqn 2 we get,

𝟒 𝑹𝟏 𝑪𝟏 𝑹𝟐
T= 𝑹𝟑
• Hence the frequency of oscillation fo is,

1 𝑹𝟑
fo = 𝑇 = 𝟒 𝑹𝟏 𝑪𝟏 𝑹𝟐
2.5.4 SAW TOOTH WAVE GENERATOR

• The sawtooth waveform can also be generated by an asymmetrical astable multivibrator followed
by an integrator.
• The difference between the triangular wave and sawtooth waveform is that the rise time of
triangular wave is always equal to its fall time while in sawtooth generator rise time > fall time or
fall time > rise time
• The triangular wave generator can be converted into a sawtooth wave generator by connecting a
variable dc voltage into the non inverting terminal of the integrator
• In this circuit a potentiometer is used (47 KΩ) .
• potentiometer is used when
❖ the wiper moves towards –V,the rise time become longer than fall time
❖ the wiper moves towards +V , the fall time become more than rise time
2.6 IC 555 TIMER
Introduction
• The 555 timer is a highly stable device for generating accurate time delay or oscillation
• Timer IC is available in two package styles , 8 pin circular style,TO-99 can or 8-pin mini DIP or
as 14-pin DIP.
• Single 555 timer can provide time delay ranging from microseconds to hours whereas counter
timer can have a maximum timing range of days.
• The 555 timer can be used with supply voltage in the range of +5V to +18V and can drive load
upto 200mA
• It is compatible with both TTL and CMOS logic circuits.
Features of 555 Timer
• High temperature stability
• Time delay ranging from microseconds to hours
• Supply voltage range is + 5 to +18 V and IL = 200 mA
• Output is compatible with CMOS,DTL & TTL families
• Duty cycle is adjustable
• Monostable and astable operations
Applications
• Because of wide range of supply voltage the 555 timer is versatile and easy to use in various
applications.
• Various applications include oscillator, pulse generator, ramp generator and square wave
generator, mono-shot multivibrator , burglar alarm ,traffic light control and voltage monitor .
8 pin DIP 555 timer
Figure 2.23 pin diagram of IC 555 timer
2.6.1 FUNCTIONAL DIAGRAM OF 555 TIMER

Figure 2.24 functional diagram of 555 timer
• From the figure 2.24 three 5 KΩ internal resistors act as voltage divider providing bias voltage of
(2/3)VCC to the upper comparator and (1/3)VCC to the lower comparator where VCC is supply
voltage.
• At pin 5 i.e., control voltage input terminal we can apply a modulation voltage to vary time
interval
• In applications where no such modulation is required it is recommened by the manufactures that a
capacitor (0.01 µF) be connected between control voltage terminal (pin 5) and a ground (pin 1) to
by pass noise or ripple from the supply.
Operation
• In the steady stable state the output 𝑄̅ of the control FF is HIGH. This makes the output LOW
(0) because of power amplifier which is basically an inverter and 𝑄1 (discharge transistor) is ON.
• A negative going trigger pulse is applied to pin2 and should have its dc level greater than the
threshold level of the lower comparator (VCC/3).
• At the negative going edge of the trigger as the trigger passes through (V CC/3),the output of the
lower comparator goes HIGH and sets the FF i.e S =1 & R=0 . Therefore Q=1 & 𝑄̅ = 0 and the
output is HIGH and Q1 is OFF
• During the positive excursion when the threshold voltage at pin 6 passes through (2/3)Vcc , the
output of the UC goes HIGH and resets the FF (S= 0 & R=1).Therefore
Q=0 & 𝑄̅ = 1 and the output is LOW and Q1 is ON.

• Here transistor Q2 serves as buffer to isolate the reset input from the FF and transistor Q1.The
transistor Q2 is driven by an internal reference voltage VREF obtained from supply voltage VCC
2.6.2 MONOSTABLE OPERATION
• In the stable state Q1 is ON thus clamping the external timing capacitor C to ground.
• The output is LOW
• Figure 2.25 shows monostable multivibrator
Figure 2.25 monostable multivibrator

• As shown in figure 2.26 trigger input passes through VCC/3, the LC sets flip flop (S = 1, R=0
&Q=1 , 𝑄̅ =0)
• As 𝑄̅ is LOW ,output is high and Q1 is OFF
• As Q1 is OFF ,‘C’ is unclamped i.e it starts charging and the voltage across it rises exponentially
through ‘R’ towards VCC with a time constant RC
• After the time period ‘T’ the capacitor voltage is just greater than 2/3 VCC i.e ., VC > 2/3 VCC then
UC resets the flipflop i.e., S=0 ,R=1 & Q=0 , 𝑄̅ =1
• As 𝑄̅ is HIGH ,output is LOW and Q1 is ON
• As Q1 is ON ,’C’ starts discharging towards ground rapidly
• The output is low (it returns to the steady state)
Figure 2.26 timer in monostable operation with functional diagram

• The voltage across the capacitor is given by
Vc = VCC (1- 𝑒 −𝑡⁄𝑅𝐶 )
At t = T, VC = 2/3VCC
∴ 2/3 VCC = VCC (1- 𝑒 −𝑡⁄𝑅𝐶 )
T=1.1 RC (seconds) {T changes wrt to R&C}

• If once triggered output remains in HIGH state until T elapse it depends upon R &C
• Any additional trigger pulse during this time interval (T) willnot change the output state
• But if a negative going reset pulse is applied to reset pin 4 then Q2 is OFF & Q1 is ON and the
external timing capacitor C is immediately discharged and output is LOW
• Even if the reset released the output will remain LOW until a negative going trigger pulse is
applied at pin2
• Timing pulses are shown in figure 2.27
Figure 2.27 timing pulses

2.6.2.1 APPLICATIONS OF MONOSTABLE MODE
• Missing pulse detector
❖ When trigger input is low the emitter diode of transistor Q is forward biased.
Q= ON ∴ VBE(ON) = 0.7 V thus capacitor is clamped to 0.7V and o/p is HIGH.

❖ The circuit is designed so that ‘T’ time period of monostable circuit is slightly greater than
(1/3longer) that of the trigger pulses.
❖ As longs as trigger pulse train keeps coming at pin2,the output remains HIGH.
❖ If the pulse misses, the trigger input is high and transistor Q is OFF. The 555 timer enters
into normal state of operation shown in figure 2.28.
Applications
➢ Used to detect missing heart beat
➢ Speed control and measurement
Figure 2.28 A missing pulse detector

• Linear ramp generator
❖ The resistor R of the monostable circuit is replaced by a constant current source as shown
in figure 2.29. The capacitor is charged linearly by the constant current source formed by
the transistor Q3.
❖ The capacitor voltage VC can be written as,
𝟏 𝒕
VC = 𝑪 ∫𝟎 𝒊. 𝒅𝒕 eqn 1
Where i is the current supplied by the constant current source.

❖ The KVL equation can be written as,
𝑅1
VCC =𝐼𝐸 𝑅𝐸 + 𝑉𝐵𝐸
𝑅1 +𝑅2
= (1+𝛽)𝐼𝐵 𝑅𝐸 + 𝑉𝐵𝐸
𝑅1
VCC-VBE = 𝛽𝐼𝐵 𝑅𝐸 = 𝐼𝐶 𝑅𝐸 = i.𝑅𝐸
𝑅1 +𝑅2
𝑅1 𝑉𝐶𝐶 −𝑉𝐵𝐸 (𝑅1 +𝑅2 )

i= (𝑅1 +𝑅2 )𝑅𝐸
eqn 2
sub eqn 2 in eqn 1,
1 𝑡 𝑅1 𝑉𝐶𝐶 −𝑉𝐵𝐸 (𝑅1 +𝑅2 )

∴ VC = 𝐶 ∫0 [ (𝑅1 +𝑅2 )𝑅𝐸
]. 𝑑𝑡

= xt
𝐶 (𝑅1 +𝑅2 )𝑅𝐸
❖ At time t= T, the voltage across capacitor VC =2/3 VCC

2/3 VCC = xT
𝐶 (𝑅1 +𝑅2 )𝑅𝐸
❖ The time period of the linear ramp generator is

2
𝑉 (𝑅1 +𝑅2 )𝑅𝐸 𝐶
3 𝐶𝐶
T =
❖ When VC >2/3 VCC the capacitor discharges to GND

❖ The capacitor voltage remains zero till another trigger input is applied as shown in figure
2.31.
Figure 2.29 linear ramp generator


• Frequency divider
❖ A continuously triggered monostable circuit when triggered by a square wave generator
can be used as a frequency divider, if the timing interval is adjusted to be longer than the
period of the triggering square wave input signal
❖ The monostable multivibrator will be triggered by the first negative going edge of the
square wave input but the output will remain high for the next negative going edge of the
input square wave.
❖ The mono-shot will be triggered on the third negative going input, depending on the
choice of the time delay.
❖ In this way, the output can be made integral fractions of the frequency square wave as
shown in figure 2.31.

• Pulse width modulator
❖ This is a monostable multivibrator with a modulating input signal applied at pin 5 and
trigger at pin 2 a series of output pulses are applied.
❖ The modulating signal applied at pin 5 gets superimposed upon the already existing
voltage (2/3)VCC at the inverting input terminal of UC.
❖ This in turn changes the threshold level of UC and the output pulse width modulation
takes place.
❖ From the waveform 2.32,pulse duration (duty cycle) varies, keeping the frequency same as
that of the continuous input pulse train trigger.
Figure 2.32 pulse width modulator

2.6.3ASTABLE OPERATION
• The timing resistor is now split into two sections RA and RB as shown in figure 2.33.
• Pin 7 of discharging transitor Q1 is connected to the junction of RA and RB
• When the power supply VCC is connected the external timing capacitor C charges towards VCC
through RA &RB,with a time constant (RA +RB)C
• During this time ,Capacitor charges and o/p is high as R=0 &S=1 .The LC sets the flipflop
&Q=1, 𝑄̅ =0. Thus Q1 is OFF.
Figure 2.33 astable multivibrator

During charging
❖ When the capacitor voltage equals or just greater than 2/3 VCC then UC triggers the control flip
flop,(R=1 ,S=0 ,Q= 0, 𝑄̅ = 1).Thus Q1 is ON & output is low.
❖ As Q1 is ON, the capacitor C starts discharging towards ground through RB with a time constant
RBC
During discharging
❖ When the capacitor voltage equals or just less than 1/3 VCC then LC triggers the control flip
flop,(R=0 ,S=1 ,Q= 1, 𝑄̅ = 0).Thus Q1 is OFF & output is HIGH.
❖ As Q1 is OFF, the capacitor C starts charging & the cycle repeats
❖ The capacitor is periodically charged and discharged between 2/3 VCC & 1/3 VCC respectively.
• The length of time that the o/p remains HIGH is the time for the capacitor to charge from 1/3 VCC
to 2/3 VCC .
• It can be calculated as follows : the capacitor voltage for a low pass RC circuit subjected to a step
input of VCC volts is given by,
VC = VCC (1- 𝑒 −𝑡1⁄𝑅𝐶 )

• The time t1 taken by the circuit to charge from 0 to 2/3 VCC is
2/3 VCC = VCC (1- 𝑒 −𝑡1⁄𝑅𝐶 )
t1= 1.09 RC
• The time t1 taken by the circuit to charge from 0 to 1/3 VCC is
1/3 VCC = VCC (1- 𝑒 −𝑡2⁄𝑅𝐶 )
t1= 0.405 RC
• So the time to charge from 1/3 VCC to 2/3 VCC is
t HIGH = t1 – t2 = 0.69 RC
• So for the given circuit, THIGH = 0.69 (RA+RB)C

• The o/p is low while the capacitor discharges from 2/3 VCC to 1/3 VCC
• The voltage across the capacitor is given by
1/3VCC = 2/3 VCC𝑒 −𝑡⁄𝑅𝐶
On solving we get, tLOW = 0.69 RC

• For the given circuit, TLOW = 0.69 RBC
• Total time, T =TLOW +THIGH
T = 0.69 (RA+2RB)C
1.45
• f = 1/T =
(𝑅𝐴 +2𝑅𝐵 ).𝐶
• The duty cycle D of a circuit is defined as the ratio of ON time to total time period
• In this circuit, when the transistor Q1 is ON ,o/p goes low.
𝑇𝐿𝑂𝑊 𝐵𝑅
Here, D% = 𝑋 100 = (𝑅 +2𝑅 x 100
𝑇 𝐴 𝐵)
• To have symmetrical square wave D= 50%

• Figure 2.34 shows the timing sequence of astable multivibrator
Figure 2.34 timing sequence of astable multivibrator

2.6.3.1APPLICATIONS IN ASTABLE MODE
• FSK Generator
❖ In digital data communication,binary code is transmitted by shifting a carrier
frequencybetween two preset frequencies. This type of transmission is called as frequency
shift keying (FSK) technique as shown in figure 2.35.
Figure 2.35 FSK generator

❖ In a teletype writer using a modulator-demodulator (MODEM) a frequency between 1070
Hz to 1270 Hz is used as one of the standard FSK signal.
❖ The standard digital data input frequency is 150 Hz.
❖ When the input is high,transistor Q is OFF and 555 timer works in normal astable mode of
operation. The frequency of the o/p waveform is,
1.45
fO=
(𝑅𝐴 +2𝑅𝐵 ).𝐶
❖ The components RA and RB and C can be selected so that fo is 1070 Hz.

❖ When the input is LOW ,Q goes on and connects the resistance RC across RA. the output
1.45
frequency is given by
(𝑅𝐴 ||𝑅𝐶 )+2𝑅𝐵
❖ The resistance RC can be adjusted to get an output frequency 1270 Hz.

• PPM
❖ The PPM as shown in figure 2.36 can be constructed by applying a modulating signal to
pin 5 of a 555 timer connected for astable operation.
❖ The o/p pulse position varies with the modulating signal since the threshold voltage and
hence the time delay is varied.
Figure 2.36 Pulse position modulator

❖ The waveforms shows the o/p waveform generated for a triangular wave modulation
signal. From the o/p waveform the frequency is varying leading to pulse position
modulation.
❖ The typical practical component values:
RA = 3.9 KΩ,RB = 3 KΩ, C=0.01µF & VCC =5 V

• Schmitt trigger using 555 timer
❖ The use of 555 timer as a Schmitt trigger is shown in figure 2.37
Figure 2.37 timer in schmitt trigger operation

❖ Here the two internal components are tied together and externally biased at VCC/2 through
R1 and R2
❖ Since the upper comparator will trip at 2/3 VCC and the lower comparator will trip at 1/3
VCC ,the bias provided by R1 & R2 is centered within these two thresholds [i.e VCC/2]
❖ Thus a sine wave of sufficient amplitude (> VCC/6 = 2/3 VCC – VCC/2) to exceed the
reference levels causes the internal flip flop to alternately set and reset, providing a square
wave output as shown below in figure 2.38
Figure 2.38 input output waveforms of Schmitt trigger

❖ The frequency of the output square wave remains the same as that of the input sine signal.
2.7 PHASE LOCKED LOOP
Introduction
• The phase locked loop (PLL) is an important building block of linear systems.It came into
existence in 1930’s
• PLLs are available as inexpensive monolithic IC’s
• PLL is a technique for electronic frequency control
• Applications include satellite communication systems, air borne navigational systems, FM
communication systems, computers etc.,
2.7.1 BLOCK SCHEMATIC OF PLL
• The basic block schematic of PLL figure 2.39,which is a feedback system consists of
❖ Phase detector / comparator
❖ A low pass filter
❖ An error amplifier
❖ A voltage controlled oscillator (VCO)
Figure 2.39 Block schematic of the PLL

• The VCO is a free running multivibrator and operates at a set of frequency fO called as free
running frequency. This fO is determined by an external timing capacitor and an external resistor .
• The ‘fO’ can also be shifted to either side by applying a dc control voltage ‘vC’. The frequency
deviation is directly proportional to the dc control voltage and hence it is called as “voltage
controlled oscillator” or VCO
• If an input signal ‘VS’ of frequency ‘fS’ is applied to the PLL,the phase detector compares the
phase and frequency of the incoming signal to that of the output ‘VO’ of frequency ‘fO’ of the
VCO
• If the two signals differ in frequency and /or phase,an error voltage VC is generated
• The phase detector is basically a multiplier and produces the sum (fS + fO) and difference (fS -fO)
components at its output .ie., (fS ± fO)
• The high frequency component (fS ± fO) is removed by the lowpass filter and the difference
frequency component ie., (fS -fO) is amplified by error amplifier and then applied as control
voltage VC to vco
• The signal VC shifts the VCO frequency in a direction to reduce the frequency difference between
fS and fO
• Once this action starts, we say that the signal is in the capture range
• The VCO continues to change frequency till its output frequency ‘fO’ is exactly the same as the
input signal frequency ‘fS’ i.e fS = fO . The circuit is then said to be locked.
• Once locked, the o/p frequency ‘fO’ of VCO is identical to ‘fS’ except for a finite phase difference
φ .This phase difference φ generates a corrective control voltage VC to shift the VCO frequency
form ‘fO’ to ‘fS’ and thereby maintain the lock.
• Once locked,PLL tracks the frequency changes of the i/p signal
• Thus ,a PLL goes through three stages figure 2.40
❖ Free running
❖ Capture
❖ Locked or tracking
Figure 2.40 the capture transient

• From figure,as capture starts,a small sine wave appears.This is due to the difference frequency
between the VCO and the i/p signal. The dc component of the beat drives the VCO towards the
lock.
• The low pass filter controls the capture range,if difference between ‘fS’ & ‘fO’ is very high it
attenuates and PLL will not respond.
• If fS = fO ,PLL is locked,LPF allows the frequency and VCO can track the signal even beyond the
capture band.
• Thus ,tracking range is always larger than the capture range.
Some of the important definitions in relation to PLL
Lock in Range: Once the PLL is locked, it can track the frequency changes in the incoming signals.
The range of frequencies over which the PLL can maintain lock with the incoming signal is called the
lock I range or tracking range. The lock range is usually expressed as a percentage of f O, the VCO
frequency.
Capture Range: The range of frequencies over which the PLL can acquire lock with an input signal
is called the capture range. This parameter is also expressed as a percentage of ‘fO’.
Pull in time: The total time taken by the PLL to establish lock is called pull in time. This depends on
the initial phase and frequency difference between the two signals as well as on the overall loop gain
and loop filter characteristics.
2.7.2 DESCRIPTION OF INDIVIDUAL BLOCKS

Phase Detector /comparator
• The phase detection is the important part of PLL system.There are two types of phase detectors.
❖ Analog phase detector
❖ Digital phase detector
Analog phase detector /half wave detectors
• The principle of analog phase detection using switch type phase detector is shown in figure 2.41
• An electronic switch ‘S’ is opened and closed by signal coming from VCO (normally a square
wave)
Figure 2.41 basic scheme of PLL

• The i/p signal is therefore chopped at a repetition rate determined by VCO frequency.
• Since,the switch ‘S’ is closed only when VCO o/p is positive,the o/p waveform V F will be half
sinusoids(shown hatched) .This typre of phase detector is called as half wave detector ; since the
phase information for only one half of the output waveform is detected and averaged.
• The o/p of the phase comparator when filtered through a LPF gives an error signal which is the
average value of the o/p waveform shown by the dotted line as shown in figure 2.42
• When the error voltage is zero,when the phase shift between the two i/p’s (fS & fO) is 90°. So,for
perfect lock,the VCO o/p should be 90° out of phase with respect to the i/p signal. [Ve =0 when φ
= 90°]
Figure 2.42 VCO output waveforms

Analysis
• A phase comparator is basically a multiplier which multiplies the i/p signals by the VCO signal
i/p signal VS = VS sin 2 𝜋𝑓𝑆 𝑡
VCO signal VO = VO sin(2𝜋𝑓𝑂 𝑡 + 𝜑)

• Thus the phase comparator o/p is,
Ve = K VS .VO sin(2𝜋𝑓𝐶 𝑡) sin(2𝜋𝑓𝑂 𝑡 + 𝜑)
Where, K = phase comparator gain (attenuation constant)
𝜑 = phase shift between the input signal and the VCO output
𝐾 𝑉𝑆 𝑉𝑂
∴ Ve = [cos(2𝜋𝑓𝑆 𝑡 − 2𝜋𝑓𝑜 𝑡 − 𝜑) − cos(2𝜋𝑓𝑆 𝑡 + 2𝜋𝑓𝑂 𝑡 + 𝜑)]
2
When PLL is locked,fS=fO

Then ,Ve = [cos(−𝜑) − cos(4𝜋𝑓𝑂 𝑡 + 𝜑)]
2
• The phase comparator o/p contains a double frequency term and a dc term which varies as a
function of phase φ i.e., cos φ between the two signals.
• The double frequency term can be eliminated by the low pass filter and the dc signal is amplified
and applied to the modulating input terminal of a VCO
• When PLL is in perfect locked state & the phase shift φ =90°, Ve =0
Ve = cos 𝜑 at φ =90° ,Ve = 0
2
Drawbacks
• The o/p Ve is proportional to the i/p signal amplitude VS.This is undesirable since it makes phase
detector gain and the loop gain dependent on the i/p signal amplitude.
• The o/p voltage is proportional to cos φ and not proportional to φ,making it non linear
• Both of these problems can be eliminated by limiting the amplitude of the i/p signal
,i.e.,converting the i/p to a constant amplitude square wave.
Balanced modulator / Full wave switching phase detector
• In balanced modulator, the input to the phase detector is a square wave & the VCO output is also
a square wave.
• The input signal is applied to the differential pair Q1Q2
• Transistors Q3-Q4 and Q5 –Q6 are two sets of SPDT switches activated by the VCO output as
shown in figure 2.43
• The input signal V3 and the VCO output VO are assumed to be high to switch the transistors fully
ON/OFF
• When VS and VO are both high during the time 0 to (π-φ),
Transistors Q1 is ON & Q3 is ON & Q6 is ON and current IE flows through Q1 & Q3
output voltage VE = -𝑰𝑬 𝑹𝑳

• Next for the period (π-φ) for π,when VS is high and VO is low,
Transistors Q1 is ON & Q4 is ON & Q5 is ON and IE flows through Q1 & Q4
Output voltage VE = 𝑰𝑬 𝑹𝑳.

• The average value of the phase detector output VE can be calculated as,
1
(VE)AV = [(𝑎𝑟𝑒𝑎 𝐴1 ) + (𝑎𝑟𝑒𝑎 𝐴2 )]
𝜋
1
= [IE R L 𝜑 + (−IE R L ) x (π − φ)]
𝜋
2𝜑
= 𝐼𝐸 𝑅𝐿 ( − 1)
𝜋
𝐼𝑄 𝑅𝐿 𝜋
= (𝜑 − )
𝜋 2
𝜋
(VE)AV = 𝐾𝜑 (𝜑 − )
2
• Where Kφ is the phase angle to voltage transfer co-efficient or conversion ratio of the phase
detector.
0.7−(−0.7) 1.4
Kφ = =
𝜋 𝜋
Figure 2.43 ouput dc voltage versus input phase difference of balanced modulator FW switching
phase detector
Digital phase detector
• The figure 2.44 shows the digital type XOR (Exclusive-OR)phase detector.It uses CMOS type
4070 Quad 2 input XOR gate.
Figure 2.44 phase detector

• The output of the XOR gate is high when only one of the input signals fS or fO is high.
• This type of detectors is used when both the input signals are square waves.
• The input and output waveforms for fo = fS is shown in figure
• In this figure fO is leading fO by φ degrees.
• The variation of dc output voltage with phase difference φ is shown in figure
• The maximum dc output voltage occurs when the phase difference is π because the output of the
gate remains high throughout
• The slope of the curve gives the conversion ration Kφ for a supply VCC = 5V is,
5
Kφ = 𝜋 = 1.59 V/rad
• Another type of digital phase detector is an edge triggered phase detector

• It is an R-S flip flop made by NOR gates.
• The circuit is useful when fS (incoming signal) and fO (VCO output) are with duty cycle less than
50%
• Output of R-S flip flop changes its state on the leading edge of fS and fO
• Variation of dc output voltage vs phase difference between fS and fO is shown in figure 2.45
Figure 2.45 DC ouput voltage versus phase difference curve

• This type of detector has better capture tracking and locking characteristics
Figure 2.46 Edge triggered phase detector

Voltage controlled oscillator
• A common type of VCO available in IC form is signetics NE/SE566.
• The pin configuration and block diagram of 565 VCO is shown in figure 2.47
Figure 2.47 voltage controlled oscillator

• Timing capacitor CT is linearly charged or discharged by a constant current source/sink.
• Amount of current can be controlled by changing the voltage VC applied at the modulating input
or by changing the timing resistor RT.
• Voltage at pin 5 is equal to pin 6
• If modulating voltage at pin 5 is increased ,the voltage at pin 6 increases, resulting in less voltage
across RT and thereby decreasing the charging current.
• A small capacitor of 0.001 µF connected between pin 5 and 6 to eliminate possible oscillations.
• A VCO is commonly used in converting low frequency into an audio frequency range.
• Voltage across CT is applied to the inverting input terminal of Schmitt trigger A2 via buffer
amplifier A1.
• Voltage swing is designed to VCC and 0.5 VCC
• If Ra= Rb ,the voltage at the non inverting input terminal of A2 swings from 0.5 VCC to 0.25 VCC .
• When the voltage on CT exceeds 0.5 VCC during charging, output of Schmitt trigger goes LOW
(0.5 VCC).
• Since the source and sink are equal, capacitor charges and discharges for the same amount of
time.
• This gives a triangular voltage waveform across CT at pin 4
• The square wave output is inverted by inverter A3 and is available at pin 3.
• Output waveform is calculated as follows 2.48
Figure 2.48 output waveform

• Total voltage on the capacitor changes from 0.25 VCC to 0.5 VCC. Thus ∆v=0.25 VCC.
The capacitor charges with constant current source.
∆𝑉 𝑖
So, =𝐶
∆𝑡 𝑇
𝟎.𝟐𝟓 𝑽𝑪𝑪 𝒊
=
∆𝒕 𝑪𝑻
𝟎.𝟐𝟓 𝑽𝑪𝑪 𝑪𝑻
∆𝒕 = 𝒊
• The time period T of the triangular waveform =2 ∆𝒕 . The frequency of oscillator fO is ,
1
f O=
𝑇
1 𝑖
= =
2∆𝑡 0.5 𝑉𝐶𝐶 𝐶𝑇
𝑉𝐶𝐶 −𝑉𝐶
i=
𝑅𝑇
VC is the voltage at pin 5 .
2(𝑉𝐶𝐶 −𝑉𝐶 )
∴ fO = 𝐶𝑇 𝑅𝑇 𝑉𝐶𝐶
• The output frequency of the VCO can be changed either by RT and CT or the voltage VC.
• VC can be varied by connecting a R1R2 circuit.
• RT and CT are first selected so that VCO output frequency lies in the centre of the operating
frequency range.
• Output VCO frequency is
2(𝑉𝐶𝐶 −(7/8)𝑉𝐶𝐶 ) 0.25

fO = =𝑅
𝐶𝑇 𝑅𝑇 𝑉𝐶𝐶 𝑇 𝐶𝑇
Voltage to frequency conversation factor

• Voltage to frequency conversation factor KV,
∆𝑓𝑂
KV = ∆𝑉𝑐
∆𝒇𝑶 =𝒇𝟏 − 𝒇𝒐
2(𝑉𝐶𝐶 −𝑉𝐶 +∆𝑉𝑐 ) 2(𝑉𝐶𝐶 −𝑉𝐶 )
= -
𝐶𝑇 𝑅𝑇 𝑉𝐶𝐶 𝐶𝑇 𝑅𝑇 𝑉𝐶𝐶
2∆𝑉𝐶
=𝐶
𝑇 𝑅𝑇 𝑉𝐶𝐶
∆𝑓𝑂 𝐶𝑇 𝑅𝑇 𝑉𝐶𝐶
∆𝑉𝐶 = 2
∆𝑓𝑂
KV = ∆𝑉𝑐
8𝑓𝑂
=𝑉
𝐶𝐶
Low pass filter

• The filter used in a PLL may be either passive type as shown in figure a,b or active type c 2.49
• LPF not only removes the high frequency components and noise,but also controls the dynamic
characteristics of the PLL.
• The characteristics include capture range and lock range,bandwidth,transient response.
• If filter bandwidth is reduced,response time increases.
Figure 2.49 LPF

• This reduces the capture range of the PLL.
• The charge on the filter gives short time memory to the PLL.
• This produces high noise immunity and locking stability.
2.7.3 PLL APPLICATION

Tracking Band-Pass Filter for Angle Modulated Signals
Because of their temperature dependence, narrowband bandpass filters cannot be implemented by

conventional analog filters. In other applications, the carrier frequency of angle-modulated signal to
be selected varies. These problems may be overcome if a PLL tracking the carrier is used as a bandpass
filter. The PLL separates the spectrum of the angle-modulated signal from other interfering signals, or
limits the transmitted spectrum to within specified bounds. The relationship between the input and
output phase modulation is determined by the closed-loop transfer function
Θo(s) = H(s)Θi(s) . (1)
Since differentiation in time corresponds to multiplication by s, the relationship between input and
output FM is obtained from Eq. (1) as
sΘo(s) = H(s)[sΘi(s)] .
The filter characteristic is determined by the closed-loop transfer function. A further advantage of PLL
bandpass tracking filter is that it rejects the amplitude modulation, that is, it may also be used as a
limiter. The block diagram of a bandpass tracking filter is shown in Fig. 1. If the loop parameters
depend on the amplitude of the input signal, an AGC circuit must precede the PD in order to keep the
filter parameters constant. Note that the problems of and the difficulties associated with the design and
implementation of a high-frequency bandpass filter are reduced to the design and implementation of a
baseband loop filter as shown in 2.50
Figure 2.50 PLL configurations for band-pass tracking filter and CW carrier recovery. The AGC circuit
is used to keep the input amplitude, that is, the loop parameters, constant.
CW Carrier Recovery
In every coherent receiver, the carrier has to be recovered from the noisy input signal [9]. Here, it is
assumed that the carrier is present all the time in the received spectrum; the recovery of a suppressed
carrier will be considered later. The aim of CW carrier recovery is to retrieve the carrier and to
suppress as much noise, modulation, and interference as possible. The CW carrier recovery circuit is a
narrowband bandpass tracking filter implemented by a PLL as shown in figure.
The noise-free recovery of a carrier in a noisy environment requires a very narrowband PLL.
Unfortu- nately, the acquisition properties of narrowband PLLs are very poor. This problem may be
eliminated by using two different loop bandwidths: a wide one during acquisition and a narrow one in
steady-state, after the phase-locked condition has been achieved .
The Doppler effect must also be considered in many carrier recovery circuits. The ideal second-
order PLL may track a frequency ramp, but the reduction of tracking error requires a wide loop
bandwidth. Unfortunately, the noise-rejection performance of a PLL is inversely proportional to the
loop bandwidth. For low SNR, this contradiction may be solved by using third- or higher-order loop
configurations.
PLL Frequency Divider and Multiplier
The PLL may be used as a frequency divider if a frequency multiplier is placed into the feedback path as
shown in figure 2.51 , where M denotes the frequency-multiplier ratio.
Figure 2.51 Block diagram of a PLL frequency divider.
Let ωi denote the frequency of input signal s(t, Φ). Under phase locked condition the PLL divides
the input frequency by M
When the carrier frequency of an angle modulated signal is divided, its modulation frequency fm
does not change, but its phase/frequency deviation is divided by M
H(s) denotes the closed-loop PLL transfer function. However, the frequency multiplier in the feedback
path increases the loop gain as shown by
K = MKgKdKv.
The PLL may be used as a frequency multiplier if, instead of the multiplier, a frequency divider with
division ratio of N is placed into the feedback path in Fig. Again, the modulation frequency of angle
modulated signal does not change, but the carrier frequency and the phase/frequency deviation is
multiplied by N
where the loop gain is
Frequency Synthesis and Angle Modulation by PLL
Signals with high frequency stability and high spectral purity are often required in electrical engineering.
In many applications, the frequency of generated signal must be varied by a digital code.
The PLL is widely used in frequency synthesis to generate spectrally pure signals and, if necessary,
to operate as an analog or digital frequency or phase modulator. Frequency multiplication or division,
frequency addition or subtraction may be performed, using a PLL in conjunction with programmable
frequency dividers and mixers as shown in Fig.2.52. As a result, the output frequency f o depends on the
reference fR and offset fS frequencies, moreover, on the division ratios of frequency dividers. In
frequency synthesis, the PLL input is called reference signal and its frequency is denoted by f R. To
optimize the system performance, frequently a multiloop circuit configuration is used.
Figure 2.52 Frequency synthesis by phase lock.
In frequency synthesis, the dominant noise sources are the VCO, frequency dividers, mixers, and
phase detectors. The main design goals are to minimize the output phase noise, to avoid the generation of
spurious output signals, and to minimize the unwanted output FM caused by the periodic output of the
phase detector. These requirements can be satisfied with special PD configurations, such as sample-and-
hold phase detector or phase-frequency detector with a charge-pump circuit. The operation of these
edge-triggered PDs and the analysis of PLLs implemented with them is discussed in the last section of
the article.
In addition to frequency synthesis, PLLs may be also used as FM or PM modulators. The
corresponding transfer functions for FM and PM are
Problems
1. Design a wide band pass filter having fL = 400 Hz , fH= 2 KHz and pass band gain of 4. Find the value of Q of
the filter
Solution :
Pass band gain = 4
LPF and HPF many be designed to give gain of 2
𝑅𝐹
i.e., Ao = 1 + =2
𝑅𝐼
𝑅𝐹 = 𝑅𝐼 assume 𝑅𝐹 = 𝑅𝐼 = 10 KΩ for both LPF anf HPF

For LPF,
1
FH =2 KHz = 2𝜋𝑅
1 𝑐1
Let C1 =0.01 𝜇𝐹
1
R1= 2𝜋(2𝑥103 )(0.01𝑥10−6 ) = 7.9 KΩ
For HPF,
1
Fl= 400 Hz =2𝜋𝑅
2 𝑐2
Let C2 =0.01μF
1
R2 =2𝜋(400)(0.01𝑥10−6 ) =39.8 KΩ
Fo = √𝑓ℎ 𝑓𝑙 = √2000𝑥400 = 894.4 Hz

𝑜 𝑓 𝑓𝑜 894.4
Qo = 𝐵𝑊 = [𝑓 = [2000−400] = 0.56
ℎ −𝑓𝑙 ]
2 In a monostable multivibrator ,R= 100 KΩ and the time delay T=100 ms. Calcaulate the value of C
Solution:
We know that,
T= 1.1 RC seconds
𝑇 100𝑋103
C=1.1 𝑅 = 1.1𝑋100𝑋103 = 0.9 Μf
3 In astable multivibrator, for 𝑅𝐴 = 6.8 KΩ, 𝑅𝐵 = 3.3 KΩ , C= 0.1 μF.
Calculate a) tHIGH b) tLOW c) free running frequency d) duty cycle ,D

Solution :
THIGH = 0.69 [RA+ RB]C
= 0.69 [6.8 k +3.3 k][0.1 μ] = 0.7 ms
TLOW = 0.69 RBC
= 0.69 [3.3 k][0.1μ] = 0.23 ms
1.45 1.45
F= =[6.8𝐾+2(3.3𝐾)][0.1𝜇] = 1.07 KHz
[𝑅𝐴 +2𝑅𝐵 ]
𝑇𝑙𝑜𝑤 RB 3.3𝐾
D = 𝑇
= [𝑅 = 6.8𝐾+2(3.3𝐾) =0.25 or 25 %
𝐴 +2𝑅𝐵 ]
4 If fs=100 KHz, voltage to frequency transfer coefficient of VCO ,KV=2MHz/V, fo the VCO frequency is 5
MHz and N= 100 is the frequency multiplier.What is the dc control voltage at lock ?
Solution
[𝑓𝑠 −𝑓𝑜 ]
Vc = 𝐾𝑣
At lock , fo = Nfs
𝑁𝑓𝑆 −𝑓𝑜 100𝑥100𝑥103 −5000𝑥103

Vc = 𝑘𝑣
= 2𝑥106
= 2.5 V
UNIT III DATA CONVERTERS

3.1 INTRODUCTION
• Most of the real world operation of any digital communication system is based upon analog to
digital (A/D) and digital to analog (D/A) conversion. The below fig. highlights a typical application
within which A/D and D/A conversion is used.
• The transducer circuit will gives an analog signal. This signal is transmitted through the anti-
aliasing filter to avoid higher components, and then the signal is sampled at twice the frequency
of the signal to avoid the overlapping.
• The output of the sampling circuit is applied to A/D converter where the samples are converted
into binary data i.e. 0’s and 1’s. Like this the analog data converted into digital data.
• The digital data is again reconverted back into analog i.e D/A conversion is done by exact
opposite operation of A/D converter.
• The output of the D/A convertor is staircase. This staircase output is transmitted through the
smoothing filter to reduce the effect of quantization noise.
3.2 BASIC DAC TECHNIQUES (Resistive Techniques)

Digital –Analog Converter:
• The input of the DAC is n-bit binary word ‘d’ and ‘n’ number of input bits designated as
d1,d2,d3,…..dn and is combined with the reference voltage VR to give an analog output signal.
• The output of DAC can be either a voltage or current.
• For a voltage output DAC, the D/A converter is mathematically described as
…..(1)
Where,
Vo = output voltage
VFS = full scale output voltage
K = scaling factor usually adjusted to unity
d1,d2…..dn = n-bit binary fractional word with the decimal point located at the left
d1 = most significant bit (MSB) with a weight of VFS/2
dn = least significant bit (LSB) with a weight of VFS/2n
• There are many ways to implement the above equation (1), but here we will discuss the following
resistive techniques only.
1) Weighted Resistor DAC
2) R-2R Ladder
3) Inverted R-2R Ladder
3.3 DIFFERENT TYPES OF DACs

3.3.1 WEIGHTED RESISTOR DAC
Fig.(a) A simple weighted resistor DAC
• Fig.(a) shows a simplest circuit of weighted resistor DAC. It uses a summing inverting amplifier.
• It contains n-electronic switches (i.e. n switches) and these switches are controlled by binary
input bits d1, d2,…..dn. These switches are Single Pole Double Throw (SPDT) type.
• If the binary input bit to a switch is ‘1’ then the switch connects the resistor to reference voltage
(–VR)
• If the binary input bit to a switch is ‘0’ then the switch connects the resistor to the ground.
• From Fig(a) , the output current I0 for an ideal op-amp can be written as,
• The output voltage is,
…..(2)
By comparing eq’s (1) & (2), if Rf = R then K=1 and VFS = VR
• The circuit shown in fig (a) uses a negative reference voltage (- VR). The analog output voltage is
positive staircase as shown in fig (b) for a 3-bit weighted resistor DAC.
V0= VR [d1 2-1+d2 2-2+d3 2-3]
Where d1 is MSB and d3 is LSB
When d1d2d3=000 V0=0v
d1d2d3=001 V0=1/8 VR
…
& d1d2d3=110 V0=6/8 VR

d1d2d3=111 V0=7/8 VR
Disadvantages
1) Very wide ranges of different values of resistors are required.
2) When number of binary input increases, it is not easy to maintain the resistance ratio. But for better
resolution, the input word length has to be increased.
3) For 8-bit DAC, the resistors required are 21R,22R,….,28R the larger resistance is 128 times the
smallest one for only 8-bit DAC.
4) For a 12-bit DAC, the largest resistance required is 5.12MΩ if the smallest is 2.5KΩ.
5) The fabrication of such a large resistance in IC is not practical. Therefore especially in monolithic
form restricts the use of weighted resistor DAC’s to below 8-bits.
3.3.2 R-2R LADDER DAC
• Wide range of resistors required in binary weighted resistor type DAC. This can be avoided by
using R-2R ladder type DAC where only ‘2’ values of resistors are required. The circuit of R-2R
ladder network is shown in fig(a).
• The typical value of ‘R’ ranges from 2.5KΩ to 10KΩ.
• Consider a 3-bit DAC as shown in fig(a), where the switch position d1d2d3 corresponds to the
binary word 100.
• From fig (c), the voltage at node ‘C’ is,

• The output voltage Vo for an inverting amplifier is, Vo = -(RF/R1).Vi
• Similarly, the switch position corresponding to binary word 001 in 3-bit DAC is as shown in fig.
Analysis:
KCL at node ‘a’,
𝑉𝑎 𝑉𝑎+𝑉𝑅 𝑉𝑎−𝑉𝑏
+ + =0 (1)
2𝑅 2𝑅 𝑅
KCL at node ‘b’,

𝑉𝑏−𝑉𝑎 𝑉𝑏 𝑉𝑏−𝑉𝑐
+ 2𝑅 + =0 (2)
𝑅 𝑅
KCL at node ‘c’,

𝑉𝑐−𝑉𝑏 𝑉𝑐 𝑉𝑐
+ 2𝑅 + =0 (3)
𝑅 𝑅
From equation (3),

2Vc-2Vb+Vc+2Vc=0
𝟐
Vc = 𝟓 𝑽𝒃
From Equation (2),

2Vb-2Va+Vb+2Vb-2Vc=0 & 5Vb-2Va-2(2/5Vb) = 0
𝟐𝟏
Va = 𝟏𝟎 𝑽𝒃
From Equation (1),

Va+Va+VR+2Va-2Vb = 0 & 4(21/10Vb)-2Vb = -VR
𝟓
Vb = − 𝟑𝟐 𝑽𝑹
Substituting Vb, we have

𝟐𝟏 𝟏
Va = − 𝟔𝟒 𝑽𝑹 & Vc = − 𝟏𝟔 𝑽𝑹
The Output Voltage,
• In a similar way, the output voltage for R-2R ladder type DAC corresponding to other 3-bit binary
words can be calculated.
3.3.3 INVERTED R-2R LADDER DAC (Current mode R-2R Ladder DAC)
• In weighted resistor and R-2R ladder DAC the current flowing through the resistor is always
changed because of the changing input binary bits 0 and 1.
• More power dissipation causes heating, which in turn cerates non-linearity in DAC. This problem
can be avoided by using INVERTED R-2R LADDER DAC.
• A 3-bit INVERTED R-2R LADDER DAC is as shown in fig (a) where the position of MSB and
LSB is interchanged.
• Each input binary word connects the corresponding switch either to ground or to the inverting
input terminal of op-amp which is also at virtual ground.
• Since both the terminals of switches ‘di’ are at ground potential, current flowing in the resistances
is constant and independent of switch position i.e independent of input binary word.
Fig (a) Inverted R-2R ladder DAC

• From fig(a), when switch ‘di’ is at logical ‘0’ i.e to the left, the current through 2R resistor flows
to the ground and when the switch ‘di’ is at logical ‘1’ i.e to the right, the current through 2R
sinks to the virtual ground.
• The circuit has the important property that the current divides equally at each of the nodes. This is
because the equivalent resistance to the right (or) to the left of any node is exactly 2R.
• The division of the current is as shown in fig(b).
Fig (b) Inverted R-2R ladder DAC showing division of current for digital input word 100.
• Consider a reference current of 2mA. Just to the right of the node A, the equivalent resistor is 2R.
Thus 2mA of reference input current divides equally to value 1mA at node A.
• Similarly to the right of node B, the equivalent resistor is 2R. Thus 1mA of current further divides
to value 0.5mA at node B.
• Similarly current divides equally at node C to 0.25mA
• The equal division of current in successive nodes remains the same in the “inverted R-2R ladder”
irrespective of the input binary word.
• Thus the currents remains constant in each branch of the ladder. Since constant current implies
constant voltage, the ladder node voltages remains constant at VR/20, VR/21,VR/22.
• The circuit works on the principle of summing currents and is also said to be operate in the
current mode.
• The most important advantage of the current mode (or) inverted ladder node voltages remain
constant even with changing input binary words, the stray capacitances are not able to produce
slow-down effects on the performance of the circuit.
Advantage of Current mode (or) Inverted Ladder

• The equal division of current in successive nodes remains same(constant). So, in inverted R/2R
ladder DAC, node voltages also remain constant with changing input binary words, this avoids
any slowdown effects by stray capacitances.
3.4 ANALOG TO DIGITAL CONVERTERS
• An analog to digital converter is defined as a circuit, which converts analog signal, applied at its
input into equivalent digital output.
(or)
• It can also be defined as a circuit which accepts analog input voltage and converts into its
equivalent binary word i.e d1,d2,d3,........dn.
• The block schematic of ADC is as shown in fig.
• The functional value of (D) of an analog to digital converter can be expressed as,
D = d12-1 + d22-2+……+dn2-n
Where d1 is MSB & dn is LSB
• ADC has two control lines: START input to tell the ADC when to start the conversion and EOC
(End of conversion) output to announce when the conversion is complete.
• Depending upon the type of application, ADC’s are designed for microprocessor interfacing (or)
to directly drive LCD (or) LED displays.
3.5 DIFFERENT TYPES OF ADC

ADCs are broadly classified into two groups according to their conversion techniques
1) Direct type ADCs
2) Integrating type ADCs
1) Direct type ADCs
• Direct type ADCs compares a given analog signal with the internally generated equivalent
signal.
• This group includes

1) Flash (Comparator) type converter
2) Counter type converter
3) Servo or Tracking type converter
4) Successive approximation type converter
2) Integrated type ADCs
• Integrated type ADCs perform conversion in an indirect manner by first changing the analog
input signal to linear function of time or frequency and then to a digital code.
• The integrating type of ADCs does not require a S/H circuit at the input. If the input changes
during conversion, the ADC output code will be proportional to the value of the input averaged
over the integration period.
1) Charge balancing ADC
2) Dual slope ADC
3.5.1 Flash (Parallel Comparator) A/D converter
• The flash A/D converter is the simplest, fastest and most expensive technique for high degree of
accuracy.
• The fig. (a) shows a 3-bit A/D converter. This circuit consists of a resistive divider network, 8
op-amp comparators and a 8-line to 3-line encoder (3-bit priority encoder).
• The comparator and its truth table is shown in fig.(b)

• The truth table for the flash type ADC is as shown in fig(c).
• At each node of resistive divider, a comparison voltage is available. Since all the resistors are of
equal value, the voltage levels available at the nodes are equally divided between the reference
voltage VR and the ground.
• The purpose of the circuit is to compare the analog input voltage Va with each of the node
voltages.
Advantages
1) The flash ADC is the fastest type of ADC because the conversion is performed simultaneously through
a set of comparators, hence referred as flash type ADC.
2) Typical conversion time is 100ns or less.
3)The construction is simple and easier to design.
Disadvantages
1) The flash ADC is not suitable for higher number of bits.
2) To convert the analog input voltage into a digital signal of n-bit , (0 to 2n – 1) or 2n comparators are
required. The number of comparators required doubles for each added bit. A 2-bit ADC requires 4
comparators, 3-bit ADC requires 8 comparators.
3) The larger the value of ‘n’, the more complex is the priority encoder.
3.5.2 COUNTER TYPE A/D CONVERTER

• The counter type ADC is constructed using a binary counter, DAC, a comparator and an AND
gate.
• Its operating principal involves that the input to the DAC is varied and its output is continuously
compared with the analog input which is to be converted into the digital form.
• The block arrangement of counter type A/D converter is as shown in fig.(a)
• Consider a 3-bit counting ADC.
Fig.(a) A counter type A/D converter

Operation:
• In the beginning of operation the counter is reset to zero count by reset pulse. After releasing the
reset pulse the clock pulses are counted by the binary counter. These pulses go through the AND
gate which is enabled by the voltage comparator high output. The number of pulses counted
increase with time.
• The binary word representing this count is used as the input of a D/A converter whose output is a
stair case. The analog output Vd of DAC is compared to the analog input Va by the comparator.
• When Va>Vd the output of the comparator becomes high and the AND gate is enabled to allow
the transmission of the clock pulses to the counter, the counter counts the no. of pulses &
provides its output to DAC.
• When Va<Vd the output of the comparator becomes low and the AND gate is disabled. This
stops the counting at the time Va ≤ Vd and the digital output of the counter represents the analog
input voltage Va.
• For a new value of analog input Va, a second reset pulse is applied to clear the counter.
• Upon the end of the reset, the counting begins again as shown in fig(b).
Fig.(b) D/A output staircase waveform

Advantages:
1) Its operation is simple and it requires less hardware components.
Disadvantages:
1) Low speed is the most serious drawback of this method.
2) The conversion time is as long as (2n – 1) clock periods depending upon the magnitude of the
input voltage Va.
Ex: For 12-bit system,1MHZ frequency Conversion Time = (212 – 1)*1µs = 4.095ms
3.5.3 SUCCESSIVE-APPROXIMATION ADC
• The Successive Approximation technique uses a very efficient code search strategy to
complete n-bit conversion in just n-clock periods.
• An eight bit converter would require eight clock pulses to obtain a digital output.
• Fig .shows an 8-bit successive approximation ADC.
• The circuit uses a Successive Approximation Register (SAR) to find the required value of each
bit by trial and error.
Operation
• With the arrival of START command, the SAR sets MSB d1=1 with all other bits to zero so
that the trail code is 1000 0000.
• The output Vd of the DAC is now compared with analog input Va
• If Va > Vd, then 1000 0000 is less than the correct digital representation , the MSB is left at
‘1’ and the next LSB is made ‘1’ and further tested.
• If Va < Vd, then 1000 0000 is greater than the correct digital representation , So reset MSB to
‘0’ & go on the next LSB.
• This procedure is repeated for all subsequent bits, one at a time, until all bit positions have
been tested.
• Whenever the DAC output crosses Va, the comparator changes state and this can be taken as
the end of conversion(EOC) command.
• Fig (a) shows a typical conversion sequence.
• From fig (b), the D/A output voltage becomes successively closer to actual analog input
voltage.
• It requires ‘8’ pulses to establish the accurate output regardless of the value of the analog
input. One additional clock pulse is used to load the output register & reinitialize the circuit.
Advantages:
1 Conversion time is very small.
2 Conversion time is constant and independent of the amplitude of the analog 2 input signal VA.
Disadvantages:
1 Circuit is complex.
2 The conversion time is more compared to flash type ADC.
Comparison of Speed of 8-bit Tracking ADC and Successive Approximation ADC
3.5.4 DUAL-SLOPE ADC (or) Dual Ramp ADC
• The functional diagram of the dual-slope (or) dual-ramp converter is as shown in fig(a).
• The Analog part of the circuit consists of a high input impedance buffer A1, Precision
Integrator A2 and a voltage comparator.
• The converter first integrates the analog input signal Va for a fixed duration of 2n clock
periods as shown in fig.(b)
• Then it integrates an internal reference voltage VR of opposite polarity until the integrator
output is zero.
• The no. of clock pulses ‘N’ required to return the integrator to zero is proportional to the value
of Va averaged over the integration period. Hence ‘N’ represents the desired output code.
Operation:
• Before the START command arrives, the switch SW1 is connected to ground and SW2 is
closed.
• Any offset voltage present in the A1,A2 comparator loop after integration appears across the
capacitor CAZ till the threshold of the comparator is achieved.
• The capacitor CAZ thus provides automatic compensation for the input-offset voltages of all the
three amplifiers.
• Later when SW2 opens, CAZ acts as memory to hold the voltage required to keep the offset
nulled.
• At the arrival of START command, at t = t1, the control logic opens SW2 and connects SW1
to Va and enables the counter starting from zero.
• The circuit uses an n-stage ripple counter and therefore the counter resets to zero after
counting 2n pulses.
• The analog voltage Va is integrated for a fixed no. 2n counts of clock pulses after which the
counter resets to zero.
• If the clock period is ‘T’, the integration takes place for a time T1 = 2n *T and the output is a
ramp going downwards as shown in fig(b).
• The counter resets itself to zero at the end of interval T1 and SW1 is connected to the
reference voltage (-VR). The output voltage vo will now have a positive slope.
• As long as vo is negative, the output of the comparator is positive and the control logic allows
the clock pulse to be counted.
• When vo becomes just zero at time t = t3, the control logic issues an end of conversion (EOC)
command and no further clock pulses enter the counter. It can be shown that the reading of the
counter at t3 is proportional to the analog input voltage Va.
• In fig (b),
And
For an integrator,
• The voltage vo will be equal to V1 at the instant t2 and can be written as
……(1)
• The voltage V1 is also given by
….(2)
By comparing eq(1) &(2),we get
Substitute (t2 – t1) = 2n and (t3 – t2) = N, we get
• The following important observations can be made:
1. Since VR and ‘n’ are constant, the analog voltage Va is proportional to the count reading
N and is independent of R,C and T.
2. The dual-slope ADC integrates the input signal for a fixed time, hence it provides excellent
noise rejection of ac signals whose periods are integral multiples of the integration time
T1. Thus ac noise superimposed on the input signal such as 50HZ power line pick-up will
be averaged during the input integration time. So choose clock period T, so that 2nT is an
exact integral multiple of the line period (1/50)second = 20ms.
3. The main disadvantage of the dual slope ADC is the long conversion time. For instance, if
2n – T = 1/50 is used to reject line pick-up, the conversion time will be 20ms.
Applications:
• Dual slope converters are particularly suitable for accurate measurement of slowly varying
signals such as thermocouples and weighing scales.
• Dual-slope ADC’s also form the basis of digital panel meters & multimeters.
3.6 DAC/ADC SPECIFICATIONS

• D/A & A/D converters are available with wide range of specifications specified by
manufacturer. Some of the important specifications are Resolution, Accuracy, linearity,
monotonicity, settling time and stability.
1) Resolution
• Resolution of a converter is defined as the smallest change in voltage which may be produced
at the output (or input) of the converter. Simply, resolution is the value of LSB.
Ex: An 8-bit D/A converter has 28-1=255equal intervals. Hence the smallest change in output
voltage is (1/255) of the full scale output range.
Resolution (in volts) = VFS/2n-1 = 1 LSB increment
Example: Resolution for an 8 – bit DAC for example is said to have : 8 – bit resolution
: A resolution of 0.392 of full-Scale (1/255)
: A resolution of 1 part in 255.
Thus resolution can be defined in many different ways.
• Resolution of an A/D converter is defined as the smallest change in analog input for a one bit
change at the output.
Ex: Input range of an 8-bit A/D converter is divided into 255 intervals. So the resolution for a 10V
input range is 39.22mV (=10V/255).
• The following table shows the resolution for 6 to 16 bit DACs
2) Linearity
• The linearity of an A/D (or) D/A converter is an important measure of its accuracy and tell us
how close the converter output is to its ideal transfer characteristics.
• In an ideal DAC, equal increment in the digital input should produce equal increment in the
analog output and the transfer curve should be linear.
• In an actual DAC, output voltage does not fall on a straight line because of gain and offset
errors.
• The linearity error measures the derivation of the actual output from the fitted line and is given
by ε/∆.
• The error is usually expressed as a fraction of LSB increment (or) percentage of full-scale
voltage.
• A good converter exhibits a linearity error of less than ±(1/2)LSB.

3) Accuracy
• Absolute accuracy is the maximum deviation between the actual converter output and the
ideal converter output.
• Relative accuracy is the maximum deviation after gain and offset errors have been removed.
• The accuracy of a converter is also specified in terms of LSB increments (or) percentage of
full scale voltage.
4) Monotonicity
• A monotonic DAC is the one whose analog output increases for an increase in digital input.
• From fig. it represents the transfer curve for a non-monotonic DAC, since the output decreases
when input code changes from 001 to 010.
• A monotonic characteristic is essential in control applications, otherwise oscillations can
result.
• In successive approximation ADCs, a non-monotonic characteristic may lead to missing
codes.
• If a DAC has to be monotonic, the error should be less than ±(1/2)LSB at each output level.
• All the commercially available DACs are monotonic because the linearity error never exceeds
±(1/2)LSB at each output level.
5) Settling time
• The most important dynamic parameter is the settling time.
• Settling time is the time it takes for the output to settle within a specified band ±(1/2)LSB of
its final value following a code change at the input (usually a full scale change).
• It depends upon the switching time of the logic circuitry due to internal parasitic capacitances
and inductances.
• Settling time ranges from 100ns to 10µs depending on word length and type of circuit used.
6) Stability
• The performance of converter changes with temperature, age and power supply variations.
• So, all the parameters such as offset, gain, linearity error and monotonicity must be specified
over the full temperature and power supply ranges.
PROBLEMS
1. A 12-bit D to A converter has a full-scale range of 15 volts. Its maximum differential linearity
error is ± 1/2 LSB.
i. What is the percentage resolution?
ii. What are the minimum and maximum possible values of the increment in
its output voltage?
Sol: Given, n=12
VFS=15v
(i) Percentage resolution:
= 15/(212 – 1) *100 = 0.366%
(ii) Min and Max values of output voltage
𝑉𝐹𝑆
MSB = = 15/2 = 7.5v
2
LSB = VFS/2n = 15/212 = 3.66mV

2. Calculate the number of bits required to represent a full scale voltage of 10V with a resolution
of 5mV approximately.
Sol:
5mV = 10 / (2n – 1)
2n – 1 = 10/ 5mV => 2n – 1 = 2000
=> 2n = 2001
For n=11, 2n = 2048
i.e No. of bits = 11
3. A dual slope ADC uses a16-bit counter and a 4MHz clock rate. The maximum input voltage
is+10v. The maximum integrator output voltage should be-8v when the counter has cycled through 2n
counts. The capacitor used in the integrator is 0.1 μF Find the value of the resistor R of the integrator.
Sol:
Time period T1 = 2n / (clock rate)
Problem.4
UNIT IV DIGITAL INTEGRATED CIRCUITS

4.1 INTRODUCTION
• Digital logic : possible numbers or logic values are ‘0’ & ‘1’
• Binary digital bit : n-bit can represent 2n different values.
• Low : logic ‘0’ designated as LOW
• High : logic ‘1’ designated as HIGH
• Positive logic : 0-LOW & 1-HIGH
• Negative logic : 0-HIGH & 1-LOW
Definition of digital IC
• Digital IC or integrated circuit is a miniature ,low cost electronic circuit consisting of number
of gates that are connected or fabricated on a single crystal chip of silicon
• Internally gates are made up of transistors ,diodes ,resistors and capacitors.
Advantages of digital IC’s
• Small in size
• High reliability
• Low cost
• Low power consumption
IC packages
• Two types of IC packages are available
❖ DIP Dual In Package
❖ SOIC Small Outline Integrated Circuit Package
• SOIC package is smaller than DIP
Complexity classification of Digital Integrated Circuits
• SSI,MSI,LSI,VLSI are different complexity classification of Digital IC’s.
INTEGRATIO NO. OF APPLICATIONS

N COMPONENTS/CHI
P
Small Scale SSI 10 gates/chip Flip flops & logic gates
Medium Scale 10-100 gates/chip Encoders,decoders,countes,registers,multiplexe

MSI rs
Large scale LSI 100-10000 gates/chip Memories
Very scale VLSI 10000-100000 Microprocessors

gates/chip
Ultra large scale >100,000 gates/chip Very large memories,large microprocessors and
large single chip computers
ULSI
4.2 CLASSIFICATION OF INTEGRATED CIRCUIT TECHNOLOGIES

• ‘2’ major digital IC technologies used to implement logic gates are CMOS & Bipolar (TTL)
• Classification of IC technologies is shown in figure 4.1.
IC'S
MOSFET'S BJT'S
TTL
CMOS
BIPOLAR
Figure 4.1 classifications of IC technologies

• BICMOS uses combination of both CMOS & BIPOLAR
Basics of Digital integrated circuits
• ‘2’ major IC technologies – CMOS & TTL BIPOLAR
• The logic operations of NOT,AND,OR,NAND,NOR,EX-OR are the same regardless of the
IC technology used.
• Example : An AND gate has the same logic function whether it is implemented with CMOS
or bipolar
Definition of logic family

• A logic family is a collection of different integrated circuit chips that have similar
input,output and internal circuit characteristics but they perform different logic functions.
• Chips of same logic family can be interconnected to perform desired logic function.
• Chips from different families may not be compatible they may different power supply
voltages or may use different input and output conditions to represent their logic families.
CMOS logic family
• CMOS is the dominant one
• Within the CMOS family there are many categories that vary in terms of supply voltage,
power dissipation, switching speed and other parameter.
Types of CMOS logic family
DESIGNATION DESCRIPTION VCC
AC Advanced CMOS 5V
ACT Advanced CMOS with bipolar (TTL)compatible inputs 5V
AHC Advanced high speed CMOS 5V

AHCT Advanced high speed CMOS with bipolar (TTL) 5 V
compatible inputs
ALVC Advanced low voltage CMOS 3.3 V
AUC Advanced ultra low voltage CMOS 1.8 V
AUP Advanced ultra low power CMOS 3.3 V
AVC Advanced very low voltage CMOS 2.5 V
CD4000 Standard CMOS 5V
FCT Fast CMOS technology 5V
HC High speed CMOS 5V
HCT High speed CMOS with bipolar (TTL) compatible inputs 5V
LV-A Low voltage CMOS 3.3 V

LV-AT Low voltage CMOS with bipolar (TTL) compatible inputs 5V
LVC Low voltage CMOS 3.3 V

Table 4.1 Types of CMOS logic family
Bipolar (TTL) logic family

• Several categories differ in various parameters
• All of them operate with VCC of 5V as shown in table 4.2
ALS ADVANCED LOW POWER SCHOTTKY 5V
AS Advanced schottky 5V
F Fast 5V
LS Low power schottky 5V
S Schottky 5V
NONE Standard TTL 5V

Table 4.2 bipolar logic family
Bi-CMOS logic family
• Common categories in Bi-CMOS logic family are shown below.All operate with a typical
VCC of 5V as shown in table 4.3.
ABT Advanced Bi-CMOS 5V
ALB Advanced low-voltage Bi-CMOS 5V
BCT Standard Bi-CMOS 5V
LVT Low voltage Bi-CMOS 5V
Table 4.3 Bi-CMOS logic family

LOGIC GATES
• All of the basic logic operations NOT,AND,OR,NAND,NOR,EX-OR,EX-NOR are available
in both CMOS and Bipolar.
• The types of gate configurations typically available in IC packages are indentified by the last
two or three digits in the series designation
• EX: 74 LS 04 (74 – TTL Family , LS – Low Power Schottky ,04 – hex inverter)
• Some of the common logic gates configurations and their standard identifier digits are as
follows in table 4.3
74x00 Quad 2-i/p NAND
74x02 Quad 2-i/p NOR
74x04 Hex inverter (6 NOT gates)
74x08 Quad 2-i/p AND
74x10 Triple 3-i/p NAND
74x11 Triple 3-i/p AND
74x20 Dual 4-i/p NAND
74x21 Dual 2-i/p AND
74x27 Triple 3-i/p NOR
74x30 Single 8-i/p NAND
74x32 Quad 2-i/p OR
74x86 Quad 2-i/p XOR
74x266 Quad 2-i/p XNOR

Table 4.3 common logic gates configurations and their standard identifier digits
Basic performance (operational) characteristics and parameters
• Switching speed (propagation delay time)
• Power dissipation
• DC supply voltage
• Input and output logic levels
• Speed power product
• Fan out and loading
• Handling unused gate inputs
• Noise immunity and noise margin
Switching Speed (propagation delay time)
• Switching speed is measured in terms of the propagation delay time.
• The low speed and high speed refers to propagation delay time.
• The shorter the propagation delay, higher the speed of the circuit and higher the frequency at
which it can operate.
• Propagation delay tP of a logic gate is defined as the time interval between the transition of
an input pulse and the occurrence of the transition of the output pulse as shown in figure 4.2.
Figure 4.2 Propagation Delay

• Two different measurements of propagation delay time are:
❖ TPHL : the time between a specified reference point on the input pulse and a
corresponding reference point on the resulting o/p pulse,with the o/p changing from
the HIGH level to the LOW level (HL)
❖ TPLH : the time between a specified reference point on the input pulse and a
corresponding reference point on the resulting o/p pulse,with the o/p changing from
the LOW level to the HIGH level (LH)
Power Dissipation/consumption
• The power dissipation , PD of a logic gate is the product of the dc supply voltage and the
average supply current. ∴ PD = V x I
• The average supply current is determined based on 50% duty cycle so the average power
dissipation of a logic gate is,
𝐼𝐶𝐶𝐻+ 𝐼𝐶𝐶𝐿
PD = 𝑉𝐶𝐶 [ ]
2
Where ICCH is the supply current for low o/p state
ICCL is the supply current for high o/p state

• CMOS gates have low power dissipations compared to the bipolar family.
• Power dissipation of CMOS depends on frequency of operation.
• Power dissipation of Bipolar is independent of frequency.

Static and dynamic power dissipation (CMOS circuits)
• The power consumption/dissipation of a CMOS circuit whose output is not changing is called
static power dissipation or quiescent power dissipation.
• A CMOS circuit consumes significant power only during transitions is called dynamic power
dissipation
• The amount of power consumed for o/p transitions is expressed as
2
PT = 𝐶𝑃𝐷 𝑉𝐶𝐶 𝑓
PT is internal power dissipation due to o/p transitions.

2
VCC is power supply voltage and P.D across RL is directly proportional to square of 𝑉𝐶𝐶
F is the transition frequency of o/p signal
CPD is the power dissipation capacitance

• A second source of CMOS power consumption is the capacitive load on the O/P
• If there are transitions per second the total power dissipated due to the capacitive load is
2
PL = 𝐶𝐿 𝑉𝐶𝐶 𝑓
CL is the capacitive load
VCC is the supply voltage

• The total dynamic power dissipation of a CMOS circuit is sum of PT and PL
PD = PT + P L
2
PD = (CPD + CL) 𝑉𝐶𝐶 𝑓 = C𝑉 2 𝑓 where C = CPD + CL
• The dynamic power dissipation is often called C𝑉 2 𝑓 power.
DC supply voltage (VCC)
• The DC supply voltage for CMOS logic is either 5 V,3.3V,2.5V or 1.8V.
• The DC supply coltgae for bipolar logic is 5 V. minimum of 4.5 V and max of 5.5 V
Input and output logic levels
• CMOS logic levels: 4 different logic specifications :VIL,VIH,VOL,VOH as shown in figure 4.3
Figure 4.3 CMOS logic levels

TTL Logic levels
• TTL Logic levels : four different logic specifications : VIL,VIH,VOL,VOH as shown in figure
4.4
VOH
VIH
VIL
VOL
Figure 4.4 TTL logic levels

Noise immunity and noise margin

• Noise immunity is defined as the ability to tolerate a certain amount of unwanted voltage
fluctuation on its inputs without changing its output state.
• Noise margin is the measure of circuit’s noise immunity which is expressed in volts.
• Two levels of noise margins as shown in figure 4.5
❖ HIGH LEVEL NOISE MARGIN (VNH)
❖ LOW LEVEL NOISE MARGIN (VNL)
∴ 𝑉𝑁𝐻 = 𝑉𝑂𝐻(𝑀𝐼𝑁) − 𝑉𝐼𝐻(𝑀𝐼𝑁) , 𝑉𝑁𝐿 = 𝑉𝐼𝐿(𝑀𝐴𝑋) − 𝑉𝑂𝐿(𝑀𝐴𝑋)
Figure 4.5 Noise margin

Speed power product (SPP)
• Speed power product can be used as a measure of the performance of a logic circuit taking
into account the propagation delay time and the power dissipation.
• The SPP of a logic circuit is the product of the propagation delay time and the power
dissipation and is expressed in joules which is the unit of energy.
SPP =tPPD
Fan out and loading
• The fan out of a logic gate is the maximum no of inputs of the same series in a IC family that
can be connected to a gates output and still maintain the output logic levels within specified
limits.
• Fan out is specified in terms of unit loads.
• Loading is of two types, CMOS loading and TTL loading
CMOS loading
• CMOS logic presents a predominantly capacitive load to the driving gate as shown in figure
4.6.
• When the o/p of the driving gate is HIGH,the i/p capacitance of the load gate is charging.
• When the o/p of the driving gate is LOW,the i/p capacitance is discharging.
Figure 4.6 CMOS loading

TTL loading
• A TTL driving gate sources current to a load gate input in the HIGH state (IIH) and sink
current from the load gate in the low state (IIL)
• Current sinking and current sourcing are illustrated in simplified form below in figure 4.7
where the resistors represent the internal i/p and o/p resistance of the gate for the two
conditions.
Figure 4.7 TTL loading

Handling unused gate inputs
• Unused gate inputs for bipolar (TTL) and CMOS should be connected to the appropriate logic
level (HIGH or LOW) as shown in figure 4.8
• AND/NAND gate unused i/p’s connected to +VCC
• OR/NOR gate unused i/p’s connected to GND
Figure 4.8 Unused gate input

Advantages and disadvantages of CMOS family
Advantages
• Consumes less power
• Can be operated athigh voltages resulting in improved noise immunity
• Fan out is more
• Better noise margin
Disadvantages
• Suspectable to static charge
• Switching speed low
• Greater propagation delay
4.3 COMPARISION OF VARIOUS LOGIC FAMILIES
• Comparison of various logic families is shown in table 4.4

PARAMETER BIPOLAR CMOS
5V 3.3 V
F LS ALS HC AC AH LV LVC ALVC
C
SPEED(propagation delay 3.3 10 7 7 5 3.7 9 4.3 3
time in ns)
Maximum clock frequency 145 33 45 50 160 170 90 100 150
(MHz)
Power dissipation per gate 6 2.2 1.4 2.75 0.55 2.75 1.6 0.8 0.8
Bipolar (mW)
CMOS (uW)
Output drive IC (mA) 20 8 8 4 24 8 12 24 24
Table 4.4 Comparison of various logic families

COMPARISION BETWEEN CMOS & TTL
• Comparison between CMOS & TTL is shown in table 4.5

S.NO. PARAMETER CMOS TTL
1 Device used n-channel & p- BJT
channel MOSFET
2 VIH(min) 3.5 V 2V
3 VIL(max) 1.5 V 0.8 V
4 VOH(min) 4.95 V 2.7 V
5 VOL(max) 0.005 V 0.4 V
6 High level noise margin VNH 1.45 V 0.4 V
7 Low level noise margin VNL 1.45 V 0.4 V
8 Noise immunity Better than TTL Less than CMOS
9 Propagation delay time 70ns 10 ns
10 Switching speed Less than TTL Faster than CMOS
11 Power dissipation per gate 0.1 mw 10 mW
12 Speed power product 0.7 PJ 100 PJ
13 Fan out 50 10
14 Power supply voltage 1.8 V – 5 V Fixed 5 V
15 Unconnected i/p CMOS i/p’s should Treated as logic 1
never be left
unconnected
16 Application Portable instrument Laboratory
where battery instruments
supply is used
Table 4.5 Comparison between CMOS and TTL
4.4 COMBINATIONAL LOGIC IC’S

4.4.1CMOS CIRCUITS/CMOS GATES
MOSFET
• Symbolic representation of n-channel and p-channel MOSFET is shown in figure 4.9.
Figure 4.9 MOSFET

4.4.2 CMOS inverting gates
• CMOS inverter gate
• CMOS NAND gate
• CMOS NOR gate
CMOS Inverter
• Figure 4.10 shows the CMOS inverter (a)circuit diagram (b)function table (c)logic symbol
Figure 4.10 CMOS inverter (a)circuit diagram (b)function table (c)logic symbol
CMOS NAND gate
• Figure 4.11 shows the CMOS NAND (a)circuit diagram (b)function table (c)logic symbol
Figure 4.11 CMOS NAND (a)circuit diagram (b)function table (c)logic symbol
CMOS NOR gate
• Figure 4.12 CMOS NOR (a)circuit diagram (b)function table (c)logic symbol
Figure 4.12 CMOS NOR (a)circuit diagram (b)function table (c)logic symbol
4.4.3 CMOS Non-Inverting gates
• CMOS non –invering buffer
• CMOS AND gate
• CMOS OR gate
CMOS Non-Inverting Buffer
• Figure 4.13 shows the CMOS Non-inverting buffer (a)circuit diagram (b)function table
(c)logic symbol
Figure 4.13 CMOS Non-inverting buffer (a)circuit diagram (b)function table (c)logic symbol
CMOS AND gate
• Figure 4.14 shows CMOS AND (a)circuit diagram (b)function table (c)logic symbol
Figure 4.14CMOS AND (a)circuit diagram (b)function table (c)logic symbol

CMOS OR gate
• Combining CMOS OR gate with an inverter yields a CMOS OR gate as shown in figure 4.15.
Figure 4.15CMOS OR
4.4.4 CMOS AND-OR –Inverter gate
• Figure 4.16 shows the CMOS AND-OR –Inverter gate
Figure 4.16 CMOS AND-OR –Inverter gate

4.4.5 CMOS OR -AND –Inverter gate
• Figure 4.17 CMOS OR -AND –Inverter gate
Figure 4.17 CMOS OR -AND –Inverter gate

4.4.6 Open drain CMOS gate
• The term open drain means that the drain terminal of the output transistor is unconnected and
must be connected externally to VDD through the load.
• An open drain output circuit is a single N-channel MOSFET as shown in figure 4.18
• With pull-up resistor the output state is high.
Figure 4.18 open drain output circuit

4.4.7 Tristate CMOS gate
• Tristate outputs are available in both CMOS and TTL logic as shown in figure 4.19
• Tristate CMOS gates have three output states :
❖ HIGH
❖ LOW
❖ HIGH impedance(high –Z)
Figure 4.19 Tristate buffer

4.4.8 CMOS Transmission gate
• A p-channel and n-channel transistor pair can be connected together to form a logic controlled
switch, this circuit is called a CMOS transmission gate as shown in figure 4.20
Figure 4.20 transmission gate

Operation CMOS transmission gate
• A transmission gate is operated so that its input signal A(EN) and A’(EN-L) are always at
opposite levels.
• When EN is HIGH and EN-L is LOW,there is a low impedance connection between points
OUT & IN
• When EN is LOW and EN-L is HIGH, points OUT& IN are disconnected
• Once a transmission gate is enabled,the propagation delay from OUT to IN or viceversa is
very short
Advantage
• Because of their short delays and conceptual simplicity, transmission gates are often used in
larger scale CMOS devices such as multiplexers and flipflops.
Applications
• Multiplexer and flipflops
Ex: two input multiplexer using CMOS transmission gates
• Figure 4.21 shows two input multiplexer using CMOS transmission gates
Figure 4.21 two input multiplexer using CMOS transmission gates

Operation
• When S is LOW,the above transmission gate with input ‘X’ is enabled.
∴ Input ‘X’ is connected to the Z output

• When S is HIGH,the below transmission gate with input ‘Y’ is enabled.
• ∴ Input ‘Y’ is connected to the Z output.
4.4.9 Interfacing
• Interfacing means converting the outputs of one circuit or system to the inputs of another
circuit or system with different electrical characteristics.
TTL driving CMOS
• The MOS & CMOS gates are slower than TTL gates but consume less space. Hence there is
an advantage in using TTL & MOS drives in combination.
• The input current values of CMOS are extremely low compared with the output current
capabilities of any TTL series.
• Thus TTL has no problem in meeting the CMOS input current requirements. So a level
translator is used to raise the level of the output of the TTL gate to an acceptable level for
CMOS. In this the TTL output is connected to +5 V source with a pull up resistor.
• The presence of pull up resistor will cause the TTL output to rise to approximately +5 V in
the high state, thereby providing an adequate CMOS input.
• If the TTL has to drive a high voltage CMOS,the pull-up resistor cannot be used to raise the
level of the TTL output to the level of CMOS input, since the TTL is sensitive to voltage
levels in such a case, an open collector buffer can be used to interface TTL to a high voltage
CMOS. Figure 4.22 showsTTL driving CMOS
Figure 4.22 TTL driving CMOS

CMOS driving TTL

• The CMOS output can supply enough voltage and current to satisfy the TTL input
requirements in the high state. Hence no special considerations are required for the high state.
• But the TTL input current requirements at low state cannot be met directly.
• An interface circuit with a low input current requirement and a sufficiently high output
current rating is required.
• When a high voltage CMOS has to drive TTL gate, a voltage level translator that converts
the high voltage input to a +5V output is used between CMOS&TTL.
• Figure 4.23 shows the CMOS driving TTL
Figure 4.23 CMOS driving TTL
4.5 SPECIFICATIONS AND APPLICATION OF TTL

74XX SERIES
4.5.1 CODE CONVERTERS
BCD to Binary conversion
• One method to BCD to binary code conversion uses adder circuits.The conversion process is
as follows:
❖ The value or weight of each bit in the BCD number is represented by a binary number
❖ All of the binary representations of the weights of bits that are in 1s in the BCD
number are added.
❖ The result of this addition is the binary equivalent of the BCD number.
❖ The binary numbers representing the weights of the BCD bits are summed to produce
the total binary number.
• Ex:8 bit BCD code : 1000 0111
Weight: 80 40 20 10 8 4 2 1
Bit designation: B3 B2 B1 B0 A3 A2 A1 A0
BCD BIT BCD WEIGHT BINARY REPRESENTATION
MSB 32 16 8 4 2 LSB
64 1
A0
1 0 0 0 0 0 0 1
A1
2 0 0 0 0 0 1 0
A2
4 0 0 0 0 1 0 0
A3
8 0 0 0 1 0 0 0
B0
10 0 0 0 1 0 1 0
B1
20 0 0 1 0 1 0 0
B2
40 0 1 0 1 0 0 0
B3
80 1 0 1 0 0 0 0
Table 4.5 BCD to Binary representation

• Ex: Convert the BCD numbers 00100111 and 10011000 to binary.

Sol : Write the binary representations of the weights of all ones appearing in the numbers and
add them together as shown in figure 4.24
Figure 4.24 shows the conversion of BCD to binary

Binary to BCD converter
• Table 4.6 shows the truth of binary to BCD converter
• Logic diagram of binary to BCD converter is shown in figure 4.25

Table 4.6 Binary to BCD converter

Figure 4.25 logic diagram of binary to BCD converter
Code converter IC’s

• IC 74x184 – can be used as 6 bits BCD to binary converter
• IC 74x185 – can be used as 6 bits binary to BCD converter
Binary to gray and gray to binary conversion

• Ex-or gates can be used for these conversion
Figure 4.26 logic diagram of Binary to gray and gray to binary conversion
4.5.2 DECODERS
• Figure 4.27 shows the Decoder circuit structure
Figure 4.27 Decoder circuit structure

74X139 DUAL 2 TO 4 DECODER
• Logic symbol for one half of a 74x139 dual 2 to 4 decoder (a)conventional symbol (b)default
symbol associated with external pins (c)truth table for one half of a 74x139 dual 2 to 4
decoder as shown in figure 4.28
(a) (b)
INPUTS OUTPUTS
G_L B A Y3_L Y2_L Y1_L YO_L
1 X x 1 1 1 1
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 1
(c)
Figure 4.28 Logic symbol for one half of a 74x139 dual 2 to 4 decoder (a)conventional symbol
(b)default symbol associated with external pins (c)truth table for one half of a 74x139 dual 2 to 4
decoder
• Figure 4.29 shows The 74x139 dual 2 to 4 decoder (a) traditional logic symbol (b) logic
diagram including pin number for a standard 16 pin dual in package
(a)
(b)
Figure 4.29 The 74x139 dual 2 to 4 decoder (a) traditional logic symbol (b) logic diagram including
pin number for a standard 16 pin dual in package
74X138 3 to 8 decoder
• Figure 4.30 shows74x138 3 to 8 decoder (a) Logic symbol (b)truth table (c)Logic diagram
(a)
INPUTS OUTPUTS
G1 G2A_ G2B_ C B A Y7_ Y6_ Y5_ Y4_ Y3_ Y2_ Y1_L Y0_
L L L L L L L L L
0 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
X X 1 X X X 1 1 1 1 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1 0
1 0 0 0 0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 0 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 0 0 1 1 1 0 1 1 1 1
1 0 0 1 0 1 1 1 0 1 1 1 1 1
1 0 0 1 1 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 1 1 1 1 1 1 1
(b)
(c)
Figure 4.29 74x138 3 to 8 decoder (a) Logic symbol (b)truth table (c)Logic diagram
Cascading binary decoders
Design of a 4 to 16 decoder using 74x138 ICs
• Figure 4.30 shows the Design of a 4 to 16 decoder using 74x138 IC’s

Figure 4.30 Design of a 4 to 16 decoder using 74x138 IC’s

BCD to decimal decoder (74x42/74x45)
• Figure 4.31 shows BCD to decimal decoder using (74x42/74x45)
Figure 4.31 BCD to decimal decoder (74x42/74x45)

4.5.3 LED AND LCD DECODERS WITH DRIVER
SEVEN SEGMENT DECODERS
• Figure 4.32 seven segment decoder(a) segment identification (b)decimal digit (c) logic
symbol and logic diagram
(a) (b)
(c)
Figure 4.32 seven segment decoder(a) segment identification (b)decimal digit (c) logic symbol and
logic diagram
• Truth table for a 74x49 seven segment decoder is shown in table 4.7
INPUTS OUTPUTS
BI_L D C B A a b C d e f g
0 X X X X 0 0 0 0 0 0 0
1 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
1 0 0 1 0 1 1 0 1 1 0 1
1 0 0 1 1 1 1 1 1 0 0 1
1 0 1 0 0 0 1 1 0 0 1 1
1 0 1 0 1 1 0 1 1 0 1 1
1 0 1 1 0 0 0 1 1 1 1 1
1 0 1 1 1 1 1 1 0 0 0 0
1 1 0 0 0 1 1 1 1 1 1 1
1 1 0 0 1 1 1 1 0 0 1 1
1 1 0 1 0 0 0 0 1 1 0 1
1 1 0 1 1 0 0 1 1 0 0 1
1 1 1 0 0 0 1 0 0 0 1 1
1 1 1 0 1 1 0 0 1 0 1 1
1 1 1 1 0 0 0 0 1 1 1 1
1 1 1 1 1 0 0 0 0 0 0 0
Table 4.7 truth table for a 74x49 seven segment decoder
4 to 16 decoder :74x154 (1 of 16 demultiplexer)
• 74x154(1 of 16 demultiplexer) pin diagram is shown in figure 4.32
Figure 4.32 74x154(1 of 16 demultiplexer)

CIRCUIT FOR DRIVING SINGLE SEVEN SEGMENT DISPLAY USING 7446/7447
• Circuit for driving single seven segment display using 7446/7447 is shown in figure 4.33
Figure 4.33 circuit for driving single seven segment display using 7446/7447
Question:design a 3 to 8 decoder using 74x139 decoder & provide the truth table
• Figure 4.34 3 to 8 decoder using 74x139 decoder
Figure 4.34 3 to 8 decoder using 74x139 decoder
4.5.4 ENCODERS
4.5.4.1 PRIORITY ENCODER
Decimal to BCD encoder – IC 74X147
• Figure 4.35 shows the Decimal to BCD IC 74x147
Figure 4.35 Decimal to BCD IC 74x147

74LS148 – 8 to 3 encoder (8 line to 3 line encoder) or octal to binary priority encoder
• Figure 4.36 shows 74x148 octal to binary priority encoder
• Truth table for 74ls148 8 to 3 encoder is shown in Table 4.8
Figure 4.36 74x148 octal to binary priority encoder

Table 4.8 Truth table for 74ls148 8 to 3 encoder

Design a 16 line to 4 line encoder using 74LS148S and external logic
• Figure 4.37 16 line to 4 line encoder
Figure 4.37 16 line to 4 line encoder

Design the 32 input to 5 output priority encoder using four 74LS148 and gates
• 32 line to 5 line encoder is shown in Figure 4.38
Figure 4.38 32 line to 5 line encoder

4.5.5 MULTIPLEXERS (DATA SELECTOR)
74x151 8 input 1 bit multiplexer (8 x 1 MUX)
• 74x151 8 input 1 bit multiplexer (8 x 1 MUX) is shown in figure 4.39
• Table 4.9 shows the Truth table for 74x151 8 input,1bit muliplexer
(a)
(b)
Figure 4.39 (a) Multiplexer structure (b) 74x151 (8x1 mux)logic symbol
INPUTS OUTPUTS
EN_L A B C Y Y_L
1 X X X 0 1
0 0 0 0 𝑫𝑶 ̅̅̅̅
𝑫𝑶
0 0 0 1 𝑫𝟏 ̅̅̅̅
𝑫𝟏
0 0 1 0 𝑫𝟐 ̅̅̅̅
𝑫𝟐
0 0 1 1 𝑫𝟑 ̅̅̅̅
𝑫𝟑
0 1 0 0 𝑫𝟒 ̅̅̅̅
𝑫𝟒
0 1 0 1 𝑫𝟓 ̅̅̅̅
𝑫𝟓
0 1 1 0 𝑫𝟔 ̅̅̅̅
𝑫𝟔
0 1 1 1 𝑫𝟕 ̅̅̅̅
𝑫𝟕
Table 4.9 Truth table for 74ls148 8 to 3 encoder

74x157 – Quad 2 input multiplexer (4 -2x1 mux’s)
• Figure 4.40 shows 74x157 2 input,4-bit mux traditional logic symbol
• Table 4.10 shows the Truth table for a 74x157 2-input,4 bit multiplexer
Figure 4.40 74x157 2 input,4-bit mux traditional logic symbol

INPUTS OUTPUTS
EN_L S 1Y 2Y 3Y 4Y
1 X 0 0 0 0
0 0 1A 2A 3A 4A
0 1 1B 2B 3B 4B
Table 4.10 Truth table for a 74x157 2-input,4 bit multiplexer
74x153 – dual 4 input multiplexer (2- 4X1 mux’s)
• Figure 4.41 shows 74x153 dual 4 input multiplexer logic symbol
Figure 4.4174x153 dual 4 input multiplexer logic symbol

• Table 4.10 shows the Truth table for a 74x153 4input,2bit multiplexer
INPUT OUTPUT
1G_L 2G_L B A 1Y 2Y
0 0 0 0 1C0 2C0
0 0 0 1 1C1 2C1
0 0 1 0 1C2 2C2
0 0 1 1 1C3 2C3
0 1 0 0 1C0 0
0 1 0 1 1C1 0
0 1 1 0 1C2 0
0 1 1 1 1C3 0
1 0 0 0 0 2C0
1 0 0 1 0 2C1
1 0 1 0 0 2C2
1 0 1 1 0 2C3
1 1 X X 0 0
Table 4.10 Truth table for a 74x153 4input,2bit multiplexer

74x150 – 16x1 MUX
Design a 16x1 multiplexer using 74LS151 IC’s
• Figure 4.42 shows 16x1 mux using 74ls151
Figure 4.42 16x1 mux using 74ls151

4.5.6 DEMULTIPLEXERS (DECODERS)

IC74HC154 DEMUX (1-16 DEMUX)
• IC74HC154(1-16 DEMUX) is shown in figure 4.43
Figure 4.43 1x16 IC74HC154
4.5.7 PARITY GENRATOR/CHECKER

IC 74LS280 – 9 BIT PARITY GENRATOR/CHECKER
• Logic symbol of IC 74LS280 – 9 bit parity genrator/checker is shown in figure 4.44
Figure 4.44 74x280 logic symbol

• A-I is a ‘9’ bit code => eight ‘8’ data bits and ‘1’ parity bit
• The i/p’s A-I have even no. of 1’s then Ʃeven output is HIGH &Ʃodd output LOW
• The i/p’s A-I have odd no. of 1’s then Ʃodd output is HIGH &Ʃeven output LOW
• Function table for 74x280 9 bit parity generator is shown in table 4.11
Number of Outputs
inputs(1’s) A-I
Ʃeven Ʃodd
that are HIGH
0,2,4,6,8 H L
(even no of 1’s)
1,3,5,7,9 L H
(odd no of 1’s)
Table 4.11 Function table for 74x280 9 bit parity generator
PARITY CHECKER
• When parity checker is used as an even parity checker,the no of (1’s) input bits should always
be even and when a parity error occurs the Ʃeven output goes LOW and the Ʃodd output goes
HIGH
• When this device is used as an odd parity checker,the no. of input bits should always be odd
and when a parity error occurs,the Ʃodd output goes LOW and the Ʃeven output goes HIGH
PARITY GENERATOR
• If parity generator is used as an even parity generator,the parity bit is taken at the Ʃodd output
because this output is a 0 if there is an even number of input bits and it is a 1 if there is an odd
number
• When it is used as an odd parit generator,the parity bit is taken at the Ʃeven output because it
is a 0 when the number of input bits is odd.
• Figure 4.45 parity generator and parity checker

Figure 4.45 parity generator and parity checker
4.5.8 PARALLEL BINARY ADDER/SUBTRACTOR

ADDERS
74LS283 4 Bit parallel adder
• Pin diagram of 74LS283 4 Bit parallel adder is shown in figure 4.46
Figure 4.46 74LS283 4 Bit parallel adder
Cascading of IC parallel adders

Question : design 8 bit parallel adder using 4 bit adder
• Figure 4.47 shows the design 8 bit parallel adder using 4 bit adder
Figure 4.47 design 8 bit parallel adder using 4 bit adder

2’s complement addition
• Positive and negative numbers including the sign bits can be added together is the basic
parallel adder circuit
• Figure 4.48 shows 2’s complement addition
Figure 4.48 2’s complement addition

2’s complement subtraction
• Figure 4.49 shows 2’s complement subtraction

Figure 4.49 2’s complement subtraction

4.5.9 MAGNITUDE COMPARATORS
• Basic schematic of magnitude comparator is shown in figure 4.50
• Table 4.12 shows truth table for 2 bit comparator
Figure 4.50 magnitude comparators

INPUTS OUTPUTS
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 1
0 1 0 1 0 1 0
0 1 1 0 0 0 0
0 1 1 1 0 0 1
1 0 0 0 0 0 0
1 0 0 1 1 0 0
1 0 1 0 1 1 0
1 0 1 1 0 0 1
1 1 0 0 0 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 1 1 0
Table 4.12 truth table for 2 bit comparator

74L85 4 bit magnitude comparator
• Figure 4.51 shows 74L85 4 bit magnitude comparator
• Truth table for magnitude comparator is shown in Table 4.13
Figure 4.51 74L85 4 bit magnitude comparator
Comparing Cascading inputs Outputs

inputs
I(A>B) I(A=B) I(A<B) (A>B) (A=B) (A<B)
AB
A>B X X X 1 0 0
A=B 1 0 0 1 0 0
X 1 X 0 1 0
0 0 1 0 0 1
0 0 0 1 0 1
1 0 1 0 0 0
A<B X X X 0 0 1
Table 4.13 truth table for magnitude comparator
Question : design an 8 bit comparator using 74LS85 IC’s
• Figure 4.52shows the design of an 8 bit comparator using 74LS85 IC’s
Figure 4.52 design of an 8 bit comparator using 74LS85 IC’s

UNIT-5
SEQUENTIAL LOGIC ICs & MEMORIES
5.1 All types of Latches and Flipflops IC’s:

5.1.1 74LS279A-Set-Reset Latch (Quad S-R Latch)
Fig.
Gated S-R Latch

Gated D Latch
5.1.2 74LS75-D latch (Quad gated D latches)

Edge triggered flip-flops:

5.1.3 74AHC74 – Dual D flip-flop
5.1.4 74HC112 Dual J-K flip-flop
Fig.
5.2 ASYNCHRONOUS COUNTERS
5.2.1 2- BIT ASYNCHRONOUS BINARY COUNTER
Fig.
Fig. Timing diagram
5.2.2 3- BIT ASYNCHRONOUS BINARY COUNTER

5.2.3 4-bit Asynchronous binary counter (using –ve edge triggered JK

flipflops)
5.2.4 Asynchronous Decade Counter (MOD 10 Counter / BCD Counter)

• MOD 10 /Decade asynchronous counter has ‘10’ stable states i.e from 0000 to 1001.
• When the 10th clock pulse is applied, the counter temporarily goes to 1010, but immediately
resets to 0000 because of feedback provided.
• It requires ‘4’ flip-flops, Let N=10, to obtain no. of flip-flops
N ≤ 2n i.e 10 ≤ 24 i.e 10 ≤ 16
‘n’ no. of flip-flops = 4
• Reset R = 0 for 0000 to 1001 (9)
R = 1 for 1010 (10)
R = x for 1011 (11) to 1111 (15)
Pb. Design a Modulo-12 ripple counter using 74X74

5.2.5 IC 74x90 – Asynchronous Decade counter

5.2.6 74LS93 4-bit Asynchronous Binary Counter
5.3 SYNCHRONOUS COUNTERS

A synchronous counter is one in which all the flipflops in the counter are clocked at the same time by
a common clock pulse.
Design of Synchronous counters:
Step:1 No. of flip-flops : N ≤ 2n
Step:2 State diagram
Step:3 Choice of flip-flops and excitation table
Step:4 Minimal expressions for excitations
Step:5 Logic diagram
5.3.1 2-bit Synchronous binary counter
5.3.4 74HC163 4-bit Synchronous binary counter

5.3.5 74X169 – Up/Down Counter
5.4 Decade counters

5.4.1 4-bit Synchronous decade counter
5.4.2 74HC190 up/down decade counter

5.5 Shift Registers

5.6 Shift Register IC’s

5.6.1 74X194 4 –bit Universal Shift Register

5.6.2 74X299 8 –bit Universal Shift Register

5.6.3 74HC195 4-bit Parallel- Access Shift Register

5.7 MEMORIES
• Memories are made up of registers.
• Each register in the memory is one storage location also called memory location.
• Each memory location is identified by an address
• The total no of bits that a memory can store is its capacity
• The capacity is specified in temrs of bytes (group of eight bits)
• The byte can split into two 4 bit units called as nibbles
• Byte can also be grouped into words
• Each register consists of storage elements,each of which stores one bit of data. A storage
element is called cell.
• The data stored in a memory by a process called writing and are retirved from the memory by
a process called reading.
• Figure shows how the read and write operation is performed in memory cell
Figure read and write operation

• 16 bit word contains 2 bytes
• 32 bit word contains 4 bytes
BLOCK DIAGRAM
• Data lines provide information to be stored in memory
• K-address lines are used to choose particular word among many
• The two control i/p’s READ and WRITE specify the direction transfer
• If K address lines we can access 2k memory words as shown in figure
Figure Block diagram of memory
CLASSIFICATION OF MEMORY
• Table shows the classification of memory.
CLASSIFICATION OF SEMICONDUCTOR MEMORIES

NON-VOLTAILE MEMORY VOLATILE MEMORY
READ ONLY READ/WRITE READ/WRITE MEMORY (RWM)
MEMORY MEMORY
RANDOM ACCESS NON-RANDOM
(ROM) (NVRAM)
ACCESS
Mask programmable EPROM SRAM FIFO
ROM (MPROM)
Programmable ROM EEPROM DRAM LIFO
(PROM) FLASH Shift register
Table Classification of semiconductor memories
• EEPROM-Erasable PROM
• EEPROM-Electically Erasable PROM

• SRAM- Static Random Access Memory
• DRAM- Dyamic Random Access Memory
• FIFO-First in First out
• LIFO-Last in First Out
• Non volatile memories can hold data even if power is turned off
• Volatile memories which can hold data as long as power is ON are called Static
RAMs(SRAMs)
• Dynamic RAMs(DRAM) stores the data as a charge on the capacitor and they need refreshing
of charge on the capacitor after every few milliseconds to hold the data even if power is OFF
• Read/write memories are those memories which allows both read and write operations
• EPROM & EEPROM are erasable memories in which the stored data can be erased and new
data can be stored
Comparision between sequential and random access memories
• Comparison between sequential and random access memories is shown in table

SEQUENTIAL ACCESS MEMORIES RANDOM ACCESS MEMORIES
• Uses sequential access method • Uses random access method
• Memroy is organized into units of • Each storage location in the memory has
data,called records.Records are accessed an unique address and it can be accessed
sequentially.If cuurent record is ‘1’,then independently of the other locations
in order to read record N,it is necessary
to raed 1 through N-1 records
• Memory access time is dependent on the • Memory access time is independent of
position of storage location storage location being accessed
• Memory access time is more & so • Memory access time is less
sequential access is slower than random
access
• Cheaper than random access memories • Random access memories are
comparatively costly
• Non volatile memories • May be volatile or non volatile

depending on physical characteristics
• Magnetic tapes is an example of • Semiconductor memories are random
sequential access memories access memories
Table comparison between sequential and random access memories
5.7.1ROM ARCHITECTURE
• ROM consists of transitor ‘T’ & switch ‘P’
• Figure shows the ROM architecture
Figure ROM architecture

• The transitor ‘T’ is driven by the word line
• The contents of cell is read if the transitor is connected to GND through switch ‘P’
• The bit line isa connected through a resistor to the power supply.
• Data is stored into the ROM when it is manufactured
• There are 4 types of ROM : Masked ROM,EPROM,EEPROM.
PROM (PROGRAMMBLE READ ONLY MEMORY)
• PROMs are programmed by user
• PROMs are one time programmable. once programmed, the information store is permanent
Single fused PROM cell
• When the fuse is intact, the memory cell is configured as logic ‘1’ & switch is ‘0’
• When the fuse is blown ,the memory cell is configured as logic ‘0’ & switch is ‘1’
• Single fused PROM cell is shown in figure
Figure single fused PROM

• The fuse uses material like nichrome and polycrystalline
• For blowing of fuses according to the trith table is called programming of ROM
• The user can program PROM with special PROM programmer
• The PROM programmer selectively burns the fuses according to the bit pattern to be stored.
This process is also known as burning of PROM
• Figure shows four byte PROM (4x8 -32 fuses with diodes)
Figure four byte PROM (4x8 -32 fuses with diodes)

Mask PROM (mask programmable READ ONLY memory)
• MPROM are programmed by manufacturer
• In MPROM the user specifies the data to be stored to the manufacture of the memory.
• The data pattern specified by the user are programmed as a part of the fabrication process.
• Once programmed the data pattern cannot be changed.This MROM are generally referred as
ROM
EPROM
• EPROM use MOS. They store 1’s and 0’s as a packet of charge in a buried layer of the IC
chip
• EPROM can be programmed by the user with a special EPROM programmer
• We can erase the stored data in EPROM by exposing the chip to ultraviolet light through its
quartz window for 15 to 20 minutes.
• The chip can be reprogrammed
• This memory is ideally suitable for product development, experimental projects since this
chip can be used many times
EPROM programming
• When erased each cell in EPROM contains 1.Data is introduced by selectively programming
0’s into the desired bit locations.
• During programming address and data are applied to address and data pins of the
EPOM,when the address and data are stable, program pulse is applied to the program i/p of
the EPROM
• The program pulse duration is around 50ms and its amplitude depends on EPROM IC. It is
typically 5.5.v to 25v
• In EPROM it is possible to program any location at any time either individually ,sequentially
or at random
EEPROM
• EEPROM also use MOS circuitry
• EEPROM allows selective erasing at the register level rather than erasing all the information,
since the information can be changed by using electrical signals
• The EEPROM memory also has a special chip erase made by which entire chip can be erased
in 10ms.This time is small as compared to time required to erase EPROM
• EEPROMs are expensive.
5.7.2 TYPES OF ROM
• Table shows types of ROM

Table types of ROM

BASIC STRUCTURE OF ROM
• Block diagram and truth table of ROM is shown in figure
Figure Block diagram and truth table of ROM

5.7.3 ROM APPLICATION
• Used to store programs in microprocessor systems & computer memory
• Used to store data like lookup tables and constants which is referred by the computer
programs
• Used to implement/realize complex or random combinational logic function.
5.7.4RAM (RANDOM ACCESS MEMORY) ARCHITECTURE

• The two major categories of RAM are
1. Static RAM (SRAM) uses flipflop
2. Dynamic RAM (DRAM)uses capacitors

5.7.4.1 SRAM
• Memories that consists of circuits capable of retaining their state as long as power is applied
are known as static memories
Figure SRAM using SR latch

• The storage part of the cell is modeled by an SR latch with associated gates to form a D latch.
SRAM using SR latch ,D latch is shown in figure
Figure SRAM using D latch

• The binary cell is capable of storing one bit in its internal latch
• The selct i/p enables the cell for reading and writing and the read/write i/p determines the
operation of the cell when it is selected
• ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ input is logic 1,read operation is performed otherwise write operation
When 𝑅𝐸𝐴𝐷/𝑊𝑅𝐼𝑇𝐸
is performed.
5.7.4.2 DRAM
• DRAM stored the data as a charge on the capacitor
• When bit line & word line goes HIGH, the MOSFET conducts and charge the capacitor
• When bit line & word line goes LOW,the MOSFET opens and the capacitor retains the
charge as shown in figure
Figure DRAM
Disadvantages
• It needs refreshing of charge on the capacitor after every fw milliseconds.
• Extra hardware is needed for refreshing
Comparison between SRAM & DRAM
• Table shows the Comparison between SRAM & DRAM

SRAM DRAM
• SRAM contains less memory cells • Dynamic RAM contains more
per unit area memory cells as compared to
SRAM per unit area
• It has greater access time than
• It has less access time hence faster
SRAM
• Stores data as a charge on the
• SRAM consists of flip flops of one
capacitor. It contains MOSFET &
bit each
capacitor
• Refreshing circuitry is required to
• Refreshing circuitry is not required
maintain charge on the capacitor
• Cost is less
• Cost is more
Table shows the Comparison between SRAM & DRAM

TUTORIAL SHEETS
UNIT – I
1. Calculate:
i. maximum output offset voltage caused by the input offset voltage Vios
ii. maximum output offset voltage caused by the input bias current IB. For an
inverting amplifier with R1 = 100 k & Rf = 10 k. Here 741 OP-Amp is used with
Vios = 6 mV IB = 500 nA.
2. Design a Schmitt trigger for UTP =0.5v and LTP = -0.5V.assume necessary data.
3. In the circuit shown below fig. R1=12kΩ, R2=5KΩ,R3=8KΩ,Rf=12KΩ. The inputs
are: V1=9v, v2=-3v & v3= -1v.Compute the output voltage.
4. Suggest modification in the given circuit of op amp to make it (i) inverting (ii) non-
inverting.
5. The input to an op amp differentiator circuit is a sinusoidal voltage of peak value 10 µV and
frequency of 2KHZ. If the values of differentiating components are given as R= 40 KΩ and
C=3µF. Determine the output voltage.
6. Design a differentiator circuit that will differentiate input signal with fmax=100Hz.
UNIT – II
1. Design and observe the waveforms of a 1KHZ square waveform generator using 555 timer
for duty cycle (a) D=0.25 (b) D=0.50.
2. Design a wide band pass filter with fL=500Hz and fH=2kHz, and a pass band gain =5 for
both sections of filter. Also determine the value of Q for the filter.
3. Design a narrow band pass filter using op-amp. The resonant frequency is 100Hz and Q = 2.
Assume c=0.1µF.
4. From the given component values find the free running frequency, control voltage Vc=10.9v,
Vcc=12v, R1=4.7k Ω & C1=1.1nF.
5. Design a sine wave generator for f0 = 500HZ and study its operation.
6. Design a LPF at a cutoff frequency of 400Hz and a pass band gain of -2.
7. Design a HPF at a cutoff frequency of 1 KHz and a pass band gain of 2.
UNIT – III
1. A 12-bit D to A converter has a full-scale range of 15 volts. Its maximum
Differential linearity error is ± 1/2 LSB.
i. What is the percentage resolution
its output voltage?
2. A dual slope ADC uses a16-bit counter and a 4MHz clock rate. The maximum input voltage
is+10v. The maximum integrator output voltage should be-8v when the counter has cycled
through 2n counts. The capacitor used in the integrator is 0.1 μF Find the value of the resistor R
of the integrator.
3. Calculate the values of the LSB,MSB and full scale output for an 8 bit DAC for the 0 to 10V
range.
4. What is the conversion time of a 10-bit successive approximation ADC if its input clock is
5MHz.
5. The LSB of a 6-bit D/A converter represents 0.1V. What voltage value will
be represented by the following binary words? i. 101010
ii. 110110
6. Calculate the number of bits required to represent a full scale voltage of 10V
with a resolution of 5mV approximately.
7. The LSB of a 9-bit DAC is represented by 19.6mv. If an input of 9 zero bits is represented by
0V.
(i) Find the output of the DAC for an input 101101101 & 011011011
(ii) What is the FSR of this DAC.
UNIT-IV
1. Design a CMOS transistor circuit with the functional behavior f(x) = (A+B’) (B+D’)(A+D’)
2. Using two 74x138 decoders design a 4 to 16 decoder?
3. Design a 5 to 32 line decoder using 3 to 8 line decoder, active low outputs with ‘2’ active low
and ‘1’ active high enable.
4. Realize F(A,B,C,D) = ∑m(0,1,2,5,6,7,9,12,15) using 4x1 multiplexer.
5. Design a 24-bit group ripple adder using 74x283 IC’s.
6. Realize the following expression using 74X151 IC F(Y) = AB+BC+AC
7. Design 1:8 de-multiplexer using two 1:4 de-multiplexer.
UNIT -V
1. Design a 3-bit binary synchronous counter using JK flipflops.
2. Design a Modulo-12 ripple counter using 74×74.
3. Design a conversion circuit to convert a T flip-flop to D flip-flop.
4. Design and implement 4-bit synchronous down counter using IC.
5. How many address & data lines are required to access all the locations of dynamic RAM cell
array specified below?
a) 4Mx4 b) 1Mx1 c)1Mx4 d)4Mx1
6. Design and implement FIFO shift register using IC’s.
7. Design an 8-bit parallel-in & serial-out shift register.

ASSIGNMENT QUESTIONS
UNIT-I
1. (a) Discuss about stability of an OP-Amp.

(b) Draw high frequency model of an OP-Amp and explain its working.
2. (a) With a neat diagram explain about construction of differential amplifier with three
OP
Amps.
(b) Explain how variable gain can be achieved with differential amplifiers.
3. (a) Explain the various techniques used to compensate for thermal drift in Op-Amps.
(b) Explain the effects of time on input-Offset voltage and input-offset current.
4. (a) Calculate:
i. maximum output offset voltage caused by the input offset voltage Vios
ii. maximum output offset voltage caused by the input bias current IB.
For an inverting amplifier with R1 = 100 k & Rf = 10 k. Here 741 OP-Amp is used with
Vios = 6 mV IB = 500 nA.
(b) Draw and explain the practical circuit for offset voltage measurement of OP Amps.
5. (a) Explain the operation of limiters using Op-Amp.
(b) Explain the characteristics of comparator and draw the circuit for comparator using
Op-
Amp.
6. (a) Draw the frequency response of practical differentiator and explain its working.
(b) Design a differentiator that will differentiate an input signal with fmax=100Hz.
(c) Mention some applications of Differentiation.
7. (a) Write about Instrumentation Amplifier with neat diagram.
(b) Design a practical integrator circuit to integrate a sinusoidal input of 10 mV and upto 1
KHz.
(c) Explain how Instrumentation amplifier can be used as Analog weight scale.
UNIT-II
1. (a) Mention the advantages and disadvantages of active filters over passive filters.
(b) Write the various Design steps of First order high pass Butter worth filter.
(c) Explain about frequency scaling in active filters.
2. (a) With a neat diagram explain about all pass filter.
(b) Determine the order of a low pass Butter worth filter that is to provide 40 dB
attenuation at ω/ωh = 2.
3.(a) Define the conditions on the feedback circuit of an amplifier to convert it into
an oscillator.
(b) What is VCO? Give two applications of it.
(c) Design a 60 Hz Active LPF.
4) (a) Write the specifications of NE555 timer IC.
(b) Design a 555 timer circuit whose output frequency is 2 KHz when the trigger
input signal frequency is 4 KHz.
(c) In the 555 monostable multivibrator circuit if RA = 10 kΩ determine the value
of C for output pulse duration of 1 m sec.
5) (a) Describe the application of 555 timer as pulsing buzzer.
(b) What are the functions of threshold and control voltage pins in 555 timer IC?
6) (a) How an symmetrical wave form generator can be constructed using 555 timer?
(b) If RA = 6.8 k, RB = 3.3 k, c = 0.1 _F in 555 astable multivibrator.
Calculate:
i. thigh
ii. tlow
iii. Free running frequency
iv. Duty cycle.
7) (a) Define the terms:
i. Free-running frequency fO
ii. Lock in range
iii. Capture range
iv. Pull in time.
(b) Differentiate between analog and digital phase detector.
UNIT-III
1.(a) Explain the difference between Analog to Digital converter and Digital to
Analog converters through underlying equations.
(b) Illustrate one application each of Analog to Digital and Digital to Analog
converters.
2. (a) Write a note on multiplying DACs.

(b) Compare and contrast R-2R ladder type and weighted resistor type DACs.
(c) List the specifications of a Digital-to-Analog converter IC, 1408.
3. (a) Explain the operation of parallel comparator type ADC with the help of a
neat diagram.
(b) The LSB of a 6-bit D/A converter represents 0.1V. What voltage value will
be represented by the following binary words?
i. 101010
ii. 110110
4. (a) Explain the operation of a Successive Approximation type analog to digital
converter.
(b) Calculate the number of bits required to represent a full scale voltage of 10V
with a resolution of 5mV approximately.
5. (a) Compare R-2R and weighted resistor types of DACs.
(b) Write short notes on A/D converters.
(c) Define the following terms as related to DAC:
i. Linearity
ii. Resolution.
6. (a) Explain the operation of a multiplying DAC and mention its applications.
(b) A 12-bit D to A converter has a full-scale range of 15 volts. Its maximum
differential linearity error is ± 1/2 LSB.
its output voltage?
7. (a) Explain the operation of an 8-bit tracking type Analog to Digital converter.
(b) Compare the conversion times and efficiencies of 8-bit tracking type and successive
approximation type Analog to Digital converters.
UNIT-IV
1. (a) Design a CMOS transistor circuit with the functional behavior
(b) Distinguish between static and dynamic power dissipation of a CMOS circuit?
Derive the expression for dynamic power dissipation?
2. (a) Draw the circuits of NAND and NOR gates using CMOS logic and explain their operation
with truth tables.

(b) Compare the performance of various logic families with reference to power dissipation,
propagation time delay, Fan in and Fan out.
3. (a) Draw the CMOS circuit diagram of tri-state bu_er. Explain the circuit with the help
of logic diagram and function table.
(b) Design a CMOS transistor circuit that realizes the following Boolean function.
Also explain its functional operations.

4. (a) Give the logic diagram of 74_139? Explain with the help of truth table?
Using this device design a 3 to 8 decoder and provide the truth table?
(b) Design a 16-bit comparator using 74_85 ICs?
5. (a) Design a 32 to 1 multiplexer using four 74×151 multiplexers and 74×139 decoder.
(b) Realize the following expression using 74×151 IC
f(Y ) = AB + BC + AC
6. Design the 32 input to 5 output priority encoder using four 74LS148 and gates?
7. (a) With the help of logic diagram explain 74x157 multiplexer.
(b) Design a full subtractor with logic gates?
(c) Using the above subtractor design a 8-bit ripple subtractor.
UNIT-V
1. (a) Design a 4-bit binary synchronous counter using 74x74.
(b) Design a modulo-60 counter using 74x163 ICs.
2. (a) Design a modulo-8 binary counter and decoder with glitch-free outputs. Explain the
Operation.
(b) Design a modulo-100 counter using two 74×163 binary counters.
3. (a) Design a conversion circuit to convert a T flip-flop to D flip-flop.
(b) Explain the operation of parallel-in-parallel-out shift register.
4. (a) Draw the circuit diagram, function table of a controlled D- latch.
(b) Explain the operation of a D latch through suitable timing diagrams for various
possibilities of input.
(c) What are the problems encountered while using a D latch? Suggest methods to overcome
these problems.
5. Draw the logic diagram of 74×194 and explain the operation.
6. Write short notes on:
i. Edge triggered flip-flop

ii. Master slave flip-flop
7. (a) Compare SRAM and DRAM. (b) Compare various types of ROM Memories.
UNIT WISE IMPORTANT QUESTION QUESTIONS
UNIT-I
PART-A-UNIT-I (2 or 3 marks)
1. Mention the advantages of integrated circuits.

2. Define an operational amplifier.
3. Mention the characteristics of an ideal op-amp.

4. Define input offset voltage
5. What is slew rate? Discuss the methods of improving slew rate.
6. Draw the circuit of lossy integrator showing initial conditions?
7. What is the function of voltage regulator?
8. Explain why integrators are preferred over differentiators in analog
9. What voltage options are available in 78xx and 79xx voltage regulators?
10. Define thermal drift?
11. Why do we use Rcomp resistor?
12. What is the gain of non inverting op-amp
PART-B-UNIT-I (5-10 marks)

1. Derive the gain for non inverting op-amp.
2. Explain the following terms in an OP-AMP.
1.Input Bias current 2. Input offset voltage 3. Input offset current
3. Explain various DC and AC characteristics of an op.amp. Distinguish between ideal and
practical characteristics.
4. Write a technical note on frequency response characteristics of differential amplifier. State the
importance of frequency compensation.
5. What is t instrumentation amplifier? What are the required parameters of an instrumentation
amplifier? Explain the working of instrumentation amplifier with neat circuit diagram.
6. Explain various DC and AC characteristics of an op.amp. Distinguish between ideal and
practical characteristics.
7. With circuit and waveforms explain the application of OPAMP as differentiator and write the
advantages of practical differentiator.
8. Explain practical integrator circuit using IC 741.
9. Explain the operation of a Schmitt trigger circuit using IC 741.
10. Explain the internal structure of voltage regulator IC 723. Also draw a low voltage Regulator
circuit using IC 723andexplain its operation.
UNIT-II
PART-A-UNIT-II (2 or 3 marks)
1. Why active filters are preferred?

2. What is meant by cut off frequency of a high pass filter and how it is found out in a first order
high pass filter
3. List the applications of 555 timer in monostable mode of operation
4. List the basic blocks of IC 555 timer?
5. List the applications of 565 PLL
6. Define lock range in PLL.
7. Define capture range in PLL.
8. Define pass band and stop band of a filter.
9. What is the difference between triangular and sawtooth wave.
10. Draw a circuit to for converting a square wave into a series of positive pulses.
PART-B-UNIT-II (5-10 marks)
1. Design a second order low pass filter.

2. Draw the circuit of a 1st order low pass filter and derive its transfer function.
3. Explain the functional block diagram of 555timer.
4. Explain working of PLL using appropriate block diagram.
5. Draw the block diagram of an Astable multivibrator using 555timer and derive an expression for
its frequency of oscillation.
6. Draw the block diagram of monostable multivibrator using 555timer and derive an expression
for its frequency of oscillation.
7. Derive the expression for i) capture range in PLL ii) Lock in range in PLL.
8. Draw the circuit of a 1st order band pass filter and derive its transfer function.
9. Draw the circuit of a all pass filter and derive its transfer function.
10. Derive the voltage to frequency converter factor for VCO.
11. Explain triangular waveform generator using IC 741
12. Design second order high pass filter.
UNIT-III
PART-A-UNIT-III (2 or 3 marks)
1. Define data converters?

2. Name the different DAC techniques.
3. Define weighted resistor type DAC.

4. Define R-2R Ladder DAC.
5. Give applications of data converters.
6. Give the drawbacks of weighted resistor type DAC.
7. What output voltage would be produced by monolithic DAC whose output range is 0 to 10V and
whose input binary is 0110?
8. Calculate the values of the full scale output for an 8 bit DAC for the 0 to 10V range.
9. How many levels are possible in a two bit DAC what is its resolution if the output range is 0 to
3V.
10. Calculate basic step of 9 bit DAC is 10.3 mV. If 000000000 represents 0V, what output
produced if the input is 101101111?
PART-B-UNIT-III (5-10 marks)
1. Explain in brief the principle of operation of successive Approximation ADC.

2. Explain the operation of parallel comparator type ADC with the help of a
3. neat diagram.
4. Explain the operation of a multiplying DAC and mention its applications.
5. Explain the operation of an 8-bit tracking type Analog to Digital converter.
6. Compare the conversion times and efficiencies of 8-bit tracking type and successive
approximation type Analog to Digital converters.
7. In which type of Analog to Digital converter, a Digital to Analog converter is
used? Explain its operation in detail.
8. Explain the operation of weighted resistor DAC.
9. What is the significance of linearity and conversion time in ADC.
10. List important specifications of Analog to Digital converter and Digital to
Analog converters indicating their typical values.
11. Explain the operation of counter type ADC
12. With neat diagram, explain the working principle of inverter R-2R ladder DAC.
13. Explain the working of a dual slope A/D converter
14. A 12-bit D to A converter has a full-scale range of 15 volts. Its maximum
differential linearity error is ± 1/2 LSB.


its output voltage?

UNIT-IV
PART-A-UNIT-IV (2 or 3 marks)
1. Design CMOS transistor circuit for 2-input NOR gate.

2. Compare various logic families.
3. Explain the CMOS transmission gate.
4. Explain with neat diagram interfacing of CMOS gate driving TTL gates.
5. Explain the DC Noise margin with reference to TTL gate.
6. Sketch the 4x16 decoder using 74LS138.
7. Write a short note on priority encoder.
8. Illustrate the principle of 74LS151 IC.
9. Explain the DC Noise margin with reference to CMOS gate.
10. Explain the term Voltage levels for logic ‘1’ & logic ‘0’ with reference to TTL gate.
PART-B-UNIT-IV (5-10 marks)
1. Distinguish between static and dynamic power dissipation of a CMOS circuit?

Derive the expression for dynamic power dissipation?
2. Design a CMOS 4-input AND-OR-INVERT gate. Draw the logic diagram and
function table.
3. Compare the performance of various logic families with reference to power
dissipation, propagation time delay, Fan in and Fan out.
4. Design a CMOS transistor circuit that realizes the following Boolean function.
Also explain its functional operations.

5. Draw the circuits of NAND and NOR gates using CMOS logic and explain
their operation with truth tables.
6. Using two 74_138 decoders design a 4 to 16 decoder?
Give the logic diagram of 74_139? Explain with the help of truth table?
7. Design a 32 to 1 multiplexer using four 74×151 multiplexers and 74×139
decoder.
8. Design the 32 input to 5 output priority encoder using four 74LS148 and gates?
9. Design 16 bit adder using two 7483 ICs.
10. Explain the following terms with reference to CMOS logic. i. Logic Levels ii. Noise margin iii.
Power supply rails iv. Propagation delay
11. Explain operation of 74LS85 IC.
12. Illustrate parity generator/checker IC.
UNIT-V
PART-A-UNIT-V (2 or 3 marks)
1. Explain static RAM.

2. Classify types of ROMs.
3. What is race around condition? How it is avoided?
4. Draw and explain the working of master slave JK flip-flop.
5. Indicate the pin configuration of IC74x74.
6. How synchronous counters differ from asynchronous counters?
7. What do you mean by sequential circuit? Explain with the help of block diagram.
8. Draw and explain 4 bit Johnson counter.
9. Explain the operation of a D latch through suitable timing diagrams for various
possibilities of input.
10. Compare static RAM and dynamic RAM.
PART-B-UNIT-V (5-10 marks)
1. Draw the basic cell structure of Dynamic RAM. What is the necessity of refresh cycle? Explain
the timing requirements of refresh operation.
2. Discuss in detail ROM Architecture.
3. Design a modulo-100 counter using two 74×163 binary counters.
4. Design a Modulo-12 ripple counter using 74×74.
5. Draw and explain 4 bit universal shift register.
6. Design a conversion circuit to convert a T flip-flop to J-K flip-flop
7. Explain the operation of asynchronous decade counter.

8. Design a 3-bit LFSR counter using 74_194? List out the sequence assuming
that the initial state is 10.
9. What is ROM. Write the applications of ROM.
10. Compare different types of ROM memories.
OBJECTIVE QUESTIONS
UNIT - 1
1. Example of linear IC is
a. Logic gate 7400 b.timer IC 555 and IC 741
c. Mux d.microprocessor 8085

2. 74IC is available in
a.8,10,14 pin configuration b.16,18,20 pin configuration
c.5,9,12 pin configuration d.none

3. Which is not the internal circuit of op-amp?
a.differential amplifier b.output driver c.level translator d.clamper

4. If input frequency exceed the slew rate the output will
a.distorted b.not distorted c.amplified d.remain same

5. The operational amplifier can be nulled by
a.using an offset voltage compensating network
b.using an error minimizing resistance
c.cutting off the power supplies
d.all the above

6. Slew rate is defined by
a.dv/dt(max) b.di/dt (max) c.dp/dt(max) d.none of the above

7. The practical value of CMRR for 741 op-amp is
a.30 dB b.40dB c.90dB d.20dB

8. Voltage follower is a special case of
a.inverting configuration b.non-inverting configuration c.differential configuration d.none
UNIT – 2
1. The first order low pass butterworth filter is used in
2. First order low pass butterowrth filter is also called as
3. A first order can be converted to second order type by using an additional --------- network.
4. The frequency at which the gain is 0.707 times the gain of the filter in pass band is called-----
-----frquency
5. The voltage gain magnitude equation for the second order high pass filter is --------
6. For wide band pass response fH must be --------- than fL
7. Wide band reject filter consists of a ------------ and --------------sections
8. All pass filters are also called as ------------
9. --------------converts electrical energy from DC to AC
10. The wein bridge oscillator is useful at------------frequencies
11. The 555 time is available in two package styles---------and---------
12. The operating frequency of 565 PLL ranges from --------- to --------------
UNIT – 3
1. The DACs use ------- to account for variations in logic levels
2. The value of sampling frequency for signal recovery should be qual to or ------twice the
maximum frequency of the signal to be digitized
3. The resolution of n-bit DAC is--------
4. The range of resistors used in weighted resistor type DAC is------------
5. The unit to specify the linearity of a commercial D/A converter is----------
6. The counter type is------------type of ADC
7. The no. of comparators required for n-bit A/D converters are--------
8. The dual slope interfacing type adc,the output is independent of the ------of the passive
components R and C
9. The counter type ADC is used to read------------voltages
10. Maximum conversion time of staircase of ADC is--------------
UNIT - 4
1. The propagation delay time of schottky TTL is --------- when compare to TTL
2. A -----------logic family uses only MOS devices
3. A figure of meri of a digial IC is given by the product of -------------- and ----------
4. A measure of the nosie which can be tolerated by a logic circuits is called----------
5. ----------signifies the number of a a gate
6. Outpus of -------- gates with active pull up must not be connected together
7. -----------------input terminal of a TTL gate gives logic 1

8. The CMOS counterpart of an open collector TTL gate is ----------------
9. -------------gates with open collector output can be used in wired logic operation
10. In a decoder,the relation between i/p and o/p is------------
UNIT - 5
1. Depending on the timing of the signals,sequential circuis are classified as --------- and ----
2. When S=1 and R=0 ,for any value of present sae he flipflop is said to be-------
3. The phenomenon of interpreting unwanted signals on J and K while closk pulse is high is
called as-----------
4. The -------IC is a JK flipflop with active low clock input
5. In a master slave flipflop,the master is enabled when the gate is---------
6. ----------flipflop is said to be transparent
7. IC -----------consists f 2 independent +ve edge triggered D flip flops wih asynchronous
direct inputs.
8. If all the flipflops are triggered by the same clock in a counter,then the counter is ------
counter
9. A -----------allows shifting of data either to the left or right
10. In a --------------the serial o/p is connected back to the serial input.
PREVIOUS UNIVERSITY EXAMINATION

QUESTION PAPERS
REFERENCES:
1. Digital Fundamentals – Floyd and Jain, Pearson Education, 8th Edition, 2005.
2. Linear Integrated Circuits –D. Roy Chowdhury, New Age International
(p) Ltd, 2nd Ed., 2003.
3. Digital Design: Principles and Practices, 4/e, John F. Wakerly, 2008, Pearson Education.

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LINEAR AND DIGITAL IC APPLICATION

LINEAR AND DIGITAL IC APPLICATIONS

B.Tech. III Year I Sem. LTP C

1. Op-Amps & Linear ICs – Ramakanth A. Gayakwad, PHI, 2003.

1. Linear Integrated Circuits –D. Roy Chowdhury, New Age International

The main objectives of the course are:

On completion of this course, the students will have:

S.NO. TOPIC NAME PAGE

Definition of INTEGRATED CIRCUIT

ADVANTAGES OF INTEGRATED CIRCUITS (over circuits made by interconnecting

1. Miniaturization and hence increased equipment density.

OP-AMP CIRCUIT SYMBOL:

Fig: Op-Amp Circuit Symbol

Fig. Various packages of µA741 op-amp

PIN DIAGRAM OF IC 741

1.3 IDEAL OP-AMP

Fig (a) Ideal op-amp

An ideal op-amp would exhibit the following electrical characteristics:

Fig. Ideal voltage transfer curve

• The graphic representation of the output equation is shown in fig. in which

1.4 EQUIVALENT CIRCUIT OF AN OPAMP (PRACTICAL OP-AMP):

• In practical op-amp, AoL ≠ ∞, Ri ≠ ∞and Ro ≠ 0.

• Basically the op-amp is a voltage controlled voltage source.

• Hence the output side is represented by a thevenin’s equivalent model.

Fig. (b) Equivalent circuit of OP-AMP

• The internal block diagram of an opamp is shown in the fig.

Fig. Internal circuit of OP-AMP

1.6 MODES OF OPERATION OF OP-AMP

1.6.1 OPEN LOOP OPAMP MODE

1.6.2 CLOSED LOOP OP-AMP MODE

1.6.3 INVERTING AMPLIFER

Fig. Inverting amplifier

Voltage gain < Unity

Where Va is the voltage at node ‘a’

1.6.4 PRACTICAL INVERTING AMPLIFIER

fig(a) Equivalent circuit of a practical op-amp inverting amplifier

Fig (b) Simplified circuit by using Thevenin’s equivalent.

Input Resistance Rif (with feedback)

Fig (c) Equivalent circuit for computing Rof.

1.6.5 NON-INVERTING AMPLIFIER

Fig. Non-inverting amplifier

As no current flows into the op-amp

• Thus, for non-inverting amplifier the voltage gain,

voltage gain > unity

1.6.6 PRACTICAL NON-INVERTING AMPLIFIER

Fig . Equivalent circuit of non-inverting amplifier using low frequency model

1.6.7 VOLTAGE FOLLOWER

fig. voltage follower

therefore, v0 = vi i.e voltage gain AcL= unity

Difference mode and common mode gains:

Substitute v1 & v2 in eq(3), we get

• ADM is voltage gain for the difference signal.

1.6.9 COMMON MODE REJECTION RATION: (CMRR)

1.7 OP AMP CHARACTERISTICS

1.8 DC CHARACTERISTICS OF AN OP-AMP

1.8.1 Input bias current (IB)

• For 741, a bipolar op-amp, the bias current is 500nA or less

1.8.2 Input offset current (IOS)

• For BJT op-amp offset current Ios=200mA

KCL at node ‘a’ gives,

fig. inverting amplifier with T- feedback network

• To design a T-network, first pick Rt<<Rf/2

1.8.3 Input offset voltage (Vios)

Effect of Vios on the output of non-inverting & inverting op-amp amplifiers: