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Schematic Diagrams

Appendix B:Schematic Diagrams


This appendix has circuit diagrams of the C5505/C5505Q/C5505C/C5505Q-C notebook’s PCB’s. The following table
indicates where to find the appropriate schematic diagram.

Diagram - Page Diagram - Page Diagram - Page Table B - 1


Schematic
System Block Diagram - Page B - 2 SB700-1 - Page B - 15 VCORE_Core - Page B - 28
Diagrams
Clock Generator - Page B - 3 SB700-2 - Page B - 16 0.9V, 1.8V, 1.8VS, 1.5VS - Page B - 29

B.Schematic Diagrams
CPU-1 - Page B - 4 SB700-3 - Page B - 17 1.1VS, 1.2V, 1.2VS - Page B - 30

CPU-2 - Page B - 5 SB700-4 - Page B - 18 VDD3, VDD5 - Page B - 31

CPU-3 - Page B - 6 New Card, Mini PCIE - Page B - 19 Charger, DC In - Page B - 32

CPU-4 - Page B - 7 CCD, 3G, SATA ODD - Page B - 20 Click Board - Page B - 33

DDRII SO-DIMM_0 - Page B - 8 USB, Fan, TP, Multi-Con - Page B - 21 Audio Board/USB - Page B - 34


DDRII SO-DIMM_1 - Page B - 9 Card Reader/LAN JMC261 - Page B - 22 Power Switch Board - Page B - 35

RS780M-1 - Page B - 10 SATA HDD, LED, MDC, BT - Page B - 23 External ODD Board - Page B - 36
Version Note
RS780M-2 - Page B - 11 Audio Codec ALC272 - Page B - 24
The schematic dia-
grams in this chapter
RS780M-3 - Page B - 12 KBC ITE IT8502E - Page B - 25
are based upon ver-
LVDS, Inverter - Page B - 13 System PWR, 2.5V - Page B - 26 sion 6-7P-C5505-002.
If your mainboard (or
HDMI, CRT - Page B - 14 other boards) are a lat-
PWRGD, RST - Page B - 27 er version, please
check with the Service
Center for updated di-
agrams (if required).

B - 1
Schematic Diagrams

System Block Diagram


CLEVO C5500Q
EXTERNAL CLOCK GENERATOR UN BUF F E RED D D R2 CP U
AMD S1G2 CPU Ch annel A S O DI M M 0 Te mp e rat u re s en so r
CL I CK BO A RD I CS 9 L P RS 4 8 0
64 PIN 638-Pin uFCPGA 638
6- 71 -E51 Q2 -D0 1 Channe l B UN BUF F E RED D D R2
S O DI M M 1
DD R II
AUD I O BO AR D HDT
US B X 1
6- 71 -C4 50 8 -D0 2A

OU T
P OW ER S W I TCH BO A RD
Hyp erTransport (HT)

IN
P ow e r s w i tch + H ot k ey X 3

6- 71 -E51 QS- D01


L V DS CO N RS780M(C)
B.Schematic Diagrams

EXTER NAL O DD B OA RD Hy pe rTra nsport LI NK 0 CPU I /F


H D MI CO N
I NTEG RATED G RAP HIC S
6- 71 -E51 QN- D01 LVD S/ CRT
Sheet 1 of 35 C RT C ON 1 X 8 PCI E I /F
6-7P-C5505-002 1 X 4 PCI E I /F WI TH SB
System Block PCB 5? 1 ? ? : 4 X 1 PCI E I /F

Diagram 6-71-C5500-D02
4 65 PI N FC BG A I n t S pe a k er L

6-71-E51Q2-D01A GPP PCIE IN TERFACE


6-71-C4508-D02A 100 MHz I NT M I C
P CI E3 P CI E0 P CI E2
6-71-E51QS-D01A MD C
PCIE
6-71-E51QN-D01 M I NI P CI E- 3 G Ca rd R ea d er \L a n NE W CA RD M IN I P CI E- W L
USB4 JM C2 6 1 USB7 USB5 X4
AL C 2 7 2 CO DE C/ AUDIO B OARD
S B700 HD AUDIO I/F TP A6 0 1 7 AM P
He a d pho n e J ac k
US B2. 0 (1 0 ) 24 MHz
US B 2.0 SA TA I I (4 PO RTS)
480 Mbps AZALI A H D AUDI O MI C I n J a c k
US B# 2 US B# 1 US B #0 AC 97 2 .3
P ort 2 P ort 1 P ort 0
ATA 6 6/ 10 0/ 13 3
S YS TEM P W R,2 . 5 V I n t S pe a k er R
1 .8 V S ,3 .3 V S ,5 VS , 3 .3 V ,1 .2 V S AUDIO BOARD SP I I/F

Bl u e to o th C CD
LPC I/ F
AC PI 1. 1
USB8 U SB9 or USB6 HD D
P W RG D, RS T IN T RTC
SATA I/F S ATA# 1
5 49 PIN FC BG A
S ATA O DD
S ATA #4
VC OR E_VD D _CO RE
CP U_ VD D0 , CP U_ VD DD 1 NEW CA RD ONLY C4500 32.768 KHz

0 .9 V ,1 .8 V , LPC
1 .8 V S ,1 .5 V S
33 MHz
1 .1 V S ,1 .2 V ,1 . 2 VS ,1 . 2 V_H T 32.768 KHz
KB C I T8 5 0 2 E
128pins LQFP
VC OR E_VD D _NB CP U F AN
1 4*1 4*1 .6 mm
D EB UG P O RT

VD D 3 , VD D 5

B ATTERY CH AG ER I NT PS2
KE YBO ARD TO UCH P A D S P I R OM
CH AR GE R,D C I N

B - 2 System Block Diagram


Schematic Diagrams

Clock Generator
3 .3 VS CL K _ V DD 1. 2 V S C L K _ V DD IO

L3 2 H C B 1 6 0 8K F -1 21 T 2 5 -06 . 1U _ 1 6V _ 0 4 . 1 U _ 16 V _ 0 4 .1 U_ 1 6 V _ 0 4
L54 H C B 1 60 8 K F -1 2 1 T 25 -0 6 . 1 U _ 16 V _ 0 4 .1 U_ 1 6 V _ 0 4 . 1 U _1 6 V _ 0 4

C 321 C2 6 0 C2 7 0 C2 9 1 C2 9 2 C 241 C 2 38
C5 2 7 C 2 39 C 24 0 C2 9 3 C2 3 7 C2 5 8 C2 8 9 C 306
1 U _ 16 V _ 0 6 1 0 U _6 . 3 V _ 0 8
1 0U _ 6. 3 V _ 0 8
.1 U_ 1 6 V _ 0 4 . 1 U _ 1 6 V _0 4 . 1 U _1 6 V _ 0 4
. 1U _ 16 V _ 0 4 . 1 U _ 1 6V _0 4 . 1U _ 16 V _ 0 4 Pla ce n ext to VD D48

Pl ac e v e ry P la ce w ithi n 0 .5" of
cl ose t o U1 C LK GEN

CL K _ V D D L31 H C B 1 60 8 K F -1 2 1 T2 5 -0 6 U4

C 2 90 Z0201 4 50 CP U _ CL K P _ R RN 3 0 1 4 * 0 _4 P 2 R _0 4 _ 4 mi l _ sh o rt
7 V D DA _ 2 7 C P U K G0 T _L P R S 49 2 3 CPU_CL KP 5
. 1 U _1 6 V _ 0 4 C P U _ C L K N _R
CPU_CL KN 5

B.Schematic Diagrams
G N D A _2 7 C P U K G0 C _L P R S
L25 H C B 1 60 8 K F -1 2 1 T2 5 -0 6 Z0202 56
60 V D DR E F
CL K _ V D D
C 2 59 G ND RE F 30 NB G F X _ CL K P _ R RN 3 4 1 4 * 0 _4 P 2 R _0 4 _ 4 mi l _ sh o rt
63 A TI G0 T _L P R S 29 N B G F X _ C L K N _R 2 3 NBGFX_CLKP 10
. 1 U _1 6 V _ 0 4 NBGFX_CLKN 10
26 VD D4 8 A T I G0 C _L P R S 28 GF X _ C L K P _R
48 VD DA T IG A TI G1 T _L P R S 27 GF X _ C L K N _ R
C L K _ V DD
55
35
16
VD
VD
VD
DC P U
D H TT
DS B _ S R C
A T I G1 C _L P R

S R C 7 T_ L P R S / 2 7M H z _ S S
S
6
5 Z 0 20 7
Sheet 2 of 35
40 VD
VD
DS R C
DS A T A
S R C 7 C _ L P R S / 27 M H z _N S

37 N B S LI N K _ C L K P _ R RN 3 1 1 4 * 0 _4 P 2 R _0 4 _ 4 mi l _ sh o rt
SBLINK_CLKP 10 Cl ock c hip ha s in ter na l se ri al te rmin atio ns
Clock Generator
25 S B _ S R C 0 T _L P R S 36 N B S LI N K _ C L K N _ R 2 3
CL K _ V D DIO 47 VD D A T I G _I O S B _ S R C 0 C _L P R S 32 S B S R C _ C L K P _R SBLINK_CLKN 1 0 for differencial pa irs , exte rn al r es ist ors are
RN 3 3 1 4 * 0 _4 P 2 R _0 4 _ 4 mi l _ sh o rt
SBSRC_CLKP 14
34 VD DC P U_ IO S B _ S R C 1 T _L P R S 31 S B S R C_ CL K N _ R 2 3
VD DS B _ S R C_ IO S B _ S R C 1 C _L P R S SBSRC_CLKN 14 r es er ve d f or de bu g p ur po se .
11
Layout note: 17 VD DS R C_ IO 1 22 N B G P P _ C L K P _R
VD DS R C_ IO 2 S R C 0 T _L P R S 21
PLACE CRYSTAL WITHIN 500 NB G P P _ CL K N _ R
S R C 0 C _L P R S 20 P C I E _ E X P C A R D _C L K P _ RR N 3 5 1 4 * 0 _4 P 2 R _0 4 _ 4 mi l _ sh o rt
1 S R C 1 T _L P R S 19 2 3 PCIE_EXPCARD_ CLKP 18
MILS OF ICS9LPRS480 G ND 48 S R C 1 C _L P R S
P C I E _ E X P C A R D _C L K N _ R
PCIE_EXPCARD_ CLKN 1 8
24 15 P C I E _P E 1_ C L K P _ R
46 G ND A TI G1 S R C 2 T _L P R S 14 P C I E _P E 1_ C L K N _ R
52 G ND CP U S R C 2 C _L P R S 13 P C I E _P E 2_ C L K P _ R RN 3 7 1 4 * 0 _4 P 2 R _0 4 _ 4 mi l _ sh o rt
43 G ND HT T S R C 3 T _L P R S 12 P C I E _P E 2_ C L K N _ R 2 3 PCIE_CR_CLKP 21
X2 33 G ND SATA S R C 3 C _L P R S 9 PCIE_CR_CLKN 21
P C I E _P E 3_ C L K P _ R RN 3 6 1 4 * 0 _4 P 2 R _0 4 _ 4 mi l _ sh o rt
2 1 10 G ND S B _ S RC S R C 4 T _L P R S 8 P C I E _P E 3_ C L K N _ R 2 3 PCIE_WLAN_ CLKP 18
R1 7 5 PCIE_WLAN_ CLKN 18
18 G ND S RC 1 S R C 4 C _L P R S
*1 M_ 0 4 G ND S RC 2
C 281 1 4 . 31 8 MH z C3 2 0 Z0203 61 42
X1 S R C 6 T / S A T A T _L P R S
Z 02 0 5 R1 7 9 Z0204 62 41
2 7 P _ 5 0 V _0 4 27 P _ 5 0 V _ 04 * 0 _0 4 0 2 _5 m i l _s h o rt X2 S R C 6 C / S A T A C _L P R S
Z0209 23 54 NB H T RE F _ C L K P _ R RN 3 2 1 4 * 0 _4 P 2 R _0 4 _ 4 mi l _ sh o rt
P C I E _ E X P C A R D _ C L K R E Q# 45 C LK R EQ 0# H T T 0 T/ 66 M _L P R S 53 NB H T RE F _ C L K N_ R 2 3 NBHT_CLKP 10
C LK R EQ 1# H TT 0 C / 66 M _L P R S NBHT_CLKN 10
Z0210 44
Z0211 39 C LK R EQ 2# 64 Z 0 20 8 R 1 76 3 3 _ 1 %_ 0 4
W L A N _ C LK R E Q # 38 C LK R EQ 3# 4 8 MH z_ 0 CLK_48M_USB 15
C LK R EQ 4#
R1 3 3 8 . 2 K _0 4 Z0206 51 59 S E L _ HT 6 6
CL K _ V DD PD # R E F 0/ S E L _H T T6 6 58
C2 4 9 SEL _ SATA R1 5 8 1 5 8 _ 1% _ 0 6
R E F 1 /S E L _ S A T A NB_OSC 10
* 1U _ 1 6V _ 0 6 2 57 S E L _ 27 M H z
7 ,8 ,1 5 S CL K 0 3 S M B CL K R E F 2/ S E L _2 7
7 , 8 , 1 5 S D A TA 0 S M B DA T RS780 1.1 V
G ND 5
G ND 1 T h er ma l _ GN D5 G ND 6 R1 5 1
G ND 2 T h erm a l _ GN D1 T h er ma l _ GN D6 G ND 7 9 0. 9 _ 1 % _ 06
2008/03/18 G ND 3 T h erm a l _ GN D2 T h er ma l _ GN D7 G ND 8
G ND 4 T h erm a l _ GN D3 T h er ma l _ GN D8 G ND 9
T h erm a l _ GN D4 T h er ma l _ GN D9

I C S 9 LP R S 4 8 0
R 44 6
SB_ 14.318M_OSC 1 4
*0 _ 0 4 02 _ 5 m li _ s ho rt

CL K _ V D D 0514-J
add for SB710

C L K _ V DD
* d e f a u tl

1 6 6 MH z 3 . 3 V s i ng l e en d e d H T T c ol c k
R 14 2 R1 6 0 R1 4 3 S E L _ HT T 6 6
R1 3 4 R1 3 5 0* 1 0 0 M H z d fi f e re n t i al H TT c l o ck
* 8. 2 K _ 0 4 *8 . 2 K _ 04
S E L_ H T6 6 * 8 . 2 K _0 4 * 8 . 2K _0 4 8 . 2K _0 4 1 1 0 0 MH z n o n -s pre a d i ng d i f f ere n t i a l S A TA cl o c k
P C I E _ E X P C A R D _C L K R E Q # S E L_ S A T A SEL _ SATA
15 , 1 8 P C I E _ E X P C A R D _ C LK R E Q #
W L A N _ C L K R E Q# S E L_ 2 7 MH z 0 * 1 0 0 MH z s p re a di n g d fi f e re n t ai l S R C c l oc k
1 8 W L A N _ C L K R E Q#
1 * 2 7 M H z si n g el d c l oc k
S E L _ 2 7M H z
R 15 0 R1 5 9 R1 5 2 0 1 0 0 MH z s p re a di n g d fi f e re n t ai l S R C c l oc k

8 .2 K _ 0 4 * 8 . 2K _0 4 * 8. 2K _ 0 4

Clock Generator B - 3
Schematic Diagrams

CPU-1
1.2VS U15A 1.2VS

D1 HT LINK AE2
1. 5A D2 VLDT_A0 VLDT_B0 AE3 1. 5A
60M IL D3 VLDT_A1 VLDT_B1 AE4 60MI L
D4 VLDT_A2 VLDT_B2 AE5
VLDT_A3 VLDT_B3
E3 AD1
9 HT_NB_CPU_CAD_H0 E2 L0_CADIN_H0 L0_CADOUT_H0 AC1 HT_CPU_NB_CAD_H0 9
9 HT_NB_CPU_CAD_L0 E1 L0_CADIN_L0 L0_CADOUT_L0 AC2 HT_CPU_NB_CAD_L0 9
9 HT_NB_CPU_CAD_H1 F1 L0_CADIN_H1 L0_CADOUT_H1 AC3 HT_CPU_NB_CAD_H1 9
9 HT_NB_CPU_CAD_L1 G3 L0_CADIN_L1 L0_CADOUT_L1 AB1 HT_CPU_NB_CAD_L1 9
9 HT_NB_CPU_CAD_H2 G2 L0_CADIN_H2 L0_CADOUT_H2 AA1 HT_CPU_NB_CAD_H2 9
9 HT_NB_CPU_CAD_L2 G1 L0_CADIN_L2 L0_CADOUT_L2 AA2 HT_CPU_NB_CAD_L2 9
9 HT_NB_CPU_CAD_H3 H1 L0_CADIN_H3 L0_CADOUT_H3 AA3 HT_CPU_NB_CAD_H3 9
9 HT_NB_CPU_CAD_L3 J1 L0_CADIN_L3 L0_CADOUT_L3 W2 HT_CPU_NB_CAD_L3 9
9 HT_NB_CPU_CAD_H4 K1 L0_CADIN_H4 L0_CADOUT_H4 W3 HT_CPU_NB_CAD_H4 9
9 HT_NB_CPU_CAD_L4 L3 L0_CADIN_L4 L0_CADOUT_L4 V1 HT_CPU_NB_CAD_L4 9
9 HT_NB_CPU_CAD_H5 L2 L0_CADIN_H5 L0_CADOUT_H5 U1 HT_CPU_NB_CAD_H5 9
9 HT_NB_CPU_CAD_L5 L1 L0_CADIN_L5 L0_CADOUT_L5 U2 HT_CPU_NB_CAD_L5 9
9 HT_NB_CPU_CAD_H6 M1 L0_CADIN_H6 L0_CADOUT_H6 U3 HT_CPU_NB_CAD_H6 9
9 HT_NB_CPU_CAD_L6 N3 L0_CADIN_L6 L0_CADOUT_L6 T1 HT_CPU_NB_CAD_L6 9
9 HT_NB_CPU_CAD_H7 N2 L0_CADIN_H7 L0_CADOUT_H7 R1 HT_CPU_NB_CAD_H7 9
9 HT_NB_CPU_CAD_L7 E5 L0_CADIN_L7 L0_CADOUT_L7 AD4 HT_CPU_NB_CAD_L7 9
B.Schematic Diagrams

9 HT_NB_CPU_CAD_H8 F5 L0_CADIN_H8 L0_CADOUT_H8 AD3 HT_CPU_NB_CAD_H8 9


9 HT_NB_CPU_CAD_L8 F3 L0_CADIN_L8 L0_CADOUT_L8 AD5 HT_CPU_NB_CAD_L8 9
9 HT_NB_CPU_CAD_H9 F4 L0_CADIN_H9 L0_CADOUT_H9 AC5 HT_CPU_NB_CAD_H9 9
9 HT_NB_CPU_CAD_L9 G5 L0_CADIN_L9 L0_CADOUT_L9 AB4 HT_CPU_NB_CAD_L9 9
9 HT_NB_CPU_CAD_H10 H5 L0_CADIN_H10 L0_CADOUT_H10 AB3 HT_CPU_NB_CAD_H10 9
9 HT_NB_CPU_CAD_L10 H3 L0_CADIN_L10 L0_CADOUT_L10 AB5 HT_CPU_NB_CAD_L10 9
9 HT_NB_CPU_CAD_H11 H4 L0_CADIN_H11 L0_CADOUT_H11 AA5 HT_CPU_NB_CAD_H11 9

Sheet 3 of 35 9
9
9
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
K3
K4
L5
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
Y5
W5
V4
HT_CPU_NB_CAD_L11 9
HT_CPU_NB_CAD_H12 9
HT_CPU_NB_CAD_L12 9
9 HT_NB_CPU_CAD_H13 L0_CADIN_H13 L0_CADOUT_H13 HT_CPU_NB_CAD_H13 9
CPU-1 9
9
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
M5
M3
M4
L0_CADIN_L13
L0_CADIN_H14
L0_CADOUT_L13
L0_CADOUT_H14
V3
V5
U5
HT_CPU_NB_CAD_L13 9
HT_CPU_NB_CAD_H14 9
9 HT_NB_CPU_CAD_L14 N5 L0_CADIN_L14 L0_CADOUT_L14 T4 HT_CPU_NB_CAD_L14 9
9 HT_NB_CPU_CAD_H15 P5 L0_CADIN_H15 L0_CADOUT_H15 T3 HT_CPU_NB_CAD_H15 9
9 HT_NB_CPU_CAD_L15 L0_CADIN_L15 L0_CADOUT_L15 HT_CPU_NB_CAD_L15 9
J3 Y1
9 HT_NB_CPU_CLK_H0 J2 L0_CLKIN_H0 L0_CLKOUT_H0 W1 HT_CPU_NB_CLK_H0 9
9 HT_NB_CPU_CLK_L0 J5 L0_CLKIN_L0 L0_CLKOUT_L0 Y4 HT_CPU_NB_CLK_L0 9
9 HT_NB_CPU_CLK_H1 K5 L0_CLKIN_H1 L0_CLKOUT_H1 Y3 HT_CPU_NB_CLK_H1 9
9 HT_NB_CPU_CLK_L1 L0_CLKIN_L1 L0_CLKOUT_L1 HT_CPU_NB_CLK_L1 9
N1 R2
9 HT_NB_CPU_CTL_H0 P1 L0_CTLIN_H0 L0_CTLOUT_H0 R3 HT_CPU_NB_CTL_H0 9
9 HT_NB_CPU_CTL_L0 P3 L0_CTLIN_L0 L0_CTLOUT_L0 T5 HT_CPU_NB_CTL_L0 9
9 HT_NB_CPU_CTL_H1 P4 L0_CTLIN_H1 L0_CTLOUT_H1 R5 HT_CPU_NB_CTL_H1 9
9 HT_NB_CPU_CTL_L1 L0_CTLIN_L1 L0_CTLOUT_L1 HT_CPU_NB_CTL_L1 9

SOCKET_638_PIN

* If V L DT is c on ne c te d o nly o n o ne s id e ,
o ne 4.7 u F ca p s h ou ld b e a d de d t o
t he is la nd s id e
1.2VS

4.7U_6.3V_06 4.7U_6.3V_06 .22U_10V_04


C440 C443 C447 C452 C451 C442 C441
180P_NPO_50V_04

4.7U_6.3V_06 .22U_10V_04 180P_NPO_50V_04

P lace clo se to so cket

B - 4 CPU-1
Schematic Diagrams

CPU-2
Pro cessor Memory Interface
VTT VTT
U 1 5C
75 0mA 75 0m A
8 M E M_ M B _D A T A [ 0 . . 63 ] ME M : D A T A M E M_ MA _ D A T A [ 0. . 63 ] 7
M E M_ MB _ D ATA0 C1 1 G1 2 ME M_ MA _ D A TA 0
0 .9 V M E M_ MB _ D ATA1 A1 1 MB _ D A TA 0 MA _D A T A 0 F12 ME M_ MA _ D A TA 1
0 .9 V
U 15 B M E M_ MB _ D ATA2 A1 4 MB _ D A TA 1 MA _D A T A 1 H1 4 ME M_ MA _ D A TA 2
M E M_ MB _ D ATA3 B1 4 MB _ D A TA 2 MA _D A T A 2 G1 4 ME M_ MA _ D A TA 3
D 10 W 10 M E M_ MB _ D ATA4 G1 1 MB _ D A TA 3 MA _D A T A 3 H1 1 ME M_ MA _ D A TA 4
PLACE T HEM CLOSE TO V TT 1 V T T5 MB _ D A TA 4 MA _D A T A 4
C 10 ME M : C M D / C T RL / C L K A C1 0 M E M_ MB _ D ATA5 E1 1 H1 2 ME M_ MA _ D A TA 5
CPUWITHIN1" B1 0 V TT 2 V T T6 A B 10 M E M_ MB _ D ATA6 D1 2 MB _ D A TA 5 MA _D A T A 5 C1 3 ME M_ MA _ D A TA 6
AD 1 0 V TT 3 V T T7 A A 10 M E M_ MB _ D ATA7 A1 3 MB _ D A TA 6 MA _D A T A 6 E1 3 ME M_ MA _ D A TA 7
V TT 4 V T T8 A 10 M E M_ MB _ D ATA8 A1 5 MB _ D A TA 7 MA _D A T A 7 H1 5 ME M_ MA _ D A TA 8
M _ZP AF1 0 V T T9 M E M_ MB _ D ATA9 A1 6 MB _ D A TA 8 MA _D A T A 8 E1 5 ME M_ MA _ D A TA 9
R3 0 1 39 . 2 _ 1 %_ 0 4
1. 8 V R2 9 3 39 . 2 _ 1 %_ 0 4 M _ZN AE1 0 ME M Z P Y 10 Z0407 C P U _M _ V R E F _ S U S M E M_ MB _ D A T A 10 A1 9 MB _ D A TA 9 MA _D A T A 9 E1 7 ME M _M A _ D A T A 1 0
ME M Z N V T T _S E N S E M E M_ MB _ D A T A 11 A2 0 MB _ D A TA 10 M A _ DA T A 1 0 H1 7 ME M _M A _ D A T A 1 1
ME M _ MA _ R E S E T # H 1 6 W 17 M E M_ MB _ D A T A 12 C1 4 MB _ D A TA 11 M A _ DA T A 1 1 E1 4 ME M _M A _ D A T A 1 2
R S V D _M 1 M E MV R E F M E M_ MB _ D A T A 13 D1 4 MB _ D A TA 12 M A _ DA T A 1 2 F14 ME M_ MA _ D A TA 1 3
T19 B 18 M E M_ MB _R E S E T # M E M_ MB _ D A T A 14 C1 8 MB _ D A TA 13 M A _ DA T A 1 3 C1 7 ME M_ MA _ D A TA 1 4
7 M E M_ M A 0 _O D T 0 V2 2 MA 0 _ OD T0 R S V D _ M2 M E M_ MB _ D A T A 15 D1 8 MB _ D A TA 14 M A _ DA T A 1 4 G1 7 ME M_ MA _ D A TA 1 5
7 M E M_ M A 0 _O D T 1 ME M _ MA 1 _ OD T0 U 21 MA 0 _ OD T1 W 26 M E M_ MB _ D A T A 16 D2 0 MB _ D A TA 15 M A _ DA T A 1 5 G1 8 ME M_ MA _ D A TA 1 6
V1 9 MA 1 _ OD T0 MB 0 _ OD T0 W 23 ME M _ MB 0 _ OD T0 8 A2 1 MB _ D A TA 16 M A _ DA T A 1 6 C1 9
ME M _ MA 1 _ OD T1 M E M_ MB _ D A T A 17 ME M_ MA _ D A TA 1 7
MA 1 _ OD T1 MB 0 _ OD T1 Y 2 6 M E M_ MB 1_ O D T 0 ME M _ MB 0 _ OD T1 8 M E M_ MB _ D A T A 18 D2 4 MB _ D A TA 17 M A _ DA T A 1 7 D2 2 ME M_ MA _ D A TA 1 8
T20 MB 1 _ OD T0 C2 5 MB _ D A TA 18 M A _ DA T A 1 8 E2 0
M E M_ MB _ D A T A 19 ME M_ MA _ D A TA 1 9
7 M E M_ M A 0 _C S # 0 U 19 MA 0 _ C S _ L 0 V 26 M E M_ MB _ D A T A 20 B2 0 MB _ D A TA 19 M A _ DA T A 1 9 E1 8 ME M_ MA _ D A TA 2 0
7 M E M_ M A 0 _C S # 1 U 20 MA 0 _ C S _ L 1 M B 0 _C S _ L0 W 25 ME M _ MB 0 _ C S # 0 8 C2 0 MB _ D A TA 20 M A _ DA T A 2 0 F18
Z 0 4 01 M E M_ MB _ D A T A 21 ME M_ MA _ D A TA 2 1
MA 1 _ C S _ L 0 M B 0 _C S _ L1 ME M _ MB 0 _ C S # 1 8 MB _ D A TA 21 M A _ DA T A 2 1

B.Schematic Diagrams
Z 0 4 02 V2 0 U 22 Z0408 M E M_ MB _ D A T A 22 B2 4 B2 2 ME M_ MA _ D A TA 2 2
MA 1 _ C S _ L 1 M B 1 _C S _ L0 M E M_ MB _ D A T A 23 C2 4 MB _ D A TA 22 M A _ DA T A 2 2 C2 3 ME M_ MA _ D A TA 2 3
J22 J25 M E M_ MB _ D A T A 24 E2 3 MB _ D A TA 23 M A _ DA T A 2 3 F20 ME M_ MA _ D A TA 2 4
7 M E M_ M A _ C K E 0 J20 MA _ C K E 0 M B _ CK E 0 H 26 ME M _ MB _ C K E 0 8 E2 4 MB _ D A TA 24 M A _ DA T A 2 4 F22
M E M_ MB _ D A T A 25 ME M_ MA _ D A TA 2 5
7 M E M_ M A _ C K E 1 MA _ C K E 1 M B _ CK E 1 ME M _ MB _ C K E 1 8 M E M_ MB _ D A T A 26 G2 5 MB _ D A TA 25 M A _ DA T A 2 5 H2 4 ME M_ MA _ D A TA 2 6
Z 0 4 03 N 19 P 22 Z0409 M E M_ MB _ D A T A 27 G2 6 MB _ D A TA 26 M A _ DA T A 2 6 J1 9 ME M_ MA _ D A TA 2 7
Z 0 4 04 N 20 MA _ C L K _ H 5 MB _ C L K _ H 5 R 22 Z0410 M E M_ MB _ D A T A 28 C2 6 MB _ D A TA 27 M A _ DA T A 2 7 E2 1 ME M_ MA _ D A TA 2 8
E1 6 MA _ C L K _ L 5 M B _ C L K _ L5 A 17 M E M_ MB _ D A T A 29 D2 6 MB _ D A TA 28 M A _ DA T A 2 8 E2 2 ME M_ MA _ D A TA 2 9
7
7
ME
ME
M_ MA _ C
M_ MA _ C
LK 1 _ P
LK 1 _ N
F16 MA _ C L K _ H 1 MB _ C L K _ H 1 A 18 ME M
ME M
_ MB _ C L K 1 _ P
_ MB _ C L K 1 _ N
8
8
M E M_ MB _ D A T A 30 G2 3 MB _ D A TA 29 M A _ DA T A 2 9 H2 0 ME M_ MA _ D A TA 3 0
Sheet 4 of 35

To SO-DIMM 0

To SO-DIMM 1
Y 16 MA _ C L K _ L 1 M B _ C L K _ L1 A F 18 M E M_ MB _ D A T A 31 G2 4 MB _ D A TA 30 M A _ DA T A 3 0 H2 2 ME M_ MA _ D A TA 3 1
7 ME M_ MA _ C LK 7 _ P AA1 6 MA _ C L K _ H 7 MB _ C L K _ H 7 A F 17 ME M _ MB _ C L K 7 _ P 8 M E M_ MB _ D A T A 32 AA2 4 MB _ D A TA 31 M A _ DA T A 3 1 Y2 4 ME M_ MA _ D A TA 3 2
7 ME M_ MA _ C LK 7 _ N ME M _ MB _ C L K 7 _ N 8

7 M E M_ MA _ A D D [ 0 . . 1 5 ]
Z 0 4 05
Z 0 4 06
P1 9
P2 0
MA _ C L K _ L 7
MA _ C L K _ H 4
MA _ C L K _ L 4
M B _ C L K _ L7
MB _ C L K _ H 4
M B _ C L K _ L4
R
R
26
25
Z0411
Z0412
ME M _ MB _ A D D [ 0 . . 1 5] 8
M
M
M
E M_ MB _ D
E M_ MB _ D
E M_ MB _ D
A T A 33
A T A 34
A T A 35
AA2 3
A D2 4
AE2 4
MB _ D
MB _ D
MB _ D
MB _ D
A TA
A TA
A TA
A TA
32
33
34
35
M A _ DA T A 3 2
M A _ DA T A 3 3
M A _ DA T A 3 4
M A _ DA T A 3 5
AB2 4
AB2 2
AA2 1
ME M_ MA _ D A TA 3 3
ME M_ MA _ D A TA 3 4
ME M_ MA _ D A TA 3 5
CPU-2
ME M _ MA _ A D D0 N 21 P 24 ME M _M B _ ADD 0 M E M_ MB _ D A T A 36 AA2 6 W22 ME M_ MA _ D A TA 3 6

s ocke t
M 20 MA _ A D D 0 M B _A D D 0 N 24 AA2 5 MB _ D A TA 36 M A _ DA T A 3 6 W21

socket
ME M _ MA _ A D D1 ME M _M B _ ADD 1 M E M_ MB _ D A T A 37 ME M_ MA _ D A TA 3 7
ME M _ MA _ A D D2 N 22 MA _ A D D 1 M B _A D D 1 P 26 ME M _M B _ ADD 2 M E M_ MB _ D A T A 38 A D2 6 MB _ D A TA 37 M A _ DA T A 3 7 Y2 2 ME M_ MA _ D A TA 3 8
ME M _ MA _ A D D3 M 19 MA _ A D D 2 M B _A D D 2 N 23 ME M _M B _ ADD 3 M E M_ MB _ D A T A 39 AE2 5 MB _ D A TA 38 M A _ DA T A 3 8 AA2 2 ME M_ MA _ D A TA 3 9
ME M _ MA _ A D D4 M 22 MA _ A D D 3 M B _A D D 3 N 26 ME M _M B _ ADD 4 M E M_ MB _ D A T A 40 A C2 2 MB _ D A TA 39 M A _ DA T A 3 9 Y2 0 ME M_ MA _ D A TA 4 0
ME M _ MA _ A D D5 L20 MA _ A D D 4 M B _A D D 4 L23 ME M _M B _ ADD 5 M E M_ MB _ D A T A 41 A D2 2 MB _ D A TA 40 M A _ DA T A 4 0 AA2 0 ME M_ MA _ D A TA 4 1
ME M _ MA _ A D D6 M 24 MA _ A D D 5 M B _A D D 5 N 25 ME M _M B _ ADD 6 M E M_ MB _ D A T A 42 AE2 0 MB _ D A TA 41 M A _ DA T A 4 1 AA1 8 ME M_ MA _ D A TA 4 2
ME M _ MA _ A D D7 L21 MA _ A D D 6 M B _A D D 6 L24 ME M _M B _ ADD 7 M E M_ MB _ D A T A 43 AF2 0 MB _ D A TA 42 M A _ DA T A 4 2 AB1 8 ME M_ MA _ D A TA 4 3
ME M _ MA _ A D D8 L19 MA _ A D D 7 M B _A D D 7 M 26 ME M _M B _ ADD 8 M E M_ MB _ D A T A 44 AF2 4 MB _ D A TA 43 M A _ DA T A 4 3 AB2 1 ME M_ MA _ D A TA 4 4
ME M _ MA _ A D D9 K2 2 MA _ A D D 8 M B _A D D 8 K 26 ME M _M B _ ADD 9 M E M_ MB _ D A T A 45 AF2 3 MB _ D A TA 44 M A _ DA T A 4 4 A D2 1 ME M_ MA _ D A TA 4 5
ME M _ MA _ A D D1 0 R 21 MA _ A D D 9 M B _A D D 9 T26 ME M _M B _ ADD 10 M E M_ MB _ D A T A 46 A C2 0 MB _ D A TA 45 M A _ DA T A 4 5 A D1 9 ME M_ MA _ D A TA 4 6
ME M _ MA _ A D D1 1 L22 MA _ A D D 10 M B _ A D D 10 L26 ME M _M B _ ADD 11 M E M_ MB _ D A T A 47 A D2 0 MB _ D A TA 46 M A _ DA T A 4 6 Y1 8 ME M_ MA _ D A TA 4 7
K2 0 MA _ A D D 11 M B _ A D D 11 L25 A D1 8 MB _ D A TA 47 M A _ DA T A 4 7 A D1 7
ME M _ MA _ A D D1 2 ME M _M B _ ADD 12 M E M_ MB _ D A T A 48 ME M_ MA _ D A TA 4 8
ME M _ MA _ A D D1 3 V2 4 MA _ A D D 12 M B _ A D D 12 W 24 ME M _M B _ ADD 13 M E M_ MB _ D A T A 49 AE1 8 MB _ D A TA 48 M A _ DA T A 4 8 W16 ME M_ MA _ D A TA 4 9
K2 4 MA _ A D D 13 M B _ A D D 13 J23 A C1 4 MB _ D A TA 49 M A _ DA T A 4 9 W14
ME M _ MA _ A D D1 4 ME M _M B _ ADD 14 M E M_ MB _ D A T A 50 ME M_ MA _ D A TA 5 0
ME M _ MA _ A D D1 5 K1 9 MA _ A D D 14 M B _ A D D 14 J24 ME M _M B _ ADD 15 M E M_ MB _ D A T A 51 A D1 4 MB _ D A TA 50 M A _ DA T A 5 0 Y1 4 ME M_ MA _ D A TA 5 1
MA _ A D D 15 M B _ A D D 15 M E M_ MB _ D A T A 52 AF1 9 MB _ D A TA 51 M A _ DA T A 5 1 Y1 7 ME M_ MA _ D A TA 5 2
R 20 R 24 M E M_ MB _ D A T A 53 A C1 8 MB _ D A TA 52 M A _ DA T A 5 2 AB1 7 ME M_ MA _ D A TA 5 3
7 ME M_ MA _ B A N K 0 R 23 MA _ B A N K 0 M B _ B A NK 0 U 26 ME M _ MB _ B A N K 0 8 AF1 6 MB _ D A TA 53 M A _ DA T A 5 3 AB1 5
M E M_ MB _ D A T A 54 ME M_ MA _ D A TA 5 4
7 ME M_ MA _ B A N K 1 J21 MA _ B A N K 1 M B _ B A NK 1 J26 ME M _ MB _ B A N K 1 8 M E M_ MB _ D A T A 55 AF1 5 MB _ D A TA 54 M A _ DA T A 5 4 A D1 5 ME M_ MA _ D A TA 5 5
7 ME M_ MA _ B A N K 2 MA _ B A N K 2 M B _ B A NK 2 ME M _ MB _ B A N K 2 8 AF1 3 MB _ D A TA 55 M A _ DA T A 5 5 AB1 3
M E M_ MB _ D A T A 56 ME M_ MA _ D A TA 5 6
R 19 U 25 M E M_ MB _ D A T A 57 A C1 2 MB _ D A TA 56 M A _ DA T A 5 6 A D1 3 ME M_ MA _ D A TA 5 7
7 ME M_ MA _ R A S # T22 MA _ R A S _L MB _ R A S _L U 24 ME M _ MB _ R A S # 8 AB1 1 MB _ D A TA 57 M A _ DA T A 5 7 Y1 2
M E M_ MB _ D A T A 58 ME M_ MA _ D A TA 5 8
7 ME M_ MA _ C A S # T24 MA _ C A S _L MB _ C A S _L U 23 ME M _ MB _ C A S # 8 M E M_ MB _ D A T A 59 Y1 1 MB _ D A TA 58 M A _ DA T A 5 8 W11 ME M_ MA _ D A TA 5 9
7 ME M_ MA _ W E # MA _ W E _ L M B _W E _L ME M _ MB _ W E # 8 AE1 4 MB _ D A TA 59 M A _ DA T A 5 9 AB1 4
M E M_ MB _ D A T A 60 ME M_ MA _ D A TA 6 0
M E M_ MB _ D A T A 61 AF1 4 MB _ D A TA 60 M A _ DA T A 6 0 AA1 4 ME M_ MA _ D A TA 6 1
M E M_ MB _ D A T A 62 AF1 1 MB _ D A TA 61 M A _ DA T A 6 1 AB1 2 ME M_ MA _ D A TA 6 2
M E M_ MB _ D A T A 63 A D1 1 MB _ D A TA 62 M A _ DA T A 6 2 AA1 2 ME M_ MA _ D A TA 6 3
S O C K E T_ 6 3 8_ P I N
MB _ D A TA 63 M A _ DA T A 6 3
8 ME M _M B _ D M [ 0. . 7] M E M_ MB _ D M0 A1 2 E1 2 M EM _M A _ D M0 M E M_ MA _ D M[ 0 . . 7 ] 7
M E M_ MB _ D M1 B1 6 MB _ D M0 M A _ DM 0 C1 5 M EM _M A _ D M1
M E M_ MB _ D M2 A2 2 MB _ D M1 M A _ DM 1 E1 9 M EM _M A _ D M2
1. 8 V
M E M_ MB _ D M3 E2 5 MB _ D M2 M A _ DM 2 F24 M EM _M A _ D M3
M E M_ MB _ D M4 AB2 6 MB _ D M3 M A _ DM 3 A C2 4 M EM _M A _ D M4
M E M_ MB _ D M5 AE2 2 MB _ D M4 M A _ DM 4 Y1 9 M EM _M A _ D M5
M E M_ MB _ D M6 A C1 6 MB _ D M5 M A _ DM 5 AB1 6 M EM _M A _ D M6
R 97
1K _ 0 4 _1 % M E M_ MB _ D M7 A D1 2 MB _ D M6 M A _ DM 6 Y1 3 M EM _M A _ D M7
MB _ D M7 M A _ DM 7
W idth 2 0 mil , le ngt h < 6 inch C1 2 G1 3
C P U _ M_ V R E F _S U S 8 ME M _M B _ DQ S 0 _P B1 2 MB _ D QS _ H0 M A _D QS _H 0 H1 3 ME M _M A _ DQ S 0_ P 7
8 ME M _M B _ DQ S 0 _N D1 6 MB _ D QS _ L 0 MA _ D QS _ L 0 G1 6 ME M _M A _ DQ S 0_ N 7
8 ME M _M B _ DQ S 1 _P C1 6 MB _ D QS _ H1 M A _D QS _H 1 G1 5 ME M _M A _ DQ S 1_ P 7
8 ME M _M B _ DQ S 1 _N A2 4 MB _ D QS _ L 1 MA _ D QS _ L 1 C2 2 ME M _M A _ DQ S 1_ N 7
8 ME M _M B _ DQ S 2 _P A2 3 MB _ D QS _ H2 M A _D QS _H 2 C2 1 ME M _M A _ DQ S 2_ P 7
C 11 5 C 10 5 C 13 8
R9 6 1 0U _1 0 V _ 0 8 8 ME M _M B _ DQ S 2 _N F26 MB _ D QS _ L 2 MA _ D QS _ L 2 G2 2 ME M _M A _ DQ S 2_ N 7
8 ME M _M B _ DQ S 3 _P E2 6 MB _ D QS _ H3 M A _D QS _H 3 G2 1 ME M _M A _ DQ S 3_ P 7
1K _ 0 4 _1 %
8 ME M _M B _ DQ S 3 _N A C2 5 MB _ D QS _ L 3 MA _ D QS _ L 3 A D2 3 ME M _M A _ DQ S 3_ N 7
8 ME M _M B _ DQ S 4 _P A C2 6 MB _ D QS _ H4 M A _D QS _H 4 A C2 3 ME M _M A _ DQ S 4_ P 7
8 ME M _M B _ DQ S 4 _N AF2 1 MB _ D QS _ L 4 MA _ D QS _ L 4 AB1 9 ME M _M A _ DQ S 4_ N 7
8 ME M _M B _ DQ S 5 _P AF2 2 MB _ D QS _ H5 M A _D QS _H 5 AB2 0 ME M _M A _ DQ S 5_ P 7
. 1U _ X7 R _1 0 V _ 04 1 0 00 P _ X 7 R _ 5 0V _ 0 4
8 ME M _M B _ DQ S 5 _N AE1 6 MB _ D QS _ L 5 MA _ D QS _ L 5 Y1 5 ME M _M A _ DQ S 5_ N 7
8 ME M _M B _ DQ S 6 _P A D1 6 MB _ D QS _ H6 M A _D QS _H 6 W15 ME M _M A _ DQ S 6_ P 7
8 ME M _M B _ DQ S 6 _N AF1 2 MB _ D QS _ L 6 MA _ D QS _ L 6 W12 ME M _M A _ DQ S 6_ N 7
8 ME M _M B _ DQ S 7 _P AE1 2 MB _ D QS _ H7 M A _D QS _H 7 W13 ME M _M A _ DQ S 7_ P 7
8 ME M _M B _ DQ S 7 _N MB _ D QS _ L 7 MA _ D QS _ L 7 ME M _M A _ DQ S 7_ N 7
0 .9 V
Place close to socket
S O C K E T _ 6 38 _ P I N

4 . 7 U _ 6 . 3V _0 6 4 . 7 U _ 6 . 3 V _0 6 . 2 2 U _ 1 0 V _0 4 . 2 2 U _ 1 0 V _ 04 1 0 0 0P _X 7 R _ 5 0 V _0 4 10 0 0 P _X 7 R _ 5 0 V _ 04 18 0 P _ N P O _ 50 V _ 0 4 1 8 0 P _N P O_ 5 0 V _ 04

C4 9 1 C 49 9 C4 9 3 C 50 0 C4 9 2 C 4 85 C4 7 7 C 4 89 C8 5 C 4 95 C 47 8 C4 8 3 C 48 4 C8 6 C 49 0 C4 8 8

*4 . 7U _ 6. 3 V _ 0 6 4. 7 U _6 . 3 V _ 0 6 * . 22 U _1 0 V _ 0 4 *. 2 2 U _ 1 0 V _0 4 * 1 00 0 P _ X7 R _5 0 V _ 0 4 *1 00 0 P _ X 7R _ 50 V _ 0 4 18 0 P _ N P O _ 50 V _ 0 4 *1 8 0P _ N P O_ 5 0 V _0 4

CPU-2 B - 5
Schematic Diagrams

CPU-3
L A Y OU T : R OU T E V D D A T R A C E A P P R O X . 1. 8V
50 m i l s WI D E (U S E 2 x 2 5 m i l T R A C E S T O VDDA
2. 5V _C P U EX I T B A L L F I EL D ) A N D 5 0 0 m li s L O N G . P WR GD 1. 8V 3. 3 V
250mA
U 1 5D
L4 8 F C M16 08K T-3 00 T07 C PU _ V D D A_ R U N 1 .8 V
F8 M11
C 83 F9 VD D A 1 K EY 1 W 18 R 32 4 R 32 5 R 32 3 R 3 22
10 U _1 0V _0 6 C 4 63 C 4 64 C 76 VD D A 2 K EY 2 1K _ 04 *10 K _04
2 C PU _ C LK P C PU _ C LK I N _S C _P A9 A6 C P U _S V C _R
4. 7U _ 6. 3V _0 6 .2 2U _ 16 V_ 06 C8 4 C LK I N _H SVC 1 0K _0 4 * 10K _0 4
390 0P _X 7R _ 50 V_ 04 39 00 P_ X7 R _50 V_ 04 R6 2 C PU _ C LK I N _S C _N A8 A4 C P U _S V D _R R 318 R 31 4 R 3 20 Z0 50 3
tolerance 10% 1113 C LK I N _L SVD Z0 50 5
AMD CHECK

B
L D T_ R ST # B7 300 _0 4 30 0_ 04 3 00_ 04 Q39
1 .8 V S K n o w n ol w te m p e r at u re P G i s s u e , C 75 P WR GD A7 R ES E T_ L
2 C PU _ C LK N

B
1 69 _1 %_0 4 L D T_ ST OP # F1 0 PW R OK A F6 C P U _T H ER MT R IP # _1. 8 V E C Q38
R e p l ac e w i t h an o t he r p ar t C P U _ LD T_ R E Q# C6 LD T ST OP_ L TH E R MTR I P _L A C7 C P U _P R OC H OT# _R
39 00 P_ X7 R _50 V_ 04 LD T RE Q_ L PR OC H OT _L R 3 16 2N 39 04 C P U _P R OC H OT # 14
C 4 59 . 1U _ X7R _ 10 V_ 04 A A8 C P U _ME MH OT# _1. 8 V *0_ 04 02_ 5m li _s hort C E
R 189 K e ep t rac e from res is o r to C P U w ti h i n 0 . 6" C P U _ SI C AF 4 MEMH OT _L *2N 3 90 4 C P U _ME MH OT # 7, 8
300 _0 4 p l a ce th e m to C P U w i th i n 1 5. " C P U _ SI D AF 5 SI C
k ee p tra ce f ro m ca p s to C P U w i t hi n 1. 2" SI D C P U _TH E R MT R IP # 1 5
C P U _ AL ER T AE6 W7 C P U _T H ER MD C R 2 79 * 0_0 40 2_ 10m li _s hort H _TH E R MD C
R 44 P WR GD AL E RT _L TH E R MD C W8 C P U _T H ER MD A R 2 85 * 0_0 40 2_ 10m li _s hort H _TH E R MD A
1 4 C P U _P WR GD R6 TH E R MD A
*0 _0 40 2_5 mi l_ sh ort R 63 44 . 2_1 %_ 04 CPU_HTREF0
1. 2 VS R 56 44 . 2_1 %_ 04 CPU_HTREF1 P6 H T_ RE F 0
1 .8 V S H T_ RE F 1
C P U_ V D D 0 P R3 6 2. 2_ 1%_ 06
2 7 C P U _ V D D 0_ R U N _ F B _H F6 W9
E6 VD D 0 _F B _H V DDO I _ F B_ H Y9
2 7 C P U _ V D D 0_ R U N _ F B _L VD D 0 _F B _L V D D I O_F B _L
PR 1 13 2. 2_ 1% _06 C P U _V D D 1 P R 109 2. 2 _1 %_0 6 P R 37 2 . 2_ 1%_ 06 C P U _ VD D N B
R 191 Y6 H6
2 7 C P U _ V D D 1_ R U N _ F B _H AB6 VD D 1 _F B _H V D D N B_ F B_ H G6 C P U _V D D N B _R U N _ FB _ H 2 7
300 _0 4 2 7 C P U _ V D D 1_ R U N _ F B _L VD D 1 _F B _L VD D N B _F B _L C P U _V D D N B _R U N _ FB _ L 27
R 76 L D T_S T OP# P R 10 8 2. 2_ 1%_ 06 C P U _D B R D Y G1 0 P R 11 6 2 . 2_1 %_ 06
10 ,1 4 C P U _L D T_S T OP# *0 _0 40 2_5 mi l_ sh ort C P U _T MS AA9 D BR D Y E 10 C P U _D B R E Q# R 75 3 00 _04 1. 8 V
C L O S E T O S O C K ET C P U _T C K AC9 TMS D B R E Q_L
R9 0 20 K_ 04 C P U _T R S T# AD9 TC K A E9 C P U _T D O CL OS E T O S OCKE T
B.Schematic Diagrams

3. 3V S Z 05 02 C P U _T D I AF 9 TR S T_ L T DO
TD I
C P U _T E ST 23 _TS TU P D AD7 J7 C P U _T ES T 28_ H _P LL C H R Z_ P
R9 1 34 . 8K _0 4 TE S T23 T ES T2 8_ H H8 C P U _T ES T 28_ L_ PL LC H R Z _N
1 .8 V S 3. 3 VS C P U _T E ST 18 _P LLT E ST 1 H1 0 TE S T28 _L
C P U _T E ST 19 _P LLT E ST 0 G9 TE S T18 D7 C P U _T ES T 17_ B P3
TE S T19 TE ST 17 E7 C P U _T ES T 16_ B P2
C P U _ TE ST 25 _H _ BY P A SS C LK _ H E 9 TE ST 16 F7 C P U _T ES T 15_ B P1
C P U _ TE ST 25 _L _B Y PA S SC L K _L E 8 TE S T25 _H TE ST 15 C7 C P U _T ES T 14_ B P0
R 84 R8 5

G
300 _0 4 3 00 _04 R6 4 TE S T25 _L TE ST 14

Sheet 5 of 35 1 4 C P U _L D T_R S T #
R8 0 LD T _R S T#
* 0_0 40 2_ 5mi l_ sh ort
S

Q11
D LD T _R S T# _H D T R 2 78
300 _0 4 C P U _ TE ST 21 _S C A NE N
C P U _ TE ST 20 _S C A NC L K 2
300 _0 4 C P U _ TE ST 24 _S C A NC L K 1
C P U _ TE ST 22 _S C A NS H I F TE N
AB8
AF 7
AE7
AE8
TE S T21
TE S T20
TE S T24
TE S T7
TE ST 10
C3
K8
C4
C P U _T ES T 7_A N A LOG_ T
C P U _T ES T 10_ A N AL OGOU T

C P U _T ES T 8_D I G_ T
C P U _ TE ST 12 _S C A NS H I F TE N B AC8 TE S T22 TE S T8

CPU-3 C P U _ TE ST 27 _S I N GLE C H AI N AF 8 TE S T12


MTN 7 00 2Z H S3 TE S T27
C PU _ LD T _R E Q# C9 C P U _T ES T 29_ H _F B C LK OU T_ P
10 C P U _ LD T_ R E Q# C P U _ TE ST 9_ AN A L OGI N C2 T ES T2 9_ H C8 C P U _T ES T 29_ L_ FB C LK OU T _N
C P U _ TE ST 6_ D I EC R A C K MON AA6 TE S T9 TE S T29 _L
R 274 TE S T6
A3 H 18
*0 _04 A5 R SV D 1 R S V D 10 H 19
1 .8 V R SV D 2 R S VD 9
B3 A A7
B5 R SV D 3 R S VD 8 D5
C1 R SV D 4 R S VD 7 C5
R 3 17 R 32 1 R SV D 5 R S VD 6
3 90 _0 4 39 0_0 4

R 315 C P U _S I C S OC K ET _6 38 _P I N
15 S C L K3 *0 _04 02 _5m li _s ho tr

R 319 C P U _S I D
15 SD A T A3 *0 _04 02 _5m li _s ho tr

Thermal IC VID Override Circuit


T H M_V D D R 31 2
0_ 04
20 m il 3. 3 V

C 47 5
1. 8 V
R 30 8 1 U _1 6V _0 6
10 0K _0 4 VDD3 1. 8 V

R 36 R3 5 R 89
1K _0 4 1 K_ 04 *2 .2 K _04

R 29 9 R 30 0 R9 5
C P U _S V C _R R4 7 C PU _ S VC 3 . 3V S
4. 7K _ 04 4. 7 K_ 04 *0_ 040 2_ 5mi l _sh ort C PU _ SV C 27 1 0K _0 4
U 13
1 8 C P U _S V D _R R4 6 C PU _ S VD Z 05 01 R 83
H_ TH E R MD A 10 M IL E 2 V DD S CL K 7 S MC _C P U _ TH E R M 2 4 C PU _ SV D 27
*0_ 040 2_ 5mi l _sh ort

G
H_ TH E R MD C 10 M IL E 3 D+ SD A T A 6 S MD _C P U _ TH E R M 2 4
D- AL ER T # 4. 7K _ 04
4 5
C 4 74 T H ER M# GN D P WR GD R4 3 PW R GD 1 S D C P U _P W R GD _S V ID _ R E G
10 00P _ X7R _ 50 V_ 04 AD M1 03 2A R M T H ER M_ A LE R T# 1 5, 24 *0_ 040 2_ 5mi l _sh ort C P U _P WR GD _ S VI D _ R EG 27
Q1 2
MT N 70 02 ZH S 3
Nea r to R 2 92 10K _ 04 TH M_ VD D
Layo ut Note : ADM 1032 R 48 R4 5 R 94 R 88 *0 _04
Rout e H _THE RMD A an d
H_TH ERM DC o n s ame laye r.
* 220 _0 4 * 220 _0 4 *22 0_ 04
10 m il trac e o n 10 mil
spac ing .

HDT Connector 1 . 8V J1
1 2
L D T_R S T # 3 4
P W RGD 5 6
C PU _D BR EQ # 7 8 2008/03/24
C PU _D BR D Y 9 10
C PU _T CK 11 12 P WR GD
C PU _T M S 13 14 CP U_ DB RE Q #
C PU _T DI 15 16
C PU _T RS T# 17 18 C4 8 C4 7
C PU _T DO 19 20 1. U _X 7R _ 10V _ 04 . 1U _X 7R _ 10 V_ 04
21 22
23 24 LD T _R S T# _H D T
KE Y
26

*A S P-6 820 0-0 7

B - 6 CPU-3
Schematic Diagrams

CPU-4
U 15 F
CP U _V D D0 U1 5 E CP U _ V DD 1 AA4 J6
A A 11 V SS1 V S S 66 J8
G4
H2 V D D0 _1 V D D1 _ 1
P8
P1 0
A
A
A 13
A 15
V
V
SS2
SS3
V S S 67
V S S 68
J10
J12
BOTTOM SIDE DECOUPLING
VDD0CORE J9 V D D0 _2 V D D1 _ 2 R4 VDD1CORE A A 17 V SS4 V S S 69 J14
J11 V D D0 _3 V D D1 _ 3 R7 A A 19 V SS5 V S S 70 J16
0.375-1.500V J13 V D D0 _4 V D D1 _ 4 R9
1.375-1.500V AB2 V SS6 V S S 71 J18
CP U_ V DD 0
18A J15 V D D0 _5 V D D1 _ 5 R1 1 18A AB7 V SS7 V S S 72 K2
K6 V D D0 _6 V D D1 _ 6 T2 AB9 V SS8 V S S 73 K7
K1 0 V D D0 _7 V D D1 _ 7 T6 A B 23 V SS9 V S S 74 K9 .22 U _1 0 V _ 0 4
K1 2 V D D0 _8 V D D1 _ 8 T8 A B 25 V S S 10 V S S 75 K1 1 1 80 P _ NP O_ 50 V _ 0 4
K1 4 V D D0 _9 V D D1 _ 9 T 10 A C 11 V S S 11 V S S 76 K1 3 C3 4 C 97 C 99 C 35 C9 1 C 98 C7 7 C 5 94 C5 95
L4 V D D0 _1 0 V DD 1_ 1 0 T 12 A C 13 V S S 12 V S S 77 K1 5
L7 V D D0 _1 1 V DD 1_ 1 1 T 14 A C 15 V S S 13 V S S 78 K1 7
L9 V D D0 _1 2 V DD 1_ 1 2 U7 A C 17 V S S 14 V S S 79 L6
L11 V D D0 _1 3 V DD 1_ 1 3 U9 A C 19 V S S 15 V S S 80 L8 1 0U _ 6.3 V _ 0 6 .0 1 U_ 1 6V _0 4 * 1 0U _6 .3 V _ 0 6 * 1 0U _ 6.3 V _ 0 6
L13 V D D0 _1 4 V DD 1_ 1 4 U1 1 A C 21 V S S 16 V S S 81 L10 1 0U _ 6. 3V _ 0 6 10 U _6 .3 V _ 06 1 0 U_ 6 .3V _0 6
L15 V D D0 _1 5 V DD 1_ 1 5 U1 3 A D6 V S S 17 V S S 82 L12 CP U_ V DD 1

B.Schematic Diagrams
M2 V D D0 _1 6 V DD 1_ 1 6 U1 5 A D8 V S S 18 V S S 83 L14
M6 V D D0 _1 7 V DD 1_ 1 7 V6 A D 25 V S S 19 V S S 84 L16
CPU _VDDN B M8 V D D0 _1 8 V DD 1_ 1 8 V8 A E 11 V S S 20 V S S 85 L18
V D D0 _1 9 V DD 1_ 1 9 V S S 21 V S S 86
3A M1 0
N7 V D D0 _2 0 V DD 1_ 2 0
V1 0
V1 2
A E 13
A E 15 V S S 22 V S S 87
M7
M9
.22 U _1 0 V _ 0 4

N9
N1 1
V D D0 _2 1
V D D0 _2 2
V DD 1_ 2 1
V DD 1_ 2 2
V1 4
W4
A E 17
A E 19
V
V
S S 23
S S 24
V S S 88
V S S 89
AC 6
M 17
C9 2 C 10 0 C 93 C 79 C9 4 C 78
1 8 0 P _N P O_ 5 0 V _ 04
C6 5 C 5 96 C5 97 Sheet 6 of 35
C P U_ V DD NB

K1 6
V D D0 _2 3 V DD 1_ 2 3
V DD 1_ 2 4
Y2
A C4
A E 21
A E 23
V
V
S S 25
S S 26
V S S 90
V S S 91
N4
N8
CPU-4
M1 6 V D DNB _1 V DD 1_ 2 5 A D2 1 .8V B4 V S S 27 V S S 92 N 10 1 0 U_ 6 .3 V _ 061 0 U_ 6. 3V _ 0 6 1 0 U_ 6 .3V _ 0 6 1 0 U_ 6 .3V _0 6 .0 1 U_ 1 6V _0 4 *1 0 U_ 6 .3 V _0 6 * 1 0U _ 6.3 V _ 0 6
P1 6 V D DNB _2 V DD 1_ 2 6 B6 V S S 28 V S S 93 N 16
T16 V D DNB _3 Y2 5 B8 V S S 29 V S S 94 N 18
V1 6 V D DNB _4 V DD IO2 7 V2 5 B9 V S S 30 V S S 95 P2
1 .8 V
V D DNB _5 V DD IO2 6 V2 3 B 11 V S S 31 V S S 96 P7 CP U_ V DD NB 1.8 V
H2 5 V DD IO2 5 V2 1 B 13 V S S 32 V S S 97 P9
J17 V D DIO1 V DD IO2 4 V1 8 VDDI O B 15 V S S 33 V S S 98 P1 1
K1 8 V D DIO2 V DD IO2 3 U1 7 B 17 V S S 34 V S S 99 P1 7
K2 1 V D DIO3 V DD IO2 2 T 25
2A B 19 V S S 35 V S S 1 00 R8
K2 3 V D DIO4 V DD IO2 1 T 23 B 21 V S S 36 V S S 1 01 R 10 .2 2 U_ 1 0 V _0 4
VDD IO K2 5 V D DIO5 V DD IO2 0 T 21 B 23 V S S 37 V S S 1 02 R 16 1 8 0 P _ X7 R_ 5 0 V _ 04
L17 V D DIO6 V DD IO1 9 T 18 B 25 V S S 38 V S S 1 03 R 18 C1 02 C 13 2 C 13 3
2A M1 8 V D DIO7 V DD IO1 8 R1 7 D6 V S S 39 V S S 1 04 T7 C103 C1 1 8 C 1 04 C 1 12 C1 1 3
M2 1 V D DIO8 V DD IO1 7 P2 5 D8 V S S 40 V S S 1 05 T9
M2 3 V D DIO9 V DD IO1 6 P2 3 D9 V S S 41 V S S 1 06 T11
M2 5 V D DIO1 0 V DD IO1 5 P2 1 D 11 V S S 42 V S S 1 07 T13 1 0 U_ 6 .3 V _ 06 1 0 U_ 6 .3V _ 0 6 1 0 U_ 6 .3V _ 0 6 1 0 U_ 6 .3V _0 6 .2 2 U_ 1 0V _0 4 1 8 0 P _X 7 R_ 5 0 V _ 04
N1 7 V D DIO1 1 V DD IO1 4 P1 8 D 13 V S S 43 V S S 1 08 T15
V D DIO1 2 V DD IO1 3 D 15 V S S 44 V S S 1 09 T17
D 17 V S S 45 V S S 1 10 U4
D 19 V S S 46 V S S 1 11 U6
D 21 V S S 47 V S S 1 12 U8
S O CK E T _ 6 38 _ P IN
D 23 V S S 48 V S S 1 13 U 10
D 25 V S S 49 V S S 1 14 U 12
E4 V S S 50 V S S 1 15 U 14
F2 V S S 51 V S S 1 16 U 16
F 11
F 13
V
V
S S 52
S S 53
V S S 1 17
V S S 1 18
U 18
V2
DECOUPLING BETWEEN PROCESSOR AND DIMMs
F 15
F 17
V
V
S S 54
S S 55
V S S 1 19
V S S 1 20
V7
V9
PLACE CLOSE TO PROCESSOR AS POSSIBLE
F 19 V S S 56 V S S 1 21 V1 1
F 21 V S S 57 V S S 1 22 V1 3 1 .8 V
F 23 V S S 58 V S S 1 23 V1 5
F 25 V S S 59 V S S 1 24 V1 7
H7 V S S 60 V S S 1 25 W6
H9 V S S 61 V S S 1 26 Y 21 4.7 U _6 .3 V _ 06 .2 2 U_ 1 0V _0 4 *.2 2 U_ 1 0V _0 4 .0 1 U_ 1 6 V _0 4 1 80 P _ N P O_ 5 0V _ 0 4
H 21 V S S 62 V S S 1 27 Y 23
H 23 V S S 63 V S S 1 28 N6 C 1 25 C1 2 0 C1 2 8 C 12 9 C1 1 7 C 11 6 C1 2 4 C 1 11 C1 1 4 C 1 21 C1 1 0
J4 V S S 64 V S S 1 29
V S S 65

S OC K E T _6 3 8 _P IN 4 .7U _ 6.3 V _ 0 6 * 4 .7U _ 6.3 V _ 0 6 4 .7 U_ 6 .3V _0 6 .2 2 U_ 1 0V _0 4 * .22 U _1 0 V _ 0 4 .0 1U _ 16 V _ 0 4

CPU-4 B - 7
Schematic Diagrams

DDRII SO-DIMM_0
SO-DIMM 0
J_ D I MM_1 A 0. 9 V
4 ME M_MA _ AD D [ 0 . .1 5] MEM_ MA _A D D 0 102 5 ME M_MA _D A T A0 M EM_ MA_ D A TA [ 0. . 63 ] 4
MEM_ MA _A D D 1 101 A0 D Q0 7 ME M_MA _D A T A1
MEM_ MA _A D D 2 100 A1 D Q1 17 ME M_MA _D A T A2
MEM_ MA _A D D 3 99 A2 D Q2 19 ME M_MA _D A T A3 4 1 RN2
MEM_ MA _A D D 4 98 A3 D Q3 4 ME M_MA _D A T A4 4 ME M_MA _ C KE 0 MEM_ MA _B A N K2 3 2 4 P2 R X4 7_ 04
MEM_ MA _A D D 5 97 A4 D Q4 6 ME M_MA _D A T A5
MEM_ MA _A D D 6 94 A5 D Q5 14 ME M_MA _D A T A6 MEM_ MA _A D D 9 4 1 RN3
MEM_ MA _A D D 7 92 A6 D Q6 16 ME M_MA _D A T A7 MEM_ MA _A D D 12 3 2 4 P2 R X4 7_ 04
MEM_ MA _A D D 8 93 A7 D Q7 23 ME M_MA _D A T A8
MEM_ MA _A D D 9 91 A8 D Q8 25 ME M_MA _D A T A9 MEM_ MA _A D D 8 4 1 RN4 C 1 63 *. 1U _ X7 R _1 0V _0 4
MEM_ MA _A D D 10 105 A9 D Q9 35 ME M_MA _D A T A1 0 MEM_ MA _A D D 1 3 2 4 P2 R X4 7_ 04 1 .8 V
MEM_ MA _A D D 11 90 A 1 0/ A P D Q1 0 37 ME M_MA _D A T A1 1 C 1 69 . 1U _ X7 R _10 V _04
MEM_ MA _A D D 12 89 A1 1 D Q1 1 20 ME M_MA _D A T A1 2 MEM_ MA _A D D 5 4 1 RN5
MEM_ MA _A D D 13 116 A1 2 D Q1 2 22 ME M_MA _D A T A1 3 MEM_ MA _A D D 3 3 2 4 P2 R X4 7_ 04
A1 3 D Q1 3 C 1 76 *. 1U _ X7 R _1 0V _0 4
MEM_ MA _A D D 14 86 36 ME M_MA _D A T A1 4 1 .8 V
MEM_ MA _A D D 15 84 A1 4 D Q1 4 38 ME M_MA _D A T A1 5 4 1 RN6 C 1 68 . 1U _ X7 R _10 V _04
4 ME M_MA _B A N K [0 . . 2] MEM_ MA _B A N K2 85 A1 5 D Q1 5 43 ME M_MA _D A T A2 0 4 ME M_MA _ WE # MEM_ MA _A D D 10 3 2 4 P2 R X4 7_ 04
A 1 6_B A 2 D Q1 6 45 ME M_MA _D A T A1 7 C 1 64 *. 1U _ X7 R _1 0V _0 4
MEM_ MA _B A N K0 107 D Q1 7 55 ME M_MA _D A T A1 8 MEM_ MA _B A N K0 4 1 RN7 1 .8 V
MEM_ MA _B A N K1 106 BA0 D Q1 8 57 ME M_MA _D A T A2 1 3 2 4 P2 R X4 7_ 04 C 1 88 . 1U _ X7 R _10 V _04
110 BA1 D Q1 9 44 4 ME M_MA _ C AS #
4 ME M_MA 0 _C S #0 MEM_ MA 0_C S# 0 ME M_MA _D A T A2 3
MEM_ MA 0_C S# 1 115 S0 # D Q2 0 46 ME M_MA _D A T A2 2 4 1 RN8 C 1 73 *. 1U _ X7 R _1 0V _0 4
4 ME M_MA 0 _C S #1 MEM _MA _C L K1 _P 30 S1 # D Q2 1 56 ME M_MA _D A T A1 9 4 ME M_MA 0 _C S #1 3 2 4 P2 R X4 7_ 04
4 ME M_MA _ C LK 1_ P CK 0 D Q2 2 4 ME M_MA 0 _OD T1 1 .8 V
MEM _MA _C L K1 _N 32 58 ME M_MA _D A T A1 6 C 1 78 . 1U _ X7 R _10 V _04
4 ME M_MA _ C LK 1_ N MEM _MA _C L K7 _P 164 CK 0 # D Q2 3 61 ME M_MA _D A T A2 4 1 4 RN9
4 ME M_MA _ C LK 7_ P MEM _MA _C L K7 _N 166 CK 1 D Q2 4 63 ME M_MA _D A T A2 5 4 ME M_MA _ C KE 1 MEM_ MA _A D D 15 2 3 4 P2 R X4 7_ 04
4 ME M_MA _ C LK 7_ N MEM _MA _C K E 0 79 CK 1 # D Q2 5 73 ME M_MA _D A T A2 7 C 1 85 *. 1U _ X7 R _1 0V _0 4
4 ME M_MA _C KE 0 80 CK E 0 D Q2 6 75
B.Schematic Diagrams

4 ME M_MA _C KE 1 MEM _MA _C K E 1 ME M_MA _D A T A2 6 1 .8 V


MEM_ MA _C A S # 113 CK E 1 D Q2 7 62 ME M_MA _D A T A2 8 MEM_ MA _A D D 14 1 4 RN1 0 C 1 84 . 1U _ X7 R _10 V _04
4 MEM_ MA_ C A S# 108 CA S # D Q2 8 64 2 3 4 P2 R X4 7_ 04
4 MEM_ MA_ R A S# MEM_ MA _R A S # ME M_MA _D A T A2 9 MEM_ MA _A D D 7
MEM_ MA _W E# 109 RA S # D Q2 9 74 ME M_MA _D A T A3 0 C 1 81 *. 1U _ X7 R _1 0V _0 4
4 MEM_ MA _W E# SA 0 _D I M0_ 1 198 W E# D Q3 0 76 ME M_MA _D A T A3 1 MEM_ MA _A D D 11 1 4 RN1 1
SA0 D Q3 1 1 .8 V
SA 1 _D I M0_ 1 200 12 3 ME M_MA _D A T A3 2 MEM_ MA _A D D 6 2 3 4 P2 R X4 7_ 04 C 1 75 . 1U _ X7 R _10 V _04
SC L K 0 197 SA1 D Q3 2 12 5 ME M_MA _D A T A3 8
2 , 8, 1 5 SC L K 0 SD A T A0 195 SCL D Q3 3 13 5 ME M_MA _D A T A3 3 MEM_ MA _A D D 4 1 4 RN1 2
R 123 R 12 6 2 , 8, 1 5 SD A T A0 SDA D Q3 4 13 7 ME M_MA _D A T A3 4 MEM_ MA _A D D 2 2 3 4 P2 R X4 7_ 04 C 1 83 *. 1U _ X7 R _1 0V _0 4
MEM_ MA 0_O D T0 114 D Q3 5 12 4 ME M_MA _D A T A3 6 1 .8 V
10K _ 04 10 K _04 4 ME M_MA 0_ OD T0 MEM_ MA 0_O D T1 119 OD T 0 D Q3 6 12 6 ME M_MA _D A T A3 7 MEM_ MA _A D D 0 1 4 RN1 3 C 1 72 . 1U _ X7 R _10 V _04
4 ME M_MA 0_ OD T1

Sheet 7 of 35 4 MEM_ MA _D M[ 0. . 7 ] MEM_ MA_ D M0


MEM_ MA_ D M1
MEM_ MA_ D M2
10
26
52
OD T 1
D M0
D M1
D M2
D Q3 7
D Q3 8
D Q3 9
D Q4 0
D Q4 1
13 4
13 6
14 1
14 3
ME M_MA _D A T A3 5
ME M_MA _D A T A3 9
ME M_MA _D A T A4 0
ME M_MA _D A T A4 1 4 ME M_MA _ R AS #
4 ME M_MA 0 _C S #0
MEM_ MA _B A N K1 2
1
2
3 4 P2 R X4 7_ 04
4 RN1 4
3 4 P2 R X4 7_ 04
C 1 87

C 1 86
*. 1U _ X7 R _1 0V _0 4

. 01 U _1 6V _0 4
1 .8 V
MEM_ MA_ D M3 67 15 1 ME M_MA _D A T A4 2

DDRII SO-DIMM_0 MEM_ MA_ D M4


MEM_ MA_ D M5
MEM_ MA_ D M6
MEM_ MA_ D M7
130
147
170
185
D M3
D M4
D M5
D M6
D Q4 2
D Q4 3
D Q4 4
D Q4 5
15 3
14 0
14 2
15 2
ME M_MA _D A T A4 3
ME M_MA _D A T A4 4
ME M_MA _D A T A4 5
ME M_MA _D A T A4 6
4 ME M_MA 0 _OD T0 MEM_ MA _A D D 13
1
2
4 RN1 5
3 4 P2 R X4 7_ 04

D M7 D Q4 6 15 4 ME M_MA _D A T A4 7
MEM _MA _D QS 0_ P 13 D Q4 7 15 7 ME M_MA _D A T A4 8
4 MEM_ MA _D QS 0_ P MEM _MA _D QS 1_ P 31 D QS 0 D Q4 8 15 9 ME M_MA _D A T A4 9
4 MEM_ MA _D QS 1_ P MEM _MA _D QS 2_ P 51 D QS 1 D Q4 9 17 3 ME M_MA _D A T A5 0 CLO SE TO SO-D IMM _0
4 MEM_ MA _D QS 2_ P MEM _MA _D QS 3_ P 70 D QS 2 D Q5 0 17 5 ME M_MA _D A T A5 1
4 MEM_ MA _D QS 3_ P MEM _MA _D QS 4_ P 131 D QS 3 D Q5 1 15 8 ME M_MA _D A T A5 2
4 MEM_ MA _D QS 4_ P MEM _MA _D QS 5_ P 148 D QS 4 D Q5 2 16 0 ME M_MA _D A T A5 3 1 . 8V
4 MEM_ MA _D QS 5_ P MEM _MA _D QS 6_ P 169 D QS 5 D Q5 3 17 4 ME M_MA _D A T A5 4
4 MEM_ MA _D QS 6_ P MEM _MA _D QS 7_ P 188 D QS 6 D Q5 4 17 6 ME M_MA _D A T A5 5 .1 U _X 7R _ 10 V_ 04 . 0 1U _ 16 V_ 04 * 1. U _X 7R _ 10 V_ 04
4 MEM_ MA _D QS 7_ P D QS 7 D Q5 5 17 9 ME M_MA _D A T A5 6
MEM _MA _D QS 0_ N 11 D Q5 6 18 1 ME M_MA _D A T A5 7
4 MEM_ MA _D QS 0_ N MEM _MA _D QS 1_ N 29 D QS 0 # D Q5 7 18 9 ME M_MA _D A T A6 2
4 MEM_ MA _D QS 1_ N MEM _MA _D QS 2_ N 49 D QS 1 # D Q5 8 19 1 ME M_MA _D A T A5 8
4 MEM_ MA _D QS 2_ N D QS 2 # D Q5 9 C 1 22 C 10 9 C 1 23 C 127 C 13 0 C 1 26
MEM _MA _D QS 3_ N 68 18 0 ME M_MA _D A T A6 0
4 MEM_ MA _D QS 3_ N MEM _MA _D QS 4_ N 129 D QS 3 # D Q6 0 18 2 ME M_MA _D A T A6 1
4 MEM_ MA _D QS 4_ N MEM _MA _D QS 5_ N 146 D QS 4 # D Q6 1 19 2 ME M_MA _D A T A6 3 . 1U _ X7 R _10 V _04 *. 1U _ X7 R _1 0V _0 4 . 1U _ X7 R _1 0V _0 4
4 MEM_ MA _D QS 5_ N MEM _MA _D QS 6_ N 167 D QS 5 # D Q6 2 19 4 ME M_MA _D A T A5 9
4 MEM_ MA _D QS 6_ N MEM _MA _D QS 7_ N 186 D QS 6 # D Q6 3
4 MEM_ MA _D QS 7_ N D QS 7 #
1-7 34 074 -1
1 . 8V P L A C E C L O S E T O S O C K E T ( P ER E M I / EM C )
J_ D I MM_1 B
112 18
111 V DD1 V S S1 6 24
117 V DD2 V S S1 7 41
96 V DD3 V S S1 8 53
95 V DD4 V S S1 9 42
118 V DD5 V S S2 0 54 4 ME M_MA _ C LK 7_ P
3 . 3V S 81 V DD6 V S S2 1 59 P L A C E C L O S E T O P R OC E S S OR
82 V DD7 V S S2 2 65 tole ran ce 10% 11 13 C 1 06
2 0m il s 87 V DD8 V S S2 3 60 W TI H IN 1 . 5 I N C H
103 V DD9 V S S2 4 66
C 18 9 88 V DD1 0 V S S2 5 12 7 4 ME M_MA _ C LK 7_ N 1. 5P _ X7R _ 50 V _04
C 1 90 104 V DD1 1 V S S2 6 13 9
2. 2U _6. 3 V_ 06 V DD1 2 V S S2 7 12 8 4 ME M_MA _ C LK 1_ P
199 V S S2 8 14 5
. 1U _X 7R _ 10 V_ 04 V DDS P D V S S2 9 16 5 tole ran ce 10% 11 13 C 1 01
83 V S S3 0 17 1
120 NC1 V S S3 1 17 2
Z 07 01 50 NC2 V S S3 2 17 7 4 ME M_MA _ C LK 1_ N
5 , 8 C P U _ME MH OT# R 12 5 NC3 V S S3 3 1. 5 P_ X7 R _50 V _0 4
*0_ 04 02_ 5m li _s ho rt 69 18 7
MV R EF _ D IM 163 NC4 V S S3 4 17 8
2 0m il s N C T E ST V S S3 5 19 0
MVR E F _D I M 1 V S S3 6 9
VREF V S S3 7 21
D IM M0 _GN D 0 201 V S S3 8 33
C 159 D IM M0 _GN D 1 202 GN D 0 V S S3 9 15 5
C 1 58 GN D 1 V S S4 0 34
V S S4 1 13 2
2. 2U _ 6. 3V _ 06 V S S4 2
.1 U _X 7R _ 10 V_ 04 47 14 4
133 VSS1 V S S4 3 15 6
183 VSS2 V S S4 4 16 8
77 VSS3 V S S4 5 2 0. 9V 1 . 8V
12 VSS4 V S S4 6 3
48 VSS5 V S S4 7 15
184 VSS6 V S S4 8 27
78 VSS7 V S S4 9 39 C 1 65 C 1 79
71 VSS8 V S S5 0 14 9
VSS9 V S S5 1 C 1 71 C 1 74 C 1 77 C 1 55 C 1 56 C 1 51 C 1 54 C 1 52
72 16 1
121 V S S 10 V S S5 2 28
122 V S S 11 V S S5 3 40 1 0U _ 10 V_ 08 1 0U _ 10 V_ 08 . 1U _ X7 R _10 V _04 . 1U _ X7 R _10 V _04 . 1U _ X7 R _10 V _04 . 1U _ X7R _10 V _04 *. 1U _ X7 R _1 0V _0 4 . 01 U _16 V _0 4 . 1U _ X7R _ 10 V _04 . 1U _X 7R _ 10 V_ 04
196 V S S 12 V S S5 4 13 8
193 V S S 13 V S S5 5 15 0
8 V S S 14 V S S5 6 16 2
V S S 15 V S S5 7 1. 8V 1 8. V
1-7 34 074 -1
1. 8 V
+ C 1 67 C 1 48 C 146 C 19 1 C 15 3 C 1 70 C 18 2 C 1 50 C 1 62 C 147 C 149
R 1 11 0_ 04 C 15 7 1 00U _ 6. 3 V_ B 2 1 0U _ 10 V_ 08 10U _ 10 V_ 08 *10 U _1 0V _0 8 4. 7 U _6 .3 V _0 6 *4 . 7U _ 6. 3V _0 6 *1 U _6. 3 V_ 04 1 U _6 .3 V _04 1 U _6 . 3V _0 4 .2 2U _ X7 R _0 6 *. 22U _X7 R _0 6

R 1 09 3 3. V C 1 34 *. 1U _ X7 R _1 0V _0 4
1K _1 %_ 04 *. 1 U F_ 16 V _04
MV R E F_ D I M
8

U3 B Width 20 mi l ,len gth <6 in ch


Z 070 2 5 *L M35 8 *1 0_ 04 _1%
+ 7 Z 0 703 R 1 04 MV R E F _D I M
6
-
4

R 1 12 C 1 40 R 11 3 C 16 1 C 16 0
1 00 0P F _50 V _0 4 *1 0K _0 4
1 K _1 %_0 4 Z 0 70 4 R 1 08 *0_ 04 . 1U _ X7 R _1 0V _0 4 10 00 P_ X7 R _5 0V _0 4
R 110 *0 _04

B - 8 DDRII SO-DIMM_0
Schematic Diagrams

DDRII SO-DIMM_1

SO-DIMM 1
J_ D I MM_2 A 0. 9 V
4 ME M_ MB _A D D [ 0. . 1 5] ME M_ MB _A D D 0 10 2 5 ME M_M B_ D A TA 0 ME M_MB _ D A TA [ 63 : 0] 4
ME M_ MB _A D D 1 10 1 A0 D Q0 7 ME M_M B_ D A TA 1
ME M_ MB _A D D 2 10 0 A1 D Q1 17 ME M_M B_ D A TA 2
ME M_ MB _A D D 3 9 9 A2 D Q2 19 ME M_M B_ D A TA 3 4 1 R N 16
ME M_ MB _A D D 4 9 8 A3 D Q3 4 ME M_M B_ D A TA 4 4 MEM _MB _C KE 0 M EM_ MB _B A N K 2 3 2 4P 2R X4 7_ 04
ME M_ MB _A D D 5 9 7 A4 D Q4 6 ME M_M B_ D A TA 5
ME M_ MB _A D D 6 9 4 A5 D Q5 14 ME M_M B_ D A TA 6 M EM_ MB _A D D 1 2 4 1 R N 17
ME M_ MB _A D D 7 9 2 A6 D Q6 16 ME M_M B_ D A TA 7 M EM_ MB _A D D 9 3 2 4P 2R X4 7_ 04
ME M_ MB _A D D 8 9 3 A7 D Q7 23 ME M_M B_ D A TA 8
ME M_ MB _A D D 9 9 1 A8 D Q8 25 ME M_M B_ D A TA 9 M EM_ MB _A D D 8 4 1 R N 18 C 22 5 *. 1U _ X7 R _1 0V _ 04
ME M_ MB _A D D 1 0 10 5 A9 D Q9 35 ME M_M B_ D A TA 1 0 M EM_ MB _A D D 5 3 2 4P 2R X4 7_ 04 1 . 8V
ME M_ MB _A D D 1 1 9 0 A 10 / A P D Q10 37 ME M_M B_ D A TA 1 1 C 22 4 .1 U _ X7 R _1 0V _0 4
ME M_ MB _A D D 1 2 8 9 A 11 D Q11 20 ME M_M B_ D A TA 1 2 M EM_ MB _A D D 3 4 1 R N 19
ME M_ MB _A D D 1 3 11 6 A 12 D Q12 22 ME M_M B_ D A TA 1 3 M EM_ MB _A D D 1 3 2 4P 2R X4 7_ 04 C 21 6 *. 1U _ X7 R _1 0V _ 04
ME M_ MB _A D D 1 4 8 6 A 13 D Q13 36 ME M_M B_ D A TA 1 4 1 . 8V
4 ME M_ MB_ B AN K[ 0 . . 2] ME M_ MB _A D D 1 5 8 4 A 14 D Q14 38 ME M_M B_ D A TA 1 5 M EM_ MB _A D D 1 0 4 1 R N 20 C 22 6 .1 U _ X7 R _1 0V _0 4
ME M_ MB _B A N K 2 8 5 A 15 D Q15 43 ME M_M B_ D A TA 2 2 M EM_ MB _B A N K 0 3 2 4P 2R X4 7_ 04
A 16 _B A 2 D Q16 45 ME M_M B_ D A TA 1 7 C 21 2 *. 1U _ X7 R _1 0V _ 04
ME M_ MB _B A N K 0 10 7 D Q17 55 ME M_M B_ D A TA 1 8 4 MEM _MB _W E #
4 1 R N 21 1 . 8V
ME M_ MB _B A N K 1 10 6 BA0 D Q18 57 ME M_M B_ D A TA 1 6 4 MEM _MB _C AS #
3 2 4P 2R X4 7_ 04 C 22 8 .1 U _ X7 R _1 0V _0 4
4 M EM_ MB 0_ C S #0 ME M_ MB 0_ C S #0 11 0 BA1 D Q19 44 ME M_M B_ D A TA 2 0
4 M EM_ MB 0_ C S #1 ME M_ MB 0_ C S #1 11 5 S 0# D Q20 46 ME M_M B_ D A TA 2 1 4 MEM _MB 0_ C S #1
4 1 R N 22 C 20 9 *. 1U _ X7 R _1 0V _ 04
4 M EM_ MB _C L K 1_ P ME M_ MB _C L K 1_ P 3 0 S 1# D Q21 56 ME M_M B_ D A TA 2 3 4 MEM _MB 0_ OD T 1
3 2 4P 2R X4 7_ 04 1 . 8V
3. 3 V S 4 M EM_ MB _C L K 1_ N ME M_ MB _C L K 1_ N 3 2 CK 0 D Q22 58 ME M_M B_ D A TA 1 9 C 20 7 .1 U _ X7 R _1 0V _0 4
ME M_ MB _C L K 7_ P 16 4 C K 0# D Q23 61 1 4 R N 23

B.Schematic Diagrams
4 M EM_ MB _C L K 7_ P ME M_M B_ D A TA 2 4 4 MEM _MB _C KE 1
4 M EM_ MB _C L K 7_ N ME M_ MB _C L K 7_ N 16 6 CK 1 D Q24 63 ME M_M B_ D A TA 2 5 M EM_ MB _A D D 1 4 2 3 4P 2R X4 7_ 04
ME M_ MB _C K E 0 79 C K 1# D Q25 73 ME M_M B_ D A TA 2 6 C 20 5 *. 1U _ X7 R _1 0V _ 04
4 M EM_ MB _C K E 0 80 CK E 0 D Q26 75
R 1 30 4 M EM_ MB _C K E 1 ME M_ MB _C K E 1 ME M_M B_ D A TA 2 7 1 . 8V
4 ME M_MB _ C A S# ME M_ MB _C A S # 11 3 CK E 1 D Q27 62 ME M_M B_ D A TA 2 8 M EM_ MB _A D D 1 5 1 4 R N 24 C 22 2 .0 1U _1 6V _0 4
4. 7 K _0 4 4 ME M_MB _ R A S# ME M_ MB _R A S # 10 8 CA S # D Q28 64 ME M_M B_ D A TA 2 9 M EM_ MB _A D D 7 2 3 4P 2R X4 7_ 04
4 ME M_M B_ W E# ME M_ MB _W E # 10 9 RA S # D Q29 74 ME M_M B_ D A TA 3 0 C 22 3 *. 1U _ X7 R _1 0V _ 04
S A 0_ D I M1_ 1 19 8 W E# D Q30 76 ME M_M B_ D A TA 3 1 M EM_ MB _A D D 1 1 1 4 R N 25 1 . 8V
S A 1_ D I M1_ 1 20 0 SA0 D Q31 12 3 ME M_M B_ D A TA 3 2 M EM_ MB _A D D 6 2 3 4P 2R X4 7_ 04 C 21 1 .1 U _ X7 R _1 0V _0 4

R 1 32
2, 7 ,1 5 S C L K0
2, 7 ,1 5 S D A TA 0
S C L K0
S D A TA 0
19 7
19 5

ME M_ MB 0_ OD T0 11 4
SA1
SCL
SDA
D Q32
D Q33
D Q34
D Q35
12 5
13 5
13 7
12 4
ME M_M
ME M_M
ME M_M
ME M_M
B_ D A TA 3 3
B_ D A TA 3 4
B_ D A TA 3 5
B_ D A TA 3 6
M EM_ MB _A D D 4
M EM_ MB _A D D 2
1
2
4 R N 26
3 4P 2R X4 7_ 04 C 22 1 *. 1U _ X7 R _1 0V _ 04
1 . 8V
Sheet 8 of 35
4 M EM_ MB 0_ OD T0 ME M_ MB 0_ OD T1 11 9 OD T 0 D Q36 12 6 ME M_M B_ D A TA 3 7 M EM_ MB _A D D 0 1 4 R N 27
0_ 04 4 M EM_ MB 0_ OD T1
4 ME M_M B_ D M[ 0. . 7 ] ME M_ MB _D M0
ME M_ MB _D M1
10
26
OD T 1

D M0
D Q37
D Q38
D Q39
13 4
13 6
14 1
ME M_M
ME M_M
ME M_M
B_ D A TA 3 8
B_ D A TA 3 9
B_ D A TA 4 0
4 MEM _MB _R AS #
M EM_ MB _B A N K 1 2

1
3 4P 2R X4 7_ 04

4 R N 28
C 21 4

C 22 7
.1 U _ X7 R _1 0V _0 4

*. 1U _ X7 R _1 0V _ 04
1 . 8V
DDRII SO-DIMM_1
ME M_ MB _D M2 52 D M1 D Q40 14 3 ME M_M B_ D A TA 4 1 2 3 4P 2R X4 7_ 04 C 21 8 .1 U _ X7 R _1 0V _0 4
ME M_ MB _D M3 67 D M2 D Q41 15 1 ME M_M B_ D A TA 4 2 4 MEM _MB 0_ C S #0
ME M_ MB _D M4 13 0 D M3 D Q42 15 3 ME M_M B_ D A TA 4 3 1 4 R N 29
ME M_ MB _D M5 14 7 D M4 D Q43 14 0 ME M_M B_ D A TA 4 4 4 MEM _MB 0_ OD T 0 M EM_ MB _A D D 1 3 2 3 4P 2R X4 7_ 04
ME M_ MB _D M6 17 0 D M5 D Q44 14 2 ME M_M B_ D A TA 4 5
ME M_ MB _D M7 18 5 D M6 D Q45 15 2 ME M_M B_ D A TA 4 6
D M7 D Q46 15 4 ME M_M B_ D A TA 4 7
ME M_ MB _D QS 0 _P 13 D Q47 15 7 ME M_M B_ D A TA 4 8
4 ME M_MB _ D QS 0_ P ME M_ MB _D QS 1 _P 31 D QS 0 D Q48 15 9 ME M_M B_ D A TA 4 9
4 ME M_MB _ D QS 1_ P D QS 1 D Q49 1. 8 V
ME M_ MB _D QS 2 _P 51 17 3 ME M_M B_ D A TA 5 0
4 ME M_MB _ D QS 2_ P ME M_ MB _D QS 3 _P 70 D QS 2 D Q50 17 5 ME M_M B_ D A TA 5 1
4 ME M_MB _ D QS 3_ P D QS 3 D Q51 . 1U _ X7 R _1 0V _ 04 . 1U _ X7 R _1 0V _ 04 . 1U _ X7 R _1 0V _0 4
ME M_ MB _D QS 4 _P 13 1 15 8 ME M_M B_ D A TA 5 2
4 ME M_MB _ D QS 4_ P ME M_ MB _D QS 5 _P 14 8 D QS 4 D Q52 16 0 ME M_M B_ D A TA 5 3
4 ME M_MB _ D QS 5_ P ME M_ MB _D QS 6 _P 16 9 D QS 5 D Q53 17 4 ME M_M B_ D A TA 5 4
4 ME M_MB _ D QS 6_ P ME M_ MB _D QS 7 _P 18 8 D QS 6 D Q54 17 6 ME M_M B_ D A TA 5 5
4 ME M_MB _ D QS 7_ P D QS 7 D Q55 C 2 19 C 2 04 C 2 15 C 2 08 C 2 13 C 2 17
17 9 ME M_M B_ D A TA 5 6
ME M_ MB _D QS 0 _N 11 D Q56 18 1 ME M_M B_ D A TA 5 7
4 ME M_MB _ D QS 0_ N ME M_ MB _D QS 1 _N 29 D QS 0 # D Q57 18 9 ME M_M B_ D A TA 5 8
4 ME M_MB _ D QS 1_ N D QS 1 # D Q58 . 1U _ X7 R _1 0V _ 04 . 1U _ X7 R _1 0V _ 04 . 1U _ X7 R _1 0V _ 04
ME M_ MB _D QS 2 _N 49 19 1 ME M_M B_ D A TA 5 9
4 ME M_MB _ D QS 2_ N ME M_ MB _D QS 3 _N 68 D QS 2 # D Q59 18 0 ME M_M B_ D A TA 6 0
4 ME M_MB _ D QS 3_ N ME M_ MB _D QS 4 _N 12 9 D QS 3 # D Q60 18 2 ME M_M B_ D A TA 6 1
4 ME M_MB _ D QS 4_ N ME M_ MB _D QS 5 _N 14 6 D QS 4 # D Q61 19 2 ME M_M B_ D A TA 6 3
4 ME M_MB _ D QS 5_ N ME M_ MB _D QS 6 _N 16 7 D QS 5 # D Q62 19 4 ME M_M B_ D A TA 6 2
4 ME M_MB _ D QS 6_ N D QS 6 # D Q63 P L A C E C L O S E T O S O C K ET ( P ER E M I / E M C )
ME M_ MB _D QS 7 _N 18 6
4 ME M_MB _ D QS 7_ N D QS 7 #
2-17 34 07 2-2
1 .8 V
J_ D I MM_2 B
11 2 18
11 1 VDD1 VS S 16 24 4 ME M_MB _ C LK 7_ P
11 7 VDD2 VS S 17 41
VDD3 VS S 18 P L A C E C L OS E T O P R OC E S S O R
96 53 C 1 07
95 VDD4 VS S 19 42 to le ran ce 10 % 111 3 W I T H I N 1 5. I N C H
11 8 VDD5 VS S 20 54
3 . 3V S 81 VDD6 VS S 21 59 4 ME M_MB _ C LK 7_ N 1. 5 P _X 7R _ 50 V_ 04
82 VDD7 VS S 22 65
20 m i ls 87 VDD8 VS S 23 60 4 ME M_MB _ C LK 1_ P
10 3 VDD9 VS S 24 66
88 VDD1 0 VS S 25 12 7 C 1 08
VDD1 1 VS S 26 to le ran ce 10 % 111 3
C 20 0 10 4 13 9
C 2 01 VDD1 2 VS S 27 12 8
2. 2 U _6 . 3V _0 6 . 1U _ X7 R _1 0V _ 04 19 9 VS S 28 14 5 4 ME M_MB _ C LK 1_ N 1. 5 P _X 7R _ 50 V_ 04
VDDSP D VS S 29 16 5
83 VS S 30 17 1
12 0 NC1 VS S 31 17 2
R 13 1 Z 0 80 1 50 NC2 VS S 32 17 7
5, 7 C PU _ ME MH OT # *0_ 04 02 _5 mi _l sh ort 69 NC3 VS S 33 18 7
MV R E F_ D I M 16 3 NC4 VS S 34 17 8
20 m i ls N C T E ST VS S 35 19 0
MV R E F _D I M 1 VS S 36 9
VRE F VS S 37 21
C 19 8 D I MM1 _G N D 0 20 1 VS S 38 33
C 1 97 D I MM1 _G N D 1 20 2 GN D 0 VS S 39 15 5
2. 2 U _6 . 3V _0 6 GN D 1 VS S 40 34
VS S 41 13 2
. 1U _ X7 R _1 0V _ 04 47 VS S 42 14 4
13 3 V S S1 VS S 43 15 6
18 3 V S S2 VS S 44 16 8
77 V S S3 VS S 45 2
12 V S S4 VS S 46 3 0 . 9V
48 V S S5 VS S 47 15 1 .8 V
18 4 V S S6 VS S 48 27
78 V S S7 VS S 49 39
71 V S S8 VS S 50 14 9
72 V S S9 VS S 51 16 1 C 2 44 C 2 43 C 20 3 C 23 0 C 23 1
V S S1 0 VS S 52 + C 51 5 C 19 3 C 19 2
12 1 28
12 2 V S S1 1 VS S 53 40 1 U _6 . 3V _0 4 1U _6 .3 V _0 4 1U _ 6. 3 V _0 4 . 22 U _X 7R _ 06 . 22 U _X 7R _ 06 *22 0U _ 4V _ D 10U _1 0V _0 8 1 0U _10 V _0 8
19 6 V S S1 2 VS S 54 13 8
19 3 V S S1 3 VS S 55 15 0
8 V S S1 4 VS S 56 16 2
V S S1 5 VS S 57
2-17 34 07 2-2
1 . 8V

+ C 2 20 C 2 29 C 24 2 C 24 5 C 23 4 C 19 9
C 5 17 C 5 18 C 20 6 C 21 0 C 51 9 C 51 6 C 52 0 C 52 1
1 00 U _6 .3 V _B 2 10 U _ 10 V_ 08 *1 0U _ 10 V_ 08 10 U _1 0V _ 08 *4. 7 U _6 . 3V _ 06 4. 7 U _6 . 3V _0 6
.1 U _ X7 R _1 0V _0 4 . 1 U _X 7R _1 0V _0 4 * 1. U _ X7 R _1 0V _0 4 * .1 U _X 7R _1 0V _0 4 . 1 U _X 7R _ 10 V _0 4 . 0 1U _ 16 V_ 04 . 1U _X 7R _ 10 V_ 04 . 1U _ X7 R _ 10V _ 04

DDRII SO-DIMM_1 B - 9
Schematic Diagrams

RS780M-1
U 1 0A
Y 25 D2 4
3 H T_C PU _N B_ CAD _ H0 Y 24 H T_ RXC AD0 P H T_ TXC AD 0P D2 5 H T_N B_C PU _ CAD _ H0 3
3 H T_C PU _N B_ CAD _ L0 V 22 H T_ RXC AD0 N P AR T 1 OF 6 HT_TXCAD 0 N E24 H T_N B_C PU _ CAD _ L0 3
3 H T_C PU _N B_ CAD _ H1 V 23 H T_ RXC AD1 P H T_ TXC AD 1P E25 H T_N B_C PU _ CAD _ H1 3
3 H T_C PU _N B_ CAD _ L1 V 25 H T_ RXC AD1 N HT_TXCAD 1 N F24 H T_N B_C PU _ CAD _ L1 3
3 H T_C PU _N B_ CAD _ H2 V 24 H T_ RXC AD2 P H T_ TXC AD 2P F25 H T_N B_C PU _ CAD _ H2 3
3 H T_C PU _N B_ CAD _ L2 U 24 H T_ RXC AD2 N HT_TXCAD 2 N F23 H T_N B_C PU _ CAD _ L2 3
3 H T_C PU _N B_ CAD _ H3 U 25 H T_ RXC AD3 P H T_ TXC AD 3P F22 H T_N B_C PU _ CAD _ H3 3
3 H T_C PU _N B_ CAD _ L3 T25 H T_ RXC AD3 N HT_TXCAD 3 N H2 3 H T_N B_C PU _ CAD _ L3 3
3 H T_C PU _N B_ CAD _ H4 T24 H T_ RXC AD4 P H T_ TXC AD 4P H2 2 H T_N B_C PU _ CAD _ H4 3

HYPERTRANSPORT CPUI/F
3 H T_C PU _N B_ CAD _ L4 P 22 H T_ RXC AD4 N HT_TXCAD 4 N J2 5 H T_N B_C PU _ CAD _ L4 3
3 H T_C PU _N B_ CAD _ H5 P 23 H T_ RXC AD5 P H T_ TXC AD 5P J2 4 H T_N B_C PU _ CAD _ H5 3
3 H T_C PU _N B_ CAD _ L5 P 25 H T_ RXC AD5 N HT_TXCAD 5 N K24 H T_N B_C PU _ CAD _ L5 3
3 H T_C PU _N B_ CAD _ H6 P 24 H T_ RXC AD6 P H T_ TXC AD 6P K25 H T_N B_C PU _ CAD _ H6 3
3 H T_C PU _N B_ CAD _ L6 N 24 H T_ RXC AD6 N HT_TXCAD 6 N K23 H T_N B_C PU _ CAD _ L6 3
3 H T_C PU _N B_ CAD _ H7 N 25 H T_ RXC AD7 P H T_ TXC AD 7P K22 H T_N B_C PU _ CAD _ H7 3
3 H T_C PU _N B_ CAD _ L7 H T_ RXC AD7 N HT_TXCAD 7 N H T_N B_C PU _ CAD _ L7 3
AC 24 F21
3 H T_C PU _N B_ CAD _ H8 AC 25 H T_ RXC AD8 P H T_ TXC AD 8P G2 1 H T_N B_C PU _ CAD _ H8 3
3 H T_C PU _N B_ CAD _ L8 AB 25 H T_ RXC AD8 N HT_TXCAD 8 N G2 0 H T_N B_C PU _ CAD _ L8 3
3 H T_C PU _N B_ CAD _ H9 AB 24 H T_ RXC AD9 P H T_ TXC AD 9P H2 1 H T_N B_C PU _ CAD _ H9 3
3 H T_C PU _N B_ CAD _ L9 AA 24 H T_ RXC AD9 N HT_TXCAD 9 N J2 0 H T_N B_C PU _ CAD _ L9 3
3 H T_C PU _N B_ CAD _ H1 0 AA 25 H T_ RXC AD1 0 P HT_TXCAD 1 0P J2 1 H T_N B_C PU _ CAD _ H1 0 3
3 H T_C PU _N B_ CAD _ L1 0 Y 22 H T_ RXC AD1 0 N H T_ TXC AD1 0 N J1 8 H T_N B_C PU _ CAD _ L1 0 3
3 H T_C PU _N B_ CAD _ H1 1 Y 23 H T_ RXC AD1 1 P HT_TXCAD 1 1P K17 H T_N B_C PU _ CAD _ H1 1 3
3 H T_C PU _N B_ CAD _ L1 1 W 21 H T_ RXC AD1 1 N H T_ TXC AD1 1 N L1 9 H T_N B_C PU _ CAD _ L1 1 3
3 H T_C PU _N B_ CAD _ H1 2 W 20 H T_ RXC AD1 2 P HT_TXCAD 1 2P J1 9 H T_N B_C PU _ CAD _ H1 2 3
3 H T_C PU _N B_ CAD _ L1 2 V 21 H T_ RXC AD1 2 N H T_ TXC AD1 2 N M1 9 H T_N B_C PU _ CAD _ L1 2 3
B.Schematic Diagrams

3 H T_C PU _N B_ CAD _ H1 3 V 20 H T_ RXC AD1 3 P HT_TXCAD 1 3P L1 8 H T_N B_C PU _ CAD _ H1 3 3


3 H T_C PU _N B_ CAD _ L1 3 U 20 H T_ RXC AD1 3 N H T_ TXC AD1 3 N M2 1 H T_N B_C PU _ CAD _ L1 3 3
3 H T_C PU _N B_ CAD _ H1 4 U 21 H T_ RXC AD1 4 P HT_TXCAD 1 4P P21 H T_N B_C PU _ CAD _ H1 4 3
3 H T_C PU _N B_ CAD _ L1 4 U 19 H T_ RXC AD1 4 N H T_ TXC AD1 4 N P18 H T_N B_C PU _ CAD _ L1 4 3
3 H T_C PU _N B_ CAD _ H1 5 U 18 H T_ RXC AD1 5 P HT_TXCAD 1 5P M1 8 H T_N B_C PU _ CAD _ H1 5 3
3 H T_C PU _N B_ CAD _ L1 5 H T_ RXC AD1 5 N H T_ TXC AD1 5 N H T_N B_C PU _ CAD _ L1 5 3
T22 H2 4
3 H T_C PU _N B_ CL K_ H0 T23 H T_ RXC LK0 P H T_ TXC LK 0P H2 5 H T_N B_C PU _ CL K_H 0 3

Sheet 9 of 35 3
3
3
H T_C PU _N B_ CL K_ L0
H T_C PU _N B_ CL K_ H1
H T_C PU _N B_ CL K_ L1
AB 23
AA 22
H T_ RXC LK0 N
H T_ RXC LK1 P
H T_ RXC LK1 N
HT_TXCL K0 N
H T_ TXC LK 1P
HT_TXCL K1 N
L2 1
L2 0
H T_N B_C PU _ CL K_L 0 3
H T_N B_C PU _ CL K_H 1 3
H T_N B_C PU _ CL K_L 1 3
M22 M2 4

RS780M-1 3
3
3
H T_C PU _N B_ CTL _H 0
H T_C PU _N B_ CTL _L 0
H T_C PU _N B_ CTL _H 1
M23
R 21
R 20
H T_ RXC TL 0 P
H T_ RXC TL 0 N
H T_ RXC TL 1 P
HT_ TXCTL 0P
H T_ TXC TL 0 N
HT_ TXCTL 1P
M2 5
P19
R1 8
H T_N B_C PU _ CTL_ H 0
H T_N B_C PU _ CTL_ L 0
H T_N B_C PU _ CTL_ H 1
3
3
3
3 H T_C PU _N B_ CTL _L 1 H T_ RXC TL 1 N H T_ TXC TL 1 N H T_N B_C PU _ CTL_ L 1 3
R 3 03 3 0 1_ 1 %_0 4 H T_R X C A LP C 23 B24 H T _TX C A L P R 30 2 3 01 _ 1%_ 0 4
H T_R X C A LN A 24 H T_ RXC ALP HT_ TXCA LP B25 H T _ T XC AL N
H T_ RXC ALN H T_ TXC AL N
R S7 80 ( RX78 0 )

U 1 0B
D4 A5 GFX_ TX0P C 4 66 0 . 1u _1 0 V_X7 R_ 04 HD MI_ DA TA0 P
C4 G FX_ R X0 P G FX_TX0P B5 GFX_ TX0N C 4 67 0 . 1u _1 0 V_X7 R_ 04 HD MI_ DA TA0 N H DMI _D ATA0P 13
A3 G FX_ R X0 N P AR T 2 OF 6 G FX_ TX0 N A4 GFX_ TX1P C 4 60 0 . 1u _1 0 V_X7 R_ 04 HD MI_ DA TA1 P H DMI _D ATA0N 1 3
B3 G FX_ R X1 P G FX_TX1P B4 GFX_ TX1N HD MI_ DA TA1 N H DMI _D ATA1P 13
C 4 61 0 . 1u _1 0 V_X7 R_ 04 H DMI _D ATA1N 1 3
C2 G FX_ R X1 N G FX_ TX1 N C3 GFX_ TX2P C 4 53 0 . 1u _1 0 V_X7 R_ 04 HD MI_ DA TA2 P
C1 G FX_ R X2 P G FX_TX2P B2 H DMI _D ATA2P 13
GFX_ TX2N C 4 54 0 . 1u _1 0 V_X7 R_ 04 HD MI_ DA TA2 N
E5 G FX_ R X2 N G FX_ TX2 N D1 GFX_ TX3P C 4 49 0 . 1u _1 0 V_X7 R_ 04 HD MI_ CL KP H DMI _D ATA2N 1 3
F5 G FX_ R X3 P G FX_TX3P D2 GFX_ TX3N HD MI_ CL KN H DMI _C L KP 1 3
C 4 48 0 . 1u _1 0 V_X7 R_ 04 H DMI _C L KN 1 3
G5 G FX_ R X3 N G FX_ TX3 N E2
G6 G FX_ R X4 P G FX_TX4P E1
H5 G FX_ R X4 N G FX_ TX4 N F4
H6 G FX_ R X5 P G FX_TX5P F3
J6 G FX_ R X5 N G FX_ TX5 N F1
J5 G FX_ R X6 P G FX_TX6P F2
J7 G FX_ R X6 N G FX_ TX6 N H4

PCIE I/F GFX


J8 G FX_ R X7 P G FX_TX7P H3
L5 G FX_ R X7 N G FX_ TX7 N H1
L6 G FX_ R X8 P G FX_TX8P H2
M8 G FX_ R X8 N G FX_ TX8 N J2
L8 G FX_ R X9 P G FX_TX9P J1
P7 G FX_ R X9 N G FX_ TX9 N K4
M7 G FX_ R X1 0P GF X_ TX1 0P K3
P5 G FX_ R X1 0N G FX_TX1 0 N K1
M5 G FX_ R X1 1P GF X_ TX1 1P K2
R8 G FX_ R X1 1N G FX_TX1 1 N M4
P8 G FX_ R X1 2P GF X_ TX1 2P M3
R6 G FX_ R X1 2N G FX_TX1 2 N M1
R5 G FX_ R X1 3P GF X_ TX1 3P M2
P4 G FX_ R X1 3N G FX_TX1 3 N N2
P3 G FX_ R X1 4P GF X_ TX1 4P N1
T4 G FX_ R X1 4N G FX_TX1 4 N P1
T3 G FX_ R X1 5P GF X_ TX1 5P P2
G FX_ R X1 5N G FX_TX1 5 N
AE3 AC1 G PP_TX0P_ C C4 3 4 . 1 U_ X7 R _1 6V _0 4
18 PC IE_ N B_MI NI C ARD _ RXP AD 4 G PP_R X0P G PP_TX0P AC2 G PP_TX0N _ C C 4 35 . 1U _X7 R_ 1 6V_ 04 PC I E_N B_ MI N IC AR D_ TXP 1 8
18 PC IE_ N B_MI NI C ARD _ RXN AE2 G PP_R X0N G PP_ TX0 N AB4 PC I E_N B_ MI N IC AR D_ TXN 18
AD 3 G PP_R X1P G PP_TX1P AB3
AD 1 G PP_R X1N G PP_ TX1 N AA2 G PP_TX2P_ C C4 3 8 . 1 U_ X7 R _1 6V _0 4
21 PCI E_ NB_ C ARD R EAD ER_ R XP AD 2 G PP_R X2P G PP_TX2P AA1 G PP_TX2N _ C C 4 36 . 1U _X7 R_ 1 6V_ 04 PC I E_N B_ CA RD RE ADE R_ TXP 2 1
21 PCI E_ NB_ C ARD R EAD ER_ R XN V5 G PP_R X2N P CIE I/F GP P G PP_ TX2 N Y1 G PP_TX3P_ C PC I E_N B_ CA RD RE ADE R_ TXN 21
C4 3 9 . 1 U_ X7 R _1 6V _0 4 PC I E_N B_ EXPCAR D _TXP 18
18 PC IE_ N B_E XPC AR D_ R XP W6 G PP_R X3P G PP_TX3P Y2 G PP_TX3N _ C C 4 44 . 1U _X7 R_ 1 6V_ 04
18 PC IE_ N B_E XPC AR D_ R XN U5 G PP_R X3N G PP_ TX3 N Y4 PC I E_N B_ EXPCAR D _TXN 1 8
U6 G PP_R X4P G PP_TX4P Y3
U8 G PP_R X4N G PP_ TX4 N V1
U7 G PP_R X5P G PP_TX5P V2
G PP_R X5N G PP_ TX5 N
AA8 AD7 A_ TX0 P_C C9 . 1 U_ X7 R _1 6V _0 4
14 P CI E_S B_N B_ RX0 P Y8 SB_ RX0 P SB_TX0P AE7 A_ TX0 N_ C C 12 . 1U _X7 R_ 1 6V_ 04 PC I E_N B_ SB_ TX0P 14
14 P CI E_S B_N B_ RX0 N AA7 SB_ RX0 N SB_ TX0 N AE6 A_ TX1 P_C PC I E_N B_ SB_ TX0N 14
C8 . 1 U_ X7 R _1 6V _0 4 PC I E_N B_ SB_ TX1P 14
14 P CI E_S B_N B_ RX1 P Y7 SB_ RX1 P SB_TX1P AD6 A_ TX1 N_ C C 11 . 1U _X7 R_ 1 6V_ 04
14 P CI E_S B_N B_ RX1 N AA5 SB_ RX1 N SB_ TX1 N AB6 A_ TX2 P_C PC I E_N B_ SB_ TX1N 14
P CIE I/F S B C1 0 . 1 U_ X7 R _1 6V _0 4
14 P CI E_S B_N B_ RX2 P AA6 SB_ RX2 P SB_TX2P AC6 A_ TX2 N_ C C 16 . 1U _X7 R_ 1 6V_ 04 PC I E_N B_ SB_ TX2P 14
14 P CI E_S B_N B_ RX2 N W5 SB_ RX2 N SB_ TX2 N AD5 A_ TX3 P_C C4 3 1 . 1 U_ X7 R _1 6V _0 4 PC I E_N B_ SB_ TX2N 14
14 P CI E_S B_N B_ RX3 P Y5 SB_ RX3 P SB_TX3P AE5 A_ TX3 N_ C PC I E_N B_ SB_ TX3P 14
C 4 25 . 1U _X7 R_ 1 6V_ 04 PC I E_N B_ SB_ TX3N 14
14 P CI E_S B_N B_ RX3 N SB_ RX3 N SB_ TX3 N
AC8 Z09 01 R 26 9 1 .2 7 K_1 %_ 04 VD D_ PC IE
PC E_C AL RP( PC E_B CAL R P) AB8 Z09 02 R 23 2 K_ 1%_ 0 4
PC E_C AL RN (P CE_ BC ALR N )
R S7 80 ( RX78 0 )

B - 10 RS780M-1
Schematic Diagrams

RS780M-2
3. 3 V S
L11 H C B 1 608 K F-1 21 T2 5 C K _A V D D
C 73
2. 2U _ 6. 3 V_ 06
1. 8 VS

R 70 A VD D D I
*0_ 04 02 _2 0mi _l sh ort C 72

2. 2U _ 6. 3 V_ 06 U 1 0C
1 8. V S F12 A2 2
V S Y NC# R6 8 3K _0 4 E1 2 AV D D 1 (N C ) P A R T 3 OF 6 TX OU T_ L0 P(N C ) B2 2 N B _L V D S_ TX _L 0P 12
R 2 80 *3K _ 04 3. 3 VS L16 H C B 1 608 K F-1 21 T2 5 F14 AV D D 2 (N C ) T XOU T _L 0N (N C ) A2 1 N B _L V D S_ TX _L 0N 12
C 57 G1 5 AV D D D I (N C ) TX OU T_ L1 P(N C ) B2 1 N B _L V D S_ TX _L 1P 12
Z 10 73 H 1 5 AV S S D I( N C ) T XOU T _L 1N (N C ) B2 0 N B _L V D S_ TX _L 1N 12
2. 2U _ 6. 3 V_ 06 H1 4 AV D D Q(N C ) TX OU T_ L2 P(N C ) A2 0 N B _L V D S_ TX _L 2P 12
H S Y N C # R 2 95 3K _0 4 AV S S Q(N C ) TX OU T _L2 N (D B G_GP I O0) A1 9 N B _L V D S_ TX _L 2N 12
R 2 86 *3K _ 04 3. 3 VS Z 10 76 E 1 7 TX OU T_ L3 P(N C ) B1 9
Z 10 77 F 1 7 C _P r(D FT _GP I O5) TX OU T _L3 N (D B G_GP I O2)

C RT /T V OU T
R X 7 4 0/ R S 7 4 0 /R S 78 0 d i ff e re n ce t a b l e C 64 2 2P _ 50V _ 04 Z 10 78 F 1 5 YD( F T _GP I O2) B1 8
N B _L V D S_ TX _U 0 P 12
C OMP_ P b(D F T_ GP IO 4 ) T XOU T _U 0 P(N C ) A1 8
150R termination < 1 inch trace G1 8 TX OU T_ U 0N (N C ) A1 7 N B _L V D S_ TX _U 0 N 12
R S 7 40 R X7 80 R S 7 80 13 N B _V GA _R C 62 2 2P _ 50V _ 04 N B _L V D S_ TX _U 1 P 12
R 42 1 40 _1 %_ 04 G1 7 R ED (D F T _GP I O0) TX OU T_ U 1P (P C I E_ R E SE T _GP I O3) B1 7
E1 8 R ED b (N C ) TX OU T_ U 1N (P C I E_ R E SE T _GP I O2) D 20 N B _L V D S_ TX _U 1 N 12
N B _P W R GD 3 . 3V I N 1. 8 V I N 1 . 8V I N 13 N B _V GA _G C 63 2 2P _ 50V _ 04 GR EE N (D F T_ GP OI 1) T XOU T _U 2 P(N C ) N B _L V D S_ TX _U 2 P 12
IN R 60 1 50 _1 %_ 04 F18 D 21
A LL OW _LD TS TOP OC OC OC / 1 . 8V I N E1 9 GR EE N b (N C ) TX OU T_ U 2N (N C ) D 18 N B _L V D S_ TX _U 2 N 12
13 N B _V GA _B R 61 1 50 _1 %_ 04 F19 BL U E D
( F T _GP I O3) TX OU T_ U 3P (P C I E_ R E SE T _GP I O5) D 19
OU T (de f au lt )/ I N * BL U E b(N C ) TX OU T_ U 3N (N C )
L D T_ ST OP # 3 . 3V I N 1. 8 V I N 3 . 3V I N / OC
I N (de f a ul t) / I N * HS Y NC# A1 1 B1 6
13 H SY N C # V S Y NC# B1 1 D AC _ H S Y N C (PW M_ GPI O4 ) T XC L K_ LP (D B G_GP I O1) A1 6 N B _L V D S_ TX _C L K LP 12 1. 8V S
*, C L MC mod e: N B se nd L D T_ S TOP #, A LL OW _LD TS TOP w il l b ec ome in pu t 13 VS Y N C # R4 1 *0_ 04 02 _5 mi _l sh ort Z 10 01 F 8 D AC _ V SY N C (P W M_GP I O6) TX C LK _L N (D B G_GP I O3) D 16 N B _L V D S_ TX _C L K LN 12
1 3 N B _C R T _D D C _ C LK R4 0 *0_ 04 02 _5 mi _l sh ort Z 10 02 E 8 D AC _ S C L(P C E _R C A LR N ) TX C LK _U P (P C I E_ R E SE T _GP I O4) D 17 N B _L V D S_ TX _C L K U P 1 2
1 . 1V S 1 3 N B _C R T _D D C _ D A TA D AC _ S D A(P C E _T C A LR N ) T XC L K _U N (P C I E_ R E SE T _GP I O1) N B _L V D S_ TX _C L K U N 1 2
R6 9 Z 10 03 G1 4
L1 4 H C B 16 08 K F-1 21 T2 5 71 5_1 %_ 04 D AC _ R S ET (PW M_ GPI O1 ) A1 3 Z 10 13 L50 H C B 16 08 K F-1 21 T2 5

B.Schematic Diagrams
L1 5 H C B 16 08 K F-1 21 T2 5 P LL V D D A1 2 V D D LT P1 8(N C ) B1 3 C 4 81
P LL V D D 18 D1 4 PL LV D D (N C ) V S S LT P1 8(N C ) 2 . 2U _ 6. 3 V_ 06 1. 8V S
B1 2 PL LV D D 1 8(N C ) A1 5 Z 10 14
PL LV S S(N C ) VD D LT 18_ 1(N C )
600mA

L VT M
1 . 8V S B1 5

PLL PWR
VD D LT 18_ 2(N C ) L 52 H C B 16 08 KF -12 1T 25

C 71 C9 5
L1 2
L9
H C B 16 08 KF -1 21T 25
H C B 16 08 KF -1 21T 25
V D D A 18 H TP L L
V D D A 18 P C I EP L L
R 67
H1 7

D 7
E7
VD D A 1 8H T PL L

VD D A 1 8P C I EP L L1
VD
VD
D LT 33_ 1(N C )
D LT 33_ 2(N C )
A1 4
B1 4
C 14
Z 10 15
Z 10 74
C 4 87
Sheet 10 of 35
VD D A 1 8P C I EP L L2 VS S LT 1(V S S)
10 U _6 . 3V _0 6 1 0U _ 6. 3V _ 08
2. 2 U _6 .3 V _0 6
C 4 76
2 . 2U _ 6. 3V _ 06
C 90

2. 2 U _6 . 3V _0 6
C5 8 C 61
2 . 2U _ 6. 3 V_ 06 14 , 16 , 26 A _R S T #
26 N B _ PW R GD _ I N
*0 _0 402 _5 mi l_ sh ort
A_ R S T# Z 10 04

N B_ LD T _S TOP #
D 8
A1 0
C1 0
SY S R E S ET b
POW E R GOOD
VS S LT 2(V S S)
VS S LT 3(V S S)
VS S LT 4(V S S)
D 15
C 16
C 18
C 20
C 48 0
. 1U _ 16 V_ 04 4 . 7U _ 6. 3V _ 06
RS780M-2
N B_ A LL OW_ LD T ST OP C 1 2 LD TS T OP b VS S LT 5(V S S) E2 0

PM
AL LOW _L D TS T OP VS S LT 6(V S S) C 22
N B H T_ C LK P C2 5 VS S LT 7(V S S)
2 N BH T _C L K P N B H T_ C LK N C2 4 H T_R EF C L KP
2 N BH T _C L K N H T_R EF C L KN
R5 5 N B _ R EF C L K_ P E 1 1

CLOCKs
2 N B_ OS C R EF C L K_ P /O S C I N (OS C I N )
R2 9 * 0_ 040 2_ 5m il _s ho rt N B _ R EF C L K_ N F 1 1 R EF C L K_ N (PW M_ GPI O3 ) L V D S_ D I GON (P C E_ TC A L R P)
E9 Z 10 16 R5 8 *0 _04 02 _5 mi _l sh ort N B_ LC D _ P WR _ EN 1 2
1 . 1V S R2 6 4. 7 K_ 04 Z 10 05 *0 _0 40 2_ 5mi l _sh ort F7 Z 10 79 R2 8 *0_ 04
R2 5 4 .7 K _0 4 N B GF X_ C LK P T2 LV D S _B LON (P C E _R C A L R P) G12 Z 10 18 R3 3
3 . 3V S 2 N B GF X_ C LK P N B GF X_ C LK N T1 GFX _R E F C LK P LV D S _E N A _B L(P W M_GP I O2) *0 _0 40 2_ 5mi l _sh ort N B_ LC D _ B KL _E N 12
2 N B GF X_ C LK N GFX _R E F C LK N R3 4 R 32 R 54
R 28 2 4 . 7K _0 4 Z 10 06 U 1
R 28 9 4 . 7K _0 4 Z 10 07 U 2 GPP _ R EF C L KP
R 28 1 4 . 7K _0 4 GPP _ R EF C L KN
S B LI N K _ C LK P V4
2 S B LI N K _C L K P V3 GPP S B _R E F C LK P (SB _R EF C L KP )
R 28 8 4 . 7K _0 4 2 S B LI N K _C L K N S B LI N K _ C LK N * 1. 27 K _0 4 1. 2 7K _0 41 . 27 K _04
GPP S B _R E F C LK N (S B_ R E FC L K N )
N B _L C D _D D C _ C LK B9
1 2 N B _LC D _D D C _ C LK N B _L C D _D D C _ D A TA A9 I2 C _C L K D9
1 2 N B _LC D _D D C _ D AT A
1 3 N B _H D MI _ D D C _C L K
N B _H D MI _ D D C _C L K A8 2I C _D A T A
D D C _C L K0 / AU X0P (N C )
MIS. TMD S _ H PD (N C )
H PD (N C )
D 10 TMD S _H P D 0 1 3
N B _H D MI _ D D C _D A T A B8
1 3 N B _H D MI _ D D C _D A T A Z 10 08 B 7 D D C _D A TA 0 /A U X 0N (N C ) D 12 Z 10 20
D D C _C L K1 / AU X1P (N C ) S U S _S T AT #(P W M_GP I O5) R7 4 *0 _04 S U S_ S TA T# 1 5
3 . 3V S Z 10 09 A 7
D D C _D A TA 1 /A U X 1N (N C ) AE 8 Z 10 21
R 2 87 10 K_ 04 B1 0 TH E R MA LD I OD E _P AD 8 Z 10 22 R7 3
ST R P _D A TA T H E R MAL D I OD E _N 1 0K _0 4
29 ST R P _D A TA Z 10 11 G1 1 D 13 T ES T_ E N
R SV D TE S TMOD E
Z 10 12 C 8
AU X _C A L N
( C) R 29 4
R S 78 0(R X 78 0) 1. 8 K_ 1% _0 4

U 10 D
PA R 4 O F6
Z 10 23 A B 12 A A 18 Z 1 05 0
Z 10 24 A E 16 ME M_ A0 (N C ) ME M_D Q0 / D V O_V S Y N C (N C ) A A 20 Z 1 05 1
5, 1 4 C P U _L D T_ ST OP # R 72 N B _L D T_ S TOP # Z 10 25 V 11 ME M_ A1 (N C ) ME M_D Q1 / D VO_ H S Y N C (N C ) A A 19 Z 1 05 2
* 0_ 040 2_ 5m li _s ho rt Z 10 26 A E 15 ME M_ A2 (N C ) ME M_D Q2 / D VO _D E (N C ) Y1 9 Z 1 05 3
Z 10 27 A A 12 ME M_ A3 (N C ) ME M_ D Q3/ D V O_D 0 (N C ) V 17 Z 1 05 4
Z 10 28 A B 16 ME M_ A4 (N C ) ME M_D Q4 (N C ) A A 17 Z 1 05 5
Z 10 29 A B 14 ME M_ A5 (N C ) ME M_ D Q5/ D V O_D 1 (N C ) A A 15 Z 1 05 6
Z 10 30 A D 14 ME M_ A6 (N C ) ME M_ D Q6/ D V O_D 2 (N C ) Y1 5 Z 1 05 7
1. 8 VS Z 10 31 A D 13 ME M_ A7 (N C ) ME M_ D Q7/ D V O_D 4 (N C ) A C 20 Z 1 05 8
Z 10 32 A D 15 ME M_ A8 (N C ) ME M_ D Q8/ D V O_D 3 (N C ) A D 19 Z 1 05 9
SBD_MEM/DVO_I/F

Z 10 33 A C 16 ME M_ A9 (N C ) ME M_ D Q9/ D V O_D 5 (N C ) A E 22 Z 1 06 0
Z 10 34 A E 13 ME M_ A1 0(N C ) ME M_D Q1 0/ D V O_D 6 (N C ) A C 18 Z 1 06 1
R 2 96 Z 10 35 A C 14 ME M_ A1 1(N C ) ME M_D Q1 1/ D V O_D 7 (N C ) A B 20 Z 1 06 2
3 00 _0 4 Z 10 36 Y 14 ME M_ A1 2(N C ) M EM_ D Q12 (N C ) A D 22 Z 1 06 3
ME M_ A1 3(N C ) ME M_D Q1 3/ D V O_D 9 (N C ) A C 22 Z 1 06 4
R 30 4 * 0_ 04 02_ 5m li _s ho rt Z 10 37 A D 16 ME M_ D Q14 / D VO_ D 10 (N C ) A D 21 Z 1 06 5
5 C PU _ LD T _R E Q# Z 10 38 A E 17 ME M_ BA 0 (N C ) ME M_ D Q15 / D VO_ D 11 (N C )
Z 10 39 A D 17 ME M_ BA 1 (N C ) Y1 7 Z 1 06 6
R 3 05 N B _A L LOW _L D TS TOP ME M_ BA 2 (N C ) ME M_D QS 0P / D V O_I D C K P (N C ) W 18 Z 1 06 7 S T R A P _ D E B U G _ B U S _ G P I O _E N A B L Eb
14 A LL OW _LD TS TOP
*0 _0 40 2_ 5mi l _s hort Z 10 40 W 12 ME M_D QS0 N / D V O_I D C K N (N C ) A D 20 Z 1 06 8
Z 10 41 Y 12 ME M_ R AS b (N C ) ME M_ D QS 1P (N C ) A E 21 Z 1 06 9
2 008/03/18 Z 10 42 A D 18 ME M_ C AS b (N C ) ME M_D Q S1 N (N C )
Z 10 43 A B 13 ME M_ WE b(N C ) W 17 Z 1 07 0 Enables the Test Debug Bus using GPIO .
Z 10 44 A B 18 ME M_ C Sb (N C ) ME M_D M0 (N C ) A E 19 Z 1 07 1 RX780:NB_TV_C; R S740:RS740_DFT_GPIO5; RS780:VSYNC#
Z 10 45 V 14 ME M_ C KE (N C ) ME M_ D M1/ D V O_D 8 (N C )
ME M_ OD T(N C ) A E 23 1. 8V S
Z 10 46 V 15 I OP L LV D D 18 (N C ) A E 24 1. 1V S RS740/RS780 RX780
Z 10 47 W 14 ME M_ C KP (N C ) I OP LL V D D (N C )
ME M_ C KN (N C )
1 Disable Enable
A D 23
Z 10 48 A E 12 I OP LL VS S (N C ) 0 Enable Disable
Z 10 49 A D 12 ME M_ C OMP P(N C ) A E 18 Z 1 07 2 R 27 3 0 _0 4
ME M_ C OMP N N (C ) ME M_V R E F (N C )
R S 78 0(R X7 80 ) R S 7 40 / R S 7 8 0: E n a b l e s S i d e p o rt m e m o ry

RS740:RS740_DFT_ GPIO0
RS780:HSYNC#

Selects if Memor y SIDE PORT is availa ble or not


1 = Memory Side port Not available
0 = Memory Side port available
Register Readbac k of strap:
NB_CLKCFG:CLK_TO P_SPARE_D[1]

RS780M-2 B - 11
Schematic Diagrams

RS780M-3
1 .1 VS
V D D_ P C IE 1 .1 VS
1.2V(RS740) 1.1V(RX780;RS780) 1.2V(RS740) 1.1V(RX780;RS780)
U1 0 E U 1 0F
L10 H C B 1 6 0 8 K F -1 2 1 T2 5 Z1 101 J17 A6 V D D_ P CIE L8 A2 A 25
K1 6 V DD HT _ 1 V DD P C IE _ 1 B6 H C B 1 6 0 8K F -1 2 1T 2 5 B1 V SSAPC IE1 V S S A HT 1 D 23
L16 V DD HT _ 2 PART 5/ 6 V DD P C IE _ 2 C6 D3 V SSAPC IE2 PAR T 6 /6 V S S A HT 2 E 22
C4 5 C 60 C 59 M1 6 V DD HT _ 3 V DD P C IE _ 3 D6 C5 4 C3 0 D5 V SSAPC IE3 V S S A HT 3 G 22
C4 6 C4 6 5 C 39 C 31
4 .7 U_ 6 .3 V _ 0 6 .1 U_ 1 6 V _ 0 4 .1 U_ 1 6 V _ 0 4 . 1 U _1 6 V _ 0 4 P1 6 V DD HT _ 4 V DD P C IE _ 4 E6 .1 U_ 1 6 V _ 0 4 .1 U_ 1 6 V _ 0 4 1 U_ 1 0 V _ 0 6 1 U_ 1 0 V_ 0 6 4 .7 U_ 6 .3 V _ 0 6 E4 V SSAPC IE4 V S S A HT 4 G 24
R1 6 V DD HT _ 5 V DD P C IE _ 5 F6 G1 V SSAPC IE5 V S S A HT 5 G 25
T16 V DD HT _ 6 V DD P C IE _ 6 G7 G2 V SSAPC IE6 V S S A HT 6 H 19
V DD HT _ 7 V DD P C IE _ 7 H8 G4 V SSAPC IE7 V S S A HT 7 J22
L51 H C B 1 6 0 8 K F -1 2 1 T2 5 V D DH T RX H1 8 V DD P C IE _ 8 J9 H7 V SSAPC IE8 V S S A HT 8 L17
G1 9 V DD HT R X _1 V DD P C IE _ 9 K9 J4 V SSAPC IE9 V S S A HT 9 L22
F20 V DD HT R X _2 V DD P C IE _ 1 0 M9 R7 V SSAPC IE1 0 V S S A HT 1 0 L24
4 .7 U_ 6 .3 V _ 0 6 C4 8 6 C4 7 9 C 82 C 74 E2 1 V DD HT R X _3 V DD P C IE _ 1 1 L9 L1 V SSAPC IE1 1 V S S A HT 1 1 L25
D2 2 V DD HT R X _4 V DD P C IE _ 1 2 P9 L2 V SSAPC IE1 2 V S S A HT 1 2 M 20
.1 U_ 1 6 V _ 0 4 .1 U_ 1 6 V _ 0 4 . 1 U _1 6 V _ 0 4
B2 3 V DD HT R X _5 V DD P C IE _ 1 3 R9 L4 V SSAPC IE1 3 V S S A HT 1 3 N 22
1 .2 VS A2 3 V DD HT R X _6 V DD P C IE _ 1 4 T9 L7 V SSAPC IE1 4 V S S A HT 1 4 P 20
V DD HT R X _7 V DD P C IE _ 1 5 V9 M6 V SSAPC IE1 5 V S S A HT 1 5 R 19
V D D H T TX AE2 5 V DD P C IE _ 1 6 U9 N4 V SSAPC IE1 6 V S S A HT 1 6 R 22
L7 H C B 1 6 0 8 K F -1 2 1 T 2 5
C 32 A D2 4 V DD HT T X _ 1 V DD P C IE _ 1 7 1 .1 VS P6 V SSAPC IE1 7 V S S A HT 1 7 R 24
C3 3 C 25 C2 7 A C2 3 V DD HT T X _ 2 K1 2 R1 V SSAPC IE1 8 V S S A HT 1 8 R 25
4 . 7 U _ 6. 3V _0 6 C2 6 . 1U _ 1 6V _ 04 . 1 U _ 16 V _ 0 4 . 1 U _1 6 V _ 0 4 1 0 U_ 6 .3 V _ 0 6
AB2 2 V DD HT T X _ 3 V D DC _ 1 J14 R2 V SSAPC IE1 9 V S S A HT 1 9 H 20
. 1 U _1 6 V _ 0 4
AA2 1 V DD HT T X _ 4 V D DC _ 2 U1 6 C 15 C 21 R4 V SSAPC IE2 0 V S S A HT 2 0 U 22
. 1 U _ 1 6 V _ 0 4. 1 U _ 16 V _0 4 .1 U_ 1 6 V _ 0 4 Y2 0 V DD HT T X _ 5 V D DC _ 3 J11 C 13 C2 4 C 43 C4 4 C 20 C 14 C1 9 V7 V SSAPC IE2 1 V S S A HT 2 1 V 19
W19 V DD HT T X _ 6 V D DC _ 4 K1 5 U4 V SSAPC IE2 2 V S S A HT 2 2 W 22

GROUND
POWER
V1 8 V DD HT T X _ 7 V D DC _ 5 M1 2 V8 V SSAPC IE2 3 V S S A HT 2 3 W 24
U1 7 V DD HT T X _ 8 V D DC _ 6 L14 . 1U _ 1 6V _ 04 .1 U_ 1 6 V _ 0 4 .1 U_ 1 6 V _ 0 4 . 1 U _ 1 6V _0 4 1 0 U_ 6 .3 V _ 0 6 V6 V SSAPC IE2 4 V S S A HT 2 4 W 25
B.Schematic Diagrams

T17 V DD HT T X _ 9 V D DC _ 7 L11 W1 V SSAPC IE2 5 V S S A HT 2 5 Y 21


R1 7 V DD H T T X _ 10 V D DC _ 8 M1 3 W2 V SSAPC IE2 6 V S S A HT 2 6 A D2 5
P1 7 V DD H T T X _ 11 V D DC _ 9 M1 5 W4 V SSAPC IE2 7 V S S A HT 2 7
1 .8 VS M1 7 V DD H T T X _ 12 V D DC _ 1 0 N1 2 W7 V SSAPC IE2 8 L12
V DD H T T X _ 13 V D DC _ 1 1 N1 4 W8 V SSAPC IE2 9 VSS1 1 M 14
L6 H C B 1 6 0 8 K F -1 2 1 T 2 5 .1 U_ 1 6 V _ 0 4 V D D A 18 P C I E J10 V D DC _ 1 2 P1 1 Y6 V SSAPC IE3 0 VSS1 2 N 13
P1 0 V DD A 1 8 P CIE _1 V D DC _ 1 3 P1 3 AA4 V SSAPC IE3 1 VSS1 3 P 12
C 22 C2 3 C 17 C 41 K1 0 V DD A 1 8 P CIE _2 V D DC _ 1 4 P1 4 AB5 V SSAPC IE3 2 VSS1 4 P 15

Sheet 11 of 35
C4 0 C 18
4 . 7 U _ 6. 3V _0 6 . 1 U _1 6 V _ 0 4 M1 0 V DD A 1 8 P CIE _3 V D DC _ 1 5 R1 2 AB1 V SSAPC IE3 3 VSS1 5 R 11
L10 V DD A 1 8 P CIE _4 V D DC _ 1 6 R1 5 AB7 V SSAPC IE3 4 VSS1 6 R 14
W9 V DD A 1 8 P CIE _5 V D DC _ 1 7 T11 A C3 V SSAPC IE3 5 VSS1 7 T12
4 . 7 U _6 . 3 V _ 0 6 .1 U_ 1 6 V _ 0 4 .1 U_ 1 6 V _ 0 4

RS780M-3 H9
T10
R1 0
V
V
V
DD
DD
DD
A 1 8 P CIE
A 1 8 P CIE
A 1 8 P CIE
_6
_7
_8
V D DC _ 1 8
V D DC _ 1 9
V D DC _ 2 0
T15
U1 2
T14
A C4
AE1
AE4
V
V
V
SSAPC
SSAPC
SSAPC
IE3 6
IE3 7
IE3 8
VSS1 8
VSS1 9
VSS2 0
U 14
U 11
U 15
Y9 V DD A 1 8 P CIE _9 V D DC _ 2 1 J16 AB2 V SSAPC IE3 9 VSS2 1 V 12
AA9 V DD A 1 8 P CIE _ 10 V D DC _ 2 2 V SSAPC IE4 0 VSS2 2 W 11
1 .8 VS AB9 V DD A 1 8 P CIE _ 11 AE1 0 VSS2 3 W 15
A D9 V DD A 1 8 P CIE _ 12 VD D_ M E M1 (N C) AA1 1 AE1 4 VSS2 4 A C1 2
AE9 V DD A 1 8 P CIE _ 13 VD D_ M E M2 (N C) Y1 1 D1 1 V SS1 VSS2 5 A A1 4
U1 0 V DD A 1 8 P CIE _ 14 VD D_ M E M3 (N C) AD 1 0 G8 V SS2 VSS2 6 Y 18
1U _ 1 0V _0 6 C5 5
V DD A 1 8 P CIE _ 15 VD D_ M E M4 (N C) AB1 0 E1 4 V SS3 VSS2 7 A B1 1
1 .8 VS F9 VD D_ M E M5 (N C) AC 1 0 E1 5 V SS4 VSS2 8 A B1 5
G9 V DD 1 8_ 1 VD D_ M E M6 (N C) 3 .3 VS J1 5 V SS5 VSS2 9 A B1 7
R 272 * 0_ 0 6 0 3 _3 2 m i l _s h o rt Z1 1 0 3 AE1 1 V DD 1 8_ 2 H1 1 Z1102 R5 9 J1 2 V SS6 VSS3 0 A B1 9
A D1 1 V DD 1 8_ M E M 1( N C ) V D D 3 3_ 1 (N C ) H1 2 *0 _ 0 60 3 _ 3 2 m li _ s h or t K1 4 V SS7 VSS3 1 A E2 0
V DD 1 8_ M E M 2( N C ) V D D 3 3_ 2 (N C ) C 42 C5 6 M1 1 V SS8 VSS3 2 A B2 1
* 1U _ 1 0 V _ 06 C4 3 0
R S 7 8 0 (R X 7 8 0 ) . 1U _ 1 6V _ 04 . 1U _ 1 6 V _ 04 L1 5 V SS9 VSS3 3 K 11
V SS1 0 VSS3 4
R S 7 8 0 (R X7 8 0 )

R S7 40 /R X78 0 /RS 78 0 PO W ER D IFFEREN CE TA BLE


P I N N A ME RS7 40 RX78 0 RS780 P I N N A ME RS740 RX7 80 RS78 0
VD D HT N C + 1 .1 V + 1. 1 V I OP LL V D D +1 . 2 V N C + 1 .1 V

V D D HT RX N C + 1 .1 V + 1. 1 V AVD D +3 . 3 V N C + 3 .3 V

VD D HT T X + 1 .2 V + 1 .2 V + 1. 2 V A V D DD I +1 . 8 V N C + 1 .8 V

V D D A 1 8P C I E N C + 1 .8 V + 1. 8 V A V D DQ +1 . 8 V N C + 1 .8 V

V D D G1 8 + 1 .8 V + 1 .8 V + 1. 8 V P L L V DD +1 . 2 V N C + 1 .1 V

V D D 18 _ M E M N C N C + 1. 8 V P L L V DD 1 8 +1 . 8 V N C + 1 .8 V

V D D P CIE + 1 .2 V + 1 .1 V + 1. 1 V V D DA 1 8 P C IE P L L +1 . 2 V + 1 .8 V + 1 .8 V

VD D C + 1 .2 V + 1 .1 V + 1. 1 V V D D A 1 8 H TP LL +1 . 8 V + 1 .8 V + 1 .8 V

V D D _M E M +1 . 8 V / 1 . 5 V N C + 1 .8 V /1 .5 V V D DL T P 1 8 +1 . 8 V N C + 1 .8 V

V D D G3 3 + 3 .3 V N C + 3. 3 V V D DL T 1 8 +1 . 8 V N C + 1 .8 V

IO P L L V DD 1 8 + 1 .8 V N C + 1. 8 V V D DL T 3 3 +3 . 3 V N C N C

B - 12 RS780M-3
Schematic Diagrams

LVDS, Inverter
PAN EL CON NEC TOR
COSTDOWN
VI N L3
H C B 16 08 KF -12 1T 25 J_ LC D 1 3 . 3V
80mil s 1 2 N B _L C D _D D C _ D AT A
3 1 2 4 N B _LC D _ D D C _D A TA 10 D 20
3 4 N B _L C D _D D C _ C LK N B _LC D _ D D C _C L K 10
5 6 C
7 5 6 8 B R I GH TN E SS B R I GH TN E SS AC C 36 7
C4 C 42 2 C 4 23 9 7 8 10 B R I GH T N E SS 24 A *. 1U _ 10 V_ X7 R _04
11 9 10 12 I N V _B LON
0 . 1u _50 V_ Y 5V _0 6 0 .1 u_ 50V _ Y5 V _06 0 . 1u_ 50 V_ Y 5V _0 6 13 11 12 14 *B AV 99
N B_ LV D S_ TX _C L KL N 1 5 13 14 16 N B _L V D S_ TX_ L2 N
10 N B_ LV D S_ TX _C LK LN N B_ LV D S_ TX _C L KL P 1 7 15 16 18 N B _L V D S_ TX_ L2 P N B _LV D S _T X_L 2N 10
10 N B_ LV D S_ TX _C LK LP 19 17 18 20 N B _LV D S _T X_L 2P 10
N B_ LV D S_ TX _L 1N 21 19 20 22
10 N B_ LV D S_ TX _L1 N N B_ LV D S_ TX _L 1P 23 21 22 24
10 N B_ LV D S_ TX _L1 P 25 23 24 26 3. 3 VS
N B_ LV D S_ TX _L 0N 27 25 26 28
10 N B_ LV D S_ TX _L0 N N B_ LV D S_ TX _L 0P 29 27 28 30
10 N B_ LV D S_ TX _L0 P 29 30
CLOSE T O LVDS CON N. 87 12 6-30 06 C 412
2A 0. 1u _1 6V _Y 5V _ 04
PIN PL VD D
C 4 11 C 40 9

4 . 7u_ 25 V_ X5 R _08
0. 1 u_ 16V _Y 5 V_ 04

AMD CHECK

B.Schematic Diagrams
C LOSE TO J_L CD1

N B_ LV D S_ TX _U 1 N N B _L VD S _T X_ U2 N
10 N B_ LV D S_ TX _U 1N N B_ LV D S_ TX _U 1 P N B _L VD S _T X_ U2 P N B_ LV D S_ TX _U 2N 1 0
10 N B_ LV D S_ TX _U 1P N B_ LV D S_ TX _U 2P 10

N B_ LV D S_ TX _C L KU P N B _L VD S _T X_ U0 N
10 N B_ LV D S_ TX _C LK U P
10 N B_ LV D S_ TX _C LK U N N B_ LV D S_ TX _C L KU N N B _L VD S _T X_ U0 P
N B_ LV D S_ TX _U 0N 1 0
N B_ LV D S_ TX _U 0P 10
Sheet 12 of 35
LVDS, Inverter
INV ER TER CO NNE CTO R
0 62 4J
C HG "* "

24 BK L _E N R 244 10K _0 4

R 24 5 C 392
10 0K _04 *0. 47 u_ 10V _ Y 5V _04
3. 3 VS 3. 3V 3 . 3V 3. 3V

U8 A

14
R 196 7 4LV C 0 8P W U 8B

14
1 74 LV C 08 PW C 3 78
4. 7K _0 4 3 4
N B _LC D _ BK L _E N R 197 0_0 4 B LON 2 6 *0 . 1u _16 V_ Y 5V _0 4
10 N B _L CD _ B KL _E N 5

7
R 198

7
*2. 7K _0 4 U 8C

14
16 S B_ BL ON 74 LV C 08 PW
9
3 . 3V 8 I N V_ B LON
R 24 6 10 0K _0 4 10
U 8D

14
74 LV C 08 PW R 24 7 C 40 2

7
12
15 , 20, 2 4 LI D _S W # 11 1M_ 04 0. 1 u_1 6V _Y 5 V_ 04
13
1 5, 26 S B _P WR GD

7
PAN EL PO WER

3. 3V S
S Y S1 5V S Y S1 5V Q2 9
P 2 703 BA G
6 PL V DD
5
R 14 R1 2 + C 4 21 C 419 2 4
1
1M_0 4 1 M_0 4 *1 00 u_6 . 3V _B _C 0. 1u _1 6V _Y 5V _ 04
R 261 R 2 62 C 4 10 C 41 3 R 26 0
3

200 _1 %_0 4 2 00 _1% _0 4 0 . 1u_ 16 V_ Y 5V _0 4 10 0K _04


10 u_ 6. 3V _X 5R _ 06
D

Q7 C5
G
MT N 70 02Z H S 3 0 .1 u_ 16V _ Y 5V _04
S

Q6
G
MTN 70 02 ZH S 3
D

Q5
G
10 N B _L C D _P WR _ EN MTN 70 02 ZH S 3
S

R 13 * 2. 7K _0 4

LVDS, Inverter B - 13
Schematic Diagrams

HDMI, CRT

HDMI Please close to HDMI connector


COSTDOWN
5 VS
L 13
HDMI CONNECTOR J _HDMI1
5V S

3. 3 VS 3 . 3V S
5 VS C
HC B 10 05 KF -12 T2 0C8 7 C8 8 AC
R30 6 D4 0 A Q10
*2 2u _6 . 3V _Y 5 V_ 08 * BA V 99
19 H DMI _HP D 3 . 3V S G

S
2 2u _6 . 3V _X 5R_ 08 H O T P LU G DE TE C T
18
+5 V 17
D DC /C EC GND *2. 2 K_ 04 R31 0 MT N70 02 ZH S 3
HDMI_DD C_ DAT A 16
SDA

D
15 HD M I_ DD C_CL K 2. 2 K_ 04
14 SCL Q33
RES E RV ED 13 S D MTN7 00 2Z HS 3 HD MI _DDC _ C LK
HD MI_ C LK N R45 2 0_0 4 12 CEC 1 0 NB_ HDMI_DD C_ CLK
TMDS CLOCK - 11 5V S
HD MI_ C LK P R45 3 0_0 4 10 CL K SHI E LD
TMDS CLOCK + 9 R45 4 0_0 4 H DMI_ DA TA 2N
8 TMDS D A TA 0-
SHI E L D0 7 H DMI_ DA TA 2P 3. 3 VS 5 VS C
T MDS D AT A0 + R45 5 0_0 4
HD MI_ D A TA 1N R45 6 0_0 4 6 AC
TMDS DA TA 1-

7 50 _1 % _0 4

7 50_ 1% _0 4

7 50_ 1% _0 4

7 50 _1 % _0 4

7 50 _1% _0 4
B.Schematic Diagrams

5 D3 9 A

75 0_ 1% _ 04

75 0_1 % _ 04

75 0_ 1% _04
HD MI_ D A TA 1P R45 7 0_0 4 4 S H IEL D 1 * BA V 99
TMDS DA TA 1+ 3 R45 8 0_0 4 H DMI_ DA TA 0N R29 7
2 TMDS D A TA 2- *2. 2 K_ 04 3 . 3V S R29 8
SHI E L D2 1 R45 9 0_0 4 H DMI_ DA TA 0P
T MDS D AT A2 +

R8 7
2. 2 K_ 04

R 86

R 82

R 79
R 78
G

R9 3
R9 2
05 20 -J

R 81
EM I CH G Q32
S D MTN7 00 2Z HS 3 HD MI _ D DC_DA TA
Sheet 13 of 35 C12 817 -11 9A 5-L
052 0- J
EMI C HG
1 0 NB_ HDMI_DD C_ DA TA
HD MI_ DA TA 2P
HD MI_ DA TA 2N HD MI _D A TA 2 P 9
HD MI _D A TA 2 N 9
HDMI, CRT CLOS E TO HDMI CONN. P I N GN D1 ~4 = GN D
HD MI _ DAT A 1P
HD MI _ DAT A 1N HD MI _D A TA 1 P 9
HD MI _D A TA 1 N 9
HD MI _D A T A0 P
3. 3V S HD MI _D A T A0 N HD MI _D A TA 0 P 9
HD MI _D A TA 0 N 9
HD MI _CL KP
HD MI _C L KP 9

C
HD MI _CL KN
B R77 2 00 K_ 04 HDMI_H P D HD MI _C L KN 9

Q9

E
2 N39 04
10 TMD S _ H PD 0 R3 07
20 0K _0 4
R29 0
1 K_ 04

R43 6

CRT 3.3 VS *1 5mi l _sh ort _ 06


5 VS

J _C RT 1
1
2
3
4

C -1 08 AX 15 FS
0 51 7- J R46 0 *1 5m li _s ho rt _ 06
RN 3 8 f or l ayo ut s wa p pin 6, 8 NB _V GA _R L 44 F CM16 08K -1 21T 06 FRE D 1
10 N B_ V GA_ R 9
R46 1 *1 5m li _s ho rt _ 06
2 . 2K _8 P 4R_0 4 NB _V GA _G L2 F CM16 08K -1 21T 06 FGR N 2
10 N B_ V GA_ G
8
7
6
5

R46 2 *1 5m li _s ho rt _ 06 10
NB _V GA _B L 45 F CM16 08K -1 21T 06 FB L UE 3
10 N B_ V GA_ B 11
4
U2 4 R26 3 R264 R2 65 C60 3 C 6 04 C60 5 C 4 14 C41 7 C 4 20 C41 5 C 4 16 C 41 8 12 D D CD AT A
10 9 D DCD A TA 5
1 0 NB _CRT _D DC _ DA TA D DC_I N1 DD C_OU T 1 13

* 1 0p _5 0V _N P O _0 4

* 10 p_ 50 V_ N P O _0 4

1 0p _50 V _N P O _0 4

1 0p _5 0V _N P O _ 04

2 2p _5 0V _N P O _ 04

22 p_ 50 V_ N P O _0 4
H S Y NC

* 10 p_ 50V _ N PO _ 04

10 p_ 50V _ N PO _ 04

22 p_ 50 V_ N PO _ 04
11 12 6

1 50_ 1% _0 4
D DCLK

15 0_ 1% _04

150 _1 % _ 04
1 0 NB _CRT _D DC _ CLK D DC_I N2 DD C_OU T 2 14 V S Y NC
13 14 R4 37 33 _0 4 HSYNC 7
10 HS Y N C# SY N C_ I N1 S Y N C_OU T 1 15 D D CLK
15 16 R4 38 33 _0 4 V SY NC 8
10 V S Y N C# SY N C_ I N2 S Y N C_OU T 2 C2 C3 C6 C 42 4
5V S 1 3 F RED

G ND2
VCC _ S Y NC V I DEO_ 1

GND1

1 000 p_ 50 V_ X 7R _ 04

10 00 p_5 0V _X 7 R _0 4

1 00 0p _50 V _X 7R _ 04

10 00 p_ 50V _ X7 R _0 4
2 4 F GRN
3. 3V S VCC _ V ID E O V I DEO_ 2
7 5 F BL UE P LEA SE C LO SE T O CO NN EC TOR 05 20 -J
0 . 22 u_ 10V _ Y5 V _04

0. 2 2u _1 0V _Y 5V _ 04

VCC _ DD C V I DEO_ 3 EM I CHG


8 6
BY P GND
0. 22 u_ 10 V_ Y 5V _0 4

05 20 -J
IP 47 72C Z1 6 EM I CH G
C 60 6

C 6 07

C 60 8

05 11- J
ch ang e

B - 14 HDMI, CRT
Schematic Diagrams

SB700-1
U1 8 A

R 3 54 3 3 _ 04 Z 1 80 1 N2 SB700 P4 L P C_ C L K 1 _ R R 18 3 * 22 _ 0 4 LP C _ C LK 1
10 , 1 6 , 2 6 A _ RST # A _R S T # PC I C LK 0 P3 Z 1 8 23
Par t 1 o f 5

PCI CLKS
C 288 .1 U _X 7 R _ 10 V _ 0 4 A_ R X 0P _C V2 3 PC I C LK 1 P1 P C I _C L K 2
9 PC IE_ SB_ N B_ R X0 P V2 2 P CIE_ T X0 P PC I C LK 2 P2
C 280 .1 U _X 7 R _ 10 V _ 0 4 A_ R X 0N _C P C I _C L K 3
9 PC IE_ SB_ N B_ R X0 N A_ R X 1P _C V2 4 P CIE_ T X0 N PC I C LK 3 T4 Z 1 8 24
9 PC IE_ SB_ N B_ R X1 P C 538 .1 U _X 7 R _ 10 V _ 0 4
C 539 .1 U _X 7 R _ 10 V _ 0 4 A_ R X 1N _C V2 5 P CIE_ T X1 P PC I C LK 4 T3 P C ICL K 5 R3 5 1 * 10 K _ 0 4
9 PC IE_ SB_ N B_ R X1 N U2 5 P CIE_ T X1 N P C ICL K5 /G PIO 4 1
PLACE THESE PCIE AC COUPLING C 544 .1 U _X 7 R _ 10 V _ 0 4 A_ R X 2P _C 3 .3 VS
9 PC IE_ SB_ N B_ R X2 P A_ R X 2N _C U2 4 P CIE_ T X2 P
CAPS CLOSE TO SB700 C 543 .1 U _X 7 R _ 10 V _ 0 4
9 PC IE_ SB_ N B_ R X2 N C 304 .1 U _X 7 R _ 10 V _ 0 4 A_ R X 3P _C T2 3 P CIE_ T X2 N
9 PC IE_ SB_ N B_ R X3 P T2 2 P CIE_ T X3 P N1
C 287 .1 U _X 7 R _ 10 V _ 0 4 A_ R X 3N _C PC IR S T #
9 PC IE_ SB_ N B_ R X3 N P CIE_ T X3 N P C IR S T # PC IR ST # 26

PCI EXPRESS INTERFACE


U2 2
9 P CIE _N B_ SB_ TX0 P U2 1 P CIE_ R X0 P U2 P C I _A D 0
9 P CIE _N B_ SB_ TX0 N U1 9 P CIE_ R X0 N AD 0 P7 P C I _A D 1
9 P CIE _N B_ SB_ TX1 P V1 9 P CIE_ R X1 P AD 1 V4 P C I _A D 2
9 P CIE _N B_ SB_ TX1 N R2 0 P CIE_ R X1 N AD 2 T1 P C I _A D 3
9 P CIE _N B_ SB_ TX2 P R2 1 P CIE_ R X2 P AD 3 V3 P C I _A D 4
9 P CIE _N B_ SB_ TX2 N R1 8 P CIE_ R X2 N AD 4 U1 P C I _A D 5
9 P CIE _N B_ SB_ TX3 P R1 7 P CIE_ R X3 P AD 5 V1 P C I _A D 6
9 P CIE _N B_ SB_ TX3 N P CIE_ R X3 N AD 6 V2 P C I _A D 7
Z 1 80 2 T2 5 AD 7 T2 P C I _A D 8
R3 5 2 5 62 _ 1 % _ 0 4
AMD CHECK P CIE _ V D D R R1 7 4 2 . 0 5K _1 % _ 0 6 Z 1 80 3 T2 4 P CIE_ C A L RP
P CIE_ C A L RN
AD 8
AD 9
W1 P C I _A D 9
1 .2 V S T9 P C I _A D 1 0
Z 1 80 4 P2 4 AD 1 0 R6 P C I _A D 1 1
L5 6 B K 1 6 0 8H S 6 0 1
P CIE _ P V DD AD 1 1 R7 P C I _A D 1 2
P2 5 AD 1 2 R5 P C I _A D 1 3
P CIE_ P V SS AD 1 3 U8 P C I _A D 1 4
C 553 C 5 48

B.Schematic Diagrams
1 0 U _1 0 V _ 0 8 1 U _1 0 V _ 0 6 AD 1 4 U5 P C I _A D 1 5
AD 1 5 Y7 P C I _A D 1 6
C60 8 AND C6 09 CLOSE AD 1 6 W8 P C I _A D 1 7
TO SB700 AD 1 7 V9 P C I _A D 1 8
AD 1 8 Y8 P C I _A D 1 9
AD 1 9 AA8 P C I _A D 2 0
AD 2 0 Y4 P C I _A D 2 1
AD 2 1 Y3
AD 2 2
AD 2 3
AD 2 4
Y2
AA2
AB4
P C I _A D 2 2
P C I _A D 2 3
P C I _A D 2 4
PC I_ CL K 2
PC I_ CL K 3
L P C _C L K 0
R3 5 5
R3 5 3
R1 9 0
10 K
10 K
10 K
_0 4
_0 4
_0 4
Sheet 14 of 35
P C I _A D 2 5 L P C _C L K 1 R2 0 6 10 K _0 4

SB700-1
N2 5 AD 2 5 AA1
S B S RC _ CL KP P C I _A D 2 6
2 S B S R C_ C L K P S B S RC _ CL KN N2 4 P C I E _ R C L K P / N B _L N K _ C L K P AD 2 6 AB3 P C I _A D 2 7
2 S B S R C_ C L K N P CIE_ R CL K N /N B_ L NK_ C L K N AD 2 7 AB2 P C I _A D 2 8
K2 3 AD 2 8 AC 1

PCI INTERFACE
Z1 8 0 5 P C I _A D 2 9
Z1 8 0 6 K2 2 N B _ D IS P _ CL K P AD 2 9 AC 2 P C I _A D 3 0
N B _ D IS P _ CL K N AD 3 0 AD 1 P C I _A D 3 1 3 . 3V S
Z1 8 0 7 M2 4 AD 3 1 W2 PC I_C BE# 0
Z1 8 0 8 M2 5 N B _ H T_ C L K P CB E 0 # U7 PC I_C BE# 1
N B _ H T_ C L K N CB E 1 # AA7 PC I_C BE# 2 G P IO 6 5 R 340 * 8 . 2 K _ 04
Z1 8 0 9 P1 7 CB E 2 # Y1 PC I_C BE# 3 P C I _ R E Q# 0 R 345 * 8 . 2 K _ 04
Z1 8 1 0 M1 8 C P U _ HT _ CL KP CB E 3 # AA6 P C I _F R A M E # P C I _ R E Q# 1 R 342 * 8 . 2 K _ 04
C P U _ HT _ CL KN F R A ME # W5 P C I _D E V S E L # P C I _ R E Q# 2 R 156 * 8 . 2 K _ 04
Z1 8 1 1 M2 3 D EVS EL # AA5 P C I _I R D Y # P C I _ R E Q# 3 R 341 * 8 . 2 K _ 04
Z1 8 1 2 M2 2 S LT _ G F X _ C L K P IR DY # Y5 P C I _T R D Y # P C I _ R E Q# 4 R 155 * 8 . 2 K _ 04
S LT _ G F X _ C L K N T R DY # U6 P C I _P A R
Z1 8 1 3 J19 PAR W6 P C I _S T OP # L D RQ # 0 R 195 * 8 . 2 K _ 04
Z1 8 1 4 J18 G PP_ C L K0 P S T OP # W4 P C I _P E R R #
G PP_ C L K0 N P E RR # V7 P C I _S E R R # L D RQ # 1 R 157 * 8 . 2 K _ 04
Z1 8 1 5 L20 S E RR # AC 3 P C I _R E Q # 0
Z1 8 1 6 L19 G PP_ C L K1 P RE Q 0 # AD 4 P C I _R E Q # 1
G PP_ C L K1 N RE Q 1 # AB7 P C I _R E Q # 2

CLOCK GENERATOR
Z1 8 1 7 M1 9 RE Q 2 # AE6 P C I _R E Q # 3
M2 0 G PP_ C L K2 P R E Q 3# / G P I O 7 0 AB6
Z1 8 1 8 P C I _R E Q # 4
G PP_ C L K2 N R E Q 4# / G P I O 7 1 AD 2 P C I _G N T# 0 P E _ GP I O 0 R 34 3 *2 . 2 K _ 0 4
0514-J Z1 8 1 9 N2 2 GN T 0 # AE4 Z 1 8 27
P2 2 G PP_ C L K3 P GN T 1 # AD 5
add for SB710 Z1 8 2 0 Z 1 8 28 P X_ E N R 13 8 *2 . 2 K _ 0 4
G PP_ C L K3 N GN T 2 # AC 6 P C I _G N T# 3
R 44 7 Z1 8 2 1 L18 GN T 3# / G P I O 7 2 AE5 P C I _G N T# 4 G P IO 6 5 R 33 9 1 0 0K _ 04
2 S B _ 1 4 . 3 1 8M _ OS C 2 5 M _4 8 M _ 66 M _ OS C GN T 4# / G P I O 7 3 AD 6
* 0 _ 04 0 2 _ 5 m li _ s h ort P C I _C L K R U N #
C L K R UN # V5 Z 1 8 29
R 1 88 *0 _ 0 4 2 5 M_ X 1 J21 LO C K #
2 5 M _X 1 AD 3 P C I _I N T A #
INT E# /G PIO 33 AC 4 P C I _I N T B #
P L A C E T H E S E C O M P O N E N TS C L O S E TO U 6 00 , A N D
INT F # /G PIO 34 AE2 Z 1 8 30 R 34 4 PX_ EN
U S E GR OU N D G U A R D F OR 3 2 K _ X 1 A N D 3 2 K _ X 2
3 2K _X 1 Z1 8 2 2 J20 I N T G# / G PIO 35 AE3 P E _ GP I O 0
2 5 M _X 2 IN T H# /G PIO 36
X4 3 2 .7 6 8 KHz
4 1 3 2K _X 2 G2 2 L P C_ C L K 0
3 2 L P C C LK 0 E2 2 Z 1 8 32 L P C _C L K 1
R 19 4 2 2 _ 04
32 K _ X 1 A3 L P C C LK 1 H2 4 L P C _ CL K 1 2 4
RTC XTAL

R 4 03 LA D 0 24
* 2 0M _ 0 6 4 1 32 K _ X 2 X1 L AD 0 H2 3 R 3 32 * 1 K _ 04
3 2 0514-J L AD 1 J25 LA D 1 24 V D D3
add colayout X4 L AD 2 J24 LA D 2 24
1 .8 VS R3 3 3
LPC

L AD 3 LA D 3 24
X6 *M C -1 46 _ 3 2 . 7 68 K H z B3 H2 5
X2 L F R A ME # H2 2 L F R AM E# 24
L D R Q# 0 4 7 0_ 0 4
L D RQ 0 # AB8 L D R Q# 1 Z1837
R3 9 3 2 0 M_ 0 6
R 370 L D R Q 1 # / GN T 5# / G P I O 6 8 AD 7 GP I O6 5 R3 3 7 0 _0 4
C R_ W A K E# 2 1

A
* 1 K_ 0 4 B M R E Q# / R E Q 5# / G P I O 6 5 V1 5
S E RIR Q S E RIR Q 24
C5 6 0 C 561 D 41
18 P _ N P O _0 4 1 8 P _ N P O_ 0 4 F2 3 R B7 5 1 V
10 A LL O W _ L D T S T O P F2 4 A LL O W _ L D T S T P C3 RT C _ CL K
5 C P U _P R O C H OT # F2 2 P R O C H OT # R TC C L K C2 INT R UD E R _ A L E RT # R 3 79 * 1 M_ 0 4
5 C P U _ P W R GD L D T _P G
CPU

IN T RU DE R_ A L E R T #
RT C

C
G2 5 B2 V B AT _ IN R 3 84 510_04 A_ VBAT C A Z1833 R 33 1 0_ 0 4 Z 18 3 4
5 , 1 0 C P U _L D T _ S T OP # G2 4 L D T _S TP # VBA T
5 C P U _ L D T_ R S T # L D T _R S T #
D 42 J _ R TC 1
C P U _ P R O C H O T # P U 3. 3v B E C AU S E F O R F A N C O N T R O L . C 56 3 C5 6 2 R B7 5 1 V

1
SB7 0 0 1 U _ 1 0 V _ 0. 61 U _ 1 6 V _ 0 4 1
OT H E RW IS E , P U T O V D DIO . RTC CLEAR
J OP E N 1
3 .3 V 2
*O P E N _ 1 0m i l -1 MM

2
8 5 20 5 -0 2 R
DISPLAY SUPPORT TABLE
PX_EN PE_ GPIO2 INT_VGA_T V_EN# DISPL AY OUT PUT R 39 5

IGP o nly mod e 0 X 0 IGP( L VDS,VGA,HDM I,T V) 1 0 K_ 0 4


RT C _ CL K
MXM on ly mo de 0 X 1 M XM ( LVDS,VGA,HDM I,T V)
Po we r Exp res s mo d e 1 0 /1 X *M XM (VGA,HDM I,T V,DP); MXM /IGP( LVDS) R 39 4

IGP + MXM 0 X 0 IGP( L VDS,VGA,HDM I,T V) * 10 K _ 0 4

SB700-1 B - 15
Schematic Diagrams

SB700-2
When Exte rnal Clock Gen, us ed as 4 8M Cloc k input
U 1 8D When Int ernal Clo ck Ge n, use d as 48M Clock
ou tp ut
3 .3 V Pa rt 4 of 5
E1 S B 7 00
24 P ME #
R 3 75 * 0_ 0 4 Z 19 0 1 E2 P C I _P ME # / GE V E N T 4 # C 8 Z 1 9 31 R 4 00 *0 _ 0 40 2 _ 5m i l _s h o rt
12 , 2 0 , 24 L I D _ S W # Z 1 9 02 H7 R I #/ E XT E V N T0 # U S B C L K / 1 4 M_ 25 M _4 8 M_ O S C C LK _ 4 8 M_ U S B 2
24 SW I # R 3 72 0_04
R 37 3 R 1 9 3 * 0_ 0 4 02 _ 5 m li _ sh o rt Z 1 9 03 F5 S L P _ S 2 / GP M 9# G8 Z 1 9 32 R2 1 9 1 1. 8 K _ 1 % _0 6

USB MI SC
18 , 2 4 , 2 5, 2 6 S U S B # SL P_ S3 # U S B _ R C O MP
* 22 K _ 0 4 R 3 6 6 * 0_ 0 4 02 _ 5 m li _ sh o rt Z 1 9 04 G1

ACPI / WAKE UP EVENTS


24 S US C# H2 SL P_ S5 #
P W R _ B T N # R 3 6 4 * 0_ 0 4 02 _ 5 m li _ sh o rt Z 1 9 05
R S MR S T# _ R 24 P W R_ B T N# H1 P W R _ B TN #
24 R S MR S T# R3 7 4 0 _0 4 1 2 , 26 S B _ P W R GD K3 P W R _ GOO D
10 S U S _S T A T # S B _ TE S T 2 H 5 S U S _ S TA T # E6 Z 1 9 33
20 08 /0 3/1 8
C 34 6 S B _ TE S T 1 H 4 T EST2 U S B _ F S D 13 P E7 Z 1 9 34
S B _ TE S T 0 H3 T EST1 U S B _ F S D1 3 N
* 2. 2 U _6 . 3 V _ 0 6
R 1 4 8 * 0_ 0 4 02 _ 5 m li _ sh o rt Z 1 9 71 Y 1 5 T EST0 F7

USB 1.1
24 GA 2 0 G A 20 I N / GE V E N T 0# U S B _ F S D 12 P
2 4 K B C _ RS T # R 1 4 9 * 0_ 0 4 02 _ 5 m li _ sh o rt Z 1 9 72 W 1 5 E8
K4 K B R S T #/ G E V E N T1 # U S B _ F S D1 2 N
24 S CI# K2 4 L P C _ P M E # / GE V E N T 3# H 1 1 Z 1 9 35
24 S MI # L P C _ S M I # / E XT E V N T 1# U S B _ H S D 11 P
R 3 67 * 0_ 0 4 Z 19 0 6 F1 J 1 0 Z 1 9 36
18 P C I E _ E X P C A R D _ P W R E N # J2 S 3 _ S T A TE / GE V E N T 5# US B _ H S D1 1 N
2 6 S Y S _ RS T # S Y S _ R E S E T # / GP M 7 #
H6 E1 1 Z 1 9 37
18 , 2 1 P C I E _ W A K E # W A K E #/ G E V E N T8 # U S B _ H S D 10 P
R 3 65 * 0_ 0 4 Z 19 7 3 F2 F11 Z 1 9 38
USB13 N.C
2 4 S W I # R 1 86 0 _ 0 4 C P U _T H E R MT R I P # S B J6 B L I N K / GP M 6# US B _ H S D1 0 N
5 C P U _T H E R M TR I P # W14 S M B A L E R T # / TH R M T R I P # / GE V E N T 2 # A1 1 USB12 N.C
3 . 3V R1 8 7 * 10 K _ 0 4
N B _P W R G D U S B _H S D 9 P B1 1 US B P 9 19
26 W D _P W R GD US B _ HS D 9 N US B N9 19 USB11 N.C
B.Schematic Diagrams

R S M R S T # _R D3
R S MR S T# USB 10 N.C
C 10
U S B _H S D 8 P D 10 US B P 8 22 USB9 CCD
US B _ HS D 8 N US B N8 22
USB8 Bule tooth
S B G P I O1 0 A E 1 8 G 11
S B GP I O 6A D 1 8 S A T A _ I S 0 # / GP I O 10 U S B _H S D 7 P H 12 US B P 7 18 USB7 New Ca rd
C LK _ R E Q3 # / S A T A _ I S 1# / G P I O6 US B _ HS D 7 N US B N7 18
S B GP I O 4A A 1 9 USB6 CCD? ? DEBUG
S B GP I O 0 W 1 7 S M A R T V O LT / S A T A _ I S 2 # / GP I O 4 E1 2
USB5 WLAN( PCIE M ini Card)
Sheet 15 of 35 2008/03/18
R1 6 6
Z 19 1 0
Z 19 1 1
Z 19 1 2
V1 7
W20
W21
C LK _ R E Q0 # / S A T A _ I S 3# / G P I O0
C LK _ R E Q1 # / S A T A _ I S 4# / F A N OU T 3/ G P I O3 9
C LK _ R E Q2 # / S A T A _ I S 5# / F A N I N 3 / G P I O4 0
U S B _H S D 6 P
US B _ HS D 6 N
E1 4

C 12
US B P 6
US B N6
19
19 USB4 3G(PCIE Mi ni Card)
USB3 N.C

USB 2.0
23 ICH _ S P K R S P K R / GP I O2 U S B _H S D 5 P US B P 5 18
SB700-2 SC LK 0,S DA TA 0= >C loc k Ge n, DD R 2 ,V GA
2 , 7, 8
2 , 7, 8
18
S CL K 0
S DA T A 0
S CL K 1
* 0_ 0 4 02 _ 5 m li _ sh o rt AA1 8
W18
K1
S C L0 / G P OC 0#
S D A 0 / GP O C 1 #
US B _ HS D 5 N
D 12

B1 2
US B N5

US B P 4
18

19
USB2
USB1
USB Po rt 2 (Au dio /B)
USB Po rt 1 (M /B)
SC LK 1,S DA TA 1= >P CI- E Mi ni C ard (W LA N, LAN ) K2 S C L1 / G P OC 2# U S B _H S D 4 P A1 2

GPIO
18 S DA T A 1 S B G P I O9 A A 2 0 S D A 1 / GP O C 3 # US B _ HS D 4 N US B N4 19 USB0 USB Po rt 0 (M /B)
S B G P I O8 Y1 8 D D C 1 _ S C L/ G P I O9 G 1 2 Z 1 9 41
3 .3 V R 3 78 1 0 K _ 04 S B G P I O6 6 C1 D D C 1 _ S D A / GP I O 8 U S B _H S D 3 P G 1 4 Z 1 9 42
t o CP U T he rm al I C
R1 6 5 1 0K _ 0 4 S B G P I O5 Y1 9 L L B #/ GP I O 66 US B _ HS D 3 N
R2 0 0 * 0_ 0 4 Z 19 1 4 G5 S H U T D O W N # / G P I O5 H 14
5 , 24 T H E R M_ A L E R T# D D R 3 _ R S T# / G E V E N T 7 # U S B _H S D 2 P H 15 US B P 2 20
R2 0 1 0_04
2 1 C R _C P P E # US B _ HS D 2 N US B N2 20
R2 2 4 *0 _ 04 A1 3
2 , 1 8 P C I E _ E X P C A R D _C L K R E Q # U S B _H S D 1 P B1 3 US B P 1 20
1 8 P C I E _ E X P C A R D _P W R E N # R3 9 9 *0 _ 04 US B N1 20
R3 9 2 0 _0 4 US B _ HS D 1 N 3 . 3V
3 .3 V B1 4
B9 U S B _H S D 0 P A1 4 US B P 0 20
R3 9 8 *1 0 K _ 04 Z 19 1 5
U S B _ OC 6 # / I R _ T X 1/ GE V E N T6 # US B _ HS D 0 N US B N0 20
R2 2 3 1 0K _ 0 4 Z 1 9 16 B8
R4 0 7 1 0K _ 0 4 Z 19 1 7 A8 U S B _ OC 5 # / I R _ T X 0/ GP M 5# A1 8 Z 1 9 43 2 .2 K_ 0 4 2 . 2 K _0 4 SC LK 2, SD ATA 2= >P CI E xpr es s Ca rd( NE W CA RD )

USB OC
Z 19 1 8 A9 U S B _ OC 4 # / I R _ R X0 / G P M4 # I MC _G P I O8 B1 8 Z 1 9 44 R 2 17 R2 1 8
NEW CARD 1 8 U S B _ O C P 6 _ 7# * 0_ 0 4 02 _ 5 m li _ sh o rt SC LK 3, SD ATA 3= >C PU
R 3 91 R2 1 3 *1 0 K _ 04 Z 19 7 4 E5 U S B _ OC 3 # / I R _ R X1 / G P M3 # I MC _G P I O9 F21 Z 1 9 45
U S B _ OC 2 # / GP M2 # I MC _P W M0 / I MC _ GP I O 10
M/B USB PORT 0,1 R2 0 3 *1 0 K _ 04 Z 19 2 0 F8 D 21
S C LK 2 18
R 1 99 * 0_ 0 4 02 _ 5 m li _ sh o rt Z 19 2 1 E4 U S B _ OC 1 # / GP M1 # S C L 2 / I MC _ GP I O 11 F19
20 U S B _ OC P 0_ 1 # U S B _ OC 0 # / GP M0 # S D A 2 / I MC _ GP I O 12 E2 0 S DA T A 2 18
M1 S C L3 _ L V / I MC _ GP I O 13 E2 1 S C LK 3 5
R3 5 8 3 3 _ 04 Z 19 0 7 * SC LK 3, SD ATA 3= >C PU
22 , 2 3 A Z _ B I T C L K M2 A Z _ B IT CL K S D A 3 _ L V / I MC _ GP I O 14 E1 9 Z 1 9 46 S DA T A 3 5
2 2, 2 3 A Z _ S D O U T J7 A Z _ S D OU T I MC _P W M1 / I MC _ GP I O 15 D 19 C PU ? P ULL H IG H
G P 16
23 A Z _ S DIN 0 J8 A Z _ S D I N 0 / GP I O4 2 I MC _P W M2 / I MC _ GP O 16 E1 8 G P 17

HD AUDIO
22 A Z _ S DIN 1 L8 A Z _ S D I N 1 / GP I O4 3 I MC _P W M3 / I MC _ GP O 17
C5 4 9 C 55 4 A Z _ S D IN2
A Z _ S D IN3 M3 A Z _ S D I N 2 / GP I O4 4 G 20 Z 1 9 47
* 68 P _ 5 0 V _0 4 2 2P _ 5 0 V _ 04 L6 A Z _ S D I N 3 / GP I O4 6 I MC _ GP I O 18 G 21 Z 1 9 48
2 2, 2 3 A Z _S Y N C A Z _ R S T# M4 A Z _ S Y NC I MC _ GP I O 19 D 25 Z 1 9 49
2 2, 2 3 A Z _R S T #

INTEGRATED uC
R1 8 4 * 0_ 0 4 S B _C R _ C P P E # L 5 A Z _ R S T# I MC _ GP I O 20 D 24 Z 1 9 50
2 1 C R _C P P E # A Z _ D OC K _R S T #/ G P M8 # I MC _ GP I O 21 C 25 Z 1 9 51
I MC _ GP I O 22 C 24 Z 1 9 52
I MC _ GP I O 23 B2 5 Z 1 9 53
I MC _ GP I O 24 C 23 Z 1 9 54
I MC _ GP I O 25
3 . 3V S B2 4 Z 1 9 55
I MC _ GP I O 26 B2 3 Z 1 9 56
I MC _ GP I O 27 A2 3 Z 1 9 57
S B G P I O6 I MC _ GP I O 28 C 22 Z 1 9 58
R 33 8 2 0 K _ 04 3 . 3V S
R 17 2 2 0 K _ 04 S B G P I O0 I MC _ GP I O 29 A2 2 Z 1 9 59
I MC _ GP I O 30 B2 2 Z 1 9 60
R 16 4 2 . 2 K _ 04 S C LK 0 I MC _ GP I O 31 B2 1 Z 1 9 61
I MC _ GP I O 32 A2 1
R 17 3 2 . 2 K _ 04 S D A TA 0 R3 7 1 Z 1 9 62
*1 0 K _ 04 Z 1 9 23 H1 9 I MC _ GP I O 33 D 20 Z 1 9 63

INTEGRATED uC
H2 0 I M C _ GP I O 0 I MC _ GP I O 34 C 20
3 . 3V Z 1 9 24 Z 1 9 64
35mil Z 1 9 25 H2 1 I M C _ GP I O 1 I MC _ GP I O 35 A2 0 Z 1 9 65
R 18 0 1 K_ 0 4 P W R _B TN # Z 1 9 26 F25 S P I _ C S 2# / I M C _ GP I O2 I MC _ GP I O 36 B2 0 Z 1 9 66
R 35 9 2 . 2 K _ 04 S C LK 1 I D E _R S T # / F _R S T #/ I MC _ G P O3 I MC _ GP I O 37 B1 9 Z 1 9 67
R 36 8 2 . 2 K _ 04 S D A TA 1 Z 1 9 27 D2 2 I MC _ GP I O 38 A1 9 Z 1 9 68
Z 1 9 28 E2 4 I M C _ GP I O 4 I MC _ GP I O 39 D 18 Z 1 9 69
R 35 7 1 0 K _ 04 S US _ S T A T # Z 1 9 29 E2 5 I M C _ GP I O 5 I MC _ GP I O 40 C 18 Z 1 9 70
R 21 6 2 . 2 K _ 04 GP 16 Z 1 9 30 D2 3 I M C _ GP I O 6 I MC _ GP I O 41
R 21 5 * 2. 2 K _ 0 4 GP 17 I M C _ GP I O 7

R 20 5 * 2. 2 K _ 0 4
R 20 4 2 . 2 K _ 04 STRAP pin t o def ine S B 70 0
us e LPC or SPI ROM

R1 8 5 1 0K _ 0 4 A Z _R S T #

B - 16 SB700-2
Schematic Diagrams

SB700-3
SAT APORTS DISTRI BUTION:
0 - 2 .5" HDD
1 - e SAT A CONN.
2,3,4,5 - NOT USED