10.7mW, 2.1mm2, 0.

13µm CMOS GPS radio

David Tester, Senior Member IEEE and Ian Watson
Air Semiconductor
Cherry Orchard North, Kembrey Park
Swindon, Wiltshire, SN2 8UH, UK
david.tester@air-semi.com

Abstract— A fully integrated GPS radio realized in a 0.13µm

CMOS technology from a leading foundry is presented. This
radio forms a key component within a single-die GPS receiver.
The receiver includes the full RF and IF signal chain including
on-chip LNA, direct support for external LNA, mixer, fully
integrated frequency synthesizer, distributed IF gain and
filtering along with multiple ADC’s. Additionally, the macro
includes local on-chip voltage regulation, enabling a direct
connection to a typical consumer 2.4V-4.9V Li-Ion battery.
RF jammer detection, temperature monitoring, automatic trim
for on-chip IF signal filtering, bandgap reference voltage and
crystal oscillator driver functions are also provided. With a
measured front-end noise figure of 3.5dB, a total power
consumption of 10.7mW, receiver gain of 84dB and a total die
area (including I/O pads) of 2.1mm2 this work is the smallest die
area and lowest power GPS radio reported to date.

I. INTRODUCTION
Location has emerged as core functionality for consumer
devices such as mobile phones and digital cameras.
GPS enabled mobile phones offer navigation capabilities and
other location based services. GPS enabled digital cameras
can location-stamp photographs (often called “geotagging”).
This paper presents performance details of the 10.7mW radio
included within a 0.13µm CMOS single-die GPS receiver.
The GPS radio reported in this paper, as of late 2009,
represents current state of the art for consumer electronics.
Intended for embedded use within a digital camera this GPS
radio is also architected and implemented for cellphone use.
II. SUMMARY OF THE PAPER
Section III outlines details of the GPS system. Section IV
describes the receiver architecture. Sections V to VIII
present specific circuit level implementation details for the
RF and IF signal paths along with the frequency synthesizer
and support functions of the receiver. Section IX outlines
process and package implementation details for the receiver
whilst section X compares the performance of this receiver
with previously reported results and presents conclusions.
III. SUMMARY OF THE GPS NAVIGATION SYSTEM
The GPS air interface is defined in [1]. Additional details
on system design and operation can be found in [2] and [3].
GPS satellites orbit at an altitude of 20,163km above the
Figure 1. Integrated GPS Radio
equatorial radius of 6,378km in six planes, each inclined by
55 degrees with respect to the equator with a semi-major axis
of 26,562km, at a circular velocity of 3.9km/s and with an
orbital period of 11 hours and 58 minutes.
Each satellite transmits a CDMA signal at 154x the system
frequency of 10.23MHz (or 1.58GHz). The C/A signal at L1
is spread using Gold codes [4]. Worst case cross-correlation
between Gold codes used for L1 GPS is 21.6dB.
Unobstructed receive power is no less than -130dBm over
the satellite lifetime with a spread of 6dB due to satellite age.
Observed power in a typical environment can be 30dB less!
Each satellite transmits a 37,500 bit navigation message
through a 25 frame TDMA protocol. Each frame contains
1,500 bits of data and is comprised of 5 sub-frames each
lasting 6 seconds containing ten 30 bit words. The entire
message provides both satellite (ephemeris) and constellation
(almanac) information.
IV. RECEIVER ARCHITECTURE AND SPECIFICATION
With a thermal noise floor in the L1 band of -109dBm and
the received signal power between -130dBm to -160dBm the
signal sits at least 21dB below the thermal noise floor. The
radio typically provides 80dB of gain, de-spreading provides
30dB of processing gain and the remaining 30dB to 60dB
required to achieve 10dB SNR needed for navigation data
decode is achieved via coherent and non-coherent integration.
An overview of the GPS radio and analog support
functions is presented in Figure 1. Utilizing a low-IF receiver
architecture, the radio is directly connected via a SAW filter
to a GPS antenna.
The radio signal path comprises an RF section and an IF
section. The RF signal path contains on-chip LNA and mixer
whilst the IF signal path consists of configurable filters,
VGA’s and ADC. The fully integrated frequency synthesizer
includes on-chip VCO running at 2x LO to avoid interfering
harmonics and ease quadrature generation.
Support circuits for temperature monitoring, bandgap
reference voltage generation, linear power supply regulation
are provided along with a serial interface for configuration.
The only external components required for the radio are
antenna, SAW filter, input impedance match for the LNA,
reference TCXO or XTAL for the synthesizer, reference
resistor and filter capacitor for the integrated bandgap and
stability capacitors for the integrated LDO regulation.
Support for optional external LNA is also provided.
The 2MHz wide GPS band centered at the L1 frequency is
mixed down to 3MHz and quantized to 3b at 16.368MHz
providing 16x sampling compared to the 1.023MHz chip rate.
Mixer side-band can be selected to avoid in-band jammers.
The receiver provides 84dB of distributed gain with the RF
section providing 38dB and the IF section providing 46dB.
V. RF SIGNAL PATH
The RF signal path comprises an internal LNA and mixer
with support for an optional external LNA.
A. LNA and Pre-Mixer Filter
The integrated differential LNA path provides 38dB of
distributed gain at 1.5GHz with a noise figure of 2.4dB. The
LNA has multiple gain modes allowing a tradeoff between
gain, bias current, noise figure and compression point to
permit power optimized operation of the radio in the presence
of jamming signals.
Negative feedback is used to form the LNA characteristic
resistive input impedance of 120Ω and enables the use of
integrated DC block capacitors between the LNA and V2I
stages. Combined with the natural low-pass roll off of these
two stages this provides a course first-order band-pass
response to the RF front-end.
Voltage output from the LNA is converted to current input
for both I and Q mixers. This stage has multiple gain modes
allowing further tradeoff between gain and compression.
Bias current for the LNA voltage to current converter is set
through a servo loop from the common mode output voltage
of the mixer.
B. Mixer and Post-Mixer Filter
Quadrature output from the LNA is shifted from RF to IF
through the use of I and Q mixers. Each mixer is a balanced
Gilbert stage. Quadrature LO is generated locally through a
divide-by-2 stage from the VCO output and is DC coupled to
the mixer to minimize parasitic capacitance.
The mixer load provides a fixed RC pole. Load resistance
is dependent on mixer bias current. Filter capacitance is
switched as a result to ensure appropriate corner frequency.
The resulting passive RC pole provides excellent blocking
rejection and LO leakage suppression.
Low-pass filter corner frequency for the mixer can be
adjusted between 5MHz and 6MHz.
C. Jammer Detect
As described in section IV the GPS signal is buried beneath
the thermal noise floor. Energy detected in the front-end
corresponds to a jammer which degrades GPS operation. RF
output from the LNA is provided to a blocking level detector
to determine overload of the front-end and form an AGC loop
around the LNA to reduce gain in the presence of jammers.
D. External LNA Bias
Flexible support for additional gain with an external LNA is
provided through provision of an LNA bias. Output current
can be adjusted from 0.4mA and 3.2mA in 0.4mA steps.
VI. IF SIGNAL PATH
A. Band-Pass Channel Select Poly-Phase Filter
A complex third-order band-pass Butterworth filter further
defines the receiver frequency response. Active stages with
cross coupling between quadrature stages provide a poly-
phase imaginary frequency response and hence single side-
band selection. The filter can select between lower or upper
side-bands and so provide a jammer avoidance capability.
Filter bandwidth is 2MHz, corresponding to the main lobe
of the GPS signal and centre frequency is configurable
between 3MHz and 4MHz to support a configurable IF
frequency. The first stage of the filter provides post-mixer
gain control and offers gain settings of 11.5dB or 21.5dB.
Filter performance is ensured through automatic calibration.
B. Variable Gain Amplifier
Output from the poly-phase filter is amplified with a VGA.
The VGA offers gain configurable between 8dB and 24dB in
2dB steps, with gain linearity of ±0.7dB and a band-pass
response between 200kHz and 10MHz.
C. Anti-Alias Filter
To prevent alias folding as a result of the ADC sampling,
the VGA is followed with an anti-alias filter. Low pass
frequency for the anti-alias filter can be varied between
2.75MHz and 8MHz in 0.75MHz steps.
D. ADC
The radio provides support for 3b and 1b quantization at a
sample rate of 16.368MHz with an input signal of ±20mV
and a high pass response to eliminate effects from inter-stage
DC offset within the VGA.
The 3b ADC offers a non-linear transform function with
12mV and 8mV step sizes and a DNL of 0.5LSB.
 VII. FREQUENCY SYNTHESIZER
The frequency synthesizer is formed from a charge-pump
based integer-N phase locked loop with integer frequency
division and a fully integrated VCO running at twice the
desired LO frequency.
Operating with a reference comparison frequency of
16.368MHz this integer-N loop can step in 511.5kHz units.
Lock time for the loop is less than 200µs and phase noise at
1Mhz offset is -109dBc/Hz. Reference spurs are less than
-60dBc and residual FM over 10kHz to 30MHz band is less
than 4kHz.
A. VCO
Constant current bias is used to provide an LC tank based
VCO with maximum PSRR and a tuning range of 2200MHz
to 3340MHz. Implemented through a combination of course
tuning, switching varactors in and out of circuit along with
fine voltage controlled tuning this offers a corresponding LO
frequency range of 1100MHz to 1670MHz over all corners.
Typical gain for the VCO is 220MHz/V.
Output from the VCO is buffered for isolation to minimize
frequency pulling and reverse injection.
B. Loop Divider and Loop Filter
The buffered 150mV peak signal from the VCO is divided
within the synthesizer and local to the mixers. Divide by two
within the mixer provides quadrature. Divide by two within
the synthesizer generates the target LO frequency for the loop
dividers. Dividers take small swing differential signal as
input and output from the CML divide-by-two is converted to
conventional CMOS levels prior to the main loop divider.
The synthesizer operates with on-chip loop filter, but also
supports an external loop filter. The internal loop filter is
composed of 228kΩ in series with 48.8pF, all in parallel with
9.3pF using both MOS and MIM capacitors.
C. PFD and Charge Pump
The central charge pump bias current can be varied between
3µA and 15µA (in 3µA steps). Central charge pump current
is set with further configurable multiplication factor of 1 to 8.
Phase and frequency detection is performed with a standard
four state PFD based on clock set, pulse reset latches. PFD
up and down request signals are completed with an
acknowledge from the charge pump to exit the fourth state.
This avoids the charge pump dead-band and reduces
comparison spur levels.
VIII. ANALOG SUPPORT FUNCTIONS
A. Bandgap
The global reference voltage for all circuits within the radio
is generated on-chip with a bandgap voltage reference. When
operating in active mode the bandgap is powered from a local
LDO (itself powered from the main analog LDO) to
maximize PSRR. Bootstrap of the system is performed by
local secondary supply voltage generation and a dedicated
start-up circuit for the bandgap when in standby mode,
enabling a low power operating mode and allowing the
voltage supply subsystem to generate all required voltage
rails in the absence of a reference voltage. The bandgap is
implemented with isolated NPN transistors to ensure
excellent PSRR to all voltage supplies and substrate. PSRR
is 90dB at DC and 50dB at 10MHz
B. Crystal Oscillator and Temperature Sensor
Support for both TCXO and XTAL based frequency
references is provided with a low power driver which delivers
full scale output from a standard AT cut crystal with bias
current of 60µA and phase noise of -135dBc at 10kHz offset.
System temperature is monitored with an integrated sensor.
Capable of monitoring temperature over a -40ºC to +88ºC
range with a bias current of 2µA.
C. Voltage Regulation, Resistor Trim, POR and PLL
Direction connection to a 2.4V to 4.9V battery is supported.
Analog, digital and auxiliary voltage domains are provided.
The analog LDO provides output voltage of 1.9V to 2.15V in
15mV steps operating with quiescent current of 3µA. The
digital LDO provides regulated 1.2V output voltage at a
quiescent current of less than 3µA. The auxiliary LDO
provides output voltages of 1.2V, 1.8V, 2.5V or 3.3V and
operates with a quiescent current of less than 3µA.
An external precision resistor is used to trim an on-chip
100kΩ P+ poly resistor over the ±20% process range,
ensuring bias for all blocks operates within 2% of nominal.
Local power-on-reset is generated on-chip to initialize all
circuits after establishment of power supplies. External POR
is also supported should this be needed by the host system.
Clocks required by GPS digital signal processing blocks
downstream of the radio in the signal path are provided.
Built around a charge pump PLL with a ring oscillator VCO
this block is able to provide multiple general purpose clocks.
IX. IMPLEMENTATION DETAILS
A. Process
The radio is implemented in a 1P6M standard 0.13µm
CMOS process with additional process options for high-Q
inductors, deep N-well isolation and MIM capacitors.
Isolation is achieved with N-well / deep N-well underneath
and guard rings around all analog blocks. Sensitive circuits
are provided with isolated voltage rails and care is taken on
signals crossing between analog and digital domains. The
pad ring is broken to isolate sensitive I/O pads from noise.
Volume production utilizes a minimum pin QFN package.
System–level evaluation is performed with BGA package
option. Figure IV shows the QFN packaged radio.
Operating range is -40ºC to +80ºC and 2.4V to 4.7V.
X. CONCLUSIONS
Performance results for this work are presented in Table II
with results from previously published work for comparison.
The reported GPS radio provides power consumption of
10.7mW for a die area of 2.1mm2 and exceeds all previous
results, establishing a new state of the art.
ACKNOWLEDGMENT
Contribution from the entire team at Air is acknowledged.
 THIS ION JSSC ISSCC JSSC ISSCC JSSC JSSC ION
Unit
WORK 2008 2007 2006 2006 2005 2005 2004 2002
[5] [6] [7] [8] [9] [10] [11] [12]

POWER
10.7 20.4 20.5 19.8 27 84 19 24 21.6 mW
DISSIPATION

DRAWN
5.1 17 11.4 11 17 60 10.5 15 7.2 mA
CURRENT

SUPPLY
2.1 1.2 1.8 1.8 1.6-1.8 1.4 1.5-2.5 1.6-2.0 2.7-3.3 V
VOLTAGE

LNA NF 2.4 1.8 1.6 dB

RADIO NF 3.5 2.5 5 5 4.8 2 8.5 4 dB

2
RADIO AREA 2.1 3.24 3.2 4.1 12.8 2.6 4.6 mm

PROCESS 0.13µm 90nm 0.18µm 0.18µm 0.18µm 90nm 0.18µm 0.18µm

TECHNOLOGY CMOS CMOS BiCMOS BiCMOS CMOS CMOS CMOS CMOS BiCMOS

Air NXP GloNav RFDomus ST TI PHYCHIPS Sony NemeriX

.
REFERENCES
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