International Journal of Circuit Theory and Application

General Space Vector Modulation of A High-Frequency AC

Linked Universal Converter for Distributed Generations

Journal: International Journal of Circuit Theory and Applications

Manuscript ID CTA-18-0270
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Wiley - Manuscript type: Research Article

Date Submitted by the Author: 09-Sep-2018

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Complete List of Authors: Liu, Yushan; Beihang University, School of Automation Science and
Electrical Engineering
He, Jie; Beihang University,
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Ge, Baoming; Texas A&M University, Department of Electrical and

Computer Engineering
Xue, Yaosuo; Oak Ridge National Laboratory
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Distributed generations, high-frequency isolation, space vector modulation,

Keyword:
matrix converter
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Page 1 of 15 International Journal of Circuit Theory and Application

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General Space Vector Modulation of A High-
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Frequency AC Linked Universal Converter for
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Distributed Generations
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12 Yushan Liu1*, Jie He1, Baoming Ge2, Yaosuo Xue3
13 1
School of Automation Science and Electrical Engineering, Beihang University, Beijing, 100191, China
14 2
Department of Electrical and Computer Engineering, Texas A&M University, College Station, 77843, USA
15 3
Oak Ridge National Laboratory, Oak Ridge, TN 37831, USA
16 E-mail: yushan_liu@yeah.net
17
18 Abstract—A high-frequency (HF) ac linked universal converter interfacing three-phase ac with single-phase
19 ac or dc is proposed for distributed generations (DGs). The primary side of HF transformer consists of a
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20 three-phase-to-single-phase matrix converter, converting the three-phase voltage to a HF ac voltage. The
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secondary side of HF transformer is a cyclo converter, unfolding the HF ac voltage to single-phase ac or dc
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voltage, depending on the DGs. A simple to be implemented general space vector modulation (SVM) is also
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developed. Simulation studies and real-time implementation carried out on different amplitudes and
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25 frequencies of single-phase ac and dc outputs demonstrate the compact volume, unified structure, and simple
26 modulation of the proposed solution.
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27 Index Terms—Distributed generations, high-frequency isolation, space vector modulation, matrix converter,
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cyclo converter.
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30
31
I. INTRODUCTION
32 The rapidly increasing penetration of distributed generations (DGs) has created a growing demand for
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33 smarter energy management, where smart transformers are playing a crucial role [1]-[3]. The traditional
34 line-frequency (LF) transformer operating at 50/60 Hz is bulky, expensive, and vulnerable to power quality
35 issues, such as system disruptions and overvoltage. Growing interests are devoted to the smart transformer
36
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[4]-[6], known as the high-frequency (HF) operation and high controllability. The high operating frequency
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at tens of kilo Hertz enables dramatic reductions in transformer sizes and consequently in distribution
38
39
system volumes and weights. The controllability offers voltage regulation, power factor correction, fault
40 tolerance, etc., compared to the LF transformer.
41 The dual-active-bridge (DAB) converter-based smart transformer is relatively easy to incorporate
42 renewable energy sources and energy storage due to its low-voltage dc link [7]-[12]. However, large
43
electrolytic capacitors required at the high-voltage dc link contradicts with compact volume [13].
44
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Tremendous interests have been given to matrix converters due to its direct voltage amplitude and/or
46 frequency conversion without any dc links [14]-[16]. The smart transformer formed by back-to-back
47 connection of single/three-phase-to-single-phase matrix converters also has great potential for increased
48 lifetimes, space savings, and efficiency enhancements, because of no bulky dc-link capacitors [17]-[24].
49 However, it is difficult to interface with dc power sources/loads, such as energy storage batteries and
50 Photovoltaic panels, due to lack of dc links [23], [24].
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A HF ac distribution system was discussed for the three-phase ac, single-phase ac, and dc DGs [25].
53 Different DGs were equipped with different power electronic interfaces. For instance, a modified cyclo
54 converter was applied to the single-phase ac loads/sources, and unidirectional H-bridge converters were
55 performed to dc loads/sources. Accordingly, different modulation strategies were developed to the
56 respective interface, though under sinusoidal pulse width modulation (SPWM). Soft switching technique
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 International Journal of Circuit Theory and Application Page 2 of 15

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3 was also developed for the matrix converter and H-bridge converter-based HF isolated three-phase ac to dc
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conversion, based on SPWM [26], [27].
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6 Due to the coupled performance of primary and secondary sides, the HF-ac linked converter needs to
7 handle the voltage and current control of both sides simultaneously, the power flow, the current
8 commutation, and the leakage energy management. Therefore, the space vector modulation (SVM) is a
9 good choice in achieving those control goals owing to duty cycle-based implementation [28]. An SVM was
10
proposed for the three to three/single-phase matrix converters-based smart transformers [18], [19], which
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had complicated duty cycles combination. An indirect SVM was proposed aimed at simplifying the
13 implementation [20], [21], but both sides were three-phase ac. Model predictive control was developed for
14 that kind of smart transformer, with simple control structure and fast responses [22], [29], however, the
15 switching frequency is varied, resulting in difficulty in the HF transformer design.
16 This paper proposes a HF-ac linked universal converter, which interfaces the three-phase ac with single-
17
phase ac or dc DGs, bidirectionally and uniformly. The primary side is a three-phase-to-single-phase (TPSP)
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matrix converter, converting the three-phase ac to HF ac voltage. The secondary side is a cyclo converter
obtaining single-phase ac or dc voltage for the DGs in a unified topology. Furthermore, a simple to be
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21 implemented general SVM is coordinated for the proposed universal converter no matter single-phase ac
22 or dc output. The paper is structured as follows: Section II introduces the proposed universal converter;
23 Section III details the general SVM and operating modes anlaysis; Section IV illustrates simulation studies
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24 and real-time implementation; finally, Section V concludes the work.

25
26 II. PROPOSED UNIVERSAL CONVERTER
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27 Fig. 1 shows the proposed universal converter interfacing three-phase ac grid and single-phase ac or dc
28 DGs. A TPSP matrix converter and a cyclo converter are linked through an n1:n2 HF transformer. The
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matrix converter is with bidirectional power switches, named as Sij, iÎ{u, v, w} for the three phases and
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31 jÎ{1, 2} for the upper and lower bridges. The cyclo converter is with bidirectional switches Smj, mÎ{a, b}
32 for the two phases. The three-phase ac power source could be converted to supply single-phase ac/dc loads
or to integrate single-phase ac/dc grid. Vise verse, the single-phase ac grid or dc grid could interface with
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34 the three-phase power source/loads. The three-phase side is denoted as the transformer primary in the
35 illustration.
36
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37 =
38 Su1 Sv1 Sw1 Sa1 Sb1
39 u n1 : n2
a DC Grid/Loads
40 v or Single-Phase
41 w b AC Grid/Loads
42 Grid
Su2 Sv2 Sw2 Sa2 Sb2
43
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45 Fig. 1. Topology of proposed HF-ac linked universal converter interfacing with three-phase ac grid and single-phase ac
46 or dc DGs.
47
48 An quivalent operating circuit of the proposed HF-ac linked universal converter is presented in Fig. 2,
49 where a virtual DAB converter is coupled with the HF transformer. Denote the switches of DAB at the
50 primary and secondary sides are, resepctively, S1~S4 and S5~S8.
51
52
At the primary side, the TPSP matrix converter in Fig. 1 is equivalent to a current source rectifier with
53 a virtual active-bridge inverter. The three-phase input voltages uin{u,v,w} of the matrix converter are rectified
54 into a virtual dc voltage Vdc1, which is then choped to the HF ac voltage vp by the virtual active-bridge
55 inverter. Denote the switches of the primary equivalent rectifier stage in Fig. 2 as S'ij. The operation of
56 primary TPSP matrix covnerter in Fig. 1 could be written as
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Page 3 of 15 International Journal of Circuit Theory and Application

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3 𝑆#$ 𝑆%$ 𝑆&$ 𝑆 ,
𝑆' 𝑆#$ ,
𝑆%$ ,
𝑆&$
4 ! (=! $ (! , , , ( (1)
5
𝑆#' 𝑆%' 𝑆&' 𝑆* 𝑆+ 𝑆#' 𝑆%' 𝑆&'
6 Through the n1:n2 HF transformer, the vp is transferred to the secondary side at vs. The secondary virtual
7 active-bridge converter firstly recovers the HF ac voltage Vdc1 to Vdc2, then unfolds it to the single-phase ac
8
or adjustable dc voltage by switches S'mj. Hence, the operation of secondary cyclo converter is equal to
9
, ,
10 𝑆-$ 𝑆.$ 𝑆 𝑆0 𝑆-$ 𝑆.$
11 ! (=! / (! , , ( (2)
𝑆-' 𝑆.' 𝑆1 𝑆2 𝑆-' 𝑆.'
12
13
14
15 + +
16 S'v1 S'w1
S'u1 S'a1 S'b1
17
18 us i Lfi S1 S3 Lfo
s uin iin n1 : n2 S5 S7 io RL
19 u a +
+ + vh + vo –
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20 v Vdc1 vp vs Vdc2 Cfo
– – –
21 w b
22 Grid Cfi
23 S'u2 S'v2 S'w2
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S2 S4 S6 S8 S'a2 S'b2
24
– –
25
Virtual DAB with virtual dc-link voltages
26
ee

27 Fig. 2. Equivalent operating circuit of the proposed HF-ac linked universal converter.
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30 III. GENERAL SVM OF PROPOSED UNIVERSAL CONVERTER

31 Seen from the secondary side of equivalent operating circuit Fig. 2 and remove the virtual DAB
32
converter, the circuit becomes a bidirectional indirect matrix converter (IMC), formed by rectifier stage
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34
switches S'ij and inversion stage switches S'mj. Through (1) and (2), the S'ij and S'mj are then coupled by the
35 virtual DAB to produce those for the Sij and Smj, where the switching signals of the virtual DAB S1~S4 and
36 S5~S8 alternate in a constant 50% duty cycle at
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37 𝑆 𝑆' 𝑆 𝑆0 𝑆; 𝑆;
1 0 0 1
38 ! $ ( ∈ 45 8,5 8:, ! / ( = ! ;$ ;' ( (3)
39 𝑆* 𝑆+ 0 1 1 0 𝑆1 𝑆2 𝑆* 𝑆+
40 A general SVM is then proposed for the HF-ac linked universal converter in Fig. 1, through the SVM of
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conventional IMC and HF chop of DAB converter. Accordingly, the method is categorized as two steps: 1)
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switching states selection and duty cycles calculation of rectifier and inversion stages as that of a
44 conventional IMC, but with single-phase ac/dc voltage output at the inversion stage; 2) duty cycles
45 combination and switching states implementation taking into account the HF-ac voltage chopping, current
46 commutation, and leakage inductance management. The power flow from three-phase side to single-phase
47 side is illustrated as an example, which can be inherited for a reverse power flow.
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A. Switching States Selection and Duty Cycles Calculation
50 Referring to the SVM of a conventional IMC, Fig. 3 shows the current space vectors of the rectifier
51 stage. There are nine current vectors, including six active vectors (I1~I6) and three zero vectors (I7~I9). The
52 active vectors divide the space into six sectors I~VI. When falling into any sector, the reference current
53 vector Iref are synthesized by the two adjacent active vectors and one of the zero vectors.
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55 The duty cycles d11, d12, and d10 of the two active states and zero state are expressed as [30]
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 International Journal of Circuit Theory and Application Page 4 of 15

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𝑑$$ = 𝑀$ sin (𝜋⁄3 − 𝜃H )
4
5 𝑑$' = 𝑀$ sin (𝜃H ) (4)
6 𝑑$J = 1 − (𝑑$$ + 𝑑$' )
7 where M1 = Iref /Ip = Ism/Ip denotes the modulation index of the equivalent IMC rectifier stage, Ip denotes the
8 absolute value of transformer primary current, Ism denotes the amplitude of three-phase source current, and
9 θi denotes the angle of Iref in the ith sector.
10
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The SVM of a conventional single-phase inverter [31] is applied to the inversion stage of the equivalent
12 IMC. Fig. 4 shows the voltage space vectors, comprising two active vectors, V1 and V2, and two zero vectors,
13 V3 and V4. Duty cycles d'21 and d'20 of the active and zero states in sector I are expressed as
14 𝑑 , '$ = 𝑀' = 𝑉MNO ⁄𝑉PQ'
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16 𝑑′'J = 1 − 𝑑'$ (5)
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18 where M2 is the modulation index of the equivalent IMC inversion stage which will be 2Vom/Vdc2 or Vom/Vdc2
19 depending on single-phase ac or dc output. The Vom denotes the output voltage amplitude.
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20
21
22 β I1(100001)
23 I2
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24 I2(001001)
25 I1 I3(011000)
I3 Ⅲ Ⅱ
26
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27 d12I1 I4(010010)
28 Iref
29 I5(000110)
θi Ⅰ
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Ⅳ α
30 I6(100100)
31 d11I6
I7I8I9
32 I7(110000)
I4 I6
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33 Ⅴ Ⅵ I8(001100)
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35 I9(000011)
I5
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*Example: I1(100001) denotes

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S'u1=ON, S'u2=OFF, S'v1=OFF, S'v2=OFF, S'w1=OFF, S'w2=ON.
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39 Fig. 3. Diagram of rectifier-stage current space vectors.
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V3(1010) β
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V4(0101)
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45 V2(0110) Vref V1(1001)
46 0 d'21V1 α
47 Sector Ⅱ Sector Ⅰ
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49 *Example: V1(1001) denotes
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S'a1=ON, S'a2=OFF, S'b1=OFF, S'b2=ON.
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52 Fig. 4. Diagram of inversion-stage voltage space vectors.
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54 B. Duty Cycles Combination and Switching States Implementation
55 To control the primary input current and secondary output voltage simultaneously, the obtained duty
56 cycles of rectifier and inversion stages of the equivalent IMC are firstly combined to consider the current
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3 communication and leakage energy management. To achieve that, the inversion stage should keep at zero
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state to drive the winding current to zero, while the rectifier stage works as normal to build up winding
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current. Therefore, the duty cycles of inversion stage in (5) are revised into
7 𝑑'$ = 𝑑′'$ ∙ 𝑑$$ + 𝑑′'$ ∙ 𝑑$'
8
9 𝑑'J = 𝑑′'J ∙ 𝑑$$ + 𝑑 , 'J ∙ 𝑑$' + 𝑑$J (6)
10 In addition, the HF-ac chopping of S1~S8 in (3) is considered, to chop the virtual dc-link voltage Vdc1 to
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a square wave voltage vp at the primary side and fold the secondary voltage vs to the virtual dc-link voltage
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13
Vdc2.
14 Then, all possible switching states of the TPSP matrix converter in the proposed universal converter are
15 listed in Table I. The Ia and Ib denote the active state vectors to be selected when the reference input current
16 Iref is in the respective sector, Iz1 and Iz2 denote the zero state vectors to be used in that sector. Using sector
17
I and positive voltage vp as an example, as Fig. 3 and Table I show, I6, I1, I8, and I9 are selected for Ia, Ib,
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19
Iz1, and Iz2.
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TABLE I. SWITCHING STATES OF TPSP MATRIX CONVERTER.
21
22 Sector
23
I II III IV V VI
vp Polarity
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24 Iz1 I8 I7 I9 I8 I7 I9
25 Ia I6 I1 I2 I3 I4 I5
26 Positive
Ib I1 I2 I3 I4 I5 I6
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27 Iz2 I9 I8 I7 I9 I8 I7
28 Iz1 I9 I8 I7 I9 I8 I7
29
Ia I4 I5 I6 I1 I2 I3
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30 Negative
Ib I3 I4 I5 I6 I1 I2
31
Iz2 I8 I7 I9 I8 I7 I9
32
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34 Similarly, Table II lists the active state vector Va and zero state vectors Vz1 and Vz2 of the secondary
35
cyclo converter.
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37 TABLE II. SWITCHING STATES OF CYCLO CONVERTER.

38 vs Polarity Positive Negative
39
Sector Vz2 Va Vz1 Vz1 Va Vz2
40
41 I V3 V1 V4 V4 V2 V3
42 II V4 V2 V3 V3 V1 V4
43
44 Thereby, the duty cycles in (4) and (6), and selected switching states in Tables I and II are utilized to
45
implement the SVM of primary TPSP matrix converter and secondary cyclo converter, respectively, as
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47 shown in Figs. 5 and 6.
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 International Journal of Circuit Theory and Application Page 6 of 15

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3 1
4 1 d210 Triangular
d10 d11 carrier
5 2
6 d10
0 2 t
7
8 S'u1 0
S'u2 0
9 1 1 1 d10/2
S'i j S'v1 1 Triangular
10 S'v2 d'21.d11 d20 d10/2 carrier
11 S'w1 0
S'w2 0 d'21.d11 d10/2
12 t
S1 S4 S2 S3 1 0 d10/2
13 S'a1=S'a2 0
14 Su1 0
Su2 0 S'b1=S'b2 0
15 1 1
S i j S v1 1 S5 S8 S6 S7
16 Sv2
Sa1=Sa2 0
17 Sw1 0
Sb1=Sb2 0
Sw2 0
18 States I8 I6 I1 I9 I4 I3 I8 States V4 V1 V3 V1 V4 V2 V3 V2 V4
19 d10Ts
d11Ts d12Ts d10Ts d12Ts d11Ts
d10Ts d'21 d11Ts d'21 d12Ts d10Ts d'21 d12Ts d'21.d11Ts
. . .
4 4 Time
Fo
20 Time 2 2 2 2 2
2 2 2 2 2 d10Ts d20-d10Ts d20-d10Ts d10Ts
21
22
uin,uv 4 2 2 4
uin,uw
23 vp
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uin,vw t
vs
24 u0in,wv t t t
t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 0 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
25 0 1
uin,wu
26 uin,vu
ee

27 Polarity Positive Negative Polarity Positive Negative

28 Fig. 5. Switching states implementation of TPSP Fig. 6. Switching states implementation of cyclo
29 matrix converter. converter.
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30
31 Fig. 5 shows the switching states implementation of the TPSP matrix converter, when Iref falls in sector
32 I and θi is within π/6. It can be seen that the total zero state duty cycle d10 is divided into equal four parts
applied in the beginning, middle, and end of one control period. The active state duty cycle d11 or d12 is
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34 equally divided into two parts, applied between the zero and one active state periods. Whereas, from Table
35 I and Fig. 5, modified from the rectifier-stage SVM of equivalent IMC, different active vectors are selected
36
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for Ia or Ib in each half duty cycle of d11 or d12, depending on positive or negative vp. In addition, different
37 zero vectors Iz1 and Iz2 are selected between the beginning and medium d10/4, as well as the medium and
38 last d10/4. To maintain minimum switching actions, the same zero vector is applied to the two medium d10/4
39
parts in one control period, i.e., during the positive and negative transition of vp.
40
41 Fig. 6 shows corresponding implementation of the cyclo converter with Vref in sector I. Similarly, the
42 inversion-stage SVM of equivalent IMC is modified for the secondary cyclo converter in the proposed
43 universal converter. After the duty cycle combination of (6) and switching states modification of (2), as
44 seen in Table II and Fig. 6, different active vectors are selected during the positive and negative vs, and the
45 zero duty cycle is unequally divided into five parts, in one control period.
46
47 C. Operating Modes Analysis
48
Under the modified general SVM, Fig. 7 shows the operating modes of the proposed universal converter,
49
50
illustrated by the equivalent circuit of Fig. 2. Based on the positive and negative half cycles of HF
51 transformer voltage vp and the vs, the operation is categorized as 12 Modes in one control cycle. In the first
52 half cycle of Modes 1~6, the polarity is positive, and vp=Vdc1 and vs=Vdc2; in the secondary half cycle of
53 Modes 7~12, the polarity is negative vp= −Vdc1 and vs= −Vdc2.
54
Mode 1 (t0−t1): In the primary side, switches S'v1, S'v2, S1, and S4 are on; the dc-link current Idc1 freewheels,
55
leading to vp=0. In the secondary side, switches S'a2, S'b2, S6 and S7 are on, yet no current flows through
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3 them because of the off-state switches S'a1 and S'b1, consequently, Idc2=0. In this case, the load resistance RL
4
is powered by the capacitor Cfo. As shown in Figs. 5 and 6, the TPSP matrix converter operates at zero state
5
6
I8, and the cyclo converter operates at zero state V4. The durations of both states are Ts·d10/4.
7 Mode 2 (t1−t2): S'v1 and S'b2 are turned off, while S'u1 and S'b1 are turned on, other switches stay the same
8 as in Mode 1. One consequent change is that grid source voltages us,u and us,v are included in the primary
9 side. It can be seen that vp=uin,uv in this mode. Another noteworthy change is that in the secondary side,
10
switches S'v1, S'v2, S1, and S4 transfer the power from primary side to the load resistance RL, and Lf0 and Cf0
11
12
are charged through the HF transformer. In addition, from Figs. 5-7, it can be seen that during this interval,
13 the TPSP matrix converter and the cyclo converter operate at active state I6 and V1, respectively, and the
14 duration of this mode is Ts·d'21·d11/2.
15 Mode 3 (t2−t3): S'a2 is turned off, while S'a1 is turned on, other switches remain unchanged as in the Mode
16 2. Since neither S'a2 or S'b2 is on, the inversion stage cannot conduct current, then RL is again powered by
17
Cf0. On the other hand, since no changes happens in the rectifier stage and active-bridge inverter, the
18
19
primary side of equivalent operating circuit stays exactly the same as that in Mode 2. Accordingly, the value
of vp also stays the same. In light of that, it can be noted from Figs. 5 and 6 that the TPSP matrix converter
Fo
20
21 does stay at active state I6, while the cyclo converter has been switched to zero state V3. Obtained by
22 calculation, the duration of this mode is Ts·d'20·d11/2.
23
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It is noticeable that vp remains constant in modes 2~3, and due to the HF transformer, vp has a relatively
24
25
fixed proportion with vs. Therefore, vs also remains constant in the two modes, which can be seen from Figs.
26 5 and 6. It is also concluded that the duty cycle ratio between mode 2 and mode 3 is d'21:d'20.
ee

27 Idc1 Idc2 Idc1 Idc2

28 us,i Lfi uin,i S'u1 S'v1 Sw1
'
S1 S3 n1
S'a1 S'b1 L us,i Lfi uin,i S'u1 S'v1 Sw1
' S'a1 S'b1 L
u :n 2 S5 S7 a fo i o RL
u
S1 S3 n1 :n 2 S5 S7 a fo i o RL
29 v Vdc1 vp vs Vdc2 vh Cfo vo v Vdc1 vp vs Vdc2 vh Cfo vo
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30 w S S b w S S b
2 4 S6 S8 Load 2 4 S6 S8 Load
Grid Cfi S'u2 S'v2 Sw2
' S'a2 S'b2 Grid Cfi S'u2 S'v2 Sw2
' S'a2 S'b2
31 1 12
Idc1 Idc2 Idc1 Idc2
32
us,i Lfi uin,i iin,uS'u1 S'v1 Sw1
' S'a1 S'b1 L us,i Lfi uin,i iin,uS'u1 S'v1 Sw1
' S'a1 S'b1 L
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33 S1 S3 n1 :n S5 S7 a fo i o RL S1 S3 n1 :n S5 S7 a fo i o RL
iin,v u iin,v u
2 2

34 v Vdc1 vp vs Vdc2 vh Cfo vo v Vdc1 vp vs Vdc2 vh Cfo vo

w S S b w S S b
35 2 4 S6 S8 Load 2 4 S6 S8 Load
Grid Cfi S'u2 S'v2 Sw2' S'a2 S'b2 Grid Cfi S'u2 S'v2 Sw2' S'a2 S'b2
36 2 11
iew

Idc1 Idc2 Idc1 Idc2

37 us,i Lfi uin,i iin,uS'u1 S'v1 Sw1
' S'a1 S'b1 L us,i Lfi uin,i iin,uS'u1 S'v1 Sw1
' S'a1 S'b1 L
S1 S3 n1 :n S5 S7 a fo io RL S1 S3 n1 :n S5 S7 a fo io RL
38 iin,v u
2

vo iin,v u
2

vo
v Vdc1 vp vs Vdc2 vh Cfo v Vdc1 vp vs Vdc2 vh Cfo
39 w S S
S6 S8 b w S S
S6 S8 b
Grid Cfi S'u2 S'v2 Sw2' 2 4
S'a2 S'b2 Load Grid Cfi S'u2 S'v2 Sw2' 2 4
S'a2 S'b2 Load
40 3 10
41 Idc1 Idc2 Idc1 Idc2
42 us,i Lfi uin,i iin,uS'u1 S'v1 Sw1
'
S1 S3 n1 : n S5 S7 a
S'a1 S'b1 L
fo io RL us,i Lfi uin,i iin,uS'u1 S'v1 Sw1
'
S1 S3 n1 : n S5 S7 a
S'a1 S'b1 L
fo io RL
u 2
u 2

43 iin,w v Vdc1 vp vs Vdc2 vh Cfo vo

iin,w v Vdc1 vp vs Vdc2 vh Cfo vo
w S S b w S S b
44 Grid Cfi S'u2 S'v2 Sw2' 2 4 S6 S8
S'a2 S'b2 Load Grid Cfi S'u2 S'v2 Sw2' 2 4 S6 S8
S'a2 S'b2 Load
45 4 9
Idc1 Idc2 Idc1 Idc2
46
us,i Lfi uin,i iin,uS'u1 S'v1 Sw1
' S'a1 S'b1 L us,i Lfi uin,i iin,uS'u1 S'v1 Sw1
' S'a1 S'b1 L
47 u
S1 S3 n1 : n S5 S7 a
2
fo io RL
u
S1 S3 n1 : n S5 S7 a
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fo io RL
vp vs vo vp vs vo
48 iin,w v Vdc1
w S S
Vdc2
b
vh Cfo iin,w v Vdc1
w S S
Vdc2
b
vh Cfo
S6 S8 Load S6 S8 Load
49 Grid Cfi S'u2 S'v2 Sw2' 2 4
S'a2 S'b2 Grid Cfi S'u2 S'v2 Sw2' 2 4
S'a2 S'b2
50 5 8
Idc1 Idc2 Idc1 Idc2
51 us,i Lfi uin,i S'u1 S'v1 Sw1
' S'a1 S'b1 L us,i Lfi uin,i S'u1 S'v1 Sw1
' S'a1 S'b1 L
S1 S3 n1 : n S5 S7 fo i o RL S1 S3 n1 : n S5 S7 fo i o RL
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vp
2

vs
a vo
u
vp
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a vo
v Vdc1 Vdc2 vh Cfo v Vdc1 Vdc2 vh Cfo
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2 4 S6 S8 b
Load
w S S
2 4 S6 S8 b
Load
Grid Cfi S'u2 S'v2 Sw2
' S'a2 S'b2 Grid Cfi S'u2 S'v2 Sw2
' S'a2 S'b2
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3 Mode 4 (t3−t4): In this mode, all other switches are working as in the Mode 3, except S'w2 and S'v2. As a
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result, us,v is displaced by us,w as one of the power sources, which leads to vp=uin,uw. As for the secondary
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side, since nothing changes in the inversion stage and active-bridge rectifier, Cf0 continues to power RL.
7 Seen from Figs. 5 and 6, the TPSP matrix converter starts to operate at active state I1, while the cyclo
8 converter continues to operate at zero state V3. The duration of this mode can be written as Ts·d'20·d12/2 by
9 calculation.
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Mode 5 (t4−t5): In this mode, the primary side works as the Mode 4 because of no switching signal
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change. The secondary side returns to the operating state as the Mode 2 due to the reversal of switching
13 signals S'a1 and S'a2. Given that, seen from Figs. 5 and 6, the TPSP matrix converter’s operating state is still
14 I1, while the cyclo converter’s operating state recovers to be V1. The duration of this mode is Ts·d'21·d12/2.
15 Note that vp and vs remain constant in Modes 4 and 5, and the duty cycle ratio between Mode 4 and
16 Mode 5 is d'20:d'21, which is similar to that in Modes 2 and 3.
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18 Mode 6 (t5−t6): In the primary side, switching signals S'u1 and S'w1 are changed, which makes vp=0. In
19 the secondary side, the switching signals S'b1 and S'b2 changes; consequently, the on-off states of all switches
Fo
20 are the same as that in mode 1. Figs. 5 and 6 show that the operating states of TPSP matrix converter and
21 cyclo converter are I9 and V4, respectively, and the duration of this mode is Ts·d10/4.
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23 Mode 7~12 (t6−t12): In these modes, the on-off states of switches in the virtual IMC corresponds to those
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24 in Modes 6~1, while the on-off states of switches in the virtual DAB are opposite. In addition, as shown in
25 Figs. 5 and 6, the durations of Modes 7~12 are equal to the durations of Modes 6~1.
26
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27 D. Voltage Gain Analysis

28 From the developed SVM, the average voltage of primary virtual dc link is
29
3
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30 𝑉TPQ$ = 𝑀$ 𝑈WX 𝑐𝑜𝑠𝜑H (7)

31 2
32 where Usm denotes the amplitude of three-phase voltage us and φi denotes the power factor angel of three-
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phase side. With (4) and 𝑉TPQ' = (𝑛' /𝑛$ )𝑉TPQ$ = 𝑛𝑉TPQ$ , the amplitude of single-phase voltage vo is obtained
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35 by
36 3
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37 𝑉_X = 𝑛𝑀$ 𝑀' 𝑈WX 𝑐𝑜𝑠𝜑H (8)

38
4
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40 IV. SIMULATION AND REAL-TIME INVESTIGATIONS
41 The proposed bidirectional universal converter of Fig. 1 with the general SVM is simulated in
42 MATLAB/Simulink and investigated in PLECS RT-BOX real-time implementation platform. The power
43 flow from three-phase 400 V/50 Hz ac grid to single-phase 120 V/60 Hz ac load, 220 V/50 Hz ac load, and
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400 V dc load are investigated, respectively. Table III lists the system specifications. Simulation and
45
46 implementation results are shown in Figs. 8-13.
47 TABLE III. SYSTEM SPECIFICATIONS.
48
Parameters Values
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50 Three-phase grid RMS voltage 400 V
51 Fundamental frequency of three-phase grids, f0 50 Hz
52 Three-phase side filter inductance, Lfi 2 mH
53 Three-phase side filter capacitance, Cfi 100 µF
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Single-phase side filter inductance, Lfo 3 mH
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56 Single-phase side filter capacitance, Cfo 100 µF
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3 Case 1: 120 V/60 Hz Single-Phase AC Load
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5 From (8), the n1:n2=1:1 is applied to the HF transformer; M1=0.8 and M2=0.82 are performed to the
6 rectifier and inversion stages of the equivalent IMC; RL=10 W is applied to the single-phase ac load. Fig. 8
7 shows the three-phase input voltages of TPSP matrix converter, single-phase load voltage and current, and
8 primary and secondary voltages and currents of the HF transformer, from the simulation. Fig. 9 shows the
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36 Fig. 8. Simulation results of 120 V/60 Hz single-phase ac output. (a) Three-phase input voltages of TPSP matrix
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37 converter and single-phase load voltage and current; (b) primary voltage and current of the HF transformer; (c) secondary
38 voltage and current of the HF transformer.
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54 Fig. 9. Real-time results of 120 V/60 Hz single-phase ac output. (a) Three-phase input voltages [150 V/div] of TPSP
55 matrix converter and (b) single-phase load voltage [200 V/div] and current [20 A/div].
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3 From Figs. 8 (a) and 9, it can be seen that the three-phase 400 V/50 Hz ac voltage is converted to the
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single-phase 120 V/60 Hz ac voltage through the HF-ac linked matrix converter and cyclo converter under
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the developed SVM. The load current is sinusoidal with low harmonics, which has the total harmonic
7 distortion (THD) of 2.28%. From Fig. 8 (b) and (c), it can be seen that the primary and secondary voltage
8 of HF transformer match the 1:1 turns ratio.
9 Case 2: 220 V/50 Hz Single-Phase AC Load
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11 In this case, the n1:n2=1:2, RL=15 W, M1=0.8, M2=0.78 are performed, according to the calculation from
12 (8). Figs. 10 and 11 show results. From Figs. 10 (a) and 11 (b), it can be seen that the single-phase 220 V/50
13 Hz ac voltage is obtained, with low load harmonics that the current THD is 2.53%. From Fig. 10 (b) and
14 (c), the primary and secondary voltages of the HF transformer match the turns ratio.
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39 Fig. 10. Simulation results of 220 V/50 Hz single-phase ac output. (a) Three-phase input voltages of TPSP matrix
40 converter and single-phase load voltage and current; (b) primary voltage and current of the HF transformer; (c) secondary
41 voltage and current of the HF transformer.
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54 (a) (b)
55 Fig. 11. Real-time results of 220 V/50 Hz single-phase ac output. (a) Three-phase input voltages [150 V/div] of TPSP
56 matrix converter and (b) single-phase load voltage [200 V/div] and current [20 A/div].
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3 Case 3: 400 V DC Load
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5 The n1:n2=2:3 and RL=20 W are applied in the circuit, M2=0.75 is performed to the conversion stage of
6 equivalent converter, to regulate the dc output voltage. From Figs. 12 (a) and 13 (b), it can be seen that the
7 400 V dc voltage is obtained for the dc load, with the peak-to-peak ripple ratio within 5% of the average
8 voltage. In addition, from Figs. 8-13, it can be seen that the proposed universal converter fulfills voltage
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amplitude and frequency conversion using the proposed general SVM.
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Fo
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35 Fig. 12. Simulation results of dc output. (a) Three-phase input voltages of TPSP matrix converter and dc load voltage
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and current; (b) primary voltage and current of the HF transformer; (c) secondary voltage and current of the HF
37 transformer.
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52 Fig. 13. Real-time results of dc output. (a) Three-phase input voltages [150 V/div] of TPSP matrix converter and (b) dc
53 load voltage [200 V/div] and current [10 A/div].
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V. CONCLUSION
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5 This paper proposed a HF-ac linked universal converter interfacing three-phase ac and single-phase ac/dc,
6 by TPSP matrix converter and cyclo converter. The primary matrix converter rectified the three-phase ac
7 voltages into a virtual dc voltage and then inverted it to a HF ac voltage. The secondary cyclo converter
8 regained the virtual dc voltage, then inverted it to single-phase ac voltage or made it an adjustable dc
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voltage. A general SVM was then developed by modifying the SVM of conventional IMC, taking into
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11 considerations of the voltage chopping of HF transformer, voltage and current control of primary and
12 secondary sides, and leakage energy commutation. Simulation and real-time implementation results of
13 different voltage conditions demonstrated the validity of the proposed converter and the modulation
14 method, providing an effective solution for DGs interfacing with utility grids.
15
16
17 REFERENCES
18
[1] G. Simard, D. Chartrand, and P. Christophe, “Distribution automation: Applications to move from today’s
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37 [8] Q. Chen, N. Liu, C. Hu, L. Wang, J. Zhang, "Autonomous Energy Management Strategy for Solid State Transformer
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46 [11] J. Saeed, "A ZVS-ZCS phase shift full bridge DC-DC converter with secondary-side control for battery charging
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48 [12] J. Guacaneme, G. Garcera, E. Figueres, et al, "Dynamic modeling of a dual active bridge DC to DC converter with
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4 converter," International Journal of Circuit Theory and Applications, vol. 43, no. 4, pp. 438–454, Apr. 2015.
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8 [17] C. Gu, H. S. Krishnamoorthy, P. N. Enjeti and Y. Li, "Medium-voltage (MV) matrix converter topology for wind
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21 indirect control for high frequency AC-linked matrix converter," in Proc. International Power Electronics
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24 2016 IEEE International Conference on Industrial Technology (ICIT), pp.1248-1253, 14-17 March, 2016.
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27 [24] C. Gu, Z. Zheng, L. Xu, K. Wang and Y. Li, "Modeling and Control of a Multiport Power Electronic Transformer
28 (PET) for Electric Traction Applications," in IEEE Transactions on Power Electronics, vol. 31, no. 2, pp. 915-927,
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Applied Power Electronics Conference and Exposition (APEC), Long Beach, CA, 2016, pp. 3648-3654.
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34 Bidirectional DC–AC," in IEEE Transactions on Power Electronics, vol. 33, no. 1, pp. 137-150, Jan. 2018.
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36 Grid-Tie DC–AC–AC Converter With High-Frequency Isolation," in IEEE Transactions on Power Electronics, vol.
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37 33, no. 1, pp. 845-858, Jan. 2018.

38 [28] J. I. Leon, S. Kouro, L. G. Franquelo, J. Rodriguez and B. Wu, "The Essential Role and the Continuous Evolution of
39 Modulation Techniques for Voltage-Source Inverters in the Past, Present, and Future Power Electronics," in IEEE
40 Transactions on Industrial Electronics, vol. 63, no. 5, pp. 2688-2701, May 2016.
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With Output LC Filter for UPS Applications," in IEEE Transactions on Industrial Electronics, vol. 56, no. 6, pp.
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45 [30] A. Ammar et al., "Grid tie indirect matrix converter operating with unity power factor under double space vector
46 modulation," 2017 IEEE International Conference on Industrial Technology (ICIT), Toronto, ON, 2017, pp. 1498-
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48 [31] Y. Liu, B. Ge, H. Abu-Rub, F.Z. Peng, “An effective control method for quasi-Z-source cascade multilevel inverter
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50 2014.
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3 Article title:
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6 General Space Vector Modulation of A High-Frequency AC Linked Universal Converter for
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Distributed Generations
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12 Authors’ names:
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15 Yushan Liu*, Jie He, Baoming Ge, Yaosuo Xue
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Key findings presented in the paper:
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22 A high-frequency (HF) ac linked universal converter interfacing three-phase ac with single-phase
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ac or dc is proposed for distributed generations (DGs). The primary side of HF transformer
25 consists of a three-phase-to-single-phase matrix converter, converting the three-phase voltage to
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27 a HF ac voltage. The secondary side of HF transformer is a cyclo converter, unfolding the HF ac

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29 voltage to single-phase ac or dc voltage, depending on the DGs. A simple to be implemented
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general space vector modulation (SVM) is also developed.
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