Jawahar Education Society’s Institute of Technology, Management & Research, Nashik

Department of Computer Engineering

Class :- Second Year Computer Engineering Sem - 1
Subject :- Digital Electronics and logic design
Note:- Question for 1 , 2 , 4 Marks (More than 200 Ques on each unit with combination of 1,2,4 marks)

Id Unit Correct
(Keep it Question Option A Option B Option C Option D Marks
blank)
No. Option

Unit No:-1 Number Systems and Logic Design Techniques

1 The Gray code for decimal number 6 is equivalent to 1100 1001 101 110 C 1
1
The 2s compliment form (Use 6 bit word) of the number 1010 is 111100 110110 110111 1011 B 2
1 AB+(A+B)’ is equivalent to A Ex-Nor B A Ex OR B (A+B)A (A+B)B A 2
1 The hexadecimal number equivalent to (1762.46) 8 is 3F2.89 3F2.98 2F3.89 2F3.98 B 1
1 A three input NOR gate gives logic high output only when One input is high One input is low Two input are All input are D 1
1 None of the
The absorption law in Boolean algebra say that X+X=X X.Y=X x+x.y=x C 2
above
1 Logic X-OR operation of (4ACO)H & (B53F)H results AACB 0000 ABCD FFFF D 2
1 What is decimal equivalent of (11011.1000) 2 ? 22 22.2 20.2 27.5 D 1
1 All of the
The negative numbers in the binary system can be represented by Sign magnitude 2's complement 1's complement A 1
above
1
Signed magnitude 1’s complement 2’s complement None of the
Negative numbers cannot be represented in D 1
form form form above
1 The answer of the operation (10111) 2*(1110)2 in hex equivalence is 150 241 142 101011110 C 2
1
The Hexadecimal number equivalent of (4057.06) 8 is 82F.027 82F.014 82F.937 83F.014 B 1

1 The NAND gate output will be low if the two inputs are 00 01 10 11 D 1
1 A binary digit is called a Bit Character Number Byte A 1
1 What is the binary equivalent of the decimal number 368 101110000 110110000 111010000 111100000 A 1
1 What is the binary equivalent of the Octal number 367 11110111 011100111 110001101 101110111 A 1
1 What is the binary equivalent of the Hexadecimal number 368 1111101000 1101101000 1101111000 1110101000 B 1
1 What is the binary equivalent of the decimal number 1011 1111110111 1111000111 1111110011 1111100011 C 1
1 The gray code equivalent of (1011) 2 is 1101 1010 1111 1110 D 1
1 The decimal equivalent of hex number 1A53 is 6793 6739 6973 6379 B 1
1 ( 734)8 =( )16 C1D DC1 1CD 1DC D 1
1 The simplification of the Boolean expression (A'BC')'+ (AB'C)' is 0 1 A BC B 2
1 The hexadecimal number ‘A0’ has the decimal value equivalent to 80 256 100 160 D 1
1 The Gray code for decimal number 6 is equivalent to 1100 1001 0101 0110 C 1
1 The Boolean expression A.B+ A.B+ A.B is equivalent to A+B A'.B (A + B)' A.B A 2
1 The 2’s complement of the number 1101101 is 101110 111110 110010 10011 D 1
1 When simplified with Boolean Algebra (x + y)(x + z) simplifies to x x + x(y + z) x(1 + yz) x + yz D 2
1 The code where all successive numbers differ from their preceding number by
Binary code. BCD. Excess – 3. Gray. D 1
single bit is
1 -8 is equal to signed binary number 10001000 OOOO1000 10000000 11000000 A 2
1
OR gate and NOR gate and NOR gate and NAND gate
DeMorgan’s first theorem shows the equivalence of B 1
Exclusive OR gate. Bubbled AND gate. NAND gate. and NOT gate

1
When signed numbers are used in binary arithmetic, then which one of the 2’s 9’s
Sign-magnitude. 1’s complement. A 1
following notations would have unique representation for zero. complement. complement.
1 The decimal equivalent of Binary number 11010 is 26 36 16 23 A 1
1 1’s complement representation of decimal number of -17 by using 8 bit
representation is 1110 1110 1101 1101 1100 1100 0001 0001 A 1
1 The excess 3 code of decimal number 26 is 0100 1001 01011001 1000 1001 01001101 B 1
1 How many AND gates are required to realize Y = CD+EF+G 4 5 3 2 D 1
1 The hexadecimal number for (95.5)10 is (5F.8) 16 (9A.B) 16 ( 2E.F) 16 ( 5A.4) 16 A 1
1 The octal equivalent of (247) 10 is ( 252) 8 (350) 8 ( 367) 8 ( 400) 8 C 1
1 none of
The number 140 in octal is equivalent to (96)10 . ( 86) 10 (90) 10 . A 1
these.
1 The NOR gate output will be low if the two inputs are 11 01 10 All D 1
1 none of
Convert decimal 153 to octal. Equivalent in octal will be (231)8 ( 331) 8 ( 431) 8 . A 1
these.
1 The decimal equivalent of ( 1100) 2 is 12 16 18 20 A 1
1 none of
The binary equivalent of (FA)16 is 1010 1111 1111 1010 10110011 B 1
these
1 None of
How many two-input AND and OR gates are required to realize Y=CD+EF+G 2,2 2,3 3,3 A 1
these
1
The excess-3 code of decimal 7 is represented by 1100 1001 1011 1010 D 1
1 When an input signal A=11001 is applied to a NOT gate serially, its output
00111 00110 10101 11001 B 2
signal is
1 The result of adding hexadecimal number A6 to 3A is DD E0 F0 EF B 1
1 A universal logic gate is one, which can be used to generate any logic function.
OR AND XOR NAND D 1
Which of the following is a universal logic gate?
1 To maximize
To minimize
Reducing the To map the given the terms of
the terms in a
Karnaugh map is used for the purpose of electronic circuits Boolean logic a given a C 1
Boolean
used. function. Boolean
expression.
expression.
1 The 2’s complement of the number 1101110 is 0010001 0010001 0010010 None C 1
1 The decimal equivalent of Binary number 10101 is 21 31 26 28 A 1
1 How many two input AND gates and two input OR gates are required to
1,1 4,2 3,2 2,3 A 1
realize Y = BD+CE+AB
1 Which of following are known as universal gates NAND & NOR AND & OR. XOR & OR. None. A 1
1 Convert the octal number 7401 to Binary. 1.111E+11 1.1111E+11 1.111E+11 1.1101E+11 A 1
1 Find the hex sum of (93)16 + (DE)16 . (171)16 (271)16 (179)16 (181)16 A 1
1 1110 (OR -
Perform 2’s complement subtraction of (7)10 − (11)10 . 1100 (OR -4) 1101 (OR -5) 1011 (OR -3) A 1
6)
1 What is the Gray equivalent of (25)10 01101 110101 10110 10101 D 1
1
Simplify the Boolean expression F = C(B + C)(A + B +
C BC ABC A+BC A 2
C).

1 Simplify the following expression into sum of products using Karnaugh map A'B+C' D+ A'B'+C' D'+ A'B'+C' D+ A'B+C' D'+
A 4
F(A,B,C,D) = (1,3,4,5,6,7,9,12,13) A'D+BC' A'D'+B'C' A'D+BC' A'D'+BC'
1 ( A + B' +C'
Simplify F = (ABC)'+( AB)'C+ A'BC'+ A(BC)'+ AB'C. ( A' + B' +C' ) ( A' + B +C ) ( A + B +C ) A 4
)
1
Determine the binary numbers represented by 25.5 11001.1 011011.101 10101.110 11001.0101 A 1
1 Conversion of decimal number 10.625 into binary number: 1010.101 1110.101 1001.11 1001.101 A 1
1
Conversion of fractional number 0.6875 into its equivalent binary number: 0.1011 0.1111 0.10111 0.0101 A 1

1 Perform the following subtractions using 2’s complement method. 01000 –

00001 00010 00011 11110 A 3
01001
1 Subtraction of 01100-00011 using 2’s complement method. : 1001 1000 1010 0110 A 3
1 ABC D' + A'
Minimize the logic functionY(A,B,C,D) = m(0,1,2,3,5,7,8,9,11,14) . Using ABC D' + A' B' + ABC D + A B + B' A' B' + B' C' +
B' + B' C' + A 4
Karnaugh map. B' C' + B' D+ A'D C' + B' D+ A'D B' D+ A'D
B' D
1 Simplify the given expression to its Sum of Products (SOP) form Y = (A + AC+ BC+ A'B + BC+ A'B + A' AC+ A'B +
AC+ BC+ A'B A 4
B)(A + (AB)')C + A'(B+C')+ A'B+ ABC A' C' C' A' C'
1 (1010010.1010 (1010010.10
(1010010.1010101 (1010010.1010101
Convert the decimal number 82.67 to its binary, hexadecimal and octal 1011)2; 101011)2;
1)2; (52.AB)16 ; 1)2; (52.AB)16 ; A 1
equivalents (52.AB)16 ; (52.AB)16 ;
(122.526)8 (122.526)9
(122.526)10 (122.526)11
1 (100100 )2 OR (000100 )2 OR (- Both (A) and None of the
Add 20 and (-15) using 2’s complement. A 3
(+4)10 4)10 (B) above
1 Add 648 and 487 in BCD code. 1135. 1136 1235 1138 A 3
1 (10001.100110 (10111.1000
(23.6)10 = (X)2 FIND X (10111.1001100)2 (10101.1001100)2 A 1
0)2 011)2
1 (42.88F5C)1
(65.535)10 =(X)16 FIND X (41.88F5C28)16. (42.88F5C28)16. (41.88F5C)16. A 1
6.
1 Convert the decimal number 430 to Excess-3 code: 110110001 110110000 110110011 110100001 A 1
1 Convert the binary number 10110 to Gray code: 11101. 11001. 10101. 11100 A 1
1 Minimize the following logic function using K-maps F(A,B,C,D) = A B' C' + C' D + A B' C' + B'D + A B' C' + C'
C' D + B'D + AD A 4
m(1,3,5,8,9,11,15) + d(2,13) B'D + AD AD D + B'D
1 Convert (2222)10 in Hexadecimal number. 8AE 8BE 93C FFF A 1
1 Quotient -
Quotient -1001 Quotient -1000 Quotient -1001 1001
Divide ( 101110) 2 by ( 101)2. A 3
Remainder -001 Remainder -001 Remainder -011 Remainder -
000
1 F=[(B+D’)+(
F=[(B+D’)+(B+C’ F=[(B+D’)+(B+C’) F=[(B+D’)+(B
Minimise the logic function (POS Form) F A,B,C,D) = PI M (1, 2, 3, 8, 9, 10, B+C’)’(‘A’+
)’(A’+C’)+(A’+B) ’(‘A’+C’)+(A’+B)] +C’)’(‘A’+C’)+ A 4
11,14)× d (7, 15) C’)+(A’+B)]
]’ ’ (A’+B)]’
’
1 Perform following subtraction (i) 11001-10110 using 1’s complement 00011 00111 00010 10011 A 3
1 Perform following subtraction(ii) 11011-11001 using 2’s complement 00010 00111 00011 10011 A 3
1 Reduce the following equation using k-map Y = (ABC)'+ A(CD)'+ AB'+
B'+(AD)' B' (AD)' B'+AD A 4
ABCD'+ (AB)'C
1 = =
Write the expression for Boolean function F (A, B, C) = m (1,4,5,6,7) in = (A+B+C)(A+B' = (A+B' +C)(A+B'
(A+B+C)(A+B' (A+B+C)(A A 4
standard POS form. +C)(A+B' +C' ) +C' )
+C) +B' +C' )
1 Convert the decimal number 45678 to its hexadecimal equivalent number. (B26E)16 (A26E)16 (B26B)16 (B32E)16 A 1
1 Convert (177.25)10 to octal. (261.2)8 (260.2)8 (361.2)8 (251.2)8 A 1
1 Reduce the following equation using k-map Y = B C' D'+ A' B C' D+ A B C' BC’ + BD + BC’ + BD +
BC’ + BD BC’ + BD+A A 4
D+ A' B C D+ A B C D AC AD
1 8-bit 1’s complement form of –77.25 is 1001101.01 10110010.1011 01001101.0010 10110010.1 B 2
1 In computers, subtraction is generally carried out by 2’s
9’s complement 10’s complement 1’s complement D 1
complement
1 The 2s compliment form (Use 6 bit word) of the number 1010 is 111100 110110 110111 1011 B 1
1 The answer of the operation (10111)2*(1110) 2 in hex equivalence is 150 241 142 101011110 C 2
1 The decimal number equivalent of (4057.06) 8 is 2095.75 2095.075 2095.937 2095.0937 D 1
1 The gray code equivalent of (1011) 2 is 1101 1010 1110 1111 D 1
1 10110110.11
12-bit 2’s complement of –73.75 is 01001001.1100 11001001.1100 10110110.0100 C 2
00
1 The 2’s complement of the number 1101101 is 101110 111110 110010 10011 D 1
1 The hexadecimal number equivalent to (1762.46) 8 is 3F2.89 3F2.98 2F3.89 2F3.98 B 1
1 What is decimal equivalent of BCD 11011.1100 ? 22.0 22.2 20.2 21.2 B 2
1 What is the binary equivalent of the decimal number 368 101110000 110110000 111010000 111100000 A 1
1 The Gray code for decimal number 6 is equivalent to 1100 1001 0101 0110 C 2
1 The decimal equivalent of hex number 1A53 is 6793 6739 6973 6379 B 1
1 (001011111010 Both (A) and None of
(2FAOC)16 is equivalent to (195 084)10 B 1
0000 1100)2 (B) these
1 The octal equivalent of hexadecimal (A.B)16 is 47.21 12.74 12.71 17.21 B 1
1 Logic X-OR operation of (4ACO)H & (B53F)H results AACB 0000 FFFF ABCD C 1
1 The simplified form of the Boolean expression (X+Y+XY)(X+Z) is X + Y + ZX + Y XY – YZ X + YZ XZ + Y C 2
1 The output of a logic gate is 1 when all its inputs are at logic 0. the gate is An AND or A NOR or
A NAND or an XO An OR or an XNOR D 1
either XOR an XNOR
1
calculating
1's
subtracting 1
adding 1's adding 1 to 1's complement
2's complement of any binary number can be calculated by from 1's B 1
complement twice complement and inverting
complement.
Most
significant
bit
1 to convert
to convert from
to decode from serial
Sum-of-Weights method is used one number system to encode data A 1
data to parralel
to other
data
1
The complement of a variable is always 1 0 inverse None C 1

1 The difference of 111 - 001 equals 100 111 001 110 D 2

1 The Unsigned Binary representation can only represent positive binary Both (A) and None of
TRUE FALSE A 1
numbers (B) Above
1 which of the following rules states that if one input of an AND gate is always
A +1 =1 A +A =A A.A = A A.1= A C 1
1, the output is equal to the other input?
1 Which of the number is not a representative of hexadecimal system 1234 ABCD 1001 DEFH D 1
1 Which one of the following is NOT a valid rule of Boolean algebra? A = A' AA = A A+1=1 A+0=A A 1
1 2^1 (2
2^4(2 raise to 2^3 (2 raise to 2^0 (2 raise
In the binary number ' 10011 ' the weight of the most significant digit is raise to A 1
power 4) power 3) to power 0)
power 1)
1 The binary value ' 1010110 ' is equivalent to decimal 86 87 88 89 A 1
1 2's complement of hexadecimal number B70A is B70B B709 48F6 48F5 C 1
1 2's complement of 5 is 1101 1011 1010 1100 B 1
1 The 4-bit 2's complement representation of ' -7 ' is 111 1111 1001 110 C 1
1 If we multiply ' 723 ' and ' 34 ' by representing them in floating point notation
i.e. By first, converting them in floating point representation and then 24.582 2.4582 24582 0.24582 A 2
multiplying them, the value of mantissa of result will be
1 The output of the expression F=A+B+C will be Logic when A=0, 10
Undefined One Zero B 2
B=1, C=1. the symbol ' + ' here represents OR Gate. (binary)
1 any input is any input is
A NAND gate's output is LOW if all inputs are LOW all inputs are HIGH C 1
LOW HIGH
1 OR Gate and
OR Gate and then NOT Gate and then AND Gate and
NOR gate is formed by connecting then AND C 1
NOT Gate OR Gate then OR Gate
Gate
1 The AND Gate performs a logical function Addition Subtraction Multiplicatio Division C 1
1 The Extended ASCII Code (American Standard Code for Information
2-bit 7-bit 8-bit 16-bit C 1
Interchange) is a code
1 The OR gate performs Boolean . multiplication subtraction division addition D 1
1 All the
All of the Any of the input Any of the
The output of an AND gate is one when inputs are A 1
inputs are one is one input is zero
zero
1 all inputs are any input is any input is all inputs
A NOR's gate output is HIGH if D 1
HIGH HIGH LOW are LOW
1 two AND
two AND gates, three AND two AND
gates, one OR
A logic circuit with an output X = A(Bar)BC+AB(Bar) consists of . two OR gates, two gates, two OR gates, one C 1
gate, two
inverters gates, one inverter OR gate
inverters
1 the boolean expression AB'CD'is a sumterm a product term a literal term always 1 B 1
1
two ORs a 4-input AND two ANDs an
The boolean expression X = AB + CD represents C 1
ANDed together gate ORed together exclusive-Or
1 The expression is an example of Commutative Law for A(B+C) =
AB+C = A+BC AB=BA A+B=B+A C 2
Multiplication. B(A+C)
1
To implement the expression AB(bar)CD+ ABC(bar)D+ ABCD (bar), it takes three AND gates three AND gates three AND one AND
A 1
one OR gate and and three inverters and four inverters gates gate
1 the boolean expression A + B' + C is a sum term a literal term a product complement A 1
1
F(A,B,C) = F(A,B,C) = F(A,B,C) =
The minterm expansion for F(A,B,C) = (A + B + C)(A + B' + C')(A' + B + F (A,B,C) = Pi
Summation Summation Summation A 2
C')(A' + B' + C) is M(0,3,5,6)
m(0,3,5,6) m(0,3,5,6) m(1,2,4,7)
1 (A+B).(A+C) = B+C A+BC AB+C AC+B B 1
1 Product of sum Sum of product Demorgans
A'B +A'BC'+AC is an example of Associative B 1
form form law
law
1 A'B + AC' + (A' + B + both (a)
An example of SOP expression is A + B(C + D) B 1
AB'C C)(A + B' + C) nad (b)
1 A = 1, B =
Determine the values of A, B, C, and D that make the sum term A(bar) + A = 1, B = 0, C A = 1, B = 0, C A = 0, B = 1,
0, C = 1, D = B 2
B+C(bar)+D equal to zero. = 0, D = 0 = 1, D = 0 C = 0, D = 0
1
1 (A' + B)(A' + (A + B)(A' + none of
The bolean expression A + BC equals (A + B)(A + C) B 2
C) C) the above
1
Demorgan's Distributive
A.(B + C) = A.B + A.C is the expression of Commutative Law Associative C 1
Law Law
Law
1
Commutative
A.(B.C) = (A.B).C is an expression of Demorgan's Law Distributive Law Associative D 1
Law
Law
1 How many binary bits are necessary to represent 748 different numbers? 7 10 9 8 B 1
1 The correct binary equivalent for DFA16 is: 1111011001012 1101111010102 1110101110102 0110110110 B 1
1 Which of the following Boolean expressions represents the DeMorganized
version of (A′ +B + C + D) ′ (A′ +B) (C′ D) (A′ B). (C′ + D) A′ + B′ + C + C 1
the expression ((A + B′ ) + CD′ ) ′
1 A Nibble consists of bits 2 4 8 16 B 1
1 Excess-8 code assigns to “-8” 1110 1100 1000 0000 D 1
1 NOT, NOR, NOT, OR,
The three fundamental gates are AND, NAND, XOROR, AND, NAND D 1
XOR AND
1 The size of
the address
The total amount of memory that is supported by any digital system depends The organization The structure of The size of
bus of the D 1
upon of memory memory decoding unit
microproces
sor
1 Addition of two octal numbers “36” and “71” results in 213 123 127 345 C 3
1 Base 10
In which of the following base systems is 123 not a valid number? Base 16 Base8 Base 3 D 1
1 1000
Storage of 1 KB means the following number of bytes 964 1024 1064. D 2
1 What is the octal equivalent of the binary number:
10111101 675 275 572 573. B 1

1 10101.001
The binary code of (21.125)10 is 10100.001 10101.010 10100.111 A 1
1 all the
minization
many digital
any logic function techniques are
it is used by computers
A NAND gate is called a universal logic element because can be realized by applicable for B 1
everybody use NAND
NAND gates alone optimum
gates.
NAND gate
realization
1
useful over
Digital computers are more widely used as compared to analog computers, less expensive always more easier to
wider ranges of C 1
because they are accurate and faster maintain.
problem types
1 it is not
possible to
floating point of no
it is slower than perform
Most of the digital computers do not have floating point hardware because hardware is costly specific A 1
software floating point
reason.
addition by
hardware
1 FFFF (hex) All of the
The number 1000 would appear just immediately after 1111 (binary) 7777 (octal) above. D 1
1
(1(10101)2 is (37)10 ( 69)10 (41 )10 — (5)10 A 1

1 The number of Boolean functions that can be generated by n variables is equal n

2 22 n 2n-1 — 2n B 1
to
1 Consider the representation of six-bit numbers by two’s complement, one’s
Two’s
complement, or by sign and magnitude: In which representation is there
Sign and magnitude complement All three
overflow from Two’s
and one’s and one’s representatio D 2
the addition of the integers 011000 and 011000? complement only
complement only complement ns.
only

1 logic 0
logic 0 and 1 are logic 0 and, -1 are
logic 0 voltage voltage level
represented by 0 represented by
level is higher is lower than
Positive logic in a logic circuit is one in which and positive negative and D 1
than logic 1 logic 1
voltage positive voltages
voltage level voltage
respectively respectively
level.
1 OR gate EXCLUSIVE
Which of the following gate is a two-level logic gate NAND gate NOT gate. C 1
OR gate
1 all the inputs
all the inputs to the and outputs
either of the
An AND gate will function as OR if gates are “1” all the inputs are ‘0’ are D 1
inputs is “1”
complement
ed.
1 An OR gate has 6 inputs. The number of input words in its truth table are 6 32 64 128 C 1
1

provide
have lower consume least
can be used to maximum
NAND. gates are preferred over others because these fabrication area electronic B 1
make any gate density in a
power
chip.

1 1 at any input 0 any input 0 at any

causes the output
In case of OR gate, no matter what the number of inputs, a causes the output to causes the input causes A 1
to be at logic 1
be at logic 0 output to be at the output to
1 Weighted code Cyclic redundancy Self- Algebraic C 1
1 Indicate which of the following three binary additions are correct?
1.1011 + 1010 = 10101
II. 1010 + 1101 = 10111 I and II II and III III only II and I D 3
III. 1010 + 1101 = 11111

1 X=X–Y+1
X – = Y + 1 means X = –X – Y – 1 X = –X + Y + 1 X= X – Y – A 1
1 A binary digit is called a Bit Byte Number Character A 1
1 22.0
What is decimal equivalent of BCD 11011.1100 ? 22.2 20.2 21.2 B 1
1 The ASCII code for letter A is 1100011
1111111 1000001 0010011 C 1
1 1100
The Gray code for decimal number 6 is equivalent to 1001 0101 0110 C 1
1 The decimal equivalent of hex number 1A53 is 6793
6739 6973 6379 B 1
Unit No:-2 Logic Families
2 Transistor is a Current controlled Current controlled Voltage Voltage A 1
current device. voltage device. controlled controlled
current device. voltage
device.
2 A digital logic device used as a buffer should have what input/output high input D 2
characteristics? high input low input impedance
impedance and low input impedance and and low
high output impedance and high low output output
impedance output impedance impedance impedance
2 What is the standard TTL noise margin? 5.0 V 0.2 V 0.8 V 0.4 V D 2
2 0.0 V to 2.8 B 2
The range of a valid LOW input is: 0.0 V to 0.4 V 0.4 V to 0.8 V 0.0 V to 1.8 V V
2 When an IC has two rows of parallel connecting pins, the device is referred to a QFP a DIP CMOS B 1
as: a phase splitter
2 Which digital IC package type makes the most efficient use of printed circuit SMT TO can flat pack DIP A 1
board space?
2 The digital logic family which has minimum power dissipation is TTL RTL DTL CMOS D 2
2 Which of the following is the fastest logic TTL ECL CMOS LSI B 2
2 The digital logic family which has the lowest propagation delay time is ECL TTL CMOS PMOS A 2
2 Which TTL logic gate is used for wired ANDing Open collector Totem Pole Tri state output ECL gates A 2
output
2 CMOS circuits consume power Equal to TTL Less than TTL Twice of TTL Thrice of B 2
TTL
2 In a positive logic system, logic state 1 corresponds to positive voltage higher voltage level zero voltage lower B 1
level voltage level

2 The commercially available 8-input multiplexer integrated circuit in the TTL 7495 74153 74154 74151 B 2
family is
2 The logic 0 level of a CMOS logic device is approximately 1.2 volts 0.4 volts 0volts 5volts C 2
2 Which ofthe following is a universal logic gate? OR XOR AND NAND D 1
2 VOH – VOL greater of VDD – smaller of VIL VIH – VIL. C 2
How is the noise margin of a logic family VOH and VOL – – VOL and
defi ned? GND VOH – VIH
2 What parameter causes the main limit d.c. input current output current input power A 2
on fan-out of CMOS logic in high-speed capacitance supply
applications? voltage.
2 The number of standard loads that the output of the gate can drive Fan-in Fan-Out noise-margin power- B 2
with out impairment of its normal operation is dissipiation
2 A NAND gate is called a universal logic element because it is used by any logic function all the many digital B 2
everybody can be realized by minization computers
NAND gates alone techniques are use NAND
applicable for gates.
optimum
NAND gate
realization
2 Measure of power consumed by the gate when fully driven by all Fan-in Fan-Out noise-margin power- D 2
its inputs is dissipiation
2 Fan-out is specified in terms of voltage current watt unit load D 2
2 Which of the following logic family has highest fan-out DTL CMOS RTL TTL B 2
2 Which of following consume minimum power TTL RTL DTL CMOS D 1
2 Among the logic families, low power dissipation is in DTL CMOS RTL TTL B 1
2 The temperature in which the performance of the IC is effective Operating Fan-Out Normal power- A 1
2 The nominal value of the dc supply voltage for TTL (transistor-transistor logic) 0v 5v 10v 15v B 1
devices is
2 The average transition delay time for the signal to propagate from Propogation Delay Fan-Out noise-margin power- A 2
input to output when the signals change in value. It is expressed in ns is dissipiation

2 the number of inputs connected to the gate without any degradation in the Propogation Delay Fan-Out Fan- in power- C 2
voltage level. dissipiation
2 Which of the following logic gives the complementary outputs? ECL TTL CMOS PMOS A 2
2 The maximum noise voltage added to an input signal of a digital circuit that Fan-in Fan-Out noise-margin power- C 2
2 Among the logic families, Slowest logic family is TTL RTL DTL CMOS D 1
2 Operating temperature of the IC vary from 0 to70 celsius 0to35celsius 0to 50celsius 0to70celsius A 1
2 1. Open collector output 2. Totem-Pole Output 3. Tri-state output are the type TTL LOGIC RTL LOGIC CMOS LOGIC None of this A 1
of
2 If the channel is initially doped lightly with p-type impurity a conducting Depletion mode Enhancement mode Both Mode None of this A 1
2 If the region beneath the gate is left initially uncharged the gate field must Depletion mode Enhancement mode Both Mode None of this B 2
induce a operation MOS operation of MOS
channel before current can flow. Thus the gate voltage enhances the channel
current and sucha device is said to operate in the
2 The n- channel MOS conducts when its gate- to- source gate- to- source gate- to- source None of this A 2
voltage is positive. voltage is negative voltage is zero.
2 The p- channel MOS conducts when its gate- to- source gate- to- source gate- to- source None of this C 2
2 The fan-out of a MOS-logic gate is higher than that of TTL gates because of its low input high input low output high output D 2
impedance impedance impedance impedance

2 Which factor does not affect CMOS loading? Charging time Discharging time Output Input C 2
associated with the associated with the capacitance of capacitance
2 Logic gates are the basic elements that make a Analog system Basic System gating system digital D 1
system
2 Which of the following gate is a two-level logic gate OR gate NAND gate EXCLUSIVE C 1
OR gate
NOT
2 Among the logic families, the family which can be used at very high frequency TTLAS CMOS ECL TTLLS C 1
greater than 100 MHz in a 4 bit

2 NAND. gates are preferred over others because these have lower can be used to consume least provide B 2
fabrication area make any gate electronic maximum
power density in a
chip.

2 The fan Out of a 7400 NAND gate is 2TTL 5TTL 8TTL 10TTL D 2

2 Which transistor element is used in CMOS logic? FET MOSFET Bipolar Unijunction B 2
2 CMOS circuits are extensively used for ON-chip computers mainly because of low power high noise large packing low cost. C 2
their extremely dissipation. immunity. density.
2 Which equation is correct? VNL = VIL(max) VNH = VOH(min) VNL = VNH = D 2
+ VOL(max) + VIH(min) VOH(min) – VOH(min) –
VIH(min) VIH(min)
2 The greater the propagation delay, the lower the higher the maximum minimum A 2
maximum maximum frequency is frequency is
frequency frequency unaffected unaffected

2 For a CMOS gate, which is the best speed-power product? 1.4 Pj 1.6 pJ 2.4 pJ 3.3 pJ A 2
2 In a TTL circuit, if an excessive number of load gate inputs are connected, VOH(min) drops VOH drops below VOH exceeds VOH and B 2
below VOH VOH(min) VOH(min) VOH(min)
are
unaffected
2 Which is not a MOSFET terminal? Gate Drain Source Base D 2
2 An open-drain gate is the CMOS counterpart of an open-collector a tristate TTL gate a bipolar an emitter- A 2
TTL gate junction coupled
transistor logic gate
2 The active switching element used in all TTL circuits is the bipolar junction field-effect metal-oxide unijunction A 2
transistor (BJT transistor (FET semiconductor transistor
field-effect (UJ)
transistor
(MOSFET
2 One output structure of a TTL gate is often referred to as a JBT arrangement totem-pole base, emitter, C 2
arrangement collector
arrangement

diode
2 An open-collector output requires a pull-down a pull-up resistor no output an output B 2
resistor resistor resistor
2 Which is not an output state for tristate logic? HIGH LOW High-Z Low-Z D 2
2 TTL is alive and well, particularly in industrial millitary educational commerciala C 2
applications applications applications pplications
2 A TTL NAND gate with IIL(max) of –1.6 mA per input drives eight TTL –12.8 Ma –8 mA –1.6 mA –25.6 mA A 4
inputs. How much current does the drive output sink?
2 A standard TTL circuit with a totem-pole output can sink, in the LOW state 16 Ma 20 mA 24 Ma 28mA A 4
(IOL(max)),
2 It is best not to leave unused TTL inputs unconnected (open) because of TTL's noise sensitivity low-current open-collector tristate A 2
requirement outputs construction

2 Which logic family combines the advantages of CMOS and TTL? BiCMOS TTL/CMOS ECL TTL/MOS A 2
2 Which is not part of emitter-coupled logic (ECL)? Differential Bias circuit Emitter- Totem-pole D 2
amplifier follower circuit circuit
2 PMOS and NMOS circuits are used largely in MSI functions LSI functions diode functions TTL B 2
functions
2 The nominal value of the dc supply voltage for TTL and CMOS is 3V 5V 10 V 12 V B 2
2 If ICCH is specified as 1.1 mA when VCC is 5 V and if the gate is in a static 5.5 Mw 5mW 5.5 W 1.1mW A 4
(noncharging) HIGH output state, the power dissipation (PD) of the gate is

2 The switching speed of CMOS is now competitive with three times that of slower than twice that of A 2
TTL TT TTL TTL

2 One advantage TTL has over CMOS is that TTL is less expensive not sensitive to faster more widely B 2
electrostatic available
discharge
2 TTL operates from a 9-volt suppl 3-volt supply 12-volt supply 5-volt supply D 1

2 A CMOS IC operating from a 3-volt supply will consume less power than a more power than a the same power no power at A 2
TTL IC TTL IC as a TTL IC all

2 CMOS IC packages are available in DIP configuration SOIC configuration DIP and SOIC None of this C 2
configurations
2 The terms "low speed" and "high speed," applied to logic circuits, refer to the rise time fall time propagation clock speed C 2
delay time

2 The power dissipation, PD, of a logic gate is the product of the dc supply voltage dc supply voltage ac supply ac supply B 2
and the peak and the average voltage and the voltage and
2 How many different logic level ranges for TTL 1 2 3 4 D 1
2 Metal-oxide semiconductor field-effect transistors (MOSFETs) are the active CMOS circuits TTL ECL circuits
PMOS A 2
switching elements in circuits
2 ECL IC technology is……………….than TTL technology. faster slower equal none of this A 1
2 A major advantage of ECL logic over TTL and CMOS is low power high speed both low power neither low B 1
dissipation dissipation and power
high speed dissipation
nor high
speed
2 Digital technologies being used now-a-days are DTL and EMOS TTL, ECL, CMOS TTL, ECL, TTL, ECL, B 2
and RTL CMOS and CMOS and
DTL DTL
2 Which of the following is the fastest logic TTL ECL CMOS PMOS B 2
2 Which TTL logic gate is used for wired ANDing Open collector Totem Pole Tri state output ECL gates A 2
output
2 CMOS circuits consume power Equal to TTL Less than TTL Twice of TTL Thrice of B 1
TTL
2 CMOS circuits are extensively used for ON-chip computers mainly because of low power high noise large packing low cost. C 2
their extremely dissipation immunity density
2 The MSI chip 7474 is Dual edge Dual edge triggered Dual edge Dual edge C 2
triggered JK flip- D flip-flop triggered D flip- triggered JK
flop (TTL). (CMOS). flop (TTL). flip-flop
(CMOS).
2 The logic 0 level of a CMOS logic device is approximately 1.2 volts 0.4 volts 5 volts 0 volts D 2
2 These devices use The gate transistors The S denotes The S A 4
Schottky are silicon (S), and the fact that a denotes a
What is unique about TTL devices such as the 74SXX? transistors and the gates therefore single gate is slow version
diodes to prevent have lower values present in the of the
them from going of leakage current. IC rather than device,
into saturation; this the usual which is a
results in faster package of 2–6 consequence
turn-on and turn- gates. of its higher
off times, which power
translates into rating.
higher frequency
operation.

2 Which of the following logic families has the shortest propagation delay? CMOS BiCMOS ECL 74SXX C 1
2 Why must CMOS devices be handled with care? so they don’t get because they break because they all of above C 2
dirty easily can be damaged
by static
electricity
discharge

2 What should be done to unused inputs on TTL gates? They should be left All unused gates All unused Unused D 2
disconnected so as should be inputs should AND and
not to produce a connected together be connected to NAND
load on any of the and tied to V an unused inputs
other circuits and through a 1 k output; this will should be
to minimize power resistor. ensure tied to VCC
loading on the compatible through a 1 k
voltage source. loading on both resistor;
the unused unused OR
inputs and and NOR
unused outputs. inputs
should be
grounded.
2 Assume that a particular IC has a supply voltage (Vcc) equal to +5 V and 50 Mw 82.5 mW 115 mW 165 mW B 4
ICCH = 10 mA and ICCL = 23 mA. What is the power dissipation for the
chip?
2 Can a 74HCMOS logic gate directly connect to a 74ALSTTL gate? YES No A 1
2 What is the major advantage of ECL logic? very high speed wide range of very low cost very high A 2
operating voltage power
2 As a general rule, the lower the value of the speed–power product, the better
long propagation long propagation Both none of B 2
the device because of its: delay and high delay and low above
power power consumption
consumption
2 What is the difference between the 54XX and 74XX series of TTL logic gates? 54XX is faster. 54XX is slower. 54XX has a 54XX has a C 2
wider power narrower
supply and power
expanded supply and
temperature contracted
range. temperature
range.
2 What is the range of invalid TTL output voltage? 0.0–0.4 V 0.4–2.4 V 2.4–5.0 V 0.0–5.0 V B 2
2 An open collector output can current, but it cannot . sink, source source, sink current sink, source source, sink A 2
current voltage voltage
2 Why is a decoupling capacitor needed for TTL ICs and where should it be to block dc, to reduce noise, to reduce the NONE OF C 2
connected connect to input connect to input effects of noise, ABOVE
pins pins connect
between power
supply and
ground
2 Which of the following summarizes the important features of emitter-coupled low noise margin, good noise low poor noise A 2
logic (ECL)? low output voltage immunity, negative propagation immunity,
swing, negative logic, high- time, high- positive
voltage operation, frequency frequency supply
fast, and high capability, low response, low voltage
power power dissipation, power operation,
consumption and short consumption, good low-
propagation time and high output frequency
voltage swings operation,
and low
power
2 Why is a pull-up resistor needed for an open collector gate? to provide Vcc for to provide ground to provide the to provide C 2
the IC for the IC HIGH voltage the LOW
voltage
2 Why is a pull-up resistor needed when connecting TTL logic to CMOS logic? to increase the to decrease the to increase the to decrease C 2
output LOW output LOW output HIGH the output
voltage voltage voltage HIGH
voltage
2 The word "interfacing" as applied to digital electronics usually means: a conditioning a circuit connected any gate that is any TTL B 2
circuit connected between the driver a TTL circuit that is
between a standard and load to operational an input
TTL NAND gate condition a signal amplifier buffer stage
and a standard so that it is designed to
TTL OR gate compatible with the condition
load signals between
NMOS
transistors

2 The rise time (tr) is the time it takes for a pulse to rise from its point 10%, 90%, 90%, 90%, 10%, 10%, 20%, 80%, 10%, 70.7%, A 4
up to its point. The fall time (tf) is the length of time it takes to fall 10% 90% 80%, 20% 70.7%, 10%
from the to the point.
2 The term buffer/driver signifies the ability to provide low output currents to TRUE FALSE B 2
drive light loads.
2 PMOS and NMOS . represent are enhancement- represent None of the A 4
MOSFET devices type CMOS devices positive and above
utilizing either P- used to produce a negative MOS-
channel or N- series of high-speed type devices,
channel devices logic known as which can be
exclusively within 74HC operated from
a given gate differential
power supplies
and are
compatible with
operational
amplifiers

2 Why is the operating frequency for CMOS devices critical for determining At low At high At high At high C 2
power dissipation? frequencies, At frequencies, the frequencies, frequencies,
low frequencies, gate will only be charging and the gate will
power dissipation able to deliver 70.7 discharging the only be able
increases. % of rated power. gate to deliver
capacitance will 70.7 % of
draw a heavy rated power
current from the and charging
power supply and
and thus discharging
increase power the gate
dissipation. capacitance
will draw a
heavy
current from
the power
supply and
thus increase
power
dissipation.

2 Ten TTL loads per TTL driver is known as: noise immunity fan-out power propagation B 2
dissipation delay
2 The problem of different current requirements when CMOS logic circuits are a CMOS a TTL tristate a CMOS a CMOS D 4
driving TTL logic circuits can usually be overcome by the addition of: inverting bilateral inverting buffer noninverting buffer or
switch between the between the stages bilateral switch inverting
stages between the buffer
stages
2 can, in parallel, cannot, together, if should, in can, B 4
sometimes higher the outputs are in series, certain together,
Totem-pole outputs be connected because . current is required opposite states applications together they
excessively high may require can handle
currents can higher output larger load
damage one or both voltage currents and
devices higher
output
voltages

2 The high input impedance of MOSFETs: allows faster reduces input prevents dense creates low- B 2
switching current and power packing noise
dissipation reactions
2 The output current capability of a single 7400 NAND gate when HIGH is source current sink current IOH source A 2
called current of
IOH
2 The time needed for an output to change from the result of an input change is noise immunity fan-out propagation rise time C 2
known as: delay
2 The problem of interfacing IC logic families that have different supply voltages Level-shifter tristate shifter decoupling pull-down A 2
(VCC's) can be solved by using a: capacitor resistor
2 What is the advantage of using low-power Schottky (LS) over standard TTL more power less power cost is less cost is more B 2
logic? dissipation dissipation
2 When is a level-shifter circuit needed in interfacing logic? A level shifter is A level shifter is when the when the D 2
always needed. never needed. supply voltages supply
are the same voltages are
different
2 A TTL totem-pole circuit is designed so that the output transistors: are always on provide linear provide voltage are never on D 2
together phase splitting regulation together

2 The most common TTL series ICs are: E-MOSFET 7400 QUAD AC00 B 1
2 Which family of devices has the characteristic of preventing saturation during TTL ECL MOS IIL B 2
operation?
2 How many 74LSTTL logic gates can be driven from a 74TTL gate? 10 20 30 40 B 2
2 What is the difference between the 74HC00 series and the 74HCT00 series The HCT series is The HCT series is he HCT series The HCT C 4
of CMOS logic? faster. slower. is input and series is not
output voltage input and
compatible with output
TTL. voltage
compatible
with TTL.
2 Why are the maximum value of VOL and the minimum value of VOH used to These are worst- These are normal These are best- It doesn't A 2
determine the noise margin rather than the typical values for these parameters? case conditions. conditions. case conditions. matter what
values are
used.

2 What is the standard TTL noise margin? 5.0 V 0.0 V 0.8 V 0.4 V D 2
2 Which logic family is characterized by a multiemitter transistor on the input? ECL CMOS TTL None of the C 2
above
2 he problem of the VOH(min) of a TTL IC being too low to drive a CMOS adding a fixed avoiding this adding an adding an D 4
circuit and meet the CMOS requirement of VIH(min) is usually easily voltage-divider condition and only external pull- external pull-
overcome by: bias resistive using TTL to drive down resistor to up resistor to
network at the TTL ground VCC
output of the TTL
device
2 How does the 4000 series of CMOS logic compare in terms of speed and more power more power less power less power D 2
power dissipation to the standard family of TTL logic? dissipation and dissipation and dissipation and dissipation
slower speed faster speed faster speed and slower
speed
2 What should be done with unused inputs to a TTL NAND gate? let them float tie them LOW tie them HIGH None of the C 2
above
2 Which of the following logic families has the highest maximum clock S-TTL AS-TTL HS-TTL HCMOS B 2
frequency?
2 Why is the fan-out of CMOS gates frequency dependent? Each CMOS input When the The higher the The input D 4
gate has a specific frequency reaches number of gates gates of the
propagation time the critical value, attached to the FETs are
and this limits the the gate will only output, the predominant
number of be capable of more frequently ly capacitive,
different gates that delivering 70% of they will have and as the
can be connected the normal output to be serviced, signal
to the output of a voltage and thus reducing frequency
CMOS gate. consequently the the frequency at increases the
output power will which each will capacitive
be one-half of be serviced loading also
normal; this defines with an input increases,
the upper operating signal. thereby
frequency. limiting the
number of
loads that
may be
attached to
the output of
the driving
gate.

2 What must be done to interface TTL to CMOS? A dropping As long as the A 5 V Zener A pull-up D 2
resistor must be CMOS supply diode must be resistor must
used on the CMOS voltage is 5 V, they placed across be used
12 V supply to can be interfaced; the inputs of the between the
reduce it to 5 V for however, the fan- TTL gates in TTL output-
the TTL. out of the TTL is order to protect CMOS input
limited to five them from the node and
CMOS gates. higher output Vcc; the
voltages of the value of RP
CMOS gates. will depend
on the
number of
CMOS gates
connected to
the node.
2 What causes low-power Schottky TTL to use less power than the 74XX series The Schottky- Nothing. The 74XX A larger value Using C 2
TTL? clamped transistor series uses less resistor NAND gates
power.
2 What are the major differences between the 5400 and 7400 series of ICs? The 5400 series The 5400 series are The 7400 The 7400 B 2
are military grade military grade and series are an series was
and require tighter allow for a wider improvement originally
supply voltages range of supply over the developed
and temperatures. voltages and original 5400s. by Texas
temperatures. Instruments.
The 5400
series was
brought out
by National
Semiconduct
ors after TI's
patents
expired, as a
second
supply
2 Which of the following statements apply to CMOS devices? The devices should All tools, test The devices All of the D 2
not be inserted into equipment, and should be above.
circuits with the metal workbenches stored and
power on. should be tied to shipped in
earth ground. antistatic tubes
or conductive
foam.

2 Which of the logic families listed below allows the highest operating 74AS ECL HCMOS 54S B 2
frequency?
2 What is the increase in switching speed between 74LS series TTL and 5 10 50 100 B 2
74HC/HCT (High-Speed CMOS)?
2 What does ECL stand for? electron-coupled emitter-coupled energy-coupled NONE OF B 2
logic; logic; logic; ABOVE
2 What is unique about TTL devices such as the 74S00? The gate The S denotes the The S denotes a The devices D 4
transistors are fact that a single slow version of use Schottky
silicon (S), and the gate is present in the device, transistors
gates therefore the IC rather than which is a and diodes
have lower values the usual package consequence of to prevent
of leakage current. of 2–6 gates. its higher power them from
rating. going into
saturation;
this results
in faster turn
on and turn
off times,
which
translates
into higher
frequency
operation.

2 he bipolar TTL logic family that was developed to increase switching speed by emitter-coupled current-mode logic transistor- emitter- D 2
preventing transistor saturation is: logic (ECL). (CML). transistor logic coupled
(TTL). logic (ECL)
and
transistor-
transistor
logic (TTL).
2 In TTL the noise margin is between 0.4 V and 0.8 V. 0.0 V and 0.4 V. 0.0 V and 0.5 0.0V and 0.8 A 2
V. V.
2 What is the transitive voltage for the voltage input of a CMOS operating from 1V 5V 10V 15V B 2
10V supply
2 The highest noise margin is offered by CMOS TTL ECL BICMOS B 2
2 What is the transitive voltage for the voltage input of a CMOS operating from 1V 5V 10V 20V B 2
10V supply ?
2 The digital logic family which has the lowest propagation delay time is ECL TTL CMOS PMOS A 2
2 In a positive logic system, logic state 1 corresponds to Positive voltage Higher voltage Zero voltage Lower B 2
level level voltage level

2 Which of the following logic families is well suited for high-speed operations ? TTL ECL MOS CMOS B 2

2 Which of the following is the fastest logic? ECL TTL MOS CMOS A 1
2 he digital logic family which has the lowest propagation delay time is ECL TTL CMOS PMOS c 2
2 A binary digit is called a Bit Byte Number Character A 1
2
2 Which of the following statements is wrong ? Propagation delay Noise immunity is Fan-in of a Operating C 4
is the time required the amount of noise gate is always speed is the
for a gate to which can be equal to fan-out maximum
change its state applied to the input of the same gate frequency at
of a gate without which digital
causing the gate to data can be
change state applied to a
gate

2 Which table shows the logical state of a digital circuit output for every possible Function table Truth table Routing table ASCII table B 1
combination of logical states in the inputs ?

2 The digital logic family which has minimum power dissipation is TTL ECL MOS CMOS D 1
UNIT NO:- 3 COMBINATIONAL LOGIC
3 In the following question, match each of the items A, B and C on the left with ABC A B C A B C ABC B 4
an approximation item on the right
A. Shift register can be used 1. for code conversion 123 3 4 1 5 4 2 135
B. A multiplexer can be used 2. to generate memory slipto select
C. A decoder can be used 3. for parallel to serial conversion
4. as many to one switch
5. for analog to digital conversion

3 A standard SOP form has terms that have all the variables in the SUM SUB Mult DIV A 1
domain of the expression.
3 How many data select lines are required for selecting eight inputs? 1 2 3 4 C 2
3 Half adder circuit is ? Half of an AND A circuit to add Half of a none of B 2
gate two bits together NAND gate above
3 The full adder adds the Kth bits of two numbers to the difference of the sum of all previous carry from ( K - sum of C 2
previous bits bits 1 )TH bit previous bit

3 The number of two input multiplexers required to construct a 210 input 31 10 127 1023 D 2
multiplexer is,
3 A small dot or circle printed on top of an IC indicates Vcc Gnd Pin 14 Pin 1 D 1

3 Which of the following adders can add three or more numbers at a time ? Parallel adder Carry-look-ahead Carry-save- Full adder B 2
adder adder

D.
3 An AND circuit is a memory gives an output is a -ve OR is a linear B 2
circuit when all input gate circuit
signals are present
simultaneously

3 What are the three output conditions of a three-state buffer? HIGH, LOW, float 1, 0, float both of the neither of C 2
above the above
3 When is it important to use a three-state buffer? when two or more when all outputs when all when two or A 2
outputs are are normally HIGH outputs are more outputs
connected to the normally LOW are
same input connected to
two or more
inputs
3 The device which changes from serial data to parallel data is COUNTER MULTIPLEXER DEMULTIPLE FLIP-FLOP C 2
XER
3 A device which converts BCD to Seven Segment is called MULTIPLEXER DEMULTIPLEXE ENCODER DECODER D 2
R
3 How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? 1 2 4 8 C 2
3 A device which converts BCD to Seven Segment is called Encoder Decoder Multiplexer Demultiplex B 2
er
3 A multiplexer is a logic circuit that accepts one input accepts many inputs accepts many accepts one C 2
and gives several and gives many inputs and gives input and
output output one output gives one
output
3 In order to implement a n variable switching function, a MUX must have 2n inputs 2n+1 inputs 2n-1 inputs 2n-1 inputs A 2
3 Logic gates with a set of input and outputs is arrangement of Combinational Logic circuit Design circuits Register A 2
circuit
3 A latch is constructed using two cross-coupled AND and OR AND gates NAND and NAND gates D 2
gates NOR gates
3 A combinational logic circuit which sends data coming from a single source to Decoder Encoder Multiplexer Demultiplex D 2
two or more separate destinations is er
3 Data can be changed from special code to temporal code by using Shift registers Counters Combinational A/D A 2
circuits converters
3 A device which converts BCD to Seven Segment is called Encoder Decoder Multiplexer Demultiplex
er
3 The gray code equivalent of (1011)2 is 1101 1010 1110 1111 B 2
3 Odd parity of word can beconveniently tested by OR gate AND gate NOR gate XOR gate D 2

3 Which one of the following will give the sum of full adders as output ? Three point Three bit parity Three bit Three bit D 2
majority circuit checker comparator counter

3 The number of full and half-adders required to add 16-bit numbers is 4 half- B 2
8 half-adders, 8 1 half-adder, 15 full 16 half-adders, adders, 12
full-adders adders 0 full-adders full-adders

3 A one-to-four line demultiplexer is to be implemented using a memory. How 1 bit 2 bits 4 bits 8 bits A 2
many bits must each word have ?

3 What logic function is produced by adding an inverter to the output of an AND NAND NOR XOR OR A 1
gate ?

3 A demultiplexer is used to Route the data Select data from Perform serial All of these A 1
from single input several inputs and to parallel
to one of many route it to single conversion
outputs output

3 How many full adders are required to construct an m-bit parallel adder ? m/2 m-1 m m+1 B 1

3 Parallel adders are combinational sequential logic both (a) and None of B 1
logic circuits circuits (b) these
3 The digital multiplexer is basically a combination logic circuit to perform the AND-AND OR-OR AND-OR OR-AND C 2
operation

3 How many lines the truth table for a four-input NOR gate would contain to 4 8 12 16 D 2
cover all possible input combinations ?

3 How many truth tables can be made from one function table ? 1 2 3 ANY NO B 2

3 A comparison between serial and parallel adder reveals that serial order is slower is faster operates at the is more A 2
same speed as complicated
parallel adder

3 What is the largest number of data inputs which a data selector with two 2 4 6 8 B 1
control inputs can have ?

3 If a logic gates has four inputs, then total number of possible input 4 8 16 32 C 1
combinations is

3 If a logic gates has four inputs, then total number of possible input input input combination input present A 2
combinations is combination at the and the previous combination at output and
time output that time and the previous
the previous output
input
combination
3 A combinational logic circuit which generates a particular binary word or Decoder Multiplexer Encoder Demultiplex A 1
number is er

3 Which of the following circuit can be used as parallel to serial converter ? Multiplexer Demultiplexer Decoder Digital A 2
counter

3 In which of the following adder circuits, the carry look ripple delay is Half adder Full adder Parallel Carry-look- C 2
eliminated ? adder ahead adder

3 Adders adds 2 bits is called so needs two All of these D 2

because a full adder input and
involves two half- generates two
adders output

3 Weighted code Cyclic redundancy Self- Algebraic C 1

code complementin code.
g code
Excess-3 code is known as
3 The number of control lines for 32 to 1 multiplexer is 4 16 5 6 C 2

3 The selector inputs to an arithmetic-logic unit (ALU) determine the: selection of the IC arithmetic or logic data word clock B 2
function selection frequency to
be used
3 What are the two types of basic adder circuits? half adder and half adder and asynchronous one's A 2
full adder parallel adder and complement
synchronous and two's
complement
3 The inverter OR-gate and AND gate are called deeision-making elements words,high bytes,low bytes,high character,lo A 2
because they can recognize some input while disregarding others. A gate w
3 Which one of the following set of gates are best suited for 'parity' checking and AND, OR, NOT EX-NOR or EX- NAND gates NOR gates B 2
'parity' generation. gates OR gates

3 What are the three output conditions of a three-state buffer? HIGH, LOW, float 1, 0, float both of the neither of C 2
above the above
3 When is it important to use a three-state buffer? when two or when all outputs when all when two or A 2
more outputs are are normally HIGH outputs are more outputs
connected to the normally LOW are
same input connected to
two or more
inputs
3 How many inputs are required for a 1-of-10 BCD decoder? 4 8 10 1 A 1
Most demultiplexers facilitate which of the following?
decimal to single input, odd parity to
3 ac to dc B 1
hexadecimal multiple outputs even parity
One application of a digital multiplexer is to facilitate: parallel-to-
data
3 code conversion parity checking serial data C 1
generation
conversion
Select one of the following statements that best describes the parity method of best suited for
error detection: detecting double-bit
best suited for
detecting single- errors that occur NONE OF
3 bit errors in during the A AND B THE A 2
transmitted transmission of ABOVE
codes. codes from one
location to another.
A multiplexed display: accepts data
accepts data inputs from
accepts data inputs
uses one display to inputs from several lines
from one line and
present two or multiple lines and
3 passes this data to B 1
more pieces of and passes this multiplexes
multiple output
information data to multiple this input
lines
output lines data to four
BCD lines
In which of the following gates, the output is 1, if and only if at least one input
3 NOR AND OR NAND C 1
is 1?
The time required for a gate or inverter to change its state is called Rise time Propagation Charging
3 Decay time C 1
time time
The time required for a pulse to change from 10 to 90 percent of its maximum Rise time Propagation Operating
3 Decay time A 1
value is called time speed
The maximum frequency at which digital data can be applied to gate is called Binary level
Charging
3 Operating speed Propagation speed transaction A 1
time
period
What is the minimum number of two-input NAND gates used to perform the
3 one two three Four C 2
function of two input OR gate ?
Odd parity of word can beconveniently tested by XOR gate
3 OR gate AND gate NOR gate D 1
 Which one of the following will give the sum of full adders as output ? Three point Three bit parity Three bit Three bit
3 D 1
majority circuit checker comparator counter
The number of full and half-adders required to add 16-bit numbers is 4 half-
8 half-adders, 8 1 half-adder, 15 16 half-adders,
3 adders, 12 B 1
full-adders full-adders 0 full-adders
full-adders
The time required for a pulse to decrease from 90 to 10 per cent of its Binary level
Propagation
3 maximum value is called Rise time Decay time transition B 1
delay
period
Which of the following gates would output 1 when one input is 1 and other
3 input is 0 ? OR gate AND gate NAND gate AND gate D 1

Which of the following statements is wrong ? Operating

Noise immunity is speed is the
Propagation delay the amount of noise Fan-in of a gate maximum
is the time required which can be is always equal frequency at
3 for a gate to applied to the input to fan-out of the which digital C 1
change its state of a gate without same gate data can be
causing the gate to applied to a
change state gate

3 Which of the following expressions is not equivalent to X ' ? X NAND X X NOR X X NAND 1 X NOR 1 D 1
Which of the following gates are added to the inputs of the OR gate to convert
3 it to the NAND gate ? NOT AND OR XOR A 1

The EXCLUSIVE NOR gate is equivalent to which gate followed by an

3 OR gate AND NAND XOR D 1
inverter ?
A one-to-four line demultiplexer is to be implemented using a memory. How
3 1 BIT 2 BITS 4 BITS 8 BITS A 1
many bits must each word have ?
What logic function is produced by adding an inverter to the output of an AND
3 gate ? NAND NOR XOR OR A 1

Which of the following gates is known as coincidence detector ? NAND

3 AND GATE OR GATE NOT GATE A 1
GATE
Which table shows the logical state of a digital circuit output for every possible
3 combination of logical states in the inputs ? Function table Truth table Routing table ASCII table B 1

3 A positive AND gate is also a negative NAND gate NOR gate AND GATE OR GATE D 1
A demultiplexer is used to Route the data Select data from
Perform serial
from single input several inputs and
3 to parallel All of these A 1
to one of many route it to single
conversion
outputs output
 An OR gate can be imagined as MOS
Switches Switches connected transistors None of
3 B 1
connected in series in parallel connected in these
series
Which combination of gates does not allow the implementation of an arbitrary OR gates and
OR gates and OR gates and NAND gates
3 boolean function? exclusive OR gate A 1
AND gates only NOT gates only only
only
How many full adders are required to construct an m-bit parallel adder ?
3 m/2 m-1 m m+1 B 2
Parallel adders are combinational sequential logic None of
3 both (a) and (b) A 1
logic circuits circuits these
The digital multiplexer is basically a combination logic circuit to perform the
3 AND-AND OR-OR AND-OR OR-AND C 1
operation
The output of NOR gate is High if only
High if all of its Low if all of its High if all of its
3 of its inputs C 1
inputs are high inputs are low inputs are low
is low
How many lines the truth table for a four-input NOR gate would contain to
3 4 8 12 16 D 1
cover all possible input combinations ?
A toggle operation cannot be performed using a single
3 NOR gate AND gate NAND gate XOR gate B 1
Which table shows the electrical state of a digital circuit's output for every
3 possible combination of electrical states in the inputs ? Function table Truth table Routing table ASCII table A 1

What is the minimum number of 2 input NAND gates required to implement

the function
3 6 5 4 3 C 1
F = (x'+y') (z+w)

How many truth tables can be made from one function table ? Any
3 One Two Three B 1
numbers
A comparison between serial and parallel adder reveals that serial order operates at the
is more
3 is slower is faster same speed as A 1
complicated
parallel adder
What is the largest number of data inputs which a data selector with two
3 2 4 8 16 B 1
control inputs can have ?
If a logic gates has four inputs, then total number of possible input
3 combinations is 4 8 16 32 C 1
 A combinational circuit is one in which the output depends on the input
combination at present
input combination
input combination that time and output and
3 and the previous A 1
at the time the previous the previous
output
input output
combination
The function of a multiplexer is
to select 1 out of N to perform
to decode input data sources to transit data serial to
3 B 1
information and to transmit it to on N lines parallel
single channel conversion
A combinational logic circuit which generates a particular binary word or Demultiplex
3 Decoder Multiplexer Encoder A 1
number is er
Which of the following circuit can be used as parallel to serial converter ? Digital
3 Multiplexer Demultiplexer Decoder A 1
counter
In which of the following adder circuits, the carry look ripple delay is Carry-look-
3 Half adder Full adder Parallel adder C 1
eliminated ? ahead adder
Adders Is called so because
needs two input
a full adder
3 adds 2 bits and generates All of these A 1
involves two half-
two output
adders
3 How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? 1 2 4 8 C 1
For the device shown here, let all D inputs be LOW, both S inputs be HIGH, Cannot be
3 LOW HIGH Don't Care A 1
and the input be LOW. What is the status of the Y output? determined
3 Convert BCD 0001 0010 0110 to binary. 1111110 1111000 1111101 1111111 A 2
3 Convert BCD 0001 0111 to binary. 10101 10001 10010 11000 C 2
3 How many data select lines are required for selecting eight inputs? 1 2 3 4 C 1
How many 1-of-16 decoders are required for decoding a 7-bit binary number?
3 5 6 7 8 D 1
The implementation of simplified sum-of-products expressions may be easily
implemented into actual logic circuits using all universal gates with
3 AND/OR NAND NOR OR/AND B 1
little or no increase in circuit complexity. (Select the response for the blank
space that will BEST make the statement true.)
Which of the following statements accurately represents the two BEST Boolean
Actual circuit
methods of logic circuit simplification? algebra and
Boolean algebra Karnaugh mapping trial and error
actual circuit
3 and Karnaugh and circuit evaluation and A 1
trial and
mapping waveform analysis waveform
error
analysis
evaluation
 Which of the following combinations cannot be combined into K-map groups?
Overlapping
Corners in the Corners in the same Diagonal
3 combination C 2
same row column corners
s
As a technician you are confronted with a TTL circuit board containing dozens
A defective IC A defective
of IC chips. You have taken several readings at numerous IC chips, but the A solar bridge An open input
chip that is output IC
readings are inconclusive because of their erratic nature. Of the possible faults between the inputs on the first IC
3 drawing excessive chip that has C 2
listed, select the one that most probably is causing the problem. on the first IC chip chip on the
current from the an internal
on the board board
power supply open to V cc
3 Which gate is best used as a basic comparator? NOR OR Exclusive-OR AND C 1
The device shown here is most likely a . parity
3 comparator multiplexer demultiplexer C 2
generator
For the device shown here, assume the D input is LOW, both S inputs are All but are All but are
3 All are HIGH. All are LOW. A 1
HIGH, and the input is HIGH. What is the status of the outputs? LOW. HIGH.
In VHDL, macrofunctions is/are: preprogram
a set of bit
3 digital circuits. analog circuits. med TTL D 1
vectors.
devices.
3 Which of the following expressions is in the product-of-sums form? (A + B )(C + D ) (AB )(CD ) AB (CD ) AB + CD A 2
Which of the following is an important feature of the sum-of-products form of The
expressions? maximum
No signal must number of
All logic circuits
pass through gates that
are reduced to The delay times are
more than two any signal
3 nothing more than greatly reduced A 1
gates, not must pass
simple AND and over other forms.
including through is
OR operations.
inverters. reduced by a
factor of
two.
An output gate is connected to four input gates; the circuit does not function.
Preliminary tests with the DMM indicate that the power is applied; scope tests
show that the primary input gate has a pulsing signal, while the interconnecting Logic
3 Current tracer Logic probe Oscilloscope A 1
node has no signal. The four load gates are all on different ICs. Which analyzer
instrument will best help isolate the problem?

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a
A > B = 1, A < B = A > B = 0, A < B =
3 comparator. What are the output levels?
0, A < B = 1 1, A = B = 0
A > B = 1, A < A > B = 0, A
B = 0, A = B = < B = 1, A = C 4
0 B=1
 A logic probe is placed on the output of a gate and the display indicator is dim. The dim
A pulser is used on each of the input terminals, but the output indication does The dim indication
indication is a The gate
not change. What is wrong? The output of the on the logic probe
result of a bad may be a
3 gate appears to be indicates that the A 1
ground tristate
open. supply voltage is
connection on device.
probably low.
the logic probe.
Each "1" entry in a K-map square represents: a DON'T
CARE
a HIGH for each
a HIGH output on a LOW output condition for
input truth table
the truth table for for all possible all possible
3 condition that A 1
all LOW input HIGH input input truth
produces a HIGH
combinations. conditions. table
output.
combination
s.
Looping on a K-map always results in the elimination of: variables within variables
variables within
the loop that within the
the loop that
variables that appear in both loop that
appear only in
3 remain unchanged complemented appear only C 2
their
within the loop. and in their
complemented
uncomplemente uncompleme
form.
d form. nted form.
What will a design engineer do after he/she is satisfied that the design will
Give the design
work?
Put it in a flow Program a chip and to a technician Perform a
3 B 2
chart test it to verify the vector test
design
What is the indication of a short on the input of a load gate? There is a
signal loss to
all gates on
The affected
Only the output of There is a signal the node,
node will be
3 the defective gate loss to all gates on and the D 1
stuck in the
is affected. the node. affected
LOW state.
node will be
stuck in the
LOW state.
In HDL, LITERALS is/are:
binary coded a numbering
3 digital systems. scalars. B 1
decimals. system.
3 Which of the following expressions is in the sum-of-products form? (A + B )(C + D ) (AB )(CD ) AB (CD ) AB + CD D 1
3 The carry propagation can be expressed as . Cp = AB Cp = A + B B 1
A decoder can be used as a demultiplexer by . using the
input lines
tying all data- for data
tying all enable tying all data-select
3 select lines selection and D 1
pins LOW lines LOW
HIGH an enable
line for data
input
How many 4-bit parallel adders would be required to add two binary numbers
3 1 2 3 4 C 1
each representing decimal numbers up through 30010?
Which statement below best describes a Karnaugh map? Karnaugh
Variable maps
A Karnaugh map The Karnaugh map complements provide a
can be used to eliminates the need can be visual
3 D 1
replace Boolean for using NAND eliminated by approach to
rules. and NOR gates. using Karnaugh simplifying
maps. Boolean
expressions.
A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW None. All
3 outputs. Which output goes LOW when the inputs are 1001? 0 3 9 outputs are C 1
HIGH.
A full-adder has a Cin = 0. What are the sum and the carry (Cout) when A = 1 = 1, Cout = = 1,
3 = 0, Cout = 0 = 0, Cout = 1 B 1
and B = 1? 0 Cout = 1
When adding an even parity bit to the code 110010, the result is .
3 1110010 110010 1111001 1101 A 1
Which of the following combinations of logic gates can decode binary 1101? One 4-input One 4-input
One 4-input AND One 4-input AND
3 NAND gate, AND gate, D 1
gate gate, one OR gate
one inverter one inverter
What is the indication of a short to ground in the output of a driving gate? The node may
The affected
Only the output of There is a signal be stuck in
node will be
3 the defective gate loss to all load either the HIGH B 1
stuck in the
is affected. gates. or the LOW
HIGH state.
state.
How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-
3 3 4 5 6 B 1
to-4-line encoder, have?
A half-adder does not have . all of the
3 carry in carry out two inputs A 1
above
is a correct combination for an ODD-parity data transmission data = 0001 data = 1010
data = 1101 1011 data = 1101 0010
3 system. 0101 1111 A 1
parity = 1 parity = 0
parity = 1 parity = 0
 A circuit that can convert one of ten numerical keys pressed on a keyboard to demultiplexe
3 priority encoder decoder multiplexer A 1
BCD is a . r
The prefix on IC's indicates a broader operating temperature range,
3 54 2N 74 TTL A 1
and the devices are generally used by the military.
When an open occurs on the input of a TTL device, the output will .
go HIGH, since still be good,
go LOW, because
react as if the open full voltage if only the
3 there is no current B 1
input were a HIGH appears across good inputs
in an open circuit
an open are used
The largest truth table that can be implemented directly with an 8-line-to-1-line
3 3 rows 4 rows 8 rows 16 rows C 1
MUX has .
Parity generation and checking is used to detect . when a
errors in binary
which of two errors in binary data
3 arithmetic in counter B 1
numbers is greater transmission
computers counts
incorrectly
3 Except for , STD_LOGIC may have the following values. 'z' 'U' '?' 'L' C 1
A gate that could be used to compare two logic levels and provide a HIGH
3 XOR gate XNOR gate NAND gate NOR gate B 1
output if they are equal is a(n) .
VHDL is very strict in the way it allows us to assign and compare LOGIC_VECTOR
3 objects designs arrays A 1
such as signals, variables, constants, and literals. S
The AND-OR-INVERT gates are designed to simplify implementation of DeMorgan's
3 POS logic NAND logic SOP logic B 1
. theorem
The output of a gate has an internal short; a current tracer will . be able to
show whether the probably not be
identify the identify the
3 gate is shorted to
able to locate A 1
defective gate defective
V cc or ground the problem
load node
Parity generators and checkers use gates. exclusive-
3 exclusive-AND exclusive-OR/NOR exclusive-OR B 1
NAND
The 7447A is a BCD-to-7-segment decoder with ripple blanking input and
test the
output functions. The purpose of these lines is to . turn off the display turn off the
display to
for any turn off the display display for
3 assure all A 1
nonsignificant for any zero leading or
segments are
digit trailing zeros
operational
One reason for using the sum-of-products form is that it can be implemented
3 NOR NAND AND DOOR B 1
using all gates without much difficulty.
When an open occurs on the input of a CMOS gate, the output will . be
go HIGH, since
go LOW, because unpredictabl
react as if the open full voltage
3 there is no current e; it may go D 2
input were a HIGH appears across
in an open circuit HIGH or
an open
LOW
 To subtract a signed number (the subtrahend) from another signed number (the never
complemented complemented only always
3 minuend) in the 2's complement system, the minuend is . complement D 2
only if it is positive if it is negative complemented
ed
In an odd-parity system, the data that will produce a parity bit = 1 is . All of the
3 data = 1010011 data = 1111000 data = 1100000 D 2
above
The addition of two signed numbers in the 2's complement system can cause have
have the same
3 overflow. For overflow to occur both numbers must . be positive be negative opposite C 2
sign
signs
A Karnaugh map will . give an
overall
eliminate the need allow any circuit to produce the
picture of
for tedious be implemented simplest sum-of-
3 how the A 2
Boolean with just AND and products
signals flow
simplifications OR gates expression
through the
logic circuit
An 8-bit binary number is input to an odd parity generator. The parity bit will the number
equal 1 only if . the number of 1s in the number is of 1s in the
3 the number is odd D 2
the number is odd even number is
even
Two 4-bit comparators are cascaded to form an 8-bit comparator. The to the cascading A = B to a logic
to the outputs from
cascading inputs of the most significant 4 bits should be connected . inputs of the least high, A < b and
3 the least significant ground A 1
significant 4-bit a > B to a logic
4-bit comparator
comparator low
When Karnaugh mapping, we must be sure to use the number of
3 maximum minimum median Karnaugh B 1
loops.
3 The final output of a POS circuit is generated by . an AND an OR a NOR a NAND A 2
After each circuit in a subsection of a VHDL program has been ,
3 designed tested engineered produced B 1
they can be combined and the subsection can be tested.
The series of IC's are pin, function, and voltage-level compatible
3 ALS CMOS HCT 2N C 2
with the 74 series IC's.
The circuit produces a HIGH output whenever the two inputs are exclusive-
3 exclusive-AND exclusive-NAND exclusive-NOR C 2
equal. OR
A 4-bit adder has the following inputs: C0 = 0, A1 = 0, A2 = 1, A3 = 0, A4 = 1,
3 1100 10101 11000 11 C 2
B1 = 0, B2 = 1, B3 = 1, B4 = 1. The output will be .
3 The statement evaluates the variable status. IF/THEN IF/THEN/ELSE CASE ELSIF A 2
In VHDL, data can be each of the following types except . STD_VECT
3 BIT BIT_VECTOR STD_LOGIC D 2
OR
When grouping cells within a K-map, the cells must be combined in groups of
3 2's 1, 2, 4, 8, etc. 4's 3's B 1
.
The circuit produces a HIGH output whenever the two inputs are inexclusive-
3 exclusive-AND exclusive-NOR exclusive-OR C 1
unequal. OR
 Occasionally, a particular logic expression will be of no consequence in the
operation of a circuit, such as in a BCD-to-decimal converter. These result in don't care, 1's, 0's, spurious, AND's, duplicate, 1's, spurious, 1's,
3 A 2
terms in the K-map and can be treated as either or simplify OR's, eliminate 0's, verify 0's, simplify
, in order to the resulting term.
A good rule of thumb for determining the pin numbers of dual-in-line package
None of the Can not
3 IC chips would be to place the notch to your right and pin #1 will always be in TRUE FALSE B 2
above predict
the lower right corner.
The carry output of each adder in a ripple adder provides an additional sum None of the Can not
3 TRUE FALSE A 1
output bit. above predict
Truth tables are great for listing all possible combinations of independent None of the Can not
3 TRUE FALSE A 1
variables. above predict
A square in the top row of a K-map is considered to be adjacent to its None of the Can not
3 TRUE FALSE A 1
corresponding square in the bottom row. above predict
To implement the full-adder sum functions, two exclusive-OR gates can be None of the Can not
3 TRUE FALSE A 1
used. above predict
The input at the 1, 2, 4, 8 inputs to a 4-line to 16-line decoder with active-low None of the Can not
3 TRUE FALSE B 2
outputs is 1110. As a result, output line 7 is driven LOW. above predict
When decisions demand two possible actions, the IF/THEN/ELSE control None of the Can not
3 TRUE FALSE A 2
structure is used. above predict
TTL stands for transistor-technology-logic. None of the Can not
3 TRUE FALSE B 1
above predict
The 54 prefix on ICs indicates a broader operating temperature range, None of the Can not
3 TRUE FALSE A 2
generally intended for military use. above predict
This is an example of a POS expression: None of the Can not
3 TRUE FALSE A 2
above predict
The abbreviation for an exclusive-OR gate is XOR. None of the Can not
3 TRUE FALSE A 2
above predict
In an even-parity system, the parity bit is adjusted to make an even number of None of the Can not
3 TRUE FALSE A 2
one bits. above predict
In an even-parity system, the following data will produce a parity bit = 1. None of the Can not
3 TRUE FALSE B 2
data = 1010011 above predict
The following combination is correct for an ODD parity data transmission None of the Can not
3 TRUE FALSE A 1
system: data = 011011100 and parity = 0 above predict
The XOR gate will produce a HIGH output if only one but not both of the None of the Can not
3 TRUE FALSE A 1
inputs is HIGH. above predict
When decisions demand one of many possible actions, the ELSIF control None of the Can not
3 TRUE FALSE A 1
structure is used. above predict
The K-map provides a "graphical" approach to simplifying sum-of-products None of the Can not
3 TRUE FALSE A 1
expressions. above predict
Even parity is the condition of having an even number of 1s in every group of None of the Can not
3 TRUE FALSE A 1
bits. above predict
 The look-ahead carry method suffers from propagation delays. None of the Can not
3 TRUE FALSE B 1
above predict
A pull-up resistor is a resistor used to keep a given point in a circuit HIGH None of the Can not
3 TRUE FALSE A 1
when in the active state. above predict
A data selector is also called a demultiplexer. None of the Can not
3 TRUE FALSE B 1
above predict
A digital circuit that converts coded information into a familiar or non-coded None of the Can not
3 TRUE FALSE B 1
form is known as an encoder. above predict
An exclusive-OR gate will invert a signal on one input if the other is always None of the Can not
3 TRUE FALSE A 1
HIGH. above predict
The following combination is correct for an EVEN parity data transmission None of the Can not
3 TRUE FALSE B 2
system: data = 100111100 and parity = 0 above predict
The CASE control structure is used when an expression has a list of possible None of the Can not
3 TRUE FALSE A 2
values. above predict
An encoder in which the highest and lowest value input digits are encoded None of the Can not
3 TRUE FALSE B 2
simultaneously is known as a priority encoder. above predict
Three select lines are required to address four data input lines. None of the Can not
3 TRUE FALSE B 2
above predict
Single looping in groups of three is a common K-map simplification technique. None of the Can not
3 TRUE FALSE B 2
above predict
In true sum-of-products expressions, the inversion signs cannot cover more None of the Can not
3 TRUE FALSE A 2
than single variables in a term. above predict
A combinatorial logic circuit has memory characteristics that "remember" the None of the Can not
3 TRUE FALSE B 2
inputs after they have been removed. above predict

Unit 4-Sequntial Logic

4 Which of the following is not a form of multivibrator? Astable. Monostable. Tristable. Bistable. C 1
The Q output The Q output is set The Q output is The Q A
A J-K flip-flop has two control inputs. What happens to the Q output on the toggles to the other to 1. reset to 0. output
active edge of the clock if both control inputs are asserted simultaneously? state. remains
4 unchanged. 2

A master/slave bistable is formed using two bistable connected in series.

4 TRUE False A 1

An astable has two metastable states and produces the function of a digital
oscillator
4 TRUE False A 1
In synchronous counters the clock input of each of the bistables are connected
4 together so that each changes state at the same time. TRUE False A 1
1: When the maximum clock rate is quoted for a logic family, then it applies to
4 a shift register flip-flop counter Multiplexer B 1
 2: The number of flip-flops required in a modulo N counter is

4 log2 (N) + 1 log2(N-1) log2 (N) N log2 (N) C 2

3: Flip-flop outputs are always same as
Independent of previous
4 Complimentary The same each other input A 1
4: How many gates (minimum) are needed for a 3-bit up-counter using
4 standard binary and using T lip-lops ? Assume unlimited fan-in. 6 3 2 1 C 2
Synchronous
4 5: The clear data and present input of the JK lip-lop are known as inputs Directed inputs Either (a) or (b) None of these C 1
Same as a mode-5
counter followed A decade counter
by a mod- 2 A mod-7 Ripple carry
4 A mod-2 counter followed by a mod-5 counter is counter counter Counter A 1
What is the maximum counting speed of a 4-bit binary counter which is
4 composed of flip-flops with a propagation delay of 25 ns ? 1 MHz 10 MHz 100 MHz 8 MHz B 2

Go to state 0
and stay there

Retain its
8: A JK flip-lop has its J input connected to logic level 1 and its input to the Q Change its state at Go to state 1 and previous
4 output. A clock pulse is fed to its clock input. The flip-lop will now each clock pulse stay there state D 2
Q will flip from 0 Q will flip from 0
9: Consider an RS lip-lops with both inputs set to 0. If a momentary '1' is to 1 and then back to 1 and then back Q will flip from Q will flip
4 applied at the input S,then the output to 0 to 0 1 to 0 from 0 to 1 D 2
Present
outputs only
Past outputs only

Both present
4 The output of a sequential circuit depends on Present inputs only and past inputs C 2

4 The ring counter is analogous to Toggle switch Latch Stepping switch J-K flip-flop C 1

Reduce the Asynchrono

number of input us input and
pulses to reset output
4 12: In a digital counter circuit feedback loop is introduced to Improve distortion Improve stability the counter pulses C 1

A J-K lip-lop has its J-input connected to logic level 1 and its input to the Q Change its state at Go to state 1 and Go to state 0 Retain its
4 output pulse is fed to its clock input the flip-flop will now each clock pulse stay there and stay there present state A 2
 None of
4 Which of the following conditions must be met to avoid race around problem ? Δ t < tp < T T > Δt > tp 2 tp < Δt < T these B 2
Match List I with List II and select the correct answer form the codes given
below the list List I
A. A shift register can be
B. A multiplexer
C. A decoder can List II
1.for parallel to serial conversion
2.to generate memory can be used chip select
3.for parallel to serial conversion

CODES:
ABC

4 312 231 132 123 C 4

With the use of an electronic counter six capsules are to be filled in bottles 2
automatically. In such a counter what will be the number of flip-flops required
4 ? 3 12 6 8 C
1
A parallel-in
A serial-in serial- A serial-in parallel- parallel-out
4 A pulse train can be delayed by a finite number of clock periods using out shift register out shift register Both (a) and (b) shift register D
4 How many illegitimate states has synchronous mod-6 counter ? 3 2 1 6 A 1
2 input XORs and 4 2 input NORs NOR gates 2
input AND gates and one XNOR and shift
4 A 2 bit binary multiplier can be implemented using 2 input ANDs only only gate registers B
Ripple carry 1
4 A ring counter is same as up-down counter parallel-counter shift register Counter C
Combinational Sequential circuit None of 1
4 The dynamic hazard problem occurs in circuit alone only Both (a) and (b) these C
4 A n-stage ripple counter will count up to 2n 2n-1 n 2n-1 A 1
2
Tell how much time Synchronize
has elapsed since events in
Tell the time of the the system was Carry parllel various parts
4 The clock signals are used in sequential logic circuits to day turned on data signals of system D
Encoder 1
Demultiplex
Decoder/demultipl er
4 74L5138 chip functions as exer Multiplexer A
 A sequential circuit outputs a ONE when an even number (> 0) of one's are 2
input; otherwise the output is ZERO. The minimum number of states required None of
4 is 0 1 2 these C
1
Serial to parallel Parallel to serial
4 A shift register can be used for Digital delay line conversion conversion All of these D
4 Popular application of flip-flop are Transfer register Shift registers Counters All of these D 2
Q type flip-flop
For which of the following flip-flops, the output is clearly defined for all
4 combinations of two inputs ? R-S flip-lop J-K flip-lop D flip-flop C 2
Successive
When a large number of analog signals are to be converted an analog Ripple carry Forward approximatio
4 multiplexer is used. In this case most suitable A.D. converter will be counter type Dual stop type counter type n type D 2
4 To build a mod-19 counter the number of flip-flops required is 3 5 7 9 B 2
One stable and
Two quasi stable one quasi-stable None of
4 The astable multivibrator has states Two stable states state these A 2
How many bits are required to encode all twenty six letters, ten symbols, and
4 ten numerals ? 5 6 10 48 B 2
The functional difference between S-R flip-flop and J-K flip-flop is that J-K is faster than S-R Has a feed-back Accepts both Both (a) and
4 flip-flop flip-flop path inputs 1 (b) C 1
High state

4 In a positive edge triggered JK flip-flop, a low J and low K produces No change Low state None of these A 1

When an inverter is placed between both inputs of an SR flip-flop, then Master slave
4 resulting flip-lop is JK flip-flop D flip-flop SR flip-flop JK flip-flop B 2
A 2 MHz signal is applied to the input of a J-K lip-lop which is operating in
4 the 'toggle' mode. The frequency of the signal at the output will be 1 MHz 2 MHz 6 MHz 8 MHz D 2
A T flip-flop
A SR flip-flop and An SR flip-lfop and and a D flip- Two D flip-
4 The master slave JK lip-flop is effectively a combination of a T flip-flop a D flip-flop flop flops A 2

Generally
they involve
External clock is to stability
4 It is difficult to design asynhronous sequential circuit because be provided It is more complex Both (a) and (b) problem D 2
Frequency to Voltage to
voltage frequency
4 A stable multivibrator is used as Comparator circuit Demultiplexer converter converter A 2
4 How many flip-flop are needed to divide the input frequency by 64 ? 2 5 6 8 C 1
 J and K
41: In a ripple counter using edge triggered JK flfp-flops, the pulse input is clock input of all clock input of one J and K inputs inputs of one
4 applied to the flip-flops flip-flops of all flip-flops flip-flop C 1
The number of clock pulses needed to shift one byte of data from input to the
4 output of a 4-bit shift register is 10 12 16 32 C 2

JK flip-flop
is acronym
JK flip-flop of Junction
JK flip flop needs There is a feedback accepts both cathode
4 The main difference between JK and RS flip-flop is that a clock pulse in JK lip-lop inputs as 1 multivibrator C 2
Which of the following unit will choose to transform decimal number to binary 1
4 code ? Encoder Decoder Multiplexer Counter A
The flip-flops which operate in synchronism with external clock pulses are Synchronous flip- Asynchronous flip- Either of the None of 1
4 known as flop flop above these A
2
Master-slave
4 Which of the following flip-flop is free from race-around problem ? Q flip-flop T flip-flop SR flip-flop JK flip-flop D
2
If the input J is connected through K input of J-K, then flip-flop will behave as Master slave
4 a D type flip-flop T type flip-flop S-R flip-flop JK flip-flop A
If a clock with time period 'T' is used with n stage shift register, then output of 2
4 final stage will be delayed by nT sec (n-1)T sec n/T sec (2n+1)T sec B
temporary 1
storage unit
set of capacitor set to paper tapes within the CPU part of the
used to register and cards put in a having main
input instructions file dedicated or memory
in a digital general purpose
4 Register is a computer use C
4 The number of flip-flops required in a decade counter is 3 4 8 10 B 1
1
Twisted ring Ring counter
Twisted ring with Ring counter with with 2N : 1 with 2 N : 1
4 If in a shift resistor Q0 is fed back to input the resulting counter is N : 1 scale N : 1 scale scale scale C

A 8-bit serial in / parallel out shift register contains the value “8”, clock
signal(s) will be required to shift the value completely out of the register.
4 1 2 4 8D 2
Current state Input and
State variable, Current state, flip- and external clock signal
4 In a sequential circuit the next state is determined by and current state flop output input applied D 2
 The divide-by-60 counter in digital clock is implemented by using two Mod-10, Mod- Mod-50,
4 cascading counters: Mod-6, Mod-10 Mod-50, Mod-10 50 Mod-6 A 2
In NOR gate based S-R latch if both S and R inputs are set to logic 0, the
4 previous output state is maintained. True FALSE A 2
The minimum time for which the input signal has to be maintained at the input Pulse
of flip-flop is called of the flip-flop. Pulse Interval Stability
4 Set-up time Hold time time time (PST) B 2
4 74HC163 has two enable input pins which are and ENP, ENT ENI, ENC ENP, ENC ENT, ENI A 4
is said to occur when multiple internal variables change due to Hold and
4 change in one input variable Clock Skew Race condition Hold delay Wait B 2
Clear input
Preset input (CLR),
Asynchronous, Synchronous, (PRE), Clear Preset input
4 The input overrides the input synchronous asynchronous input (CLR) (PRE) A 4
Mod-10
4 A decade counter is . Mod-3 counter Mod-5 counter Mod-8 counter counter D 2

State of
transmission
line is not
It is set to logic It is set to logic Remains in used to start
4 In asynchronous transmission when the transmission line is idle, low high previous state transmission B 2
4 A Nibble consists of bits 2 4 8 16 B 1
4 The output of this circuit is always . 1 0A Abar C 1
4 Excess-8 code assigns to “-8” 1110 1100 1000 0 D 1
Vout / Vin = - Rf / Vout / Rf = - Vin / Rf / Vin = - Ri / Rf / Vin =
4 The voltage gain of the Inverting Amplifier is given by the relation Ri Ri Vout Ri / Vout A 2
None of
Local User Least Upper given
4 LUT is acronym for Look Up Table Terminal Time Period options A 2
AND, NAND, NOT, NOR, NOT, OR,
4 The three fundamental gates are XOR OR, AND, NAND XOR AND D 1
The size of
the address
bus of the
The total amount of memory that is supported by any digital system depends The organization The structure of The size of microproces
4 upon of memory memory decoding unit sor D 2
Bust Flash
4 Stack is an acronym for FIFO memory LIFO memory Flash Memory Memory B 2
4 Addition of two octal numbers “36” and “71” results in 213 123 127 345 C 2
 Preset input Clear Input
4 is one of the examples of synchronous inputs. J-K input EN input (PRE) (CLR) A 2
occurs when the same clock signal arrives at different times at
different clock inputs due to None of
propagation delay given
4 Race condition Clock Skew Ripple Effect options B 2
Consider an up/down counter that counts between 0 and 15, if external
input(X) is “0” the counter counts
upward (0000 to 1111) and if external input (X) is “1” the counter counts
downward (1111 to 0000), now
suppose that the present state is “1100” and X=1, the next state of the counter
will be
4 0 1101 1011 1111 B 1
Previous
In a state diagram, the transition from a current state to the next state is Current state and Current state and Previous state state and
4 determined by the inputs outputs and inputs outputs A 1
State
4 is used to simplify the circuit that determines the next state. State diagram Next state table State reduction assignment D 2

A 8-bit serial in / parallel out shift register contains the value “8”, clock
signal(s) will be required to shift the value completely out of the register.
4 1 2 4 8D 1

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish
to store the nibble 1100. What
will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
4 1100 11 0 1111 C 2
None of
Local User Least Upper given
4 LUT is acronym for Look Up Table Terminal Time Period options A 2

Product of sum Sum of

4 The diagram given below represents Demorgans law Associative law form product form D 2

It does not It does not

Sets to clear when show transition accept
The operation of J-K flip-flop is similar to that of the SR flip-flop except that Doesn’t have an both J = 0 and K = on change in asynchronou
4 the J-K flip-flop invalid state 0 pulse s inputs A 1
Serial data to Parallel data to Serial data to Parallel data
4 A multiplexer with a register circuit converts parallel serial serial to parallel B 1
 Non- PAL that is
reprogrammable programmed only Reprogramm
4 A GAL is essentially a . PAL by the manufacturer Very large PAL able PAL D 2
None of
FAST Mode given
4 in , all the columns in the same row are either read or written. Sequential Access MOS Access Page Access options C 2
4 How many flip-flops are required to produce a divide-by-32 device? 2 5 6 4B 2
A reduced state table has 18 rows. The minimum number of flip flops needed
4 to implement the sequential machine is 18 9 5 4C 2
1
Advantage of synchronous sequential circuits over asynchronous ones is ease of avoiding
problems due to lower hardware better noise
4 faster operation hazard requirement immunity A
The characteristic equation of a JK flip flop is 1
Qn+1=J.Q’n+K’.Q Qn+1=(J+K)
4 Qn+1=J.Qn+K.Qn n Qn+1=QnJ.K Qn B
THE 2
OUTPUT
OF FLIP-
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE FLOP
SET TO LOGIC ZERO ------- REMAINS
THE FLOP-FLOP Q=1 AND Q‟=0 UNCHANG
4 IS TRIGGERED Q=0 AND Q‟=1 ED D
In Q output of the last flip-flop of the shift register is connected to 2
the data input of the first
flip-flop of the shift register.
Johnson
4 Moore machine Meally machine counter Ring counter D
5-BIT JOHNSON COUNTER SEQUENCES THROUGH STATES 2

4 7 10 32 25 B
A 8-bit serial in / parallel out shift register contains the value “8”, clock 1
signal(s) will be required to shift
the value completely out of the register.
4 1 2 4 8D
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT 1
WILL BE THE VALUE OF
REGISTER AFTER THREE CLOCK PULSES?

4 2 4 6 8D
 1
The alternate solution for a multiplexer and a register circuit is Parallel in / Serial in /
Parallel in / Serial Serial in / Parallel Parallel out Serial Out
4 out shift register out shift register shift register shift register A
A multiplexer with a register circuit converts
Serial data to Parallel data to Serial data to Parallel data
4 parallel serial serial to parallel B 2
A synchronous decade counter will have flip-flops
4 3 4 7 10 B 2
In outputs depend only on the current state. State 1
State Reduction Assignment
4 Mealy machine Moore Machine table table B
The state 1
diagram
shows only
Given the state diagram of an up/down counter, we can find Both the next the
The previous state and previous inputs/output
The next state of a of a given present states of a given s of a given
4 given present state state state states A
A SINGLE 2
ONLY A SINGLE DECADE
THE HOURS COUNTER IS IMPLEMENTED USING MOD-12 MOD-10 AND MOD-10 AND COUNTER
COUNTER IS MOD-6 MOD-2 AND A
4 REQUIRED COUNTERS COUNTERS FLIP-FLOP D
2
The design and implementation of synchronous counters start from

4 Truth table k-map state table state diagram D

NEGATIVE- 2
POSITIVE- EDGE
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY PULSE EDGE TRIGGERE
USING A GATED FLIP- TRIGGERED FLIP- TRIGGERED D FLIP-
4 FLOPS FLOPS FLIP-FLOPS FLOPS D
Preset input Clear Input 1
4 is one of the examples of synchronous inputs. J-K input EN input (PRE) (CLR) A
1
A positive edge-triggered flip-flop changes its state when Low-to-high High-to-low Enable input Preset input
4 transition of clock transition of clock (EN) is set (PRE) is set A
 Flip flops are also called 1
Bi-stable
Bi-stable Bi-stable Bi-stable singlevibrato
4 dualvibrators transformer multivibrators rs C
A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED
BY THE USER AND NOT BY
THE MANUFACTURER.

4 TRUE FALSE A 2
THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS,
CONNECTED TO FORM A 16-INPUT
MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT
GATE
4 AND OR NAND XOR B 2
3 INPUTS 3 INPUTS
A particular half adder has 2 INPUTS AND 1 2 INPUTS AND 2 AND 1 AND 2
4 OUTPUT OUTPUT OUTPUT OUTPUT B 2
A full-adder has a Cin = 0. What are the sum (<PRIVATE
"TYPE=PICT;ALT=sigma"> ) and the carry (Cout)
when A = 1 and B = 1?
4 = 0, Cout = 0 = 0, Cout = 1 =1 B 2

The sequence of states that are implemented by a n-bit Johnson counter is

2n (n multiplied by 2n (2 raise to n2 (n raise to

4 n+2 (n plus 2) 2) power n) power 2) B 2
A 8-bit serial in / parallel out shift register contains the value “8”, clock
signal(s) will be required to shift
the value completely out of the register.
4 1 2 4 8D 1

A GAL is essentially a . Non- PAL that is

reprogrammable programmed only Reprogramm
4 PAL by the manufacturer Very large PAL able PAL D 2

State of
transmission
In asynchronous transmission when the transmission line is idle, line is not
It is set to logic It is set to logic Remains in used to start
4 low high previous state transmission B 1
 The alternate solution for a demultiplexer-register combination circuit is Parallel in / Serial in /
Parallel in / Serial Serial in / Parallel Parallel out Serial Out
4 out shift register out shift register shift register shift register B 1

Parallel in / Serial in /
The alternate solution for a multiplexer and a register circuit is Parallel in / Serial Serial in / Parallel Parallel out Serial Out
4 out shift register out shift register shift register
shift register A 2
State
State Reduction Assignment
4 In outputs depend only on the current state. Mealy machine Moore Machine table table B 2
Propagation Input Hold
Delay is zero time is zero
(Output is (no need to
The changes in the The changes in the immediately maintain
data at the inputs data at the inputs of changed when input after
A transparent mode means of the latch are the latch are not clock signal is clock
4 seen at the output seen at the output applied) transition) A 4
occurs when the same clock signal arrives at different times at
different clock inputs due to None of
propagation delay. given
4 Race condition Clock Skew Ripple Effect options B 2
Clear Input 1
4 is one of the examples of asynchronous inputs. J-K input S-R input D input (CLR) D
Bi-stable devices remain in either of their states unless the inputs 1
force the device to switch its state
4 Ten Eight Three Two D
2
RCO Stands for Reconfiguration Reconfiguration Ripple Counter Ripple Clock
4 Counter Output Clock Output Output Output D
2
A positive edge-triggered flip-flop changes its state when Low-to-high High-to-low Enable input Preset input
4 transition of clock transition of clock (EN) is set (PRE) is set A
The low to high or high to low transition of the clock is considered to be a(n) 2

4 State Edge Trigger One-shot B

In asynchronous digital systems all the circuits change their state with respect 1
to a common clock
4 TRUE FALSE B
 If the S and R inputs of the gated S-R latch are connected together using a 1
gate then there is only a
single input to the latch. The input is represented by D instead of S or R (A
gated D-Latch)
4 AND OR NOT XOR C
Input is 1
4 If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop 0 1 Invalid invalid B
3-to-8 decoder can be used to implement Standard SOP and POS Boolean
4 expressions TRUE FALSE A 2
Decimal-to-
BCD-to- BCD
4 The Encoder is used as a keypad encoder. 2-to-8 encoder 4-to-16 encoder Decimal Priority D 1

4 The simplest and most commonly used Decoders are the Decoders n to 2n (n-1) to 2n (n-1) to (2n-1) n to 2n-1 A 1
A Karnaugh map is similar to a truth table because it presents all the possible
values of input variables and the
resulting output of each value.
4 TRUE False A 2
The decimal “17” in BCD will be represented as 10001(right opt is
4 not given) 11101 11011 10111 11110 C 1
Q2 :=Q1 OR X OR Q3 Q2:= Q1 & X Q2:= Q1 ! X
4 The above ABEL expression will be Q2:= Q1 $ X $ Q3 Q2:= Q1 # X # Q3 & Q3 ! Q3 B 2
Synchronous
Above is the circuit diagram of Asynchronous up- Asynchronous Synchronous up down-
4 counter down-counter counter counter A 2
4 floating-gate 6 floating- 1
The high density FLASH memory cell is implemented using 1 floating-gate 2 floating-gate MOS gate MOS
4 MOS transistor MOS transistors transistors transistors A
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. 1
The nibble 0111 is
waiting to be entered on the serial data-input line. After two clock pulses, the
4 shift register is storing . 1110 111 1000 1001 D
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of 2
register after three clock pulses?
4 2 4 6 8 D
2

State of
transmission
line is not
In asynchronous transmission when the transmission line is idle, It is set to logic It is set to logic Remains in used to start
4 low high previous state transmission B
 A multiplexer with a register circuit converts Serial data to Parallel data to Serial data to Parallel data 2
4 parallel serial serial to parallel B
is used to simplify the circuit that determines the next state. State 1
4 State diagram Next state table State reduction assignment D
State 1
In outputs depend only on the combination of current state and State Reduction Assignment
4 inputs Mealy machine Moore Machine table table A
Clear input 1
Preset input (CLR),
The input overrides the input Asynchronous, Synchronous, (PRE), Clear Preset input
4 synchronous asynchronous input (CLR) (PRE) A
Clear Input
4 is one of the examples of asynchronous inputs. J-K input S-R input D input (CLR) 2

A positive edge-triggered flip-flop changes its state when Low-to-high High-to-low Enable input Preset input
4 transition of clock transition of clock (EN) is set (PRE) is set A 1
In asynchronous digital systems all the circuits change their state with respect
to a common clock
4 TRUE False B 1
For a gated D-Latch if EN=1 and D=1 then Q(t+1) =
4 0 1 Q(t) Invalid B 2

It does not It does not

Sets to clear when show transition accept
The operation of J-K flip-flop is similar to that of the SR flip-flop except that Doesn’t have an both J = 0 and K = on change in asynchronou
4 the J-K flip-flop invalid state 0 pulse s inputs A 4
If S=1 and R=1, then Q(t+1) = for negative edge triggered flip-
flop Input is
4 0 1 Invalid invalid C 2

The sequence of states that are implemented by a n-bit Johnson counter is 2 raise to power n raise to
4 n+2 2n n power 2 B 2
1
of a ROM is the time it takes
for the data to appear at the Data
Output of the ROM chip after an
address is applied at the address
4 input lines Write Time Recycle Time Refresh Time Access Time D
In the Q output of the last flip-flop of the shift register is connected 1
to the data input of the first flipflop.
Moore Meally
4 machine machine Johnson counter Ring counter
 At T0 the value stored in a 4-bit left shift was “1”. What will be the value of 2
register after three clock pulses?
4 2 4 6 8D
2
Parallel in / Serial in /
The alternate solution for a multiplexer and a register circuit is Parallel in / Serial Serial in / Parallel Parallel out Serial Out
4 out shift register out shift register shift register shift register A
A multiplexer with a register circuit converts 2
Serial data to Parallel data to Serial data to Parallel data
4 parallel serial serial to parallel B
state 1
4 The design and implementation of synchronous counters start from Truth table k-map state table diagram D
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY NEGATIVE- 1
USING A POSITIVE- EDGE
PULSE EDGE TRIGGERE
GATED FLIP- TRIGGERED FLIP- TRIGGERED D FLIP-
4 FLOPS FLOPS FLIP-FLOPS FLOPS D
Preset input Clear Input 1
4 is one of the examples of synchronous inputs. J-K input EN input (PRE) (CLR) A

A positive edge-triggered flip-flop changes its state when Low-to-high High-to-low Enable input Preset input
4 transition of clock transition of clock (EN) is set (PRE) is set A 2
Bi-stable
Flip flops are also called Bi-stable Bi-stable Bi-stable singlevibrato
4 dualvibrators transformer multivibrators rs C 1

The sequence of states that are implemented by a n-bit Johnson counter is 2n (n multiplied by 2n (2 raise to n2 (n raise to
4 n+2 (n plus 2) 2) power n) power 2) B 1
Propagation Input Hold
Delay is zero time is zero
(Output is (no need to
The changes in the The changes in the immediately maintain
data at the inputs data at the inputs of changed when input after
of the latch are the latch are not clock signal is clock
4 A transparent mode means seen at the output seen at the output applied) transition) A 2
is one of the examples of asynchronous inputs. Clear Input
4 J-K input S-R input D input (CLR) D 2

A positive edge-triggered flip-flop changes its state when Low-to-high High-to-low Enable input Preset input
4 transition of clock transition of clock (EN) is set (PRE) is set A 2
 If the S and R inputs of the gated S-R latch are connected together using a
gate then there is only a
single input to the latch. The input is represented by D instead of S or R (A
gated D-Latch)
4 AND OR NOT XOR C 2
Input is 1
4 If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop 0 1 Invalid invalid
The state 1
diagram
shows only
Both the next the
The previous state and previous inputs/output
The next state of a of a given present states of a given s of a given
4 Given the state diagram of an up/down counter, we can find given present state state state states A
NEGATIVE- 2
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY POSITIVE- EDGE
USING A PULSE EDGE TRIGGERE
GATED FLIP- TRIGGERED FLIP- TRIGGERED D FLIP-
4 FLOPS FLOPS FLIP-FLOPS FLOPS D
In Q output of the last flip-flop of the shift register is connected to 2
the data input of the first Johnson
4 flip-flop of the shift register. Moore machine Meally machine counter Ring counter D
A counter is implemented using three (3) flip-flops, possibly it will have 2
maximum output
status.
4 3 7 8 15 C
We have a digital circuit. Different parts of circuit operate at different clock 1
frequencies (4MHZ, 2MHZ
and 1MHZ), but we have a single clock source having a fix clock frequency
(4MHZ), we can get help by
Using S-R Flop-
4 Flop D-flipflop J-K flip-flop T-Flip-Flop C
1
If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop Input is
4 0 1 Invalid invalid B
Input is 1
4 If S=1 and R=1, then Q(t+1) = for negative edge triggered flip-flop 0 1 Invalid invalid C
 THE
OUTPUT
OF FLIP-
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE FLOP
SET TO LOGIC ZERO REMAINS
THE FLOP-FLOP Q=1 AND UNCHANG
4 IS TRIGGERED Q=0 AND Q‟=1 Q’=0 ED C 2
If an S-R latch has a 1 on the S input and a 0 on the R input and then the S
input goes to 0, the latch will
4 be set reset invalid clear A 2
For a positive edge-triggered J-K flip-flop with both J and K HIGH, the
outputs will if the clock goes HIGH.

4 set A 2

The D flip-
What is the difference between a D latch and a D flip-flop? The D latch has a The D flip-flop has used for faster flop has a
4 clock input. an enable input. operation. clock input. D 2
Counts high
and low range None of
A frequency counter Counts no. of clock of given clock given
4 Counts pulse width pulses in 1 second pulse options B 2