module bitmag(O12,O16,O17,a3,b3,a2,b2,a1,b1,a0,b0);

output O12,O16,O17;

input a3,b3,a2,b2,a1,b1,a0,b0;

wire b3n,a3n,b2n,a2n,b1n,a1n,b0n,a0n;

wire s1,s2,s3,s4,s5,s6,s7,s8,s9,s10;

wire s11,s13,s14,s15;

wire [0:3]x;

not n1(b3n,b3);

not n2(a3n,a3);

not n3(b2n,b2);

not n4(a2n,a2);

not n5(b1n,b1);

not n6(a1n,a1);

not n7(b0n,b0);

not n8(a0n,a0);

and A1(s1,a3,b3n);

and A2(s2,b3,a3n);

and A3(s3,a2,b2n);

and A4(s4,b2,a2n);

and A5(s5,a1,b1n);

and A6(s6,b1,a1n);

and A7(s7,a0,b0n);

and A8(s8,b0,a0n);

xnor r1(x3,s1,s2);

xnor r2(x2,s3,s4);

xnor r3(x1,s5,s6);

xnor r4(x0,s7,s8);
and A9(s9,x3,s3);

and A10(s13,s4,x3);

and A11(s10,x3,x2,s5);

and A12(s14,x3,x2,s6);

and A13(s11,x3,x2,x1,s7);

and A14(s15,x3,x2,x1,s8);

xor r5(O12,s1,s9,s10,s11);

xor r6(O16,s2,s13,s14,s15);

and A15(O17,x3,x2,x1,x0);

endmodule